1 // SPDX-License-Identifier: GPL-2.0-only 2 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ 3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 4 * 5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 6 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 7 * 8 * Ani Joshi / Jeff Garzik 9 * - Code cleanup 10 * 11 * Michel Danzer <michdaen@iiic.ethz.ch> 12 * - 15/16 bit cleanup 13 * - fix panning 14 * 15 * Benjamin Herrenschmidt 16 * - pmac-specific PM stuff 17 * - various fixes & cleanups 18 * 19 * Andreas Hundt <andi@convergence.de> 20 * - FB_ACTIVATE fixes 21 * 22 * Paul Mackerras <paulus@samba.org> 23 * - Convert to new framebuffer API, 24 * fix colormap setting at 16 bits/pixel (565) 25 * 26 * Paul Mundt 27 * - PCI hotplug 28 * 29 * Jon Smirl <jonsmirl@yahoo.com> 30 * - PCI ID update 31 * - replace ROM BIOS search 32 * 33 * Based off of Geert's atyfb.c and vfb.c. 34 * 35 * TODO: 36 * - monitor sensing (DDC) 37 * - virtual display 38 * - other platform support (only ppc/x86 supported) 39 * - hardware cursor support 40 * 41 * Please cc: your patches to brad@neruo.com. 42 */ 43 44 /* 45 * A special note of gratitude to ATI's devrel for providing documentation, 46 * example code and hardware. Thanks Nitya. -atong and brad 47 */ 48 49 50 #include <linux/aperture.h> 51 #include <linux/module.h> 52 #include <linux/moduleparam.h> 53 #include <linux/kernel.h> 54 #include <linux/errno.h> 55 #include <linux/string.h> 56 #include <linux/mm.h> 57 #include <linux/vmalloc.h> 58 #include <linux/delay.h> 59 #include <linux/interrupt.h> 60 #include <linux/uaccess.h> 61 #include <linux/fb.h> 62 #include <linux/init.h> 63 #include <linux/pci.h> 64 #include <linux/ioport.h> 65 #include <linux/console.h> 66 #include <linux/backlight.h> 67 #include <asm/io.h> 68 69 #ifdef CONFIG_PPC_PMAC 70 #include <asm/machdep.h> 71 #include <asm/pmac_feature.h> 72 #include "../macmodes.h" 73 #endif 74 75 #ifdef CONFIG_PMAC_BACKLIGHT 76 #include <asm/backlight.h> 77 #endif 78 79 #ifdef CONFIG_BOOTX_TEXT 80 #include <asm/btext.h> 81 #endif /* CONFIG_BOOTX_TEXT */ 82 83 #include <video/aty128.h> 84 85 /* Debug flag */ 86 #undef DEBUG 87 88 #ifdef DEBUG 89 #define DBG(fmt, args...) \ 90 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); 91 #else 92 #define DBG(fmt, args...) 93 #endif 94 95 #ifndef CONFIG_PPC_PMAC 96 /* default mode */ 97 static const struct fb_var_screeninfo default_var = { 98 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 99 640, 480, 640, 480, 0, 0, 8, 0, 100 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 101 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 102 0, FB_VMODE_NONINTERLACED 103 }; 104 105 #else /* CONFIG_PPC_PMAC */ 106 /* default to 1024x768 at 75Hz on PPC - this will work 107 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 108 static const struct fb_var_screeninfo default_var = { 109 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 110 1024, 768, 1024, 768, 0, 0, 8, 0, 111 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 112 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 113 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 114 FB_VMODE_NONINTERLACED 115 }; 116 #endif /* CONFIG_PPC_PMAC */ 117 118 /* default modedb mode */ 119 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 120 static const struct fb_videomode defaultmode = { 121 .refresh = 60, 122 .xres = 640, 123 .yres = 480, 124 .pixclock = 39722, 125 .left_margin = 48, 126 .right_margin = 16, 127 .upper_margin = 33, 128 .lower_margin = 10, 129 .hsync_len = 96, 130 .vsync_len = 2, 131 .sync = 0, 132 .vmode = FB_VMODE_NONINTERLACED 133 }; 134 135 /* Chip generations */ 136 enum { 137 rage_128, 138 rage_128_pci, 139 rage_128_pro, 140 rage_128_pro_pci, 141 rage_M3, 142 rage_M3_pci, 143 rage_M4, 144 rage_128_ultra, 145 }; 146 147 /* Must match above enum */ 148 static char * const r128_family[] = { 149 "AGP", 150 "PCI", 151 "PRO AGP", 152 "PRO PCI", 153 "M3 AGP", 154 "M3 PCI", 155 "M4 AGP", 156 "Ultra AGP", 157 }; 158 159 /* 160 * PCI driver prototypes 161 */ 162 static int aty128_probe(struct pci_dev *pdev, 163 const struct pci_device_id *ent); 164 static void aty128_remove(struct pci_dev *pdev); 165 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state); 166 static int __maybe_unused aty128_pci_suspend(struct device *dev); 167 static int __maybe_unused aty128_pci_hibernate(struct device *dev); 168 static int __maybe_unused aty128_pci_freeze(struct device *dev); 169 static int __maybe_unused aty128_pci_resume(struct device *dev); 170 static int aty128_do_resume(struct pci_dev *pdev); 171 172 static const struct dev_pm_ops aty128_pci_pm_ops = { 173 .suspend = aty128_pci_suspend, 174 .resume = aty128_pci_resume, 175 .freeze = aty128_pci_freeze, 176 .thaw = aty128_pci_resume, 177 .poweroff = aty128_pci_hibernate, 178 .restore = aty128_pci_resume, 179 }; 180 181 /* supported Rage128 chipsets */ 182 static const struct pci_device_id aty128_pci_tbl[] = { 183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 269 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 271 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 273 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 275 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 277 { 0, } 278 }; 279 280 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 281 282 static struct pci_driver aty128fb_driver = { 283 .name = "aty128fb", 284 .id_table = aty128_pci_tbl, 285 .probe = aty128_probe, 286 .remove = aty128_remove, 287 .driver.pm = &aty128_pci_pm_ops, 288 }; 289 290 /* packed BIOS settings */ 291 #ifndef CONFIG_PPC 292 typedef struct { 293 u8 clock_chip_type; 294 u8 struct_size; 295 u8 accelerator_entry; 296 u8 VGA_entry; 297 u16 VGA_table_offset; 298 u16 POST_table_offset; 299 u16 XCLK; 300 u16 MCLK; 301 u8 num_PLL_blocks; 302 u8 size_PLL_blocks; 303 u16 PCLK_ref_freq; 304 u16 PCLK_ref_divider; 305 u32 PCLK_min_freq; 306 u32 PCLK_max_freq; 307 u16 MCLK_ref_freq; 308 u16 MCLK_ref_divider; 309 u32 MCLK_min_freq; 310 u32 MCLK_max_freq; 311 u16 XCLK_ref_freq; 312 u16 XCLK_ref_divider; 313 u32 XCLK_min_freq; 314 u32 XCLK_max_freq; 315 } __attribute__ ((packed)) PLL_BLOCK; 316 #endif /* !CONFIG_PPC */ 317 318 /* onboard memory information */ 319 struct aty128_meminfo { 320 u8 ML; 321 u8 MB; 322 u8 Trcd; 323 u8 Trp; 324 u8 Twr; 325 u8 CL; 326 u8 Tr2w; 327 u8 LoopLatency; 328 u8 DspOn; 329 u8 Rloop; 330 const char *name; 331 }; 332 333 /* various memory configurations */ 334 static const struct aty128_meminfo sdr_128 = { 335 .ML = 4, 336 .MB = 4, 337 .Trcd = 3, 338 .Trp = 3, 339 .Twr = 1, 340 .CL = 3, 341 .Tr2w = 1, 342 .LoopLatency = 16, 343 .DspOn = 30, 344 .Rloop = 16, 345 .name = "128-bit SDR SGRAM (1:1)", 346 }; 347 348 static const struct aty128_meminfo sdr_sgram = { 349 .ML = 4, 350 .MB = 4, 351 .Trcd = 1, 352 .Trp = 2, 353 .Twr = 1, 354 .CL = 2, 355 .Tr2w = 1, 356 .LoopLatency = 16, 357 .DspOn = 24, 358 .Rloop = 16, 359 .name = "64-bit SDR SGRAM (2:1)", 360 }; 361 362 static const struct aty128_meminfo ddr_sgram = { 363 .ML = 4, 364 .MB = 4, 365 .Trcd = 3, 366 .Trp = 3, 367 .Twr = 2, 368 .CL = 3, 369 .Tr2w = 1, 370 .LoopLatency = 16, 371 .DspOn = 31, 372 .Rloop = 16, 373 .name = "64-bit DDR SGRAM", 374 }; 375 376 static const struct fb_fix_screeninfo aty128fb_fix = { 377 .id = "ATY Rage128", 378 .type = FB_TYPE_PACKED_PIXELS, 379 .visual = FB_VISUAL_PSEUDOCOLOR, 380 .xpanstep = 8, 381 .ypanstep = 1, 382 .mmio_len = 0x2000, 383 .accel = FB_ACCEL_ATI_RAGE128, 384 }; 385 386 static char *mode_option = NULL; 387 388 #ifdef CONFIG_PPC_PMAC 389 static int default_vmode = VMODE_1024_768_60; 390 static int default_cmode = CMODE_8; 391 #endif 392 393 static int default_crt_on = 0; 394 static int default_lcd_on = 1; 395 static bool mtrr = true; 396 397 #ifdef CONFIG_FB_ATY128_BACKLIGHT 398 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 399 #endif 400 401 /* PLL constants */ 402 struct aty128_constants { 403 u32 ref_clk; 404 u32 ppll_min; 405 u32 ppll_max; 406 u32 ref_divider; 407 u32 xclk; 408 u32 fifo_width; 409 u32 fifo_depth; 410 }; 411 412 struct aty128_crtc { 413 u32 gen_cntl; 414 u32 h_total, h_sync_strt_wid; 415 u32 v_total, v_sync_strt_wid; 416 u32 pitch; 417 u32 offset, offset_cntl; 418 u32 xoffset, yoffset; 419 u32 vxres, vyres; 420 u32 depth, bpp; 421 }; 422 423 struct aty128_pll { 424 u32 post_divider; 425 u32 feedback_divider; 426 u32 vclk; 427 }; 428 429 struct aty128_ddafifo { 430 u32 dda_config; 431 u32 dda_on_off; 432 }; 433 434 /* register values for a specific mode */ 435 struct aty128fb_par { 436 struct aty128_crtc crtc; 437 struct aty128_pll pll; 438 struct aty128_ddafifo fifo_reg; 439 u32 accel_flags; 440 struct aty128_constants constants; /* PLL and others */ 441 void __iomem *regbase; /* remapped mmio */ 442 u32 vram_size; /* onboard video ram */ 443 int chip_gen; 444 const struct aty128_meminfo *mem; /* onboard mem info */ 445 int wc_cookie; 446 int blitter_may_be_busy; 447 int fifo_slots; /* free slots in FIFO (64 max) */ 448 449 int crt_on, lcd_on; 450 struct pci_dev *pdev; 451 struct fb_info *next; 452 int asleep; 453 int lock_blank; 454 455 u8 red[32]; /* see aty128fb_setcolreg */ 456 u8 green[64]; 457 u8 blue[32]; 458 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 459 }; 460 461 462 #define round_div(n, d) ((n+(d/2))/d) 463 464 static int aty128fb_check_var(struct fb_var_screeninfo *var, 465 struct fb_info *info); 466 static int aty128fb_set_par(struct fb_info *info); 467 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 468 u_int transp, struct fb_info *info); 469 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 470 struct fb_info *fb); 471 static int aty128fb_blank(int blank, struct fb_info *fb); 472 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 473 static int aty128fb_sync(struct fb_info *info); 474 475 /* 476 * Internal routines 477 */ 478 479 static int aty128_encode_var(struct fb_var_screeninfo *var, 480 const struct aty128fb_par *par); 481 static int aty128_decode_var(struct fb_var_screeninfo *var, 482 struct aty128fb_par *par); 483 static void aty128_timings(struct aty128fb_par *par); 484 static void aty128_init_engine(struct aty128fb_par *par); 485 static void aty128_reset_engine(const struct aty128fb_par *par); 486 static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 487 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 488 static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 489 static void wait_for_idle(struct aty128fb_par *par); 490 static u32 depth_to_dst(u32 depth); 491 492 #ifdef CONFIG_FB_ATY128_BACKLIGHT 493 static void aty128_bl_set_power(struct fb_info *info, int power); 494 #endif 495 496 #define BIOS_IN8(v) (readb(bios + (v))) 497 #define BIOS_IN16(v) (readb(bios + (v)) | \ 498 (readb(bios + (v) + 1) << 8)) 499 #define BIOS_IN32(v) (readb(bios + (v)) | \ 500 (readb(bios + (v) + 1) << 8) | \ 501 (readb(bios + (v) + 2) << 16) | \ 502 (readb(bios + (v) + 3) << 24)) 503 504 505 static const struct fb_ops aty128fb_ops = { 506 .owner = THIS_MODULE, 507 .fb_check_var = aty128fb_check_var, 508 .fb_set_par = aty128fb_set_par, 509 .fb_setcolreg = aty128fb_setcolreg, 510 .fb_pan_display = aty128fb_pan_display, 511 .fb_blank = aty128fb_blank, 512 .fb_ioctl = aty128fb_ioctl, 513 .fb_sync = aty128fb_sync, 514 .fb_fillrect = cfb_fillrect, 515 .fb_copyarea = cfb_copyarea, 516 .fb_imageblit = cfb_imageblit, 517 }; 518 519 /* 520 * Functions to read from/write to the mmio registers 521 * - endian conversions may possibly be avoided by 522 * using the other register aperture. TODO. 523 */ 524 static inline u32 _aty_ld_le32(volatile unsigned int regindex, 525 const struct aty128fb_par *par) 526 { 527 return readl (par->regbase + regindex); 528 } 529 530 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 531 const struct aty128fb_par *par) 532 { 533 writel (val, par->regbase + regindex); 534 } 535 536 static inline u8 _aty_ld_8(unsigned int regindex, 537 const struct aty128fb_par *par) 538 { 539 return readb (par->regbase + regindex); 540 } 541 542 static inline void _aty_st_8(unsigned int regindex, u8 val, 543 const struct aty128fb_par *par) 544 { 545 writeb (val, par->regbase + regindex); 546 } 547 548 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 549 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 550 #define aty_ld_8(regindex) _aty_ld_8(regindex, par) 551 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 552 553 /* 554 * Functions to read from/write to the pll registers 555 */ 556 557 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 558 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 559 560 561 static u32 _aty_ld_pll(unsigned int pll_index, 562 const struct aty128fb_par *par) 563 { 564 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 565 return aty_ld_le32(CLOCK_CNTL_DATA); 566 } 567 568 569 static void _aty_st_pll(unsigned int pll_index, u32 val, 570 const struct aty128fb_par *par) 571 { 572 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 573 aty_st_le32(CLOCK_CNTL_DATA, val); 574 } 575 576 577 /* return true when the PLL has completed an atomic update */ 578 static int aty_pll_readupdate(const struct aty128fb_par *par) 579 { 580 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 581 } 582 583 584 static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 585 { 586 unsigned long timeout = jiffies + HZ/100; // should be more than enough 587 int reset = 1; 588 589 while (time_before(jiffies, timeout)) 590 if (aty_pll_readupdate(par)) { 591 reset = 0; 592 break; 593 } 594 595 if (reset) /* reset engine?? */ 596 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 597 } 598 599 600 /* tell PLL to update */ 601 static void aty_pll_writeupdate(const struct aty128fb_par *par) 602 { 603 aty_pll_wait_readupdate(par); 604 605 aty_st_pll(PPLL_REF_DIV, 606 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 607 } 608 609 610 /* write to the scratch register to test r/w functionality */ 611 static int register_test(const struct aty128fb_par *par) 612 { 613 u32 val; 614 int flag = 0; 615 616 val = aty_ld_le32(BIOS_0_SCRATCH); 617 618 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 619 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 620 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 621 622 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 623 flag = 1; 624 } 625 626 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 627 return flag; 628 } 629 630 631 /* 632 * Accelerator engine functions 633 */ 634 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 635 { 636 int i; 637 638 for (;;) { 639 for (i = 0; i < 2000000; i++) { 640 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 641 if (par->fifo_slots >= entries) 642 return; 643 } 644 aty128_reset_engine(par); 645 } 646 } 647 648 649 static void wait_for_idle(struct aty128fb_par *par) 650 { 651 int i; 652 653 do_wait_for_fifo(64, par); 654 655 for (;;) { 656 for (i = 0; i < 2000000; i++) { 657 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 658 aty128_flush_pixel_cache(par); 659 par->blitter_may_be_busy = 0; 660 return; 661 } 662 } 663 aty128_reset_engine(par); 664 } 665 } 666 667 668 static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 669 { 670 if (par->fifo_slots < entries) 671 do_wait_for_fifo(64, par); 672 par->fifo_slots -= entries; 673 } 674 675 676 static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 677 { 678 int i; 679 u32 tmp; 680 681 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 682 tmp &= ~(0x00ff); 683 tmp |= 0x00ff; 684 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 685 686 for (i = 0; i < 2000000; i++) 687 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 688 break; 689 } 690 691 692 static void aty128_reset_engine(const struct aty128fb_par *par) 693 { 694 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 695 696 aty128_flush_pixel_cache(par); 697 698 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 699 mclk_cntl = aty_ld_pll(MCLK_CNTL); 700 701 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 702 703 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 704 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 705 aty_ld_le32(GEN_RESET_CNTL); 706 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 707 aty_ld_le32(GEN_RESET_CNTL); 708 709 aty_st_pll(MCLK_CNTL, mclk_cntl); 710 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 711 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 712 713 /* use old pio mode */ 714 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 715 716 DBG("engine reset"); 717 } 718 719 720 static void aty128_init_engine(struct aty128fb_par *par) 721 { 722 u32 pitch_value; 723 724 wait_for_idle(par); 725 726 /* 3D scaler not spoken here */ 727 wait_for_fifo(1, par); 728 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 729 730 aty128_reset_engine(par); 731 732 pitch_value = par->crtc.pitch; 733 if (par->crtc.bpp == 24) { 734 pitch_value = pitch_value * 3; 735 } 736 737 wait_for_fifo(4, par); 738 /* setup engine offset registers */ 739 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 740 741 /* setup engine pitch registers */ 742 aty_st_le32(DEFAULT_PITCH, pitch_value); 743 744 /* set the default scissor register to max dimensions */ 745 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 746 747 /* set the drawing controls registers */ 748 aty_st_le32(DP_GUI_MASTER_CNTL, 749 GMC_SRC_PITCH_OFFSET_DEFAULT | 750 GMC_DST_PITCH_OFFSET_DEFAULT | 751 GMC_SRC_CLIP_DEFAULT | 752 GMC_DST_CLIP_DEFAULT | 753 GMC_BRUSH_SOLIDCOLOR | 754 (depth_to_dst(par->crtc.depth) << 8) | 755 GMC_SRC_DSTCOLOR | 756 GMC_BYTE_ORDER_MSB_TO_LSB | 757 GMC_DP_CONVERSION_TEMP_6500 | 758 ROP3_PATCOPY | 759 GMC_DP_SRC_RECT | 760 GMC_3D_FCN_EN_CLR | 761 GMC_DST_CLR_CMP_FCN_CLEAR | 762 GMC_AUX_CLIP_CLEAR | 763 GMC_WRITE_MASK_SET); 764 765 wait_for_fifo(8, par); 766 /* clear the line drawing registers */ 767 aty_st_le32(DST_BRES_ERR, 0); 768 aty_st_le32(DST_BRES_INC, 0); 769 aty_st_le32(DST_BRES_DEC, 0); 770 771 /* set brush color registers */ 772 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 773 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 774 775 /* set source color registers */ 776 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 777 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 778 779 /* default write mask */ 780 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 781 782 /* Wait for all the writes to be completed before returning */ 783 wait_for_idle(par); 784 } 785 786 787 /* convert depth values to their register representation */ 788 static u32 depth_to_dst(u32 depth) 789 { 790 if (depth <= 8) 791 return DST_8BPP; 792 else if (depth <= 15) 793 return DST_15BPP; 794 else if (depth == 16) 795 return DST_16BPP; 796 else if (depth <= 24) 797 return DST_24BPP; 798 else if (depth <= 32) 799 return DST_32BPP; 800 801 return -EINVAL; 802 } 803 804 /* 805 * PLL informations retreival 806 */ 807 808 809 #ifndef __sparc__ 810 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, 811 struct pci_dev *dev) 812 { 813 u16 dptr; 814 u8 rom_type; 815 void __iomem *bios; 816 size_t rom_size; 817 818 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 819 unsigned int temp; 820 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 821 temp &= 0x00ffffffu; 822 temp |= 0x04 << 24; 823 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 824 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 825 826 bios = pci_map_rom(dev, &rom_size); 827 828 if (!bios) { 829 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 830 return NULL; 831 } 832 833 /* Very simple test to make sure it appeared */ 834 if (BIOS_IN16(0) != 0xaa55) { 835 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 836 " be 0xaa55\n", BIOS_IN16(0)); 837 goto failed; 838 } 839 840 /* Look for the PCI data to check the ROM type */ 841 dptr = BIOS_IN16(0x18); 842 843 /* Check the PCI data signature. If it's wrong, we still assume a normal 844 * x86 ROM for now, until I've verified this works everywhere. 845 * The goal here is more to phase out Open Firmware images. 846 * 847 * Currently, we only look at the first PCI data, we could iteratre and 848 * deal with them all, and we should use fb_bios_start relative to start 849 * of image and not relative start of ROM, but so far, I never found a 850 * dual-image ATI card. 851 * 852 * typedef struct { 853 * u32 signature; + 0x00 854 * u16 vendor; + 0x04 855 * u16 device; + 0x06 856 * u16 reserved_1; + 0x08 857 * u16 dlen; + 0x0a 858 * u8 drevision; + 0x0c 859 * u8 class_hi; + 0x0d 860 * u16 class_lo; + 0x0e 861 * u16 ilen; + 0x10 862 * u16 irevision; + 0x12 863 * u8 type; + 0x14 864 * u8 indicator; + 0x15 865 * u16 reserved_2; + 0x16 866 * } pci_data_t; 867 */ 868 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 869 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 870 BIOS_IN32(dptr)); 871 goto anyway; 872 } 873 rom_type = BIOS_IN8(dptr + 0x14); 874 switch(rom_type) { 875 case 0: 876 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 877 break; 878 case 1: 879 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 880 goto failed; 881 case 2: 882 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 883 goto failed; 884 default: 885 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", 886 rom_type); 887 goto failed; 888 } 889 anyway: 890 return bios; 891 892 failed: 893 pci_unmap_rom(dev, bios); 894 return NULL; 895 } 896 897 static void aty128_get_pllinfo(struct aty128fb_par *par, 898 unsigned char __iomem *bios) 899 { 900 unsigned int bios_hdr; 901 unsigned int bios_pll; 902 903 bios_hdr = BIOS_IN16(0x48); 904 bios_pll = BIOS_IN16(bios_hdr + 0x30); 905 906 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 907 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 908 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 909 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 910 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 911 912 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 913 par->constants.ppll_max, par->constants.ppll_min, 914 par->constants.xclk, par->constants.ref_divider, 915 par->constants.ref_clk); 916 917 } 918 919 #ifdef CONFIG_X86 920 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) 921 { 922 /* I simplified this code as we used to miss the signatures in 923 * a lot of case. It's now closer to XFree, we just don't check 924 * for signatures at all... Something better will have to be done 925 * if we end up having conflicts 926 */ 927 u32 segstart; 928 unsigned char __iomem *rom_base = NULL; 929 930 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 931 rom_base = ioremap(segstart, 0x10000); 932 if (rom_base == NULL) 933 return NULL; 934 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 935 break; 936 iounmap(rom_base); 937 rom_base = NULL; 938 } 939 return rom_base; 940 } 941 #endif 942 #endif /* ndef(__sparc__) */ 943 944 /* fill in known card constants if pll_block is not available */ 945 static void aty128_timings(struct aty128fb_par *par) 946 { 947 #ifdef CONFIG_PPC 948 /* instead of a table lookup, assume OF has properly 949 * setup the PLL registers and use their values 950 * to set the XCLK values and reference divider values */ 951 952 u32 x_mpll_ref_fb_div; 953 u32 xclk_cntl; 954 u32 Nx, M; 955 static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 956 #endif 957 958 if (!par->constants.ref_clk) 959 par->constants.ref_clk = 2950; 960 961 #ifdef CONFIG_PPC 962 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 963 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 964 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 965 M = x_mpll_ref_fb_div & 0x0000ff; 966 967 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 968 (M * PostDivSet[xclk_cntl])); 969 970 par->constants.ref_divider = 971 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 972 #endif 973 974 if (!par->constants.ref_divider) { 975 par->constants.ref_divider = 0x3b; 976 977 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 978 aty_pll_writeupdate(par); 979 } 980 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 981 aty_pll_writeupdate(par); 982 983 /* from documentation */ 984 if (!par->constants.ppll_min) 985 par->constants.ppll_min = 12500; 986 if (!par->constants.ppll_max) 987 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 988 if (!par->constants.xclk) 989 par->constants.xclk = 0x1d4d; /* same as mclk */ 990 991 par->constants.fifo_width = 128; 992 par->constants.fifo_depth = 32; 993 994 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 995 case 0: 996 par->mem = &sdr_128; 997 break; 998 case 1: 999 par->mem = &sdr_sgram; 1000 break; 1001 case 2: 1002 par->mem = &ddr_sgram; 1003 break; 1004 default: 1005 par->mem = &sdr_sgram; 1006 } 1007 } 1008 1009 1010 1011 /* 1012 * CRTC programming 1013 */ 1014 1015 /* Program the CRTC registers */ 1016 static void aty128_set_crtc(const struct aty128_crtc *crtc, 1017 const struct aty128fb_par *par) 1018 { 1019 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 1020 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 1021 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1022 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 1023 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1024 aty_st_le32(CRTC_PITCH, crtc->pitch); 1025 aty_st_le32(CRTC_OFFSET, crtc->offset); 1026 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 1027 /* Disable ATOMIC updating. Is this the right place? */ 1028 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 1029 } 1030 1031 1032 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 1033 struct aty128_crtc *crtc, 1034 const struct aty128fb_par *par) 1035 { 1036 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1037 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1038 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1039 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1040 u32 depth, bytpp; 1041 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1042 1043 /* input */ 1044 xres = var->xres; 1045 yres = var->yres; 1046 vxres = var->xres_virtual; 1047 vyres = var->yres_virtual; 1048 xoffset = var->xoffset; 1049 yoffset = var->yoffset; 1050 bpp = var->bits_per_pixel; 1051 left = var->left_margin; 1052 right = var->right_margin; 1053 upper = var->upper_margin; 1054 lower = var->lower_margin; 1055 hslen = var->hsync_len; 1056 vslen = var->vsync_len; 1057 sync = var->sync; 1058 vmode = var->vmode; 1059 1060 if (bpp != 16) 1061 depth = bpp; 1062 else 1063 depth = (var->green.length == 6) ? 16 : 15; 1064 1065 /* check for mode eligibility 1066 * accept only non interlaced modes */ 1067 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1068 return -EINVAL; 1069 1070 /* convert (and round up) and validate */ 1071 xres = (xres + 7) & ~7; 1072 xoffset = (xoffset + 7) & ~7; 1073 1074 if (vxres < xres + xoffset) 1075 vxres = xres + xoffset; 1076 1077 if (vyres < yres + yoffset) 1078 vyres = yres + yoffset; 1079 1080 /* convert depth into ATI register depth */ 1081 dst = depth_to_dst(depth); 1082 1083 if (dst == -EINVAL) { 1084 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1085 return -EINVAL; 1086 } 1087 1088 /* convert register depth to bytes per pixel */ 1089 bytpp = mode_bytpp[dst]; 1090 1091 /* make sure there is enough video ram for the mode */ 1092 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1093 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1094 return -EINVAL; 1095 } 1096 1097 h_disp = (xres >> 3) - 1; 1098 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1099 1100 v_disp = yres - 1; 1101 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1102 1103 /* check to make sure h_total and v_total are in range */ 1104 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1105 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1106 return -EINVAL; 1107 } 1108 1109 h_sync_wid = (hslen + 7) >> 3; 1110 if (h_sync_wid == 0) 1111 h_sync_wid = 1; 1112 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1113 h_sync_wid = 0x3f; 1114 1115 h_sync_strt = (h_disp << 3) + right; 1116 1117 v_sync_wid = vslen; 1118 if (v_sync_wid == 0) 1119 v_sync_wid = 1; 1120 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1121 v_sync_wid = 0x1f; 1122 1123 v_sync_strt = v_disp + lower; 1124 1125 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1126 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1127 1128 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1129 1130 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1131 1132 crtc->h_total = h_total | (h_disp << 16); 1133 crtc->v_total = v_total | (v_disp << 16); 1134 1135 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1136 (h_sync_pol << 23); 1137 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1138 (v_sync_pol << 23); 1139 1140 crtc->pitch = vxres >> 3; 1141 1142 crtc->offset = 0; 1143 1144 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1145 crtc->offset_cntl = 0x00010000; 1146 else 1147 crtc->offset_cntl = 0; 1148 1149 crtc->vxres = vxres; 1150 crtc->vyres = vyres; 1151 crtc->xoffset = xoffset; 1152 crtc->yoffset = yoffset; 1153 crtc->depth = depth; 1154 crtc->bpp = bpp; 1155 1156 return 0; 1157 } 1158 1159 1160 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1161 { 1162 1163 /* fill in pixel info */ 1164 var->red.msb_right = 0; 1165 var->green.msb_right = 0; 1166 var->blue.offset = 0; 1167 var->blue.msb_right = 0; 1168 var->transp.offset = 0; 1169 var->transp.length = 0; 1170 var->transp.msb_right = 0; 1171 switch (pix_width) { 1172 case CRTC_PIX_WIDTH_8BPP: 1173 var->bits_per_pixel = 8; 1174 var->red.offset = 0; 1175 var->red.length = 8; 1176 var->green.offset = 0; 1177 var->green.length = 8; 1178 var->blue.length = 8; 1179 break; 1180 case CRTC_PIX_WIDTH_15BPP: 1181 var->bits_per_pixel = 16; 1182 var->red.offset = 10; 1183 var->red.length = 5; 1184 var->green.offset = 5; 1185 var->green.length = 5; 1186 var->blue.length = 5; 1187 break; 1188 case CRTC_PIX_WIDTH_16BPP: 1189 var->bits_per_pixel = 16; 1190 var->red.offset = 11; 1191 var->red.length = 5; 1192 var->green.offset = 5; 1193 var->green.length = 6; 1194 var->blue.length = 5; 1195 break; 1196 case CRTC_PIX_WIDTH_24BPP: 1197 var->bits_per_pixel = 24; 1198 var->red.offset = 16; 1199 var->red.length = 8; 1200 var->green.offset = 8; 1201 var->green.length = 8; 1202 var->blue.length = 8; 1203 break; 1204 case CRTC_PIX_WIDTH_32BPP: 1205 var->bits_per_pixel = 32; 1206 var->red.offset = 16; 1207 var->red.length = 8; 1208 var->green.offset = 8; 1209 var->green.length = 8; 1210 var->blue.length = 8; 1211 var->transp.offset = 24; 1212 var->transp.length = 8; 1213 break; 1214 default: 1215 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1216 return -EINVAL; 1217 } 1218 1219 return 0; 1220 } 1221 1222 1223 static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1224 struct fb_var_screeninfo *var) 1225 { 1226 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1227 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1228 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1229 u32 pix_width; 1230 1231 /* fun with masking */ 1232 h_total = crtc->h_total & 0x1ff; 1233 h_disp = (crtc->h_total >> 16) & 0xff; 1234 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1235 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1236 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1237 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1238 v_total = crtc->v_total & 0x7ff; 1239 v_disp = (crtc->v_total >> 16) & 0x7ff; 1240 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1241 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1242 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1243 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1244 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1245 1246 /* do conversions */ 1247 xres = (h_disp + 1) << 3; 1248 yres = v_disp + 1; 1249 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1250 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1251 hslen = h_sync_wid << 3; 1252 upper = v_total - v_sync_strt - v_sync_wid; 1253 lower = v_sync_strt - v_disp; 1254 vslen = v_sync_wid; 1255 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1256 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1257 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1258 1259 aty128_pix_width_to_var(pix_width, var); 1260 1261 var->xres = xres; 1262 var->yres = yres; 1263 var->xres_virtual = crtc->vxres; 1264 var->yres_virtual = crtc->vyres; 1265 var->xoffset = crtc->xoffset; 1266 var->yoffset = crtc->yoffset; 1267 var->left_margin = left; 1268 var->right_margin = right; 1269 var->upper_margin = upper; 1270 var->lower_margin = lower; 1271 var->hsync_len = hslen; 1272 var->vsync_len = vslen; 1273 var->sync = sync; 1274 var->vmode = FB_VMODE_NONINTERLACED; 1275 1276 return 0; 1277 } 1278 1279 static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1280 { 1281 if (on) { 1282 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | 1283 CRT_CRTC_ON); 1284 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | 1285 DAC_PALETTE2_SNOOP_EN)); 1286 } else 1287 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & 1288 ~CRT_CRTC_ON); 1289 } 1290 1291 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1292 { 1293 u32 reg; 1294 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1295 struct fb_info *info = pci_get_drvdata(par->pdev); 1296 #endif 1297 1298 if (on) { 1299 reg = aty_ld_le32(LVDS_GEN_CNTL); 1300 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1301 reg &= ~LVDS_DISPLAY_DIS; 1302 aty_st_le32(LVDS_GEN_CNTL, reg); 1303 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1304 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1305 #endif 1306 } else { 1307 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1308 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1309 #endif 1310 reg = aty_ld_le32(LVDS_GEN_CNTL); 1311 reg |= LVDS_DISPLAY_DIS; 1312 aty_st_le32(LVDS_GEN_CNTL, reg); 1313 mdelay(100); 1314 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1315 aty_st_le32(LVDS_GEN_CNTL, reg); 1316 } 1317 } 1318 1319 static void aty128_set_pll(struct aty128_pll *pll, 1320 const struct aty128fb_par *par) 1321 { 1322 u32 div3; 1323 1324 /* register values for post dividers */ 1325 static const unsigned char post_conv[] = { 1326 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 1327 }; 1328 1329 /* select PPLL_DIV_3 */ 1330 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1331 1332 /* reset PLL */ 1333 aty_st_pll(PPLL_CNTL, 1334 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1335 1336 /* write the reference divider */ 1337 aty_pll_wait_readupdate(par); 1338 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1339 aty_pll_writeupdate(par); 1340 1341 div3 = aty_ld_pll(PPLL_DIV_3); 1342 div3 &= ~PPLL_FB3_DIV_MASK; 1343 div3 |= pll->feedback_divider; 1344 div3 &= ~PPLL_POST3_DIV_MASK; 1345 div3 |= post_conv[pll->post_divider] << 16; 1346 1347 /* write feedback and post dividers */ 1348 aty_pll_wait_readupdate(par); 1349 aty_st_pll(PPLL_DIV_3, div3); 1350 aty_pll_writeupdate(par); 1351 1352 aty_pll_wait_readupdate(par); 1353 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1354 aty_pll_writeupdate(par); 1355 1356 /* clear the reset, just in case */ 1357 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1358 } 1359 1360 1361 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1362 const struct aty128fb_par *par) 1363 { 1364 const struct aty128_constants c = par->constants; 1365 static const unsigned char post_dividers[] = { 1, 2, 4, 8, 3, 6, 12 }; 1366 u32 output_freq; 1367 u32 vclk; /* in .01 MHz */ 1368 int i = 0; 1369 u32 n, d; 1370 1371 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1372 1373 /* adjust pixel clock if necessary */ 1374 if (vclk > c.ppll_max) 1375 vclk = c.ppll_max; 1376 if (vclk * 12 < c.ppll_min) 1377 vclk = c.ppll_min/12; 1378 1379 /* now, find an acceptable divider */ 1380 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { 1381 output_freq = post_dividers[i] * vclk; 1382 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1383 pll->post_divider = post_dividers[i]; 1384 break; 1385 } 1386 } 1387 1388 if (i == ARRAY_SIZE(post_dividers)) 1389 return -EINVAL; 1390 1391 /* calculate feedback divider */ 1392 n = c.ref_divider * output_freq; 1393 d = c.ref_clk; 1394 1395 pll->feedback_divider = round_div(n, d); 1396 pll->vclk = vclk; 1397 1398 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1399 "vclk_per: %d\n", pll->post_divider, 1400 pll->feedback_divider, vclk, output_freq, 1401 c.ref_divider, period_in_ps); 1402 1403 return 0; 1404 } 1405 1406 1407 static int aty128_pll_to_var(const struct aty128_pll *pll, 1408 struct fb_var_screeninfo *var) 1409 { 1410 var->pixclock = 100000000 / pll->vclk; 1411 1412 return 0; 1413 } 1414 1415 1416 static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1417 const struct aty128fb_par *par) 1418 { 1419 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1420 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1421 } 1422 1423 1424 static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1425 const struct aty128_pll *pll, 1426 u32 depth, 1427 const struct aty128fb_par *par) 1428 { 1429 const struct aty128_meminfo *m = par->mem; 1430 u32 xclk = par->constants.xclk; 1431 u32 fifo_width = par->constants.fifo_width; 1432 u32 fifo_depth = par->constants.fifo_depth; 1433 s32 x, b, p, ron, roff; 1434 u32 n, d, bpp; 1435 1436 /* round up to multiple of 8 */ 1437 bpp = (depth+7) & ~7; 1438 1439 n = xclk * fifo_width; 1440 d = pll->vclk * bpp; 1441 x = round_div(n, d); 1442 1443 ron = 4 * m->MB + 1444 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1445 2 * m->Trp + 1446 m->Twr + 1447 m->CL + 1448 m->Tr2w + 1449 x; 1450 1451 DBG("x %x\n", x); 1452 1453 b = 0; 1454 while (x) { 1455 x >>= 1; 1456 b++; 1457 } 1458 p = b + 1; 1459 1460 ron <<= (11 - p); 1461 1462 n <<= (11 - p); 1463 x = round_div(n, d); 1464 roff = x * (fifo_depth - 4); 1465 1466 if ((ron + m->Rloop) >= roff) { 1467 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1468 return -EINVAL; 1469 } 1470 1471 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1472 p, m->Rloop, x, ron, roff); 1473 1474 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1475 dsp->dda_on_off = ron << 16 | roff; 1476 1477 return 0; 1478 } 1479 1480 1481 /* 1482 * This actually sets the video mode. 1483 */ 1484 static int aty128fb_set_par(struct fb_info *info) 1485 { 1486 struct aty128fb_par *par = info->par; 1487 u32 config; 1488 int err; 1489 1490 if ((err = aty128_decode_var(&info->var, par)) != 0) 1491 return err; 1492 1493 if (par->blitter_may_be_busy) 1494 wait_for_idle(par); 1495 1496 /* clear all registers that may interfere with mode setting */ 1497 aty_st_le32(OVR_CLR, 0); 1498 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1499 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1500 aty_st_le32(OV0_SCALE_CNTL, 0); 1501 aty_st_le32(MPP_TB_CONFIG, 0); 1502 aty_st_le32(MPP_GP_CONFIG, 0); 1503 aty_st_le32(SUBPIC_CNTL, 0); 1504 aty_st_le32(VIPH_CONTROL, 0); 1505 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1506 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1507 aty_st_le32(CAP0_TRIG_CNTL, 0); 1508 aty_st_le32(CAP1_TRIG_CNTL, 0); 1509 1510 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1511 1512 aty128_set_crtc(&par->crtc, par); 1513 aty128_set_pll(&par->pll, par); 1514 aty128_set_fifo(&par->fifo_reg, par); 1515 1516 config = aty_ld_le32(CNFG_CNTL) & ~3; 1517 1518 #if defined(__BIG_ENDIAN) 1519 if (par->crtc.bpp == 32) 1520 config |= 2; /* make aperture do 32 bit swapping */ 1521 else if (par->crtc.bpp == 16) 1522 config |= 1; /* make aperture do 16 bit swapping */ 1523 #endif 1524 1525 aty_st_le32(CNFG_CNTL, config); 1526 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1527 1528 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1529 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1530 : FB_VISUAL_DIRECTCOLOR; 1531 1532 if (par->chip_gen == rage_M3) { 1533 aty128_set_crt_enable(par, par->crt_on); 1534 aty128_set_lcd_enable(par, par->lcd_on); 1535 } 1536 if (par->accel_flags & FB_ACCELF_TEXT) 1537 aty128_init_engine(par); 1538 1539 #ifdef CONFIG_BOOTX_TEXT 1540 btext_update_display(info->fix.smem_start, 1541 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1542 ((par->crtc.v_total>>16) & 0x7ff)+1, 1543 par->crtc.bpp, 1544 par->crtc.vxres*par->crtc.bpp/8); 1545 #endif /* CONFIG_BOOTX_TEXT */ 1546 1547 return 0; 1548 } 1549 1550 /* 1551 * encode/decode the User Defined Part of the Display 1552 */ 1553 1554 static int aty128_decode_var(struct fb_var_screeninfo *var, 1555 struct aty128fb_par *par) 1556 { 1557 int err; 1558 struct aty128_crtc crtc; 1559 struct aty128_pll pll; 1560 struct aty128_ddafifo fifo_reg; 1561 1562 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1563 return err; 1564 1565 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1566 return err; 1567 1568 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1569 return err; 1570 1571 par->crtc = crtc; 1572 par->pll = pll; 1573 par->fifo_reg = fifo_reg; 1574 par->accel_flags = var->accel_flags; 1575 1576 return 0; 1577 } 1578 1579 1580 static int aty128_encode_var(struct fb_var_screeninfo *var, 1581 const struct aty128fb_par *par) 1582 { 1583 int err; 1584 1585 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1586 return err; 1587 1588 if ((err = aty128_pll_to_var(&par->pll, var))) 1589 return err; 1590 1591 var->nonstd = 0; 1592 var->activate = 0; 1593 1594 var->height = -1; 1595 var->width = -1; 1596 var->accel_flags = par->accel_flags; 1597 1598 return 0; 1599 } 1600 1601 1602 static int aty128fb_check_var(struct fb_var_screeninfo *var, 1603 struct fb_info *info) 1604 { 1605 struct aty128fb_par par; 1606 int err; 1607 1608 par = *(struct aty128fb_par *)info->par; 1609 if ((err = aty128_decode_var(var, &par)) != 0) 1610 return err; 1611 aty128_encode_var(var, &par); 1612 return 0; 1613 } 1614 1615 1616 /* 1617 * Pan or Wrap the Display 1618 */ 1619 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 1620 struct fb_info *fb) 1621 { 1622 struct aty128fb_par *par = fb->par; 1623 u32 xoffset, yoffset; 1624 u32 offset; 1625 u32 xres, yres; 1626 1627 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1628 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1629 1630 xoffset = (var->xoffset +7) & ~7; 1631 yoffset = var->yoffset; 1632 1633 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1634 return -EINVAL; 1635 1636 par->crtc.xoffset = xoffset; 1637 par->crtc.yoffset = yoffset; 1638 1639 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) 1640 & ~7; 1641 1642 if (par->crtc.bpp == 24) 1643 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1644 1645 aty_st_le32(CRTC_OFFSET, offset); 1646 1647 return 0; 1648 } 1649 1650 1651 /* 1652 * Helper function to store a single palette register 1653 */ 1654 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1655 struct aty128fb_par *par) 1656 { 1657 if (par->chip_gen == rage_M3) { 1658 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & 1659 ~DAC_PALETTE_ACCESS_CNTL); 1660 } 1661 1662 aty_st_8(PALETTE_INDEX, regno); 1663 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1664 } 1665 1666 static int aty128fb_sync(struct fb_info *info) 1667 { 1668 struct aty128fb_par *par = info->par; 1669 1670 if (par->blitter_may_be_busy) 1671 wait_for_idle(par); 1672 return 0; 1673 } 1674 1675 #ifndef MODULE 1676 static int aty128fb_setup(char *options) 1677 { 1678 char *this_opt; 1679 1680 if (!options || !*options) 1681 return 0; 1682 1683 while ((this_opt = strsep(&options, ",")) != NULL) { 1684 if (!strncmp(this_opt, "lcd:", 4)) { 1685 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1686 continue; 1687 } else if (!strncmp(this_opt, "crt:", 4)) { 1688 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1689 continue; 1690 } else if (!strncmp(this_opt, "backlight:", 10)) { 1691 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1692 backlight = simple_strtoul(this_opt+10, NULL, 0); 1693 #endif 1694 continue; 1695 } 1696 if(!strncmp(this_opt, "nomtrr", 6)) { 1697 mtrr = false; 1698 continue; 1699 } 1700 #ifdef CONFIG_PPC_PMAC 1701 /* vmode and cmode deprecated */ 1702 if (!strncmp(this_opt, "vmode:", 6)) { 1703 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1704 if (vmode > 0 && vmode <= VMODE_MAX) 1705 default_vmode = vmode; 1706 continue; 1707 } else if (!strncmp(this_opt, "cmode:", 6)) { 1708 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1709 switch (cmode) { 1710 case 0: 1711 case 8: 1712 default_cmode = CMODE_8; 1713 break; 1714 case 15: 1715 case 16: 1716 default_cmode = CMODE_16; 1717 break; 1718 case 24: 1719 case 32: 1720 default_cmode = CMODE_32; 1721 break; 1722 } 1723 continue; 1724 } 1725 #endif /* CONFIG_PPC_PMAC */ 1726 mode_option = this_opt; 1727 } 1728 return 0; 1729 } 1730 #endif /* MODULE */ 1731 1732 /* Backlight */ 1733 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1734 #define MAX_LEVEL 0xFF 1735 1736 static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1737 int level) 1738 { 1739 struct fb_info *info = pci_get_drvdata(par->pdev); 1740 int atylevel; 1741 1742 /* Get and convert the value */ 1743 /* No locking of bl_curve since we read a single value */ 1744 atylevel = MAX_LEVEL - 1745 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1746 1747 if (atylevel < 0) 1748 atylevel = 0; 1749 else if (atylevel > MAX_LEVEL) 1750 atylevel = MAX_LEVEL; 1751 1752 return atylevel; 1753 } 1754 1755 /* We turn off the LCD completely instead of just dimming the backlight. 1756 * This provides greater power saving and the display is useless without 1757 * backlight anyway 1758 */ 1759 #define BACKLIGHT_LVDS_OFF 1760 /* That one prevents proper CRT output with LCD off */ 1761 #undef BACKLIGHT_DAC_OFF 1762 1763 static int aty128_bl_update_status(struct backlight_device *bd) 1764 { 1765 struct aty128fb_par *par = bl_get_data(bd); 1766 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1767 int level; 1768 1769 if (bd->props.power != FB_BLANK_UNBLANK || 1770 bd->props.fb_blank != FB_BLANK_UNBLANK || 1771 !par->lcd_on) 1772 level = 0; 1773 else 1774 level = bd->props.brightness; 1775 1776 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1777 if (level > 0) { 1778 reg |= LVDS_DIGION; 1779 if (!(reg & LVDS_ON)) { 1780 reg &= ~LVDS_BLON; 1781 aty_st_le32(LVDS_GEN_CNTL, reg); 1782 aty_ld_le32(LVDS_GEN_CNTL); 1783 mdelay(10); 1784 reg |= LVDS_BLON; 1785 aty_st_le32(LVDS_GEN_CNTL, reg); 1786 } 1787 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1788 reg |= (aty128_bl_get_level_brightness(par, level) << 1789 LVDS_BL_MOD_LEVEL_SHIFT); 1790 #ifdef BACKLIGHT_LVDS_OFF 1791 reg |= LVDS_ON | LVDS_EN; 1792 reg &= ~LVDS_DISPLAY_DIS; 1793 #endif 1794 aty_st_le32(LVDS_GEN_CNTL, reg); 1795 #ifdef BACKLIGHT_DAC_OFF 1796 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1797 #endif 1798 } else { 1799 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1800 reg |= (aty128_bl_get_level_brightness(par, 0) << 1801 LVDS_BL_MOD_LEVEL_SHIFT); 1802 #ifdef BACKLIGHT_LVDS_OFF 1803 reg |= LVDS_DISPLAY_DIS; 1804 aty_st_le32(LVDS_GEN_CNTL, reg); 1805 aty_ld_le32(LVDS_GEN_CNTL); 1806 udelay(10); 1807 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1808 #endif 1809 aty_st_le32(LVDS_GEN_CNTL, reg); 1810 #ifdef BACKLIGHT_DAC_OFF 1811 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1812 #endif 1813 } 1814 1815 return 0; 1816 } 1817 1818 static const struct backlight_ops aty128_bl_data = { 1819 .update_status = aty128_bl_update_status, 1820 }; 1821 1822 static void aty128_bl_set_power(struct fb_info *info, int power) 1823 { 1824 if (info->bl_dev) { 1825 info->bl_dev->props.power = power; 1826 backlight_update_status(info->bl_dev); 1827 } 1828 } 1829 1830 static void aty128_bl_init(struct aty128fb_par *par) 1831 { 1832 struct backlight_properties props; 1833 struct fb_info *info = pci_get_drvdata(par->pdev); 1834 struct backlight_device *bd; 1835 char name[12]; 1836 1837 /* Could be extended to Rage128Pro LVDS output too */ 1838 if (par->chip_gen != rage_M3) 1839 return; 1840 1841 #ifdef CONFIG_PMAC_BACKLIGHT 1842 if (!pmac_has_backlight_type("ati")) 1843 return; 1844 #endif 1845 1846 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1847 1848 memset(&props, 0, sizeof(struct backlight_properties)); 1849 props.type = BACKLIGHT_RAW; 1850 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1851 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, 1852 &props); 1853 if (IS_ERR(bd)) { 1854 info->bl_dev = NULL; 1855 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1856 goto error; 1857 } 1858 1859 info->bl_dev = bd; 1860 fb_bl_default_curve(info, 0, 1861 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1862 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1863 1864 bd->props.brightness = bd->props.max_brightness; 1865 bd->props.power = FB_BLANK_UNBLANK; 1866 backlight_update_status(bd); 1867 1868 printk("aty128: Backlight initialized (%s)\n", name); 1869 1870 return; 1871 1872 error: 1873 return; 1874 } 1875 1876 static void aty128_bl_exit(struct backlight_device *bd) 1877 { 1878 backlight_device_unregister(bd); 1879 printk("aty128: Backlight unloaded\n"); 1880 } 1881 #endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1882 1883 /* 1884 * Initialisation 1885 */ 1886 1887 #ifdef CONFIG_PPC_PMAC__disabled 1888 static void aty128_early_resume(void *data) 1889 { 1890 struct aty128fb_par *par = data; 1891 1892 if (!console_trylock()) 1893 return; 1894 pci_restore_state(par->pdev); 1895 aty128_do_resume(par->pdev); 1896 console_unlock(); 1897 } 1898 #endif /* CONFIG_PPC_PMAC */ 1899 1900 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1901 { 1902 struct fb_info *info = pci_get_drvdata(pdev); 1903 struct aty128fb_par *par = info->par; 1904 struct fb_var_screeninfo var; 1905 char video_card[50]; 1906 u8 chip_rev; 1907 u32 dac; 1908 1909 /* Get the chip revision */ 1910 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; 1911 1912 strcpy(video_card, "Rage128 XX "); 1913 video_card[8] = ent->device >> 8; 1914 video_card[9] = ent->device & 0xFF; 1915 1916 /* range check to make sure */ 1917 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1918 strlcat(video_card, r128_family[ent->driver_data], 1919 sizeof(video_card)); 1920 1921 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1922 1923 if (par->vram_size % (1024 * 1024) == 0) 1924 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1925 else 1926 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1927 1928 par->chip_gen = ent->driver_data; 1929 1930 /* fill in info */ 1931 info->fbops = &aty128fb_ops; 1932 info->flags = FBINFO_FLAG_DEFAULT; 1933 1934 par->lcd_on = default_lcd_on; 1935 par->crt_on = default_crt_on; 1936 1937 var = default_var; 1938 #ifdef CONFIG_PPC_PMAC 1939 if (machine_is(powermac)) { 1940 /* Indicate sleep capability */ 1941 if (par->chip_gen == rage_M3) { 1942 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1943 #if 0 /* Disable the early video resume hack for now as it's causing problems, 1944 * among others we now rely on the PCI core restoring the config space 1945 * for us, which isn't the case with that hack, and that code path causes 1946 * various things to be called with interrupts off while they shouldn't. 1947 * I'm leaving the code in as it can be useful for debugging purposes 1948 */ 1949 pmac_set_early_video_resume(aty128_early_resume, par); 1950 #endif 1951 } 1952 1953 /* Find default mode */ 1954 if (mode_option) { 1955 if (!mac_find_mode(&var, info, mode_option, 8)) 1956 var = default_var; 1957 } else { 1958 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1959 default_vmode = VMODE_1024_768_60; 1960 1961 /* iMacs need that resolution 1962 * PowerMac2,1 first r128 iMacs 1963 * PowerMac2,2 summer 2000 iMacs 1964 * PowerMac4,1 january 2001 iMacs "flower power" 1965 */ 1966 if (of_machine_is_compatible("PowerMac2,1") || 1967 of_machine_is_compatible("PowerMac2,2") || 1968 of_machine_is_compatible("PowerMac4,1")) 1969 default_vmode = VMODE_1024_768_75; 1970 1971 /* iBook SE */ 1972 if (of_machine_is_compatible("PowerBook2,2")) 1973 default_vmode = VMODE_800_600_60; 1974 1975 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1976 if (of_machine_is_compatible("PowerBook3,1") || 1977 of_machine_is_compatible("PowerBook4,1")) 1978 default_vmode = VMODE_1024_768_60; 1979 1980 /* PowerBook Titanium */ 1981 if (of_machine_is_compatible("PowerBook3,2")) 1982 default_vmode = VMODE_1152_768_60; 1983 1984 if (default_cmode > 16) 1985 default_cmode = CMODE_32; 1986 else if (default_cmode > 8) 1987 default_cmode = CMODE_16; 1988 else 1989 default_cmode = CMODE_8; 1990 1991 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1992 var = default_var; 1993 } 1994 } else 1995 #endif /* CONFIG_PPC_PMAC */ 1996 { 1997 if (mode_option) 1998 if (fb_find_mode(&var, info, mode_option, NULL, 1999 0, &defaultmode, 8) == 0) 2000 var = default_var; 2001 } 2002 2003 var.accel_flags &= ~FB_ACCELF_TEXT; 2004 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ 2005 2006 if (aty128fb_check_var(&var, info)) { 2007 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 2008 return 0; 2009 } 2010 2011 /* setup the DAC the way we like it */ 2012 dac = aty_ld_le32(DAC_CNTL); 2013 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 2014 dac |= DAC_MASK; 2015 if (par->chip_gen == rage_M3) 2016 dac |= DAC_PALETTE2_SNOOP_EN; 2017 aty_st_le32(DAC_CNTL, dac); 2018 2019 /* turn off bus mastering, just in case */ 2020 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 2021 2022 info->var = var; 2023 fb_alloc_cmap(&info->cmap, 256, 0); 2024 2025 var.activate = FB_ACTIVATE_NOW; 2026 2027 aty128_init_engine(par); 2028 2029 par->pdev = pdev; 2030 par->asleep = 0; 2031 par->lock_blank = 0; 2032 2033 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2034 if (backlight) 2035 aty128_bl_init(par); 2036 #endif 2037 2038 if (register_framebuffer(info) < 0) 2039 return 0; 2040 2041 fb_info(info, "%s frame buffer device on %s\n", 2042 info->fix.id, video_card); 2043 2044 return 1; /* success! */ 2045 } 2046 2047 #ifdef CONFIG_PCI 2048 /* register a card ++ajoshi */ 2049 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2050 { 2051 unsigned long fb_addr, reg_addr; 2052 struct aty128fb_par *par; 2053 struct fb_info *info; 2054 int err; 2055 #ifndef __sparc__ 2056 void __iomem *bios = NULL; 2057 #endif 2058 2059 err = aperture_remove_conflicting_pci_devices(pdev, "aty128fb"); 2060 if (err) 2061 return err; 2062 2063 /* Enable device in PCI config */ 2064 if ((err = pci_enable_device(pdev))) { 2065 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2066 err); 2067 return -ENODEV; 2068 } 2069 2070 fb_addr = pci_resource_start(pdev, 0); 2071 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2072 "aty128fb FB")) { 2073 printk(KERN_ERR "aty128fb: cannot reserve frame " 2074 "buffer memory\n"); 2075 return -ENODEV; 2076 } 2077 2078 reg_addr = pci_resource_start(pdev, 2); 2079 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2080 "aty128fb MMIO")) { 2081 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2082 goto err_free_fb; 2083 } 2084 2085 /* We have the resources. Now virtualize them */ 2086 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2087 if (!info) 2088 goto err_free_mmio; 2089 2090 par = info->par; 2091 2092 info->pseudo_palette = par->pseudo_palette; 2093 2094 /* Virtualize mmio region */ 2095 info->fix.mmio_start = reg_addr; 2096 par->regbase = pci_ioremap_bar(pdev, 2); 2097 if (!par->regbase) 2098 goto err_free_info; 2099 2100 /* Grab memory size from the card */ 2101 // How does this relate to the resource length from the PCI hardware? 2102 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; 2103 2104 /* Virtualize the framebuffer */ 2105 info->screen_base = ioremap_wc(fb_addr, par->vram_size); 2106 if (!info->screen_base) 2107 goto err_unmap_out; 2108 2109 /* Set up info->fix */ 2110 info->fix = aty128fb_fix; 2111 info->fix.smem_start = fb_addr; 2112 info->fix.smem_len = par->vram_size; 2113 info->fix.mmio_start = reg_addr; 2114 2115 /* If we can't test scratch registers, something is seriously wrong */ 2116 if (!register_test(par)) { 2117 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2118 goto err_out; 2119 } 2120 2121 #ifndef __sparc__ 2122 bios = aty128_map_ROM(par, pdev); 2123 #ifdef CONFIG_X86 2124 if (bios == NULL) 2125 bios = aty128_find_mem_vbios(par); 2126 #endif 2127 if (bios == NULL) 2128 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2129 else { 2130 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2131 aty128_get_pllinfo(par, bios); 2132 pci_unmap_rom(pdev, bios); 2133 } 2134 #endif /* __sparc__ */ 2135 2136 aty128_timings(par); 2137 pci_set_drvdata(pdev, info); 2138 2139 if (!aty128_init(pdev, ent)) 2140 goto err_out; 2141 2142 if (mtrr) 2143 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 2144 par->vram_size); 2145 return 0; 2146 2147 err_out: 2148 iounmap(info->screen_base); 2149 err_unmap_out: 2150 iounmap(par->regbase); 2151 err_free_info: 2152 framebuffer_release(info); 2153 err_free_mmio: 2154 release_mem_region(pci_resource_start(pdev, 2), 2155 pci_resource_len(pdev, 2)); 2156 err_free_fb: 2157 release_mem_region(pci_resource_start(pdev, 0), 2158 pci_resource_len(pdev, 0)); 2159 return -ENODEV; 2160 } 2161 2162 static void aty128_remove(struct pci_dev *pdev) 2163 { 2164 struct fb_info *info = pci_get_drvdata(pdev); 2165 struct aty128fb_par *par; 2166 2167 if (!info) 2168 return; 2169 2170 par = info->par; 2171 2172 unregister_framebuffer(info); 2173 2174 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2175 aty128_bl_exit(info->bl_dev); 2176 #endif 2177 2178 arch_phys_wc_del(par->wc_cookie); 2179 iounmap(par->regbase); 2180 iounmap(info->screen_base); 2181 2182 release_mem_region(pci_resource_start(pdev, 0), 2183 pci_resource_len(pdev, 0)); 2184 release_mem_region(pci_resource_start(pdev, 2), 2185 pci_resource_len(pdev, 2)); 2186 framebuffer_release(info); 2187 } 2188 #endif /* CONFIG_PCI */ 2189 2190 2191 2192 /* 2193 * Blank the display. 2194 */ 2195 static int aty128fb_blank(int blank, struct fb_info *fb) 2196 { 2197 struct aty128fb_par *par = fb->par; 2198 u8 state; 2199 2200 if (par->lock_blank || par->asleep) 2201 return 0; 2202 2203 switch (blank) { 2204 case FB_BLANK_NORMAL: 2205 state = 4; 2206 break; 2207 case FB_BLANK_VSYNC_SUSPEND: 2208 state = 6; 2209 break; 2210 case FB_BLANK_HSYNC_SUSPEND: 2211 state = 5; 2212 break; 2213 case FB_BLANK_POWERDOWN: 2214 state = 7; 2215 break; 2216 case FB_BLANK_UNBLANK: 2217 default: 2218 state = 0; 2219 break; 2220 } 2221 aty_st_8(CRTC_EXT_CNTL+1, state); 2222 2223 if (par->chip_gen == rage_M3) { 2224 aty128_set_crt_enable(par, par->crt_on && !blank); 2225 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2226 } 2227 2228 return 0; 2229 } 2230 2231 /* 2232 * Set a single color register. The values supplied are already 2233 * rounded down to the hardware's capabilities (according to the 2234 * entries in the var structure). Return != 0 for invalid regno. 2235 */ 2236 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2237 u_int transp, struct fb_info *info) 2238 { 2239 struct aty128fb_par *par = info->par; 2240 2241 if (regno > 255 2242 || (par->crtc.depth == 16 && regno > 63) 2243 || (par->crtc.depth == 15 && regno > 31)) 2244 return 1; 2245 2246 red >>= 8; 2247 green >>= 8; 2248 blue >>= 8; 2249 2250 if (regno < 16) { 2251 int i; 2252 u32 *pal = info->pseudo_palette; 2253 2254 switch (par->crtc.depth) { 2255 case 15: 2256 pal[regno] = (regno << 10) | (regno << 5) | regno; 2257 break; 2258 case 16: 2259 pal[regno] = (regno << 11) | (regno << 6) | regno; 2260 break; 2261 case 24: 2262 pal[regno] = (regno << 16) | (regno << 8) | regno; 2263 break; 2264 case 32: 2265 i = (regno << 8) | regno; 2266 pal[regno] = (i << 16) | i; 2267 break; 2268 } 2269 } 2270 2271 if (par->crtc.depth == 16 && regno > 0) { 2272 /* 2273 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2274 * have 32 slots for R and B values but 64 slots for G values. 2275 * Thus the R and B values go in one slot but the G value 2276 * goes in a different slot, and we have to avoid disturbing 2277 * the other fields in the slots we touch. 2278 */ 2279 par->green[regno] = green; 2280 if (regno < 32) { 2281 par->red[regno] = red; 2282 par->blue[regno] = blue; 2283 aty128_st_pal(regno * 8, red, par->green[regno*2], 2284 blue, par); 2285 } 2286 red = par->red[regno/2]; 2287 blue = par->blue[regno/2]; 2288 regno <<= 2; 2289 } else if (par->crtc.bpp == 16) 2290 regno <<= 3; 2291 aty128_st_pal(regno, red, green, blue, par); 2292 2293 return 0; 2294 } 2295 2296 #define ATY_MIRROR_LCD_ON 0x00000001 2297 #define ATY_MIRROR_CRT_ON 0x00000002 2298 2299 /* out param: u32* backlight value: 0 to 15 */ 2300 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2301 /* in param: u32* backlight value: 0 to 15 */ 2302 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2303 2304 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2305 { 2306 struct aty128fb_par *par = info->par; 2307 u32 value; 2308 int rc; 2309 2310 switch (cmd) { 2311 case FBIO_ATY128_SET_MIRROR: 2312 if (par->chip_gen != rage_M3) 2313 return -EINVAL; 2314 rc = get_user(value, (__u32 __user *)arg); 2315 if (rc) 2316 return rc; 2317 par->lcd_on = (value & 0x01) != 0; 2318 par->crt_on = (value & 0x02) != 0; 2319 if (!par->crt_on && !par->lcd_on) 2320 par->lcd_on = 1; 2321 aty128_set_crt_enable(par, par->crt_on); 2322 aty128_set_lcd_enable(par, par->lcd_on); 2323 return 0; 2324 case FBIO_ATY128_GET_MIRROR: 2325 if (par->chip_gen != rage_M3) 2326 return -EINVAL; 2327 value = (par->crt_on << 1) | par->lcd_on; 2328 return put_user(value, (__u32 __user *)arg); 2329 } 2330 return -EINVAL; 2331 } 2332 2333 static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2334 { 2335 u32 pmgt; 2336 2337 if (!par->pdev->pm_cap) 2338 return; 2339 2340 /* Set the chip into the appropriate suspend mode (we use D2, 2341 * D3 would require a complete re-initialisation of the chip, 2342 * including PCI config registers, clocks, AGP configuration, ...) 2343 * 2344 * For resume, the core will have already brought us back to D0 2345 */ 2346 if (suspend) { 2347 /* Make sure CRTC2 is reset. Remove that the day we decide to 2348 * actually use CRTC2 and replace it with real code for disabling 2349 * the CRTC2 output during sleep 2350 */ 2351 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2352 ~(CRTC2_EN)); 2353 2354 /* Set the power management mode to be PCI based */ 2355 /* Use this magic value for now */ 2356 pmgt = 0x0c005407; 2357 aty_st_pll(POWER_MANAGEMENT, pmgt); 2358 (void)aty_ld_pll(POWER_MANAGEMENT); 2359 aty_st_le32(BUS_CNTL1, 0x00000010); 2360 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2361 msleep(100); 2362 } 2363 } 2364 2365 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state) 2366 { 2367 struct pci_dev *pdev = to_pci_dev(dev); 2368 struct fb_info *info = pci_get_drvdata(pdev); 2369 struct aty128fb_par *par = info->par; 2370 2371 /* We don't do anything but D2, for now we return 0, but 2372 * we may want to change that. How do we know if the BIOS 2373 * can properly take care of D3 ? Also, with swsusp, we 2374 * know we'll be rebooted, ... 2375 */ 2376 #ifndef CONFIG_PPC_PMAC 2377 /* HACK ALERT ! Once I find a proper way to say to each driver 2378 * individually what will happen with it's PCI slot, I'll change 2379 * that. On laptops, the AGP slot is just unclocked, so D2 is 2380 * expected, while on desktops, the card is powered off 2381 */ 2382 return 0; 2383 #endif /* CONFIG_PPC_PMAC */ 2384 2385 if (state.event == pdev->dev.power.power_state.event) 2386 return 0; 2387 2388 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2389 2390 console_lock(); 2391 2392 fb_set_suspend(info, 1); 2393 2394 /* Make sure engine is reset */ 2395 wait_for_idle(par); 2396 aty128_reset_engine(par); 2397 wait_for_idle(par); 2398 2399 /* Blank display and LCD */ 2400 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2401 2402 /* Sleep */ 2403 par->asleep = 1; 2404 par->lock_blank = 1; 2405 2406 #ifdef CONFIG_PPC_PMAC 2407 /* On powermac, we have hooks to properly suspend/resume AGP now, 2408 * use them here. We'll ultimately need some generic support here, 2409 * but the generic code isn't quite ready for that yet 2410 */ 2411 pmac_suspend_agp_for_card(pdev); 2412 #endif /* CONFIG_PPC_PMAC */ 2413 2414 /* We need a way to make sure the fbdev layer will _not_ touch the 2415 * framebuffer before we put the chip to suspend state. On 2.4, I 2416 * used dummy fb ops, 2.5 need proper support for this at the 2417 * fbdev level 2418 */ 2419 if (state.event != PM_EVENT_ON) 2420 aty128_set_suspend(par, 1); 2421 2422 console_unlock(); 2423 2424 pdev->dev.power.power_state = state; 2425 2426 return 0; 2427 } 2428 2429 static int __maybe_unused aty128_pci_suspend(struct device *dev) 2430 { 2431 return aty128_pci_suspend_late(dev, PMSG_SUSPEND); 2432 } 2433 2434 static int __maybe_unused aty128_pci_hibernate(struct device *dev) 2435 { 2436 return aty128_pci_suspend_late(dev, PMSG_HIBERNATE); 2437 } 2438 2439 static int __maybe_unused aty128_pci_freeze(struct device *dev) 2440 { 2441 return aty128_pci_suspend_late(dev, PMSG_FREEZE); 2442 } 2443 2444 static int aty128_do_resume(struct pci_dev *pdev) 2445 { 2446 struct fb_info *info = pci_get_drvdata(pdev); 2447 struct aty128fb_par *par = info->par; 2448 2449 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2450 return 0; 2451 2452 /* PCI state will have been restored by the core, so 2453 * we should be in D0 now with our config space fully 2454 * restored 2455 */ 2456 2457 /* Wakeup chip */ 2458 aty128_set_suspend(par, 0); 2459 par->asleep = 0; 2460 2461 /* Restore display & engine */ 2462 aty128_reset_engine(par); 2463 wait_for_idle(par); 2464 aty128fb_set_par(info); 2465 fb_pan_display(info, &info->var); 2466 fb_set_cmap(&info->cmap, info); 2467 2468 /* Refresh */ 2469 fb_set_suspend(info, 0); 2470 2471 /* Unblank */ 2472 par->lock_blank = 0; 2473 aty128fb_blank(0, info); 2474 2475 #ifdef CONFIG_PPC_PMAC 2476 /* On powermac, we have hooks to properly suspend/resume AGP now, 2477 * use them here. We'll ultimately need some generic support here, 2478 * but the generic code isn't quite ready for that yet 2479 */ 2480 pmac_resume_agp_for_card(pdev); 2481 #endif /* CONFIG_PPC_PMAC */ 2482 2483 pdev->dev.power.power_state = PMSG_ON; 2484 2485 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2486 2487 return 0; 2488 } 2489 2490 static int __maybe_unused aty128_pci_resume(struct device *dev) 2491 { 2492 int rc; 2493 2494 console_lock(); 2495 rc = aty128_do_resume(to_pci_dev(dev)); 2496 console_unlock(); 2497 2498 return rc; 2499 } 2500 2501 2502 static int aty128fb_init(void) 2503 { 2504 #ifndef MODULE 2505 char *option = NULL; 2506 2507 if (fb_get_options("aty128fb", &option)) 2508 return -ENODEV; 2509 aty128fb_setup(option); 2510 #endif 2511 2512 return pci_register_driver(&aty128fb_driver); 2513 } 2514 2515 static void __exit aty128fb_exit(void) 2516 { 2517 pci_unregister_driver(&aty128fb_driver); 2518 } 2519 2520 module_init(aty128fb_init); 2521 2522 module_exit(aty128fb_exit); 2523 2524 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2525 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2526 MODULE_LICENSE("GPL"); 2527 module_param(mode_option, charp, 0); 2528 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2529 module_param_named(nomtrr, mtrr, invbool, 0); 2530 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2531