xref: /linux/drivers/video/backlight/ili922x.c (revision 2fb7eb3d7e8c5c0375c726c7d5c443e6f7e53741)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * (C) Copyright 2008
4  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5  *
6  * This driver implements a lcd device for the ILITEK 922x display
7  * controller. The interface to the display is SPI and the display's
8  * memory is cyclically updated over the RGB interface.
9  */
10 
11 #include <linux/delay.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/lcd.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20 #include <linux/string.h>
21 
22 /* Register offset, see manual section 8.2 */
23 #define REG_START_OSCILLATION			0x00
24 #define REG_DRIVER_CODE_READ			0x00
25 #define REG_DRIVER_OUTPUT_CONTROL		0x01
26 #define REG_LCD_AC_DRIVEING_CONTROL		0x02
27 #define REG_ENTRY_MODE				0x03
28 #define REG_COMPARE_1				0x04
29 #define REG_COMPARE_2				0x05
30 #define REG_DISPLAY_CONTROL_1			0x07
31 #define REG_DISPLAY_CONTROL_2			0x08
32 #define REG_DISPLAY_CONTROL_3			0x09
33 #define REG_FRAME_CYCLE_CONTROL			0x0B
34 #define REG_EXT_INTF_CONTROL			0x0C
35 #define REG_POWER_CONTROL_1			0x10
36 #define REG_POWER_CONTROL_2			0x11
37 #define REG_POWER_CONTROL_3			0x12
38 #define REG_POWER_CONTROL_4			0x13
39 #define REG_RAM_ADDRESS_SET			0x21
40 #define REG_WRITE_DATA_TO_GRAM			0x22
41 #define REG_RAM_WRITE_MASK1			0x23
42 #define REG_RAM_WRITE_MASK2			0x24
43 #define REG_GAMMA_CONTROL_1			0x30
44 #define REG_GAMMA_CONTROL_2			0x31
45 #define REG_GAMMA_CONTROL_3			0x32
46 #define REG_GAMMA_CONTROL_4			0x33
47 #define REG_GAMMA_CONTROL_5			0x34
48 #define REG_GAMMA_CONTROL_6			0x35
49 #define REG_GAMMA_CONTROL_7			0x36
50 #define REG_GAMMA_CONTROL_8			0x37
51 #define REG_GAMMA_CONTROL_9			0x38
52 #define REG_GAMMA_CONTROL_10			0x39
53 #define REG_GATE_SCAN_CONTROL			0x40
54 #define REG_VERT_SCROLL_CONTROL			0x41
55 #define REG_FIRST_SCREEN_DRIVE_POS		0x42
56 #define REG_SECOND_SCREEN_DRIVE_POS		0x43
57 #define REG_RAM_ADDR_POS_H			0x44
58 #define REG_RAM_ADDR_POS_V			0x45
59 #define REG_OSCILLATOR_CONTROL			0x4F
60 #define REG_GPIO				0x60
61 #define REG_OTP_VCM_PROGRAMMING			0x61
62 #define REG_OTP_VCM_STATUS_ENABLE		0x62
63 #define REG_OTP_PROGRAMMING_ID_KEY		0x65
64 
65 /*
66  * maximum frequency for register access
67  * (not for the GRAM access)
68  */
69 #define ILITEK_MAX_FREQ_REG	4000000
70 
71 /*
72  * Device ID as found in the datasheet (supports 9221 and 9222)
73  */
74 #define ILITEK_DEVICE_ID	0x9220
75 #define ILITEK_DEVICE_ID_MASK	0xFFF0
76 
77 /* Last two bits in the START BYTE */
78 #define START_RS_INDEX		0
79 #define START_RS_REG		1
80 #define START_RW_WRITE		0
81 #define START_RW_READ		1
82 
83 /*
84  * START_BYTE(id, rs, rw)
85  *
86  * Set the start byte according to the required operation.
87  * The start byte is defined as:
88  *   ----------------------------------
89  *  | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
90  *   ----------------------------------
91  * @id: display's id as set by the manufacturer
92  * @rs: operation type bit, one of:
93  *	  - START_RS_INDEX	set the index register
94  *	  - START_RS_REG	write/read registers/GRAM
95  * @rw: read/write operation
96  *	 - START_RW_WRITE	write
97  *	 - START_RW_READ	read
98  */
99 #define START_BYTE(id, rs, rw)	\
100 	(0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
101 
102 /*
103  * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
104  *	for the SPI transfer. According to the datasheet, the controller
105  *	accept higher frequency for the GRAM transfer, but it requires
106  *	lower frequency when the registers are read/written.
107  *	The macro sets the frequency in the spi_transfer structure if
108  *	the frequency exceeds the maximum value.
109  * @s: pointer to an SPI device
110  * @x: pointer to the read/write buffer pair
111  */
112 #define CHECK_FREQ_REG(s, x)	\
113 	do {			\
114 		if (s->max_speed_hz > ILITEK_MAX_FREQ_REG)	\
115 			((struct spi_transfer *)x)->speed_hz =	\
116 					ILITEK_MAX_FREQ_REG;	\
117 	} while (0)
118 
119 #define CMD_BUFSIZE		16
120 
121 #define POWER_IS_ON(pwr)	((pwr) <= LCD_POWER_REDUCED)
122 
123 #define set_tx_byte(b)		(tx_invert ? ~(b) : b)
124 
125 /*
126  * ili922x_id - id as set by manufacturer
127  */
128 static int ili922x_id = 1;
129 module_param(ili922x_id, int, 0);
130 
131 static int tx_invert;
132 module_param(tx_invert, int, 0);
133 
134 /*
135  * driver's private structure
136  */
137 struct ili922x {
138 	struct spi_device *spi;
139 	struct lcd_device *ld;
140 	int power;
141 };
142 
143 /**
144  * ili922x_read_status - read status register from display
145  * @spi: spi device
146  * @rs:  output value
147  */
ili922x_read_status(struct spi_device * spi,u16 * rs)148 static int ili922x_read_status(struct spi_device *spi, u16 *rs)
149 {
150 	struct spi_message msg;
151 	struct spi_transfer xfer;
152 	unsigned char tbuf[CMD_BUFSIZE];
153 	unsigned char rbuf[CMD_BUFSIZE];
154 	int ret, i;
155 
156 	memset(&xfer, 0, sizeof(struct spi_transfer));
157 	spi_message_init(&msg);
158 	xfer.tx_buf = tbuf;
159 	xfer.rx_buf = rbuf;
160 	xfer.cs_change = 1;
161 	CHECK_FREQ_REG(spi, &xfer);
162 
163 	tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
164 					 START_RW_READ));
165 	/*
166 	 * we need 4-byte xfer here due to invalid dummy byte
167 	 * received after start byte
168 	 */
169 	for (i = 1; i < 4; i++)
170 		tbuf[i] = set_tx_byte(0);	/* dummy */
171 
172 	xfer.bits_per_word = 8;
173 	xfer.len = 4;
174 	spi_message_add_tail(&xfer, &msg);
175 	ret = spi_sync(spi, &msg);
176 	if (ret < 0) {
177 		dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
178 		return ret;
179 	}
180 
181 	*rs = (rbuf[2] << 8) + rbuf[3];
182 	return 0;
183 }
184 
185 /**
186  * ili922x_read - read register from display
187  * @spi: spi device
188  * @reg: offset of the register to be read
189  * @rx:  output value
190  */
ili922x_read(struct spi_device * spi,u8 reg,u16 * rx)191 static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
192 {
193 	struct spi_message msg;
194 	struct spi_transfer xfer_regindex, xfer_regvalue;
195 	unsigned char tbuf[CMD_BUFSIZE];
196 	unsigned char rbuf[CMD_BUFSIZE];
197 	int ret, len = 0, send_bytes;
198 
199 	memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
200 	memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
201 	spi_message_init(&msg);
202 	xfer_regindex.tx_buf = tbuf;
203 	xfer_regindex.rx_buf = rbuf;
204 	xfer_regindex.cs_change = 1;
205 	CHECK_FREQ_REG(spi, &xfer_regindex);
206 
207 	tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
208 					 START_RW_WRITE));
209 	tbuf[1] = set_tx_byte(0);
210 	tbuf[2] = set_tx_byte(reg);
211 	xfer_regindex.bits_per_word = 8;
212 	len = xfer_regindex.len = 3;
213 	spi_message_add_tail(&xfer_regindex, &msg);
214 
215 	send_bytes = len;
216 
217 	tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
218 					     START_RW_READ));
219 	tbuf[len++] = set_tx_byte(0);
220 	tbuf[len] = set_tx_byte(0);
221 
222 	xfer_regvalue.cs_change = 1;
223 	xfer_regvalue.len = 3;
224 	xfer_regvalue.tx_buf = &tbuf[send_bytes];
225 	xfer_regvalue.rx_buf = &rbuf[send_bytes];
226 	CHECK_FREQ_REG(spi, &xfer_regvalue);
227 
228 	spi_message_add_tail(&xfer_regvalue, &msg);
229 	ret = spi_sync(spi, &msg);
230 	if (ret < 0) {
231 		dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
232 		return ret;
233 	}
234 
235 	*rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
236 	return 0;
237 }
238 
239 /**
240  * ili922x_write - write a controller register
241  * @spi: struct spi_device *
242  * @reg: offset of the register to be written
243  * @value: value to be written
244  */
ili922x_write(struct spi_device * spi,u8 reg,u16 value)245 static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
246 {
247 	struct spi_message msg;
248 	struct spi_transfer xfer_regindex, xfer_regvalue;
249 	unsigned char tbuf[CMD_BUFSIZE];
250 	unsigned char rbuf[CMD_BUFSIZE];
251 	int ret;
252 
253 	memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
254 	memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
255 
256 	spi_message_init(&msg);
257 	xfer_regindex.tx_buf = tbuf;
258 	xfer_regindex.rx_buf = rbuf;
259 	xfer_regindex.cs_change = 1;
260 	CHECK_FREQ_REG(spi, &xfer_regindex);
261 
262 	tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
263 					 START_RW_WRITE));
264 	tbuf[1] = set_tx_byte(0);
265 	tbuf[2] = set_tx_byte(reg);
266 	xfer_regindex.bits_per_word = 8;
267 	xfer_regindex.len = 3;
268 	spi_message_add_tail(&xfer_regindex, &msg);
269 
270 	ret = spi_sync(spi, &msg);
271 	if (ret < 0) {
272 		dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
273 		return ret;
274 	}
275 
276 	spi_message_init(&msg);
277 	tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
278 					 START_RW_WRITE));
279 	tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
280 	tbuf[2] = set_tx_byte(value & 0x00FF);
281 
282 	xfer_regvalue.cs_change = 1;
283 	xfer_regvalue.len = 3;
284 	xfer_regvalue.tx_buf = tbuf;
285 	xfer_regvalue.rx_buf = rbuf;
286 	CHECK_FREQ_REG(spi, &xfer_regvalue);
287 
288 	spi_message_add_tail(&xfer_regvalue, &msg);
289 
290 	ret = spi_sync(spi, &msg);
291 	if (ret < 0) {
292 		dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
293 		return ret;
294 	}
295 	return 0;
296 }
297 
298 #ifdef DEBUG
299 /**
300  * ili922x_reg_dump - dump all registers
301  *
302  * @spi: pointer to an SPI device
303  */
ili922x_reg_dump(struct spi_device * spi)304 static void ili922x_reg_dump(struct spi_device *spi)
305 {
306 	u8 reg;
307 	u16 rx;
308 
309 	dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
310 	for (reg = REG_START_OSCILLATION;
311 	     reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
312 		ili922x_read(spi, reg, &rx);
313 		dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
314 	}
315 }
316 #else
ili922x_reg_dump(struct spi_device * spi)317 static inline void ili922x_reg_dump(struct spi_device *spi) {}
318 #endif
319 
320 /**
321  * set_write_to_gram_reg - initialize the display to write the GRAM
322  * @spi: spi device
323  */
set_write_to_gram_reg(struct spi_device * spi)324 static void set_write_to_gram_reg(struct spi_device *spi)
325 {
326 	struct spi_message msg;
327 	struct spi_transfer xfer;
328 	unsigned char tbuf[CMD_BUFSIZE];
329 
330 	memset(&xfer, 0, sizeof(struct spi_transfer));
331 
332 	spi_message_init(&msg);
333 	xfer.tx_buf = tbuf;
334 	xfer.rx_buf = NULL;
335 	xfer.cs_change = 1;
336 
337 	tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
338 	tbuf[1] = 0;
339 	tbuf[2] = REG_WRITE_DATA_TO_GRAM;
340 
341 	xfer.bits_per_word = 8;
342 	xfer.len = 3;
343 	spi_message_add_tail(&xfer, &msg);
344 	spi_sync(spi, &msg);
345 }
346 
347 /**
348  * ili922x_poweron - turn the display on
349  * @spi: spi device
350  *
351  * The sequence to turn on the display is taken from
352  * the datasheet and/or the example code provided by the
353  * manufacturer.
354  */
ili922x_poweron(struct spi_device * spi)355 static int ili922x_poweron(struct spi_device *spi)
356 {
357 	int ret;
358 
359 	/* Power on */
360 	ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
361 	usleep_range(10000, 10500);
362 	ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
363 	ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
364 	msleep(40);
365 	ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
366 	msleep(40);
367 	/* register 0x56 is not documented in the datasheet */
368 	ret += ili922x_write(spi, 0x56, 0x080F);
369 	ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
370 	usleep_range(10000, 10500);
371 	ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
372 	ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
373 	msleep(40);
374 	ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
375 	msleep(40);
376 
377 	return ret;
378 }
379 
380 /**
381  * ili922x_poweroff - turn the display off
382  * @spi: spi device
383  */
ili922x_poweroff(struct spi_device * spi)384 static int ili922x_poweroff(struct spi_device *spi)
385 {
386 	int ret;
387 
388 	/* Power off */
389 	ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
390 	usleep_range(10000, 10500);
391 	ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
392 	ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
393 	msleep(40);
394 	ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
395 	msleep(40);
396 
397 	return ret;
398 }
399 
400 /**
401  * ili922x_display_init - initialize the display by setting
402  *			  the configuration registers
403  * @spi: spi device
404  */
ili922x_display_init(struct spi_device * spi)405 static void ili922x_display_init(struct spi_device *spi)
406 {
407 	ili922x_write(spi, REG_START_OSCILLATION, 1);
408 	usleep_range(10000, 10500);
409 	ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
410 	ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
411 	ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
412 	ili922x_write(spi, REG_COMPARE_1, 0x0000);
413 	ili922x_write(spi, REG_COMPARE_2, 0x0000);
414 	ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
415 	ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
416 	ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
417 	ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
418 
419 	/* Set RGB interface */
420 	ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
421 
422 	ili922x_poweron(spi);
423 
424 	ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
425 	ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
426 	ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
427 	ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
428 	ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
429 	ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
430 	ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
431 	ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
432 	ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
433 	ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
434 	ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
435 	ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
436 	ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
437 	ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
438 	ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
439 	ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
440 	ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
441 	ili922x_reg_dump(spi);
442 	set_write_to_gram_reg(spi);
443 }
444 
ili922x_lcd_power(struct ili922x * lcd,int power)445 static int ili922x_lcd_power(struct ili922x *lcd, int power)
446 {
447 	int ret = 0;
448 
449 	if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
450 		ret = ili922x_poweron(lcd->spi);
451 	else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
452 		ret = ili922x_poweroff(lcd->spi);
453 
454 	if (!ret)
455 		lcd->power = power;
456 
457 	return ret;
458 }
459 
ili922x_set_power(struct lcd_device * ld,int power)460 static int ili922x_set_power(struct lcd_device *ld, int power)
461 {
462 	struct ili922x *ili = lcd_get_data(ld);
463 
464 	return ili922x_lcd_power(ili, power);
465 }
466 
ili922x_get_power(struct lcd_device * ld)467 static int ili922x_get_power(struct lcd_device *ld)
468 {
469 	struct ili922x *ili = lcd_get_data(ld);
470 
471 	return ili->power;
472 }
473 
474 static const struct lcd_ops ili922x_ops = {
475 	.get_power = ili922x_get_power,
476 	.set_power = ili922x_set_power,
477 };
478 
ili922x_probe(struct spi_device * spi)479 static int ili922x_probe(struct spi_device *spi)
480 {
481 	struct ili922x *ili;
482 	struct lcd_device *lcd;
483 	int ret;
484 	u16 reg = 0;
485 
486 	ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
487 	if (!ili)
488 		return -ENOMEM;
489 
490 	ili->spi = spi;
491 	spi_set_drvdata(spi, ili);
492 
493 	/* check if the device is connected */
494 	ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
495 	if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
496 		dev_err(&spi->dev,
497 			"no LCD found: Chip ID 0x%x, ret %d\n",
498 			reg, ret);
499 		return -ENODEV;
500 	}
501 
502 	dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
503 		 reg, spi->max_speed_hz, spi->mode);
504 
505 	ret = ili922x_read_status(spi, &reg);
506 	if (ret) {
507 		dev_err(&spi->dev, "reading RS failed...\n");
508 		return ret;
509 	}
510 
511 	dev_dbg(&spi->dev, "status: 0x%x\n", reg);
512 
513 	ili922x_display_init(spi);
514 
515 	ili->power = LCD_POWER_OFF;
516 
517 	lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
518 					&ili922x_ops);
519 	if (IS_ERR(lcd)) {
520 		dev_err(&spi->dev, "cannot register LCD\n");
521 		return PTR_ERR(lcd);
522 	}
523 
524 	ili->ld = lcd;
525 	spi_set_drvdata(spi, ili);
526 
527 	ili922x_lcd_power(ili, LCD_POWER_ON);
528 
529 	return 0;
530 }
531 
ili922x_remove(struct spi_device * spi)532 static void ili922x_remove(struct spi_device *spi)
533 {
534 	ili922x_poweroff(spi);
535 }
536 
537 static struct spi_driver ili922x_driver = {
538 	.driver = {
539 		.name = "ili922x",
540 	},
541 	.probe = ili922x_probe,
542 	.remove = ili922x_remove,
543 };
544 
545 module_spi_driver(ili922x_driver);
546 
547 MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
548 MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
549 MODULE_LICENSE("GPL");
550 MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
551 MODULE_PARM_DESC(tx_invert, "invert bytes before sending");
552