xref: /linux/drivers/vdpa/ifcvf/ifcvf_base.c (revision 47b60ec7ba22a6359379bce9643bfff7a1ffe9ed) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel IFC VF NIC driver for virtio dataplane offloading
4  *
5  * Copyright (C) 2020 Intel Corporation.
6  *
7  * Author: Zhu Lingshan <lingshan.zhu@intel.com>
8  *
9  */
10 
11 #include "ifcvf_base.h"
12 
13 u16 ifcvf_set_vq_vector(struct ifcvf_hw *hw, u16 qid, int vector)
14 {
15 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
16 
17 	vp_iowrite16(qid, &cfg->queue_select);
18 	vp_iowrite16(vector, &cfg->queue_msix_vector);
19 
20 	return vp_ioread16(&cfg->queue_msix_vector);
21 }
22 
23 u16 ifcvf_set_config_vector(struct ifcvf_hw *hw, int vector)
24 {
25 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
26 
27 	vp_iowrite16(vector,  &cfg->msix_config);
28 
29 	return vp_ioread16(&cfg->msix_config);
30 }
31 
32 static void __iomem *get_cap_addr(struct ifcvf_hw *hw,
33 				  struct virtio_pci_cap *cap)
34 {
35 	u32 length, offset;
36 	u8 bar;
37 
38 	length = le32_to_cpu(cap->length);
39 	offset = le32_to_cpu(cap->offset);
40 	bar = cap->bar;
41 
42 	if (bar >= IFCVF_PCI_MAX_RESOURCE) {
43 		IFCVF_DBG(hw->pdev,
44 			  "Invalid bar number %u to get capabilities\n", bar);
45 		return NULL;
46 	}
47 
48 	if (offset + length > pci_resource_len(hw->pdev, bar)) {
49 		IFCVF_DBG(hw->pdev,
50 			  "offset(%u) + len(%u) overflows bar%u's capability\n",
51 			  offset, length, bar);
52 		return NULL;
53 	}
54 
55 	return hw->base[bar] + offset;
56 }
57 
58 static int ifcvf_read_config_range(struct pci_dev *dev,
59 				   uint32_t *val, int size, int where)
60 {
61 	int ret, i;
62 
63 	for (i = 0; i < size; i += 4) {
64 		ret = pci_read_config_dword(dev, where + i, val + i / 4);
65 		if (ret < 0)
66 			return ret;
67 	}
68 
69 	return 0;
70 }
71 
72 int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *pdev)
73 {
74 	struct virtio_pci_cap cap;
75 	u16 notify_off;
76 	int ret;
77 	u8 pos;
78 	u32 i;
79 
80 	ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
81 	if (ret < 0) {
82 		IFCVF_ERR(pdev, "Failed to read PCI capability list\n");
83 		return -EIO;
84 	}
85 	hw->pdev = pdev;
86 
87 	while (pos) {
88 		ret = ifcvf_read_config_range(pdev, (u32 *)&cap,
89 					      sizeof(cap), pos);
90 		if (ret < 0) {
91 			IFCVF_ERR(pdev,
92 				  "Failed to get PCI capability at %x\n", pos);
93 			break;
94 		}
95 
96 		if (cap.cap_vndr != PCI_CAP_ID_VNDR)
97 			goto next;
98 
99 		switch (cap.cfg_type) {
100 		case VIRTIO_PCI_CAP_COMMON_CFG:
101 			hw->common_cfg = get_cap_addr(hw, &cap);
102 			IFCVF_DBG(pdev, "hw->common_cfg = %p\n",
103 				  hw->common_cfg);
104 			break;
105 		case VIRTIO_PCI_CAP_NOTIFY_CFG:
106 			pci_read_config_dword(pdev, pos + sizeof(cap),
107 					      &hw->notify_off_multiplier);
108 			hw->notify_bar = cap.bar;
109 			hw->notify_base = get_cap_addr(hw, &cap);
110 			hw->notify_base_pa = pci_resource_start(pdev, cap.bar) +
111 					le32_to_cpu(cap.offset);
112 			IFCVF_DBG(pdev, "hw->notify_base = %p\n",
113 				  hw->notify_base);
114 			break;
115 		case VIRTIO_PCI_CAP_ISR_CFG:
116 			hw->isr = get_cap_addr(hw, &cap);
117 			IFCVF_DBG(pdev, "hw->isr = %p\n", hw->isr);
118 			break;
119 		case VIRTIO_PCI_CAP_DEVICE_CFG:
120 			hw->dev_cfg = get_cap_addr(hw, &cap);
121 			hw->cap_dev_config_size = le32_to_cpu(cap.length);
122 			IFCVF_DBG(pdev, "hw->dev_cfg = %p\n", hw->dev_cfg);
123 			break;
124 		}
125 
126 next:
127 		pos = cap.cap_next;
128 	}
129 
130 	if (hw->common_cfg == NULL || hw->notify_base == NULL ||
131 	    hw->isr == NULL || hw->dev_cfg == NULL) {
132 		IFCVF_ERR(pdev, "Incomplete PCI capabilities\n");
133 		return -EIO;
134 	}
135 
136 	hw->nr_vring = vp_ioread16(&hw->common_cfg->num_queues);
137 
138 	for (i = 0; i < hw->nr_vring; i++) {
139 		vp_iowrite16(i, &hw->common_cfg->queue_select);
140 		notify_off = vp_ioread16(&hw->common_cfg->queue_notify_off);
141 		hw->vring[i].notify_addr = hw->notify_base +
142 			notify_off * hw->notify_off_multiplier;
143 		hw->vring[i].notify_pa = hw->notify_base_pa +
144 			notify_off * hw->notify_off_multiplier;
145 		hw->vring[i].irq = -EINVAL;
146 	}
147 
148 	hw->lm_cfg = hw->base[IFCVF_LM_BAR];
149 
150 	IFCVF_DBG(pdev,
151 		  "PCI capability mapping: common cfg: %p, notify base: %p\n, isr cfg: %p, device cfg: %p, multiplier: %u\n",
152 		  hw->common_cfg, hw->notify_base, hw->isr,
153 		  hw->dev_cfg, hw->notify_off_multiplier);
154 
155 	hw->vqs_reused_irq = -EINVAL;
156 	hw->config_irq = -EINVAL;
157 
158 	return 0;
159 }
160 
161 u8 ifcvf_get_status(struct ifcvf_hw *hw)
162 {
163 	return vp_ioread8(&hw->common_cfg->device_status);
164 }
165 
166 void ifcvf_set_status(struct ifcvf_hw *hw, u8 status)
167 {
168 	vp_iowrite8(status, &hw->common_cfg->device_status);
169 }
170 
171 void ifcvf_reset(struct ifcvf_hw *hw)
172 {
173 	ifcvf_set_status(hw, 0);
174 	while (ifcvf_get_status(hw))
175 		msleep(1);
176 }
177 
178 u64 ifcvf_get_hw_features(struct ifcvf_hw *hw)
179 {
180 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
181 	u32 features_lo, features_hi;
182 	u64 features;
183 
184 	vp_iowrite32(0, &cfg->device_feature_select);
185 	features_lo = vp_ioread32(&cfg->device_feature);
186 
187 	vp_iowrite32(1, &cfg->device_feature_select);
188 	features_hi = vp_ioread32(&cfg->device_feature);
189 
190 	features = ((u64)features_hi << 32) | features_lo;
191 
192 	return features;
193 }
194 
195 /* return provisioned vDPA dev features */
196 u64 ifcvf_get_dev_features(struct ifcvf_hw *hw)
197 {
198 	return hw->dev_features;
199 }
200 
201 u64 ifcvf_get_driver_features(struct ifcvf_hw *hw)
202 {
203 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
204 	u32 features_lo, features_hi;
205 	u64 features;
206 
207 	vp_iowrite32(0, &cfg->device_feature_select);
208 	features_lo = vp_ioread32(&cfg->guest_feature);
209 
210 	vp_iowrite32(1, &cfg->device_feature_select);
211 	features_hi = vp_ioread32(&cfg->guest_feature);
212 
213 	features = ((u64)features_hi << 32) | features_lo;
214 
215 	return features;
216 }
217 
218 int ifcvf_verify_min_features(struct ifcvf_hw *hw, u64 features)
219 {
220 	if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)) && features) {
221 		IFCVF_ERR(hw->pdev, "VIRTIO_F_ACCESS_PLATFORM is not negotiated\n");
222 		return -EINVAL;
223 	}
224 
225 	return 0;
226 }
227 
228 u32 ifcvf_get_config_size(struct ifcvf_hw *hw)
229 {
230 	u32 net_config_size = sizeof(struct virtio_net_config);
231 	u32 blk_config_size = sizeof(struct virtio_blk_config);
232 	u32 cap_size = hw->cap_dev_config_size;
233 	u32 config_size;
234 
235 	/* If the onboard device config space size is greater than
236 	 * the size of struct virtio_net/blk_config, only the spec
237 	 * implementing contents size is returned, this is very
238 	 * unlikely, defensive programming.
239 	 */
240 	switch (hw->dev_type) {
241 	case VIRTIO_ID_NET:
242 		config_size = min(cap_size, net_config_size);
243 		break;
244 	case VIRTIO_ID_BLOCK:
245 		config_size = min(cap_size, blk_config_size);
246 		break;
247 	default:
248 		config_size = 0;
249 		IFCVF_ERR(hw->pdev, "VIRTIO ID %u not supported\n", hw->dev_type);
250 	}
251 
252 	return config_size;
253 }
254 
255 void ifcvf_read_dev_config(struct ifcvf_hw *hw, u64 offset,
256 			   void *dst, int length)
257 {
258 	u8 old_gen, new_gen, *p;
259 	int i;
260 
261 	WARN_ON(offset + length > hw->config_size);
262 	do {
263 		old_gen = vp_ioread8(&hw->common_cfg->config_generation);
264 		p = dst;
265 		for (i = 0; i < length; i++)
266 			*p++ = vp_ioread8(hw->dev_cfg + offset + i);
267 
268 		new_gen = vp_ioread8(&hw->common_cfg->config_generation);
269 	} while (old_gen != new_gen);
270 }
271 
272 void ifcvf_write_dev_config(struct ifcvf_hw *hw, u64 offset,
273 			    const void *src, int length)
274 {
275 	const u8 *p;
276 	int i;
277 
278 	p = src;
279 	WARN_ON(offset + length > hw->config_size);
280 	for (i = 0; i < length; i++)
281 		vp_iowrite8(*p++, hw->dev_cfg + offset + i);
282 }
283 
284 void ifcvf_set_driver_features(struct ifcvf_hw *hw, u64 features)
285 {
286 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
287 
288 	vp_iowrite32(0, &cfg->guest_feature_select);
289 	vp_iowrite32((u32)features, &cfg->guest_feature);
290 
291 	vp_iowrite32(1, &cfg->guest_feature_select);
292 	vp_iowrite32(features >> 32, &cfg->guest_feature);
293 }
294 
295 u16 ifcvf_get_vq_state(struct ifcvf_hw *hw, u16 qid)
296 {
297 	struct ifcvf_lm_cfg __iomem *ifcvf_lm;
298 	void __iomem *avail_idx_addr;
299 	u16 last_avail_idx;
300 	u32 q_pair_id;
301 
302 	ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
303 	q_pair_id = qid / 2;
304 	avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
305 	last_avail_idx = vp_ioread16(avail_idx_addr);
306 
307 	return last_avail_idx;
308 }
309 
310 int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num)
311 {
312 	struct ifcvf_lm_cfg __iomem *ifcvf_lm;
313 	void __iomem *avail_idx_addr;
314 	u32 q_pair_id;
315 
316 	ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
317 	q_pair_id = qid / 2;
318 	avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
319 	hw->vring[qid].last_avail_idx = num;
320 	vp_iowrite16(num, avail_idx_addr);
321 
322 	return 0;
323 }
324 
325 void ifcvf_set_vq_num(struct ifcvf_hw *hw, u16 qid, u32 num)
326 {
327 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
328 
329 	vp_iowrite16(qid, &cfg->queue_select);
330 	vp_iowrite16(num, &cfg->queue_size);
331 }
332 
333 int ifcvf_set_vq_address(struct ifcvf_hw *hw, u16 qid, u64 desc_area,
334 			 u64 driver_area, u64 device_area)
335 {
336 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
337 
338 	vp_iowrite16(qid, &cfg->queue_select);
339 	vp_iowrite64_twopart(desc_area, &cfg->queue_desc_lo,
340 			     &cfg->queue_desc_hi);
341 	vp_iowrite64_twopart(driver_area, &cfg->queue_avail_lo,
342 			     &cfg->queue_avail_hi);
343 	vp_iowrite64_twopart(device_area, &cfg->queue_used_lo,
344 			     &cfg->queue_used_hi);
345 
346 	return 0;
347 }
348 
349 bool ifcvf_get_vq_ready(struct ifcvf_hw *hw, u16 qid)
350 {
351 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
352 	u16 queue_enable;
353 
354 	vp_iowrite16(qid, &cfg->queue_select);
355 	queue_enable = vp_ioread16(&cfg->queue_enable);
356 
357 	return (bool)queue_enable;
358 }
359 
360 void ifcvf_set_vq_ready(struct ifcvf_hw *hw, u16 qid, bool ready)
361 {
362 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
363 
364 	vp_iowrite16(qid, &cfg->queue_select);
365 	vp_iowrite16(ready, &cfg->queue_enable);
366 }
367 
368 static void ifcvf_reset_vring(struct ifcvf_hw *hw)
369 {
370 	u16 qid;
371 
372 	for (qid = 0; qid < hw->nr_vring; qid++) {
373 		hw->vring[qid].cb.callback = NULL;
374 		hw->vring[qid].cb.private = NULL;
375 		ifcvf_set_vq_vector(hw, qid, VIRTIO_MSI_NO_VECTOR);
376 	}
377 }
378 
379 static void ifcvf_reset_config_handler(struct ifcvf_hw *hw)
380 {
381 	hw->config_cb.callback = NULL;
382 	hw->config_cb.private = NULL;
383 	ifcvf_set_config_vector(hw, VIRTIO_MSI_NO_VECTOR);
384 }
385 
386 static void ifcvf_synchronize_irq(struct ifcvf_hw *hw)
387 {
388 	u32 nvectors = hw->num_msix_vectors;
389 	struct pci_dev *pdev = hw->pdev;
390 	int i, irq;
391 
392 	for (i = 0; i < nvectors; i++) {
393 		irq = pci_irq_vector(pdev, i);
394 		if (irq >= 0)
395 			synchronize_irq(irq);
396 	}
397 }
398 
399 void ifcvf_stop(struct ifcvf_hw *hw)
400 {
401 	ifcvf_synchronize_irq(hw);
402 	ifcvf_reset_vring(hw);
403 	ifcvf_reset_config_handler(hw);
404 }
405 
406 void ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid)
407 {
408 	vp_iowrite16(qid, hw->vring[qid].notify_addr);
409 }
410