xref: /linux/drivers/usb/renesas_usbhs/common.h (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3  * Renesas USB driver
4  *
5  * Copyright (C) 2011 Renesas Solutions Corp.
6  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7  */
8 #ifndef RENESAS_USB_DRIVER_H
9 #define RENESAS_USB_DRIVER_H
10 
11 #include <linux/extcon.h>
12 #include <linux/platform_device.h>
13 #include <linux/usb/renesas_usbhs.h>
14 
15 struct usbhs_priv;
16 
17 #include "mod.h"
18 #include "pipe.h"
19 
20 /*
21  *
22  *		register define
23  *
24  */
25 #define SYSCFG		0x0000
26 #define BUSWAIT		0x0002
27 #define DVSTCTR		0x0008
28 #define TESTMODE	0x000C
29 #define CFIFO		0x0014
30 #define CFIFOSEL	0x0020
31 #define CFIFOCTR	0x0022
32 #define D0FIFO		0x0100
33 #define D0FIFOSEL	0x0028
34 #define D0FIFOCTR	0x002A
35 #define D1FIFO		0x0120
36 #define D1FIFOSEL	0x002C
37 #define D1FIFOCTR	0x002E
38 #define INTENB0		0x0030
39 #define INTENB1		0x0032
40 #define BRDYENB		0x0036
41 #define NRDYENB		0x0038
42 #define BEMPENB		0x003A
43 #define INTSTS0		0x0040
44 #define INTSTS1		0x0042
45 #define BRDYSTS		0x0046
46 #define NRDYSTS		0x0048
47 #define BEMPSTS		0x004A
48 #define FRMNUM		0x004C
49 #define USBREQ		0x0054	/* USB request type register */
50 #define USBVAL		0x0056	/* USB request value register */
51 #define USBINDX		0x0058	/* USB request index register */
52 #define USBLENG		0x005A	/* USB request length register */
53 #define DCPCFG		0x005C
54 #define DCPMAXP		0x005E
55 #define DCPCTR		0x0060
56 #define PIPESEL		0x0064
57 #define PIPECFG		0x0068
58 #define PIPEBUF		0x006A
59 #define PIPEMAXP	0x006C
60 #define PIPEPERI	0x006E
61 #define PIPEnCTR	0x0070
62 #define PIPE1TRE	0x0090
63 #define PIPE1TRN	0x0092
64 #define PIPE2TRE	0x0094
65 #define PIPE2TRN	0x0096
66 #define PIPE3TRE	0x0098
67 #define PIPE3TRN	0x009A
68 #define PIPE4TRE	0x009C
69 #define PIPE4TRN	0x009E
70 #define PIPE5TRE	0x00A0
71 #define PIPE5TRN	0x00A2
72 #define PIPEBTRE	0x00A4
73 #define PIPEBTRN	0x00A6
74 #define PIPECTRE	0x00A8
75 #define PIPECTRN	0x00AA
76 #define PIPEDTRE	0x00AC
77 #define PIPEDTRN	0x00AE
78 #define PIPEETRE	0x00B0
79 #define PIPEETRN	0x00B2
80 #define PIPEFTRE	0x00B4
81 #define PIPEFTRN	0x00B6
82 #define PIPE9TRE	0x00B8
83 #define PIPE9TRN	0x00BA
84 #define PIPEATRE	0x00BC
85 #define PIPEATRN	0x00BE
86 #define DEVADD0		0x00D0 /* Device address n configuration */
87 #define DEVADD1		0x00D2
88 #define DEVADD2		0x00D4
89 #define DEVADD3		0x00D6
90 #define DEVADD4		0x00D8
91 #define DEVADD5		0x00DA
92 #define DEVADD6		0x00DC
93 #define DEVADD7		0x00DE
94 #define DEVADD8		0x00E0
95 #define DEVADD9		0x00E2
96 #define DEVADDA		0x00E4
97 #define D2FIFOSEL	0x00F0	/* for R-Car Gen2 */
98 #define D2FIFOCTR	0x00F2	/* for R-Car Gen2 */
99 #define D3FIFOSEL	0x00F4	/* for R-Car Gen2 */
100 #define D3FIFOCTR	0x00F6	/* for R-Car Gen2 */
101 #define SUSPMODE	0x0102	/* for RZ/A */
102 
103 /* SYSCFG */
104 #define SCKE	(1 << 10)	/* USB Module Clock Enable */
105 #define HSE	(1 << 7)	/* High-Speed Operation Enable */
106 #define DCFM	(1 << 6)	/* Controller Function Select */
107 #define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
108 #define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
109 #define USBE	(1 << 0)	/* USB Module Operation Enable */
110 #define UCKSEL	(1 << 2)	/* Clock Select for RZ/A1 */
111 #define UPLLE	(1 << 1)	/* USB PLL Enable for RZ/A1 */
112 
113 /* DVSTCTR */
114 #define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
115 #define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
116 #define USBRST	(1 << 6)	/* Bus Reset Output */
117 #define UACT	(1 << 4)	/* USB Bus Enable */
118 #define RHST	(0x7)		/* Reset Handshake */
119 #define  RHST_LOW_SPEED  1	/* Low-speed connection */
120 #define  RHST_FULL_SPEED 2	/* Full-speed connection */
121 #define  RHST_HIGH_SPEED 3	/* High-speed connection */
122 
123 /* CFIFOSEL */
124 #define DREQE	(1 << 12)	/* DMA Transfer Request Enable */
125 #define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */
126 
127 /* CFIFOCTR */
128 #define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
129 #define BCLR	(1 << 14)	/* CPU buffer clear */
130 #define FRDY	(1 << 13)	/* FIFO Port Ready */
131 #define DTLN_MASK (0x0FFF)	/* Receive Data Length */
132 
133 /* INTENB0 */
134 #define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
135 #define RSME	(1 << 14)	/* Enable IRQ Resume */
136 #define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
137 #define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
138 #define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
139 #define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
140 #define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
141 #define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
142 
143 /* INTENB1 */
144 #define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
145 #define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
146 #define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
147 #define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
148 #define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
149 #define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
150 
151 /* INTSTS0 */
152 #define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
153 #define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
154 #define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
155 #define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
156 #define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
157 #define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
158 #define VALID	(1 << 3)	/* USB Request Receive */
159 
160 #define DVSQ_MASK		(0x3 << 4)	/* Device State */
161 #define  POWER_STATE		(0 << 4)
162 #define  DEFAULT_STATE		(1 << 4)
163 #define  ADDRESS_STATE		(2 << 4)
164 #define  CONFIGURATION_STATE	(3 << 4)
165 
166 #define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
167 #define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
168 #define  READ_DATA_STAGE	1	/* Control read data stage */
169 #define  READ_STATUS_STAGE	2	/* Control read status stage */
170 #define  WRITE_DATA_STAGE	3	/* Control write data stage */
171 #define  WRITE_STATUS_STAGE	4	/* Control write status stage */
172 #define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
173 #define  SEQUENCE_ERROR		6	/* Control transfer sequence error */
174 
175 /* INTSTS1 */
176 #define OVRCR	(1 << 15) /* OVRCR Interrupt Status */
177 #define BCHG	(1 << 14) /* USB Bus Change Interrupt Status */
178 #define DTCH	(1 << 12) /* USB Disconnection Detect Interrupt Status */
179 #define ATTCH	(1 << 11) /* ATTCH Interrupt Status */
180 #define EOFERR	(1 << 6)  /* EOF Error Detect Interrupt Status */
181 #define SIGN	(1 << 5)  /* Setup Transaction Error Interrupt Status */
182 #define SACK	(1 << 4)  /* Setup Transaction ACK Response Interrupt Status */
183 
184 /* PIPECFG */
185 /* DCPCFG */
186 #define TYPE_NONE	(0 << 14)	/* Transfer Type */
187 #define TYPE_BULK	(1 << 14)
188 #define TYPE_INT	(2 << 14)
189 #define TYPE_ISO	(3 << 14)
190 #define BFRE		(1 << 10)	/* BRDY Interrupt Operation Spec. */
191 #define DBLB		(1 << 9)	/* Double Buffer Mode */
192 #define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
193 #define DIR_OUT		(1 << 4)	/* Transfer Direction */
194 
195 /* PIPEMAXP */
196 /* DCPMAXP */
197 #define DEVSEL_MASK	(0xF << 12)	/* Device Select */
198 #define DCP_MAXP_MASK	(0x7F)
199 #define PIPE_MAXP_MASK	(0x7FF)
200 
201 /* PIPEBUF */
202 #define BUFSIZE_SHIFT	10
203 #define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
204 #define BUFNMB_MASK	(0xFF)
205 
206 /* PIPEnCTR */
207 /* DCPCTR */
208 #define BSTS		(1 << 15)	/* Buffer Status */
209 #define SUREQ		(1 << 14)	/* Sending SETUP Token */
210 #define CSSTS		(1 << 12)	/* CSSTS Status */
211 #define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
212 #define SQCLR		(1 << 8)	/* Toggle Bit Clear */
213 #define SQSET		(1 << 7)	/* Toggle Bit Set */
214 #define SQMON		(1 << 6)	/* Toggle Bit Check */
215 #define PBUSY		(1 << 5)	/* Pipe Busy */
216 #define PID_MASK	(0x3)		/* Response PID */
217 #define  PID_NAK	0
218 #define  PID_BUF	1
219 #define  PID_STALL10	2
220 #define  PID_STALL11	3
221 
222 #define CCPL		(1 << 2)	/* Control Transfer End Enable */
223 
224 /* PIPEnTRE */
225 #define TRENB		(1 << 9)	/* Transaction Counter Enable */
226 #define TRCLR		(1 << 8)	/* Transaction Counter Clear */
227 
228 /* FRMNUM */
229 #define FRNM_MASK	(0x7FF)
230 
231 /* DEVADDn */
232 #define UPPHUB(x)	(((x) & 0xF) << 11)	/* HUB Register */
233 #define HUBPORT(x)	(((x) & 0x7) << 8)	/* HUB Port for Target Device */
234 #define USBSPD(x)	(((x) & 0x3) << 6)	/* Device Transfer Rate */
235 #define USBSPD_SPEED_LOW	0x1
236 #define USBSPD_SPEED_FULL	0x2
237 #define USBSPD_SPEED_HIGH	0x3
238 
239 /* SUSPMODE */
240 #define SUSPM		(1 << 14)	/* SuspendM Control */
241 
242 /*
243  *		struct
244  */
245 struct usbhs_priv {
246 
247 	void __iomem *base;
248 	unsigned int irq;
249 	unsigned long irqflags;
250 
251 	struct renesas_usbhs_platform_callback	pfunc;
252 	struct renesas_usbhs_driver_param	dparam;
253 
254 	struct delayed_work notify_hotplug_work;
255 	struct platform_device *pdev;
256 
257 	struct extcon_dev *edev;
258 	struct notifier_block nb;
259 
260 	spinlock_t		lock;
261 
262 	u32 flags;
263 
264 	/*
265 	 * module control
266 	 */
267 	struct usbhs_mod_info mod_info;
268 
269 	/*
270 	 * pipe control
271 	 */
272 	struct usbhs_pipe_info pipe_info;
273 
274 	/*
275 	 * fifo control
276 	 */
277 	struct usbhs_fifo_info fifo_info;
278 
279 	struct phy *phy;
280 };
281 
282 /*
283  * common
284  */
285 u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
286 void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
287 void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
288 
289 #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
290 #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
291 
292 /*
293  * sysconfig
294  */
295 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
296 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
297 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
298 void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
299 
300 /*
301  * usb request
302  */
303 void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
304 void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
305 
306 /*
307  * bus
308  */
309 void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
310 void usbhs_bus_send_reset(struct usbhs_priv *priv);
311 int usbhs_bus_get_speed(struct usbhs_priv *priv);
312 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
313 
314 /*
315  * frame
316  */
317 int usbhs_frame_get_num(struct usbhs_priv *priv);
318 
319 /*
320  * device config
321  */
322 int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
323 			   u16 hubport, u16 speed);
324 
325 /*
326  * interrupt functions
327  */
328 void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
329 
330 /*
331  * data
332  */
333 struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
334 #define usbhs_get_dparam(priv, param)	(priv->dparam.param)
335 #define usbhs_priv_to_pdev(priv)	(priv->pdev)
336 #define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
337 #define usbhs_priv_to_lock(priv)	(&priv->lock)
338 
339 #endif /* RENESAS_USB_DRIVER_H */
340