1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2013 NVIDIA Corporation 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * Benoit Goby <benoit@android.com> 9 * Venu Byravarasu <vbyravarasu@nvidia.com> 10 * 11 * This software is licensed under the terms of the GNU General Public 12 * License version 2, as published by the Free Software Foundation, and 13 * may be copied, distributed, and modified under those terms. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22 #include <linux/resource.h> 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <linux/err.h> 26 #include <linux/export.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/io.h> 30 #include <linux/gpio.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/usb/otg.h> 35 #include <linux/usb/ulpi.h> 36 #include <linux/usb/of.h> 37 #include <linux/usb/ehci_def.h> 38 #include <linux/usb/tegra_usb_phy.h> 39 #include <linux/regulator/consumer.h> 40 41 #define ULPI_VIEWPORT 0x170 42 43 /* PORTSC PTS/PHCD bits, Tegra20 only */ 44 #define TEGRA_USB_PORTSC1 0x184 45 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) 46 #define TEGRA_USB_PORTSC1_PHCD (1 << 23) 47 48 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */ 49 #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 50 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) 51 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22) 52 53 /* Bits of PORTSC1, which will get cleared by writing 1 into them */ 54 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 55 56 #define USB_SUSP_CTRL 0x400 57 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 58 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 59 #define USB_SUSP_CLR (1 << 5) 60 #define USB_PHY_CLK_VALID (1 << 7) 61 #define UTMIP_RESET (1 << 11) 62 #define UHSIC_RESET (1 << 11) 63 #define UTMIP_PHY_ENABLE (1 << 12) 64 #define ULPI_PHY_ENABLE (1 << 13) 65 #define USB_SUSP_SET (1 << 14) 66 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 67 68 #define USB1_LEGACY_CTRL 0x410 69 #define USB1_NO_LEGACY_MODE (1 << 0) 70 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) 71 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) 72 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ 73 (1 << 1) 74 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) 75 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) 76 77 #define ULPI_TIMING_CTRL_0 0x424 78 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 79 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 80 81 #define ULPI_TIMING_CTRL_1 0x428 82 #define ULPI_DATA_TRIMMER_LOAD (1 << 0) 83 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 84 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 85 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 86 #define ULPI_DIR_TRIMMER_LOAD (1 << 24) 87 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 88 89 #define UTMIP_PLL_CFG1 0x804 90 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 91 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 92 93 #define UTMIP_XCVR_CFG0 0x808 94 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 95 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) 96 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 97 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 98 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 99 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 100 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 101 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) 102 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) 103 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) 104 105 #define UTMIP_BIAS_CFG0 0x80c 106 #define UTMIP_OTGPD (1 << 11) 107 #define UTMIP_BIASPD (1 << 10) 108 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) 109 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) 110 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) 111 112 #define UTMIP_HSRX_CFG0 0x810 113 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 114 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 115 116 #define UTMIP_HSRX_CFG1 0x814 117 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) 118 119 #define UTMIP_TX_CFG0 0x820 120 #define UTMIP_FS_PREABMLE_J (1 << 19) 121 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 122 123 #define UTMIP_MISC_CFG0 0x824 124 #define UTMIP_DPDM_OBSERVE (1 << 26) 125 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 126 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) 127 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) 128 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) 129 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) 130 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 131 132 #define UTMIP_MISC_CFG1 0x828 133 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) 134 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) 135 136 #define UTMIP_DEBOUNCE_CFG0 0x82c 137 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 138 139 #define UTMIP_BAT_CHRG_CFG0 0x830 140 #define UTMIP_PD_CHRG (1 << 0) 141 142 #define UTMIP_SPARE_CFG0 0x834 143 #define FUSE_SETUP_SEL (1 << 3) 144 145 #define UTMIP_XCVR_CFG1 0x838 146 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 147 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 148 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 149 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 150 151 #define UTMIP_BIAS_CFG1 0x83c 152 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 153 154 /* For Tegra30 and above only, the address is different in Tegra20 */ 155 #define USB_USBMODE 0x1f8 156 #define USB_USBMODE_MASK (3 << 0) 157 #define USB_USBMODE_HOST (3 << 0) 158 #define USB_USBMODE_DEVICE (2 << 0) 159 160 static DEFINE_SPINLOCK(utmip_pad_lock); 161 static int utmip_pad_count; 162 163 struct tegra_xtal_freq { 164 int freq; 165 u8 enable_delay; 166 u8 stable_count; 167 u8 active_delay; 168 u8 xtal_freq_count; 169 u16 debounce; 170 }; 171 172 static const struct tegra_xtal_freq tegra_freq_table[] = { 173 { 174 .freq = 12000000, 175 .enable_delay = 0x02, 176 .stable_count = 0x2F, 177 .active_delay = 0x04, 178 .xtal_freq_count = 0x76, 179 .debounce = 0x7530, 180 }, 181 { 182 .freq = 13000000, 183 .enable_delay = 0x02, 184 .stable_count = 0x33, 185 .active_delay = 0x05, 186 .xtal_freq_count = 0x7F, 187 .debounce = 0x7EF4, 188 }, 189 { 190 .freq = 19200000, 191 .enable_delay = 0x03, 192 .stable_count = 0x4B, 193 .active_delay = 0x06, 194 .xtal_freq_count = 0xBB, 195 .debounce = 0xBB80, 196 }, 197 { 198 .freq = 26000000, 199 .enable_delay = 0x04, 200 .stable_count = 0x66, 201 .active_delay = 0x09, 202 .xtal_freq_count = 0xFE, 203 .debounce = 0xFDE8, 204 }, 205 }; 206 207 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) 208 { 209 void __iomem *base = phy->regs; 210 unsigned long val; 211 212 if (phy->soc_config->has_hostpc) { 213 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); 214 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); 215 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); 216 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); 217 } else { 218 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; 219 val &= ~TEGRA_USB_PORTSC1_PTS(~0); 220 val |= TEGRA_USB_PORTSC1_PTS(pts_val); 221 writel(val, base + TEGRA_USB_PORTSC1); 222 } 223 } 224 225 static void set_phcd(struct tegra_usb_phy *phy, bool enable) 226 { 227 void __iomem *base = phy->regs; 228 unsigned long val; 229 230 if (phy->soc_config->has_hostpc) { 231 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); 232 if (enable) 233 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; 234 else 235 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; 236 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); 237 } else { 238 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; 239 if (enable) 240 val |= TEGRA_USB_PORTSC1_PHCD; 241 else 242 val &= ~TEGRA_USB_PORTSC1_PHCD; 243 writel(val, base + TEGRA_USB_PORTSC1); 244 } 245 } 246 247 static int utmip_pad_open(struct tegra_usb_phy *phy) 248 { 249 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads"); 250 if (IS_ERR(phy->pad_clk)) { 251 pr_err("%s: can't get utmip pad clock\n", __func__); 252 return PTR_ERR(phy->pad_clk); 253 } 254 255 return 0; 256 } 257 258 static void utmip_pad_power_on(struct tegra_usb_phy *phy) 259 { 260 unsigned long val, flags; 261 void __iomem *base = phy->pad_regs; 262 struct tegra_utmip_config *config = phy->config; 263 264 clk_prepare_enable(phy->pad_clk); 265 266 spin_lock_irqsave(&utmip_pad_lock, flags); 267 268 if (utmip_pad_count++ == 0) { 269 val = readl(base + UTMIP_BIAS_CFG0); 270 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); 271 272 if (phy->soc_config->requires_extra_tuning_parameters) { 273 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | 274 UTMIP_HSDISCON_LEVEL(~0) | 275 UTMIP_HSDISCON_LEVEL_MSB(~0)); 276 277 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); 278 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); 279 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); 280 } 281 writel(val, base + UTMIP_BIAS_CFG0); 282 } 283 284 spin_unlock_irqrestore(&utmip_pad_lock, flags); 285 286 clk_disable_unprepare(phy->pad_clk); 287 } 288 289 static int utmip_pad_power_off(struct tegra_usb_phy *phy) 290 { 291 unsigned long val, flags; 292 void __iomem *base = phy->pad_regs; 293 294 if (!utmip_pad_count) { 295 pr_err("%s: utmip pad already powered off\n", __func__); 296 return -EINVAL; 297 } 298 299 clk_prepare_enable(phy->pad_clk); 300 301 spin_lock_irqsave(&utmip_pad_lock, flags); 302 303 if (--utmip_pad_count == 0) { 304 val = readl(base + UTMIP_BIAS_CFG0); 305 val |= UTMIP_OTGPD | UTMIP_BIASPD; 306 writel(val, base + UTMIP_BIAS_CFG0); 307 } 308 309 spin_unlock_irqrestore(&utmip_pad_lock, flags); 310 311 clk_disable_unprepare(phy->pad_clk); 312 313 return 0; 314 } 315 316 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) 317 { 318 unsigned long timeout = 2000; 319 do { 320 if ((readl(reg) & mask) == result) 321 return 0; 322 udelay(1); 323 timeout--; 324 } while (timeout); 325 return -1; 326 } 327 328 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) 329 { 330 unsigned long val; 331 void __iomem *base = phy->regs; 332 333 /* 334 * The USB driver may have already initiated the phy clock 335 * disable so wait to see if the clock turns off and if not 336 * then proceed with gating the clock. 337 */ 338 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0) 339 return; 340 341 if (phy->is_legacy_phy) { 342 val = readl(base + USB_SUSP_CTRL); 343 val |= USB_SUSP_SET; 344 writel(val, base + USB_SUSP_CTRL); 345 346 udelay(10); 347 348 val = readl(base + USB_SUSP_CTRL); 349 val &= ~USB_SUSP_SET; 350 writel(val, base + USB_SUSP_CTRL); 351 } else 352 set_phcd(phy, true); 353 354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) 355 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 356 } 357 358 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) 359 { 360 unsigned long val; 361 void __iomem *base = phy->regs; 362 363 /* 364 * The USB driver may have already initiated the phy clock 365 * enable so wait to see if the clock turns on and if not 366 * then proceed with ungating the clock. 367 */ 368 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 369 USB_PHY_CLK_VALID) == 0) 370 return; 371 372 if (phy->is_legacy_phy) { 373 val = readl(base + USB_SUSP_CTRL); 374 val |= USB_SUSP_CLR; 375 writel(val, base + USB_SUSP_CTRL); 376 377 udelay(10); 378 379 val = readl(base + USB_SUSP_CTRL); 380 val &= ~USB_SUSP_CLR; 381 writel(val, base + USB_SUSP_CTRL); 382 } else 383 set_phcd(phy, false); 384 385 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 386 USB_PHY_CLK_VALID)) 387 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 388 } 389 390 static int utmi_phy_power_on(struct tegra_usb_phy *phy) 391 { 392 unsigned long val; 393 void __iomem *base = phy->regs; 394 struct tegra_utmip_config *config = phy->config; 395 396 val = readl(base + USB_SUSP_CTRL); 397 val |= UTMIP_RESET; 398 writel(val, base + USB_SUSP_CTRL); 399 400 if (phy->is_legacy_phy) { 401 val = readl(base + USB1_LEGACY_CTRL); 402 val |= USB1_NO_LEGACY_MODE; 403 writel(val, base + USB1_LEGACY_CTRL); 404 } 405 406 val = readl(base + UTMIP_TX_CFG0); 407 val |= UTMIP_FS_PREABMLE_J; 408 writel(val, base + UTMIP_TX_CFG0); 409 410 val = readl(base + UTMIP_HSRX_CFG0); 411 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); 412 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); 413 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); 414 writel(val, base + UTMIP_HSRX_CFG0); 415 416 val = readl(base + UTMIP_HSRX_CFG1); 417 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 418 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); 419 writel(val, base + UTMIP_HSRX_CFG1); 420 421 val = readl(base + UTMIP_DEBOUNCE_CFG0); 422 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 423 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); 424 writel(val, base + UTMIP_DEBOUNCE_CFG0); 425 426 val = readl(base + UTMIP_MISC_CFG0); 427 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 428 writel(val, base + UTMIP_MISC_CFG0); 429 430 if (!phy->soc_config->utmi_pll_config_in_car_module) { 431 val = readl(base + UTMIP_MISC_CFG1); 432 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | 433 UTMIP_PLLU_STABLE_COUNT(~0)); 434 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | 435 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); 436 writel(val, base + UTMIP_MISC_CFG1); 437 438 val = readl(base + UTMIP_PLL_CFG1); 439 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | 440 UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); 441 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | 442 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); 443 writel(val, base + UTMIP_PLL_CFG1); 444 } 445 446 if (phy->mode == USB_DR_MODE_PERIPHERAL) { 447 val = readl(base + USB_SUSP_CTRL); 448 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); 449 writel(val, base + USB_SUSP_CTRL); 450 451 val = readl(base + UTMIP_BAT_CHRG_CFG0); 452 val &= ~UTMIP_PD_CHRG; 453 writel(val, base + UTMIP_BAT_CHRG_CFG0); 454 } else { 455 val = readl(base + UTMIP_BAT_CHRG_CFG0); 456 val |= UTMIP_PD_CHRG; 457 writel(val, base + UTMIP_BAT_CHRG_CFG0); 458 } 459 460 utmip_pad_power_on(phy); 461 462 val = readl(base + UTMIP_XCVR_CFG0); 463 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 464 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | 465 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | 466 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0)); 467 468 if (!config->xcvr_setup_use_fuses) { 469 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); 470 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); 471 } 472 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); 473 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); 474 475 if (phy->soc_config->requires_extra_tuning_parameters) { 476 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); 477 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); 478 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); 479 } 480 writel(val, base + UTMIP_XCVR_CFG0); 481 482 val = readl(base + UTMIP_XCVR_CFG1); 483 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 484 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); 485 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); 486 writel(val, base + UTMIP_XCVR_CFG1); 487 488 val = readl(base + UTMIP_BIAS_CFG1); 489 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 490 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 491 writel(val, base + UTMIP_BIAS_CFG1); 492 493 val = readl(base + UTMIP_SPARE_CFG0); 494 if (config->xcvr_setup_use_fuses) 495 val |= FUSE_SETUP_SEL; 496 else 497 val &= ~FUSE_SETUP_SEL; 498 writel(val, base + UTMIP_SPARE_CFG0); 499 500 if (!phy->is_legacy_phy) { 501 val = readl(base + USB_SUSP_CTRL); 502 val |= UTMIP_PHY_ENABLE; 503 writel(val, base + USB_SUSP_CTRL); 504 } 505 506 val = readl(base + USB_SUSP_CTRL); 507 val &= ~UTMIP_RESET; 508 writel(val, base + USB_SUSP_CTRL); 509 510 if (phy->is_legacy_phy) { 511 val = readl(base + USB1_LEGACY_CTRL); 512 val &= ~USB1_VBUS_SENSE_CTL_MASK; 513 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; 514 writel(val, base + USB1_LEGACY_CTRL); 515 516 val = readl(base + USB_SUSP_CTRL); 517 val &= ~USB_SUSP_SET; 518 writel(val, base + USB_SUSP_CTRL); 519 } 520 521 utmi_phy_clk_enable(phy); 522 523 if (phy->soc_config->requires_usbmode_setup) { 524 val = readl(base + USB_USBMODE); 525 val &= ~USB_USBMODE_MASK; 526 if (phy->mode == USB_DR_MODE_HOST) 527 val |= USB_USBMODE_HOST; 528 else 529 val |= USB_USBMODE_DEVICE; 530 writel(val, base + USB_USBMODE); 531 } 532 533 if (!phy->is_legacy_phy) 534 set_pts(phy, 0); 535 536 return 0; 537 } 538 539 static int utmi_phy_power_off(struct tegra_usb_phy *phy) 540 { 541 unsigned long val; 542 void __iomem *base = phy->regs; 543 544 utmi_phy_clk_disable(phy); 545 546 if (phy->mode == USB_DR_MODE_PERIPHERAL) { 547 val = readl(base + USB_SUSP_CTRL); 548 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 549 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); 550 writel(val, base + USB_SUSP_CTRL); 551 } 552 553 val = readl(base + USB_SUSP_CTRL); 554 val |= UTMIP_RESET; 555 writel(val, base + USB_SUSP_CTRL); 556 557 val = readl(base + UTMIP_BAT_CHRG_CFG0); 558 val |= UTMIP_PD_CHRG; 559 writel(val, base + UTMIP_BAT_CHRG_CFG0); 560 561 val = readl(base + UTMIP_XCVR_CFG0); 562 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 563 UTMIP_FORCE_PDZI_POWERDOWN; 564 writel(val, base + UTMIP_XCVR_CFG0); 565 566 val = readl(base + UTMIP_XCVR_CFG1); 567 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 568 UTMIP_FORCE_PDDR_POWERDOWN; 569 writel(val, base + UTMIP_XCVR_CFG1); 570 571 return utmip_pad_power_off(phy); 572 } 573 574 static void utmi_phy_preresume(struct tegra_usb_phy *phy) 575 { 576 unsigned long val; 577 void __iomem *base = phy->regs; 578 579 val = readl(base + UTMIP_TX_CFG0); 580 val |= UTMIP_HS_DISCON_DISABLE; 581 writel(val, base + UTMIP_TX_CFG0); 582 } 583 584 static void utmi_phy_postresume(struct tegra_usb_phy *phy) 585 { 586 unsigned long val; 587 void __iomem *base = phy->regs; 588 589 val = readl(base + UTMIP_TX_CFG0); 590 val &= ~UTMIP_HS_DISCON_DISABLE; 591 writel(val, base + UTMIP_TX_CFG0); 592 } 593 594 static void utmi_phy_restore_start(struct tegra_usb_phy *phy, 595 enum tegra_usb_phy_port_speed port_speed) 596 { 597 unsigned long val; 598 void __iomem *base = phy->regs; 599 600 val = readl(base + UTMIP_MISC_CFG0); 601 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); 602 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) 603 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; 604 else 605 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; 606 writel(val, base + UTMIP_MISC_CFG0); 607 udelay(1); 608 609 val = readl(base + UTMIP_MISC_CFG0); 610 val |= UTMIP_DPDM_OBSERVE; 611 writel(val, base + UTMIP_MISC_CFG0); 612 udelay(10); 613 } 614 615 static void utmi_phy_restore_end(struct tegra_usb_phy *phy) 616 { 617 unsigned long val; 618 void __iomem *base = phy->regs; 619 620 val = readl(base + UTMIP_MISC_CFG0); 621 val &= ~UTMIP_DPDM_OBSERVE; 622 writel(val, base + UTMIP_MISC_CFG0); 623 udelay(10); 624 } 625 626 static int ulpi_phy_power_on(struct tegra_usb_phy *phy) 627 { 628 int ret; 629 unsigned long val; 630 void __iomem *base = phy->regs; 631 632 ret = gpio_direction_output(phy->reset_gpio, 0); 633 if (ret < 0) { 634 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n", 635 phy->reset_gpio); 636 return ret; 637 } 638 msleep(5); 639 ret = gpio_direction_output(phy->reset_gpio, 1); 640 if (ret < 0) { 641 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n", 642 phy->reset_gpio); 643 return ret; 644 } 645 646 clk_prepare_enable(phy->clk); 647 msleep(1); 648 649 val = readl(base + USB_SUSP_CTRL); 650 val |= UHSIC_RESET; 651 writel(val, base + USB_SUSP_CTRL); 652 653 val = readl(base + ULPI_TIMING_CTRL_0); 654 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; 655 writel(val, base + ULPI_TIMING_CTRL_0); 656 657 val = readl(base + USB_SUSP_CTRL); 658 val |= ULPI_PHY_ENABLE; 659 writel(val, base + USB_SUSP_CTRL); 660 661 val = 0; 662 writel(val, base + ULPI_TIMING_CTRL_1); 663 664 val |= ULPI_DATA_TRIMMER_SEL(4); 665 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 666 val |= ULPI_DIR_TRIMMER_SEL(4); 667 writel(val, base + ULPI_TIMING_CTRL_1); 668 udelay(10); 669 670 val |= ULPI_DATA_TRIMMER_LOAD; 671 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 672 val |= ULPI_DIR_TRIMMER_LOAD; 673 writel(val, base + ULPI_TIMING_CTRL_1); 674 675 /* Fix VbusInvalid due to floating VBUS */ 676 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); 677 if (ret) { 678 pr_err("%s: ulpi write failed\n", __func__); 679 return ret; 680 } 681 682 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); 683 if (ret) { 684 pr_err("%s: ulpi write failed\n", __func__); 685 return ret; 686 } 687 688 val = readl(base + USB_SUSP_CTRL); 689 val |= USB_SUSP_CLR; 690 writel(val, base + USB_SUSP_CTRL); 691 udelay(100); 692 693 val = readl(base + USB_SUSP_CTRL); 694 val &= ~USB_SUSP_CLR; 695 writel(val, base + USB_SUSP_CTRL); 696 697 return 0; 698 } 699 700 static int ulpi_phy_power_off(struct tegra_usb_phy *phy) 701 { 702 clk_disable(phy->clk); 703 return gpio_direction_output(phy->reset_gpio, 0); 704 } 705 706 static void tegra_usb_phy_close(struct tegra_usb_phy *phy) 707 { 708 if (!IS_ERR(phy->vbus)) 709 regulator_disable(phy->vbus); 710 711 clk_disable_unprepare(phy->pll_u); 712 } 713 714 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) 715 { 716 if (phy->is_ulpi_phy) 717 return ulpi_phy_power_on(phy); 718 else 719 return utmi_phy_power_on(phy); 720 } 721 722 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) 723 { 724 if (phy->is_ulpi_phy) 725 return ulpi_phy_power_off(phy); 726 else 727 return utmi_phy_power_off(phy); 728 } 729 730 static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) 731 { 732 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 733 if (suspend) 734 return tegra_usb_phy_power_off(phy); 735 else 736 return tegra_usb_phy_power_on(phy); 737 } 738 739 static int ulpi_open(struct tegra_usb_phy *phy) 740 { 741 int err; 742 743 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link"); 744 if (IS_ERR(phy->clk)) { 745 pr_err("%s: can't get ulpi clock\n", __func__); 746 return PTR_ERR(phy->clk); 747 } 748 749 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio, 750 "ulpi_phy_reset_b"); 751 if (err < 0) { 752 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n", 753 phy->reset_gpio); 754 return err; 755 } 756 757 err = gpio_direction_output(phy->reset_gpio, 0); 758 if (err < 0) { 759 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n", 760 phy->reset_gpio); 761 return err; 762 } 763 764 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 765 if (!phy->ulpi) { 766 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n"); 767 err = -ENOMEM; 768 return err; 769 } 770 771 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; 772 return 0; 773 } 774 775 static int tegra_usb_phy_init(struct tegra_usb_phy *phy) 776 { 777 unsigned long parent_rate; 778 int i; 779 int err; 780 781 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u"); 782 if (IS_ERR(phy->pll_u)) { 783 pr_err("Can't get pll_u clock\n"); 784 return PTR_ERR(phy->pll_u); 785 } 786 787 err = clk_prepare_enable(phy->pll_u); 788 if (err) 789 return err; 790 791 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); 792 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { 793 if (tegra_freq_table[i].freq == parent_rate) { 794 phy->freq = &tegra_freq_table[i]; 795 break; 796 } 797 } 798 if (!phy->freq) { 799 pr_err("invalid pll_u parent rate %ld\n", parent_rate); 800 err = -EINVAL; 801 goto fail; 802 } 803 804 if (!IS_ERR(phy->vbus)) { 805 err = regulator_enable(phy->vbus); 806 if (err) { 807 dev_err(phy->u_phy.dev, 808 "failed to enable usb vbus regulator: %d\n", 809 err); 810 goto fail; 811 } 812 } 813 814 if (phy->is_ulpi_phy) 815 err = ulpi_open(phy); 816 else 817 err = utmip_pad_open(phy); 818 if (err < 0) 819 goto fail; 820 821 return 0; 822 823 fail: 824 clk_disable_unprepare(phy->pll_u); 825 return err; 826 } 827 828 void tegra_usb_phy_preresume(struct usb_phy *x) 829 { 830 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 831 832 if (!phy->is_ulpi_phy) 833 utmi_phy_preresume(phy); 834 } 835 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); 836 837 void tegra_usb_phy_postresume(struct usb_phy *x) 838 { 839 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 840 841 if (!phy->is_ulpi_phy) 842 utmi_phy_postresume(phy); 843 } 844 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); 845 846 void tegra_ehci_phy_restore_start(struct usb_phy *x, 847 enum tegra_usb_phy_port_speed port_speed) 848 { 849 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 850 851 if (!phy->is_ulpi_phy) 852 utmi_phy_restore_start(phy, port_speed); 853 } 854 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); 855 856 void tegra_ehci_phy_restore_end(struct usb_phy *x) 857 { 858 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 859 860 if (!phy->is_ulpi_phy) 861 utmi_phy_restore_end(phy); 862 } 863 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); 864 865 static int read_utmi_param(struct platform_device *pdev, const char *param, 866 u8 *dest) 867 { 868 u32 value; 869 int err = of_property_read_u32(pdev->dev.of_node, param, &value); 870 *dest = (u8)value; 871 if (err < 0) 872 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n", 873 param, err); 874 return err; 875 } 876 877 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, 878 struct platform_device *pdev) 879 { 880 struct resource *res; 881 int err; 882 struct tegra_utmip_config *config; 883 884 tegra_phy->is_ulpi_phy = false; 885 886 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 887 if (!res) { 888 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n"); 889 return -ENXIO; 890 } 891 892 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, 893 resource_size(res)); 894 if (!tegra_phy->pad_regs) { 895 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n"); 896 return -ENOMEM; 897 } 898 899 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config), 900 GFP_KERNEL); 901 if (!tegra_phy->config) 902 return -ENOMEM; 903 904 config = tegra_phy->config; 905 906 err = read_utmi_param(pdev, "nvidia,hssync-start-delay", 907 &config->hssync_start_delay); 908 if (err < 0) 909 return err; 910 911 err = read_utmi_param(pdev, "nvidia,elastic-limit", 912 &config->elastic_limit); 913 if (err < 0) 914 return err; 915 916 err = read_utmi_param(pdev, "nvidia,idle-wait-delay", 917 &config->idle_wait_delay); 918 if (err < 0) 919 return err; 920 921 err = read_utmi_param(pdev, "nvidia,term-range-adj", 922 &config->term_range_adj); 923 if (err < 0) 924 return err; 925 926 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew", 927 &config->xcvr_lsfslew); 928 if (err < 0) 929 return err; 930 931 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew", 932 &config->xcvr_lsrslew); 933 if (err < 0) 934 return err; 935 936 if (tegra_phy->soc_config->requires_extra_tuning_parameters) { 937 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew", 938 &config->xcvr_hsslew); 939 if (err < 0) 940 return err; 941 942 err = read_utmi_param(pdev, "nvidia,hssquelch-level", 943 &config->hssquelch_level); 944 if (err < 0) 945 return err; 946 947 err = read_utmi_param(pdev, "nvidia,hsdiscon-level", 948 &config->hsdiscon_level); 949 if (err < 0) 950 return err; 951 } 952 953 config->xcvr_setup_use_fuses = of_property_read_bool( 954 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses"); 955 956 if (!config->xcvr_setup_use_fuses) { 957 err = read_utmi_param(pdev, "nvidia,xcvr-setup", 958 &config->xcvr_setup); 959 if (err < 0) 960 return err; 961 } 962 963 return 0; 964 } 965 966 static const struct tegra_phy_soc_config tegra20_soc_config = { 967 .utmi_pll_config_in_car_module = false, 968 .has_hostpc = false, 969 .requires_usbmode_setup = false, 970 .requires_extra_tuning_parameters = false, 971 }; 972 973 static const struct tegra_phy_soc_config tegra30_soc_config = { 974 .utmi_pll_config_in_car_module = true, 975 .has_hostpc = true, 976 .requires_usbmode_setup = true, 977 .requires_extra_tuning_parameters = true, 978 }; 979 980 static const struct of_device_id tegra_usb_phy_id_table[] = { 981 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config }, 982 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config }, 983 { }, 984 }; 985 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); 986 987 static int tegra_usb_phy_probe(struct platform_device *pdev) 988 { 989 const struct of_device_id *match; 990 struct resource *res; 991 struct tegra_usb_phy *tegra_phy = NULL; 992 struct device_node *np = pdev->dev.of_node; 993 enum usb_phy_interface phy_type; 994 int err; 995 996 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); 997 if (!tegra_phy) 998 return -ENOMEM; 999 1000 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev); 1001 if (!match) { 1002 dev_err(&pdev->dev, "Error: No device match found\n"); 1003 return -ENODEV; 1004 } 1005 tegra_phy->soc_config = match->data; 1006 1007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1008 if (!res) { 1009 dev_err(&pdev->dev, "Failed to get I/O memory\n"); 1010 return -ENXIO; 1011 } 1012 1013 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, 1014 resource_size(res)); 1015 if (!tegra_phy->regs) { 1016 dev_err(&pdev->dev, "Failed to remap I/O memory\n"); 1017 return -ENOMEM; 1018 } 1019 1020 tegra_phy->is_legacy_phy = 1021 of_property_read_bool(np, "nvidia,has-legacy-mode"); 1022 1023 phy_type = of_usb_get_phy_mode(np); 1024 switch (phy_type) { 1025 case USBPHY_INTERFACE_MODE_UTMI: 1026 err = utmi_phy_probe(tegra_phy, pdev); 1027 if (err < 0) 1028 return err; 1029 break; 1030 1031 case USBPHY_INTERFACE_MODE_ULPI: 1032 tegra_phy->is_ulpi_phy = true; 1033 1034 tegra_phy->reset_gpio = 1035 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0); 1036 if (!gpio_is_valid(tegra_phy->reset_gpio)) { 1037 dev_err(&pdev->dev, "invalid gpio: %d\n", 1038 tegra_phy->reset_gpio); 1039 return tegra_phy->reset_gpio; 1040 } 1041 tegra_phy->config = NULL; 1042 break; 1043 1044 default: 1045 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n"); 1046 return -EINVAL; 1047 } 1048 1049 if (of_find_property(np, "dr_mode", NULL)) 1050 tegra_phy->mode = usb_get_dr_mode(&pdev->dev); 1051 else 1052 tegra_phy->mode = USB_DR_MODE_HOST; 1053 1054 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) { 1055 dev_err(&pdev->dev, "dr_mode is invalid\n"); 1056 return -EINVAL; 1057 } 1058 1059 /* On some boards, the VBUS regulator doesn't need to be controlled */ 1060 if (of_find_property(np, "vbus-supply", NULL)) { 1061 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus"); 1062 if (IS_ERR(tegra_phy->vbus)) 1063 return PTR_ERR(tegra_phy->vbus); 1064 } else { 1065 dev_notice(&pdev->dev, "no vbus regulator"); 1066 tegra_phy->vbus = ERR_PTR(-ENODEV); 1067 } 1068 1069 tegra_phy->u_phy.dev = &pdev->dev; 1070 err = tegra_usb_phy_init(tegra_phy); 1071 if (err < 0) 1072 return err; 1073 1074 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend; 1075 1076 platform_set_drvdata(pdev, tegra_phy); 1077 1078 err = usb_add_phy_dev(&tegra_phy->u_phy); 1079 if (err < 0) { 1080 tegra_usb_phy_close(tegra_phy); 1081 return err; 1082 } 1083 1084 return 0; 1085 } 1086 1087 static int tegra_usb_phy_remove(struct platform_device *pdev) 1088 { 1089 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev); 1090 1091 usb_remove_phy(&tegra_phy->u_phy); 1092 tegra_usb_phy_close(tegra_phy); 1093 1094 return 0; 1095 } 1096 1097 static struct platform_driver tegra_usb_phy_driver = { 1098 .probe = tegra_usb_phy_probe, 1099 .remove = tegra_usb_phy_remove, 1100 .driver = { 1101 .name = "tegra-phy", 1102 .of_match_table = tegra_usb_phy_id_table, 1103 }, 1104 }; 1105 module_platform_driver(tegra_usb_phy_driver); 1106 1107 MODULE_DESCRIPTION("Tegra USB PHY driver"); 1108 MODULE_LICENSE("GPL v2"); 1109