1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012-2014 Freescale Semiconductor, Inc. 4 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 5 * on behalf of DENX Software Engineering GmbH 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/platform_device.h> 11 #include <linux/clk.h> 12 #include <linux/usb/otg.h> 13 #include <linux/stmp_device.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/iopoll.h> 21 #include <linux/regulator/consumer.h> 22 23 #define DRIVER_NAME "mxs_phy" 24 25 /* Register Macro */ 26 #define HW_USBPHY_PWD 0x00 27 #define HW_USBPHY_TX 0x10 28 #define HW_USBPHY_CTRL 0x30 29 #define HW_USBPHY_CTRL_SET 0x34 30 #define HW_USBPHY_CTRL_CLR 0x38 31 32 #define HW_USBPHY_DEBUG_SET 0x54 33 #define HW_USBPHY_DEBUG_CLR 0x58 34 35 #define HW_USBPHY_IP 0x90 36 #define HW_USBPHY_IP_SET 0x94 37 #define HW_USBPHY_IP_CLR 0x98 38 39 #define GM_USBPHY_TX_TXCAL45DP(x) (((x) & 0xf) << 16) 40 #define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) 41 #define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) 42 43 /* imx7ulp */ 44 #define HW_USBPHY_PLL_SIC 0xa0 45 #define HW_USBPHY_PLL_SIC_SET 0xa4 46 #define HW_USBPHY_PLL_SIC_CLR 0xa8 47 48 #define BM_USBPHY_CTRL_SFTRST BIT(31) 49 #define BM_USBPHY_CTRL_CLKGATE BIT(30) 50 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) 51 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 52 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 53 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) 54 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) 55 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) 56 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 57 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 58 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 59 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 60 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 61 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 62 63 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) 64 65 #define BM_USBPHY_DEBUG_CLKGATE BIT(30) 66 /* imx7ulp */ 67 #define BM_USBPHY_PLL_LOCK BIT(31) 68 #define BM_USBPHY_PLL_REG_ENABLE BIT(21) 69 #define BM_USBPHY_PLL_BYPASS BIT(16) 70 #define BM_USBPHY_PLL_POWER BIT(12) 71 #define BM_USBPHY_PLL_EN_USB_CLKS BIT(6) 72 73 /* Anatop Registers */ 74 #define ANADIG_REG_1P1_SET 0x114 75 #define ANADIG_REG_1P1_CLR 0x118 76 77 #define ANADIG_ANA_MISC0 0x150 78 #define ANADIG_ANA_MISC0_SET 0x154 79 #define ANADIG_ANA_MISC0_CLR 0x158 80 81 #define ANADIG_USB1_CHRG_DETECT_SET 0x1b4 82 #define ANADIG_USB1_CHRG_DETECT_CLR 0x1b8 83 #define ANADIG_USB2_CHRG_DETECT_SET 0x214 84 #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20) 85 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19) 86 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18) 87 88 #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 89 #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 90 91 #define ANADIG_USB1_CHRG_DET_STAT 0x1d0 92 #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2) 93 #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1) 94 #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0) 95 96 #define ANADIG_USB2_VBUS_DET_STAT 0x220 97 98 #define ANADIG_USB1_LOOPBACK_SET 0x1e4 99 #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 100 #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0) 101 102 #define ANADIG_USB2_LOOPBACK_SET 0x244 103 #define ANADIG_USB2_LOOPBACK_CLR 0x248 104 105 #define ANADIG_USB1_MISC 0x1f0 106 #define ANADIG_USB2_MISC 0x250 107 108 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) 109 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) 110 111 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 112 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) 113 114 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) 115 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) 116 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) 117 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) 118 119 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29) 120 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28) 121 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29) 122 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28) 123 124 /* System Integration Module (SIM) Registers */ 125 #define SIM_GPR1 0x30 126 127 #define USB_PHY_VLLS_WAKEUP_EN BIT(0) 128 129 #define BM_ANADIG_REG_1P1_ENABLE_WEAK_LINREG BIT(18) 130 #define BM_ANADIG_REG_1P1_TRACK_VDD_SOC_CAP BIT(19) 131 132 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 133 134 /* Do disconnection between PHY and controller without vbus */ 135 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 136 137 /* 138 * The PHY will be in messy if there is a wakeup after putting 139 * bus to suspend (set portsc.suspendM) but before setting PHY to low 140 * power mode (set portsc.phcd). 141 */ 142 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 143 144 /* 145 * The SOF sends too fast after resuming, it will cause disconnection 146 * between host and high speed device. 147 */ 148 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 149 150 /* 151 * IC has bug fixes logic, they include 152 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST 153 * which are described at above flags, the RTL will handle it 154 * according to different versions. 155 */ 156 #define MXS_PHY_NEED_IP_FIX BIT(3) 157 158 /* Minimum and maximum values for device tree entries */ 159 #define MXS_PHY_TX_CAL45_MIN 35 160 #define MXS_PHY_TX_CAL45_MAX 54 161 #define MXS_PHY_TX_D_CAL_MIN 79 162 #define MXS_PHY_TX_D_CAL_MAX 119 163 164 /* 165 * At imx6q/6sl/6sx, the PHY2's clock is controlled by hardware directly, 166 * eg, according to PHY's suspend status. In these PHYs, we only need to 167 * open the clock at the initialization and close it at its shutdown routine. 168 * These PHYs can send resume signal without software interfere if not 169 * gate clock. 170 */ 171 #define MXS_PHY_HARDWARE_CONTROL_PHY2_CLK BIT(4) 172 173 struct mxs_phy_data { 174 unsigned int flags; 175 }; 176 177 static const struct mxs_phy_data imx23_phy_data = { 178 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 179 }; 180 181 static const struct mxs_phy_data imx6q_phy_data = { 182 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 183 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 184 MXS_PHY_NEED_IP_FIX | 185 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK, 186 }; 187 188 static const struct mxs_phy_data imx6sl_phy_data = { 189 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 190 MXS_PHY_NEED_IP_FIX | 191 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK, 192 }; 193 194 static const struct mxs_phy_data vf610_phy_data = { 195 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 196 MXS_PHY_NEED_IP_FIX, 197 }; 198 199 static const struct mxs_phy_data imx6sx_phy_data = { 200 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 201 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK, 202 }; 203 204 static const struct mxs_phy_data imx6ul_phy_data = { 205 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 206 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK, 207 }; 208 209 static const struct mxs_phy_data imx7ulp_phy_data = { 210 }; 211 212 static const struct of_device_id mxs_phy_dt_ids[] = { 213 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, 214 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 215 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 216 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 217 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, 218 { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, }, 219 { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, }, 220 { /* sentinel */ } 221 }; 222 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 223 224 struct mxs_phy { 225 struct usb_phy phy; 226 struct clk *clk; 227 const struct mxs_phy_data *data; 228 struct regmap *regmap_anatop; 229 struct regmap *regmap_sim; 230 int port_id; 231 u32 tx_reg_set; 232 u32 tx_reg_mask; 233 struct regulator *phy_3p0; 234 }; 235 236 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) 237 { 238 return mxs_phy->data == &imx6q_phy_data; 239 } 240 241 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) 242 { 243 return mxs_phy->data == &imx6sl_phy_data; 244 } 245 246 static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy) 247 { 248 return mxs_phy->data == &imx7ulp_phy_data; 249 } 250 251 static inline bool is_imx6ul_phy(struct mxs_phy *mxs_phy) 252 { 253 return mxs_phy->data == &imx6ul_phy_data; 254 } 255 256 /* 257 * PHY needs some 32K cycles to switch from 32K clock to 258 * bus (such as AHB/AXI, etc) clock. 259 */ 260 static void mxs_phy_clock_switch_delay(void) 261 { 262 usleep_range(300, 400); 263 } 264 265 static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) 266 { 267 void __iomem *base = mxs_phy->phy.io_priv; 268 u32 phytx; 269 270 /* Update TX register if there is anything to write */ 271 if (mxs_phy->tx_reg_mask) { 272 phytx = readl(base + HW_USBPHY_TX); 273 phytx &= ~mxs_phy->tx_reg_mask; 274 phytx |= mxs_phy->tx_reg_set; 275 writel(phytx, base + HW_USBPHY_TX); 276 } 277 } 278 279 static int mxs_phy_pll_enable(void __iomem *base, bool enable) 280 { 281 int ret = 0; 282 283 if (enable) { 284 u32 value; 285 286 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET); 287 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR); 288 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET); 289 ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC, 290 value, (value & BM_USBPHY_PLL_LOCK) != 0, 291 100, 10000); 292 if (ret) 293 return ret; 294 295 writel(BM_USBPHY_PLL_EN_USB_CLKS, base + 296 HW_USBPHY_PLL_SIC_SET); 297 } else { 298 writel(BM_USBPHY_PLL_EN_USB_CLKS, base + 299 HW_USBPHY_PLL_SIC_CLR); 300 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR); 301 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET); 302 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR); 303 } 304 305 return ret; 306 } 307 308 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 309 { 310 int ret; 311 void __iomem *base = mxs_phy->phy.io_priv; 312 313 if (is_imx7ulp_phy(mxs_phy)) { 314 ret = mxs_phy_pll_enable(base, true); 315 if (ret) 316 return ret; 317 } 318 319 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 320 if (ret) 321 goto disable_pll; 322 323 if (mxs_phy->phy_3p0) { 324 ret = regulator_enable(mxs_phy->phy_3p0); 325 if (ret) { 326 dev_err(mxs_phy->phy.dev, 327 "Failed to enable 3p0 regulator, ret=%d\n", 328 ret); 329 return ret; 330 } 331 } 332 333 /* Power up the PHY */ 334 writel(0, base + HW_USBPHY_PWD); 335 336 /* 337 * USB PHY Ctrl Setting 338 * - Auto clock/power on 339 * - Enable full/low speed support 340 */ 341 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 342 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 343 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 344 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 345 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 346 BM_USBPHY_CTRL_ENUTMILEVEL2 | 347 BM_USBPHY_CTRL_ENUTMILEVEL3, 348 base + HW_USBPHY_CTRL_SET); 349 350 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) 351 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); 352 353 if (mxs_phy->regmap_anatop) { 354 unsigned int reg = mxs_phy->port_id ? 355 ANADIG_USB1_CHRG_DETECT_SET : 356 ANADIG_USB2_CHRG_DETECT_SET; 357 /* 358 * The external charger detector needs to be disabled, 359 * or the signal at DP will be poor 360 */ 361 regmap_write(mxs_phy->regmap_anatop, reg, 362 ANADIG_USB1_CHRG_DETECT_EN_B | 363 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 364 } 365 366 mxs_phy_tx_init(mxs_phy); 367 368 return 0; 369 370 disable_pll: 371 if (is_imx7ulp_phy(mxs_phy)) 372 mxs_phy_pll_enable(base, false); 373 return ret; 374 } 375 376 /* Return true if the vbus is there */ 377 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) 378 { 379 unsigned int vbus_value = 0; 380 381 if (!mxs_phy->regmap_anatop) 382 return false; 383 384 if (mxs_phy->port_id == 0) 385 regmap_read(mxs_phy->regmap_anatop, 386 ANADIG_USB1_VBUS_DET_STAT, 387 &vbus_value); 388 else if (mxs_phy->port_id == 1) 389 regmap_read(mxs_phy->regmap_anatop, 390 ANADIG_USB2_VBUS_DET_STAT, 391 &vbus_value); 392 393 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) 394 return true; 395 else 396 return false; 397 } 398 399 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) 400 { 401 void __iomem *base = mxs_phy->phy.io_priv; 402 u32 reg; 403 404 if (disconnect) 405 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 406 base + HW_USBPHY_DEBUG_CLR); 407 408 if (mxs_phy->port_id == 0) { 409 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET 410 : ANADIG_USB1_LOOPBACK_CLR; 411 regmap_write(mxs_phy->regmap_anatop, reg, 412 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | 413 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); 414 } else if (mxs_phy->port_id == 1) { 415 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET 416 : ANADIG_USB2_LOOPBACK_CLR; 417 regmap_write(mxs_phy->regmap_anatop, reg, 418 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | 419 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); 420 } 421 422 if (!disconnect) 423 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 424 base + HW_USBPHY_DEBUG_SET); 425 426 /* Delay some time, and let Linestate be SE0 for controller */ 427 if (disconnect) 428 usleep_range(500, 1000); 429 } 430 431 static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) 432 { 433 return mxs_phy->phy.last_event == USB_EVENT_ID; 434 } 435 436 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) 437 { 438 bool vbus_is_on = false; 439 enum usb_phy_events last_event = mxs_phy->phy.last_event; 440 441 /* If the SoCs don't need to disconnect line without vbus, quit */ 442 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) 443 return; 444 445 /* If the SoCs don't have anatop, quit */ 446 if (!mxs_phy->regmap_anatop) 447 return; 448 449 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 450 451 if (on && ((!vbus_is_on && !mxs_phy_is_otg_host(mxs_phy)) 452 || (last_event == USB_EVENT_VBUS))) 453 __mxs_phy_disconnect_line(mxs_phy, true); 454 else 455 __mxs_phy_disconnect_line(mxs_phy, false); 456 457 } 458 459 static int mxs_phy_init(struct usb_phy *phy) 460 { 461 int ret; 462 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 463 464 mxs_phy_clock_switch_delay(); 465 ret = clk_prepare_enable(mxs_phy->clk); 466 if (ret) 467 return ret; 468 469 return mxs_phy_hw_init(mxs_phy); 470 } 471 472 static void mxs_phy_shutdown(struct usb_phy *phy) 473 { 474 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 475 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 476 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 477 BM_USBPHY_CTRL_ENIDCHG_WKUP | 478 BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 479 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 480 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 481 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 482 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; 483 484 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); 485 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); 486 487 writel(BM_USBPHY_CTRL_CLKGATE, 488 phy->io_priv + HW_USBPHY_CTRL_SET); 489 490 if (is_imx7ulp_phy(mxs_phy)) 491 mxs_phy_pll_enable(phy->io_priv, false); 492 493 if (mxs_phy->phy_3p0) 494 regulator_disable(mxs_phy->phy_3p0); 495 496 clk_disable_unprepare(mxs_phy->clk); 497 } 498 499 static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy) 500 { 501 unsigned int line_state; 502 /* bit definition is the same for all controllers */ 503 unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS, 504 dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS; 505 unsigned int reg = ANADIG_USB1_MISC; 506 507 /* If the SoCs don't have anatop, quit */ 508 if (!mxs_phy->regmap_anatop) 509 return false; 510 511 if (mxs_phy->port_id == 0) 512 reg = ANADIG_USB1_MISC; 513 else if (mxs_phy->port_id == 1) 514 reg = ANADIG_USB2_MISC; 515 516 regmap_read(mxs_phy->regmap_anatop, reg, &line_state); 517 518 if ((line_state & (dp_bit | dm_bit)) == dm_bit) 519 return true; 520 else 521 return false; 522 } 523 524 static int mxs_phy_suspend(struct usb_phy *x, int suspend) 525 { 526 int ret; 527 struct mxs_phy *mxs_phy = to_mxs_phy(x); 528 bool low_speed_connection, vbus_is_on; 529 530 low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy); 531 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 532 533 if (suspend) { 534 /* 535 * FIXME: Do not power down RXPWD1PT1 bit for low speed 536 * connect. The low speed connection will have problem at 537 * very rare cases during usb suspend and resume process. 538 */ 539 if (low_speed_connection & vbus_is_on) { 540 /* 541 * If value to be set as pwd value is not 0xffffffff, 542 * several 32Khz cycles are needed. 543 */ 544 mxs_phy_clock_switch_delay(); 545 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); 546 } else { 547 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 548 } 549 writel(BM_USBPHY_CTRL_CLKGATE, 550 x->io_priv + HW_USBPHY_CTRL_SET); 551 if (!(mxs_phy->port_id == 1 && 552 (mxs_phy->data->flags & 553 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK))) 554 clk_disable_unprepare(mxs_phy->clk); 555 } else { 556 mxs_phy_clock_switch_delay(); 557 if (!(mxs_phy->port_id == 1 && 558 (mxs_phy->data->flags & 559 MXS_PHY_HARDWARE_CONTROL_PHY2_CLK))) { 560 ret = clk_prepare_enable(mxs_phy->clk); 561 if (ret) 562 return ret; 563 } 564 writel(BM_USBPHY_CTRL_CLKGATE, 565 x->io_priv + HW_USBPHY_CTRL_CLR); 566 writel(0, x->io_priv + HW_USBPHY_PWD); 567 } 568 569 return 0; 570 } 571 572 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) 573 { 574 struct mxs_phy *mxs_phy = to_mxs_phy(x); 575 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 576 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 577 BM_USBPHY_CTRL_ENIDCHG_WKUP; 578 if (enabled) { 579 mxs_phy_disconnect_line(mxs_phy, true); 580 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); 581 } else { 582 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); 583 mxs_phy_disconnect_line(mxs_phy, false); 584 } 585 586 return 0; 587 } 588 589 static int mxs_phy_on_connect(struct usb_phy *phy, 590 enum usb_device_speed speed) 591 { 592 dev_dbg(phy->dev, "%s device has connected\n", 593 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 594 595 if (speed == USB_SPEED_HIGH) 596 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 597 phy->io_priv + HW_USBPHY_CTRL_SET); 598 599 return 0; 600 } 601 602 static int mxs_phy_on_disconnect(struct usb_phy *phy, 603 enum usb_device_speed speed) 604 { 605 dev_dbg(phy->dev, "%s device has disconnected\n", 606 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 607 608 /* Sometimes, the speed is not high speed when the error occurs */ 609 if (readl(phy->io_priv + HW_USBPHY_CTRL) & 610 BM_USBPHY_CTRL_ENHOSTDISCONDETECT) 611 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 612 phy->io_priv + HW_USBPHY_CTRL_CLR); 613 614 return 0; 615 } 616 617 #define MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT 100 618 static int mxs_charger_data_contact_detect(struct mxs_phy *x) 619 { 620 struct regmap *regmap = x->regmap_anatop; 621 int i, stable_contact_count = 0; 622 u32 val; 623 624 /* Check if vbus is valid */ 625 regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val); 626 if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) { 627 dev_err(x->phy.dev, "vbus is not valid\n"); 628 return -EINVAL; 629 } 630 631 /* Enable charger detector */ 632 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 633 ANADIG_USB1_CHRG_DETECT_EN_B); 634 /* 635 * - Do not check whether a charger is connected to the USB port 636 * - Check whether the USB plug has been in contact with each other 637 */ 638 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 639 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 640 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 641 642 /* Check if plug is connected */ 643 for (i = 0; i < MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT; i++) { 644 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 645 if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) { 646 stable_contact_count++; 647 if (stable_contact_count > 5) 648 /* Data pin makes contact */ 649 break; 650 else 651 usleep_range(5000, 10000); 652 } else { 653 stable_contact_count = 0; 654 usleep_range(5000, 6000); 655 } 656 } 657 658 if (i == MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT) { 659 dev_err(x->phy.dev, 660 "Data pin can't make good contact.\n"); 661 /* Disable charger detector */ 662 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 663 ANADIG_USB1_CHRG_DETECT_EN_B | 664 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 665 return -ENXIO; 666 } 667 668 return 0; 669 } 670 671 static enum usb_charger_type mxs_charger_primary_detection(struct mxs_phy *x) 672 { 673 struct regmap *regmap = x->regmap_anatop; 674 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 675 u32 val; 676 677 /* 678 * - Do check whether a charger is connected to the USB port 679 * - Do not Check whether the USB plug has been in contact with 680 * each other 681 */ 682 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 683 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 684 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 685 686 msleep(100); 687 688 /* Check if it is a charger */ 689 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 690 if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) { 691 chgr_type = SDP_TYPE; 692 dev_dbg(x->phy.dev, "It is a standard downstream port\n"); 693 } 694 695 /* Disable charger detector */ 696 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 697 ANADIG_USB1_CHRG_DETECT_EN_B | 698 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 699 700 return chgr_type; 701 } 702 703 /* 704 * It must be called after DP is pulled up, which is used to 705 * differentiate DCP and CDP. 706 */ 707 static enum usb_charger_type mxs_charger_secondary_detection(struct mxs_phy *x) 708 { 709 struct regmap *regmap = x->regmap_anatop; 710 int val; 711 712 msleep(80); 713 714 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 715 if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) { 716 dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); 717 return DCP_TYPE; 718 } else { 719 dev_dbg(x->phy.dev, "It is a charging downstream port\n"); 720 return CDP_TYPE; 721 } 722 } 723 724 static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy) 725 { 726 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 727 struct regmap *regmap = mxs_phy->regmap_anatop; 728 void __iomem *base = phy->io_priv; 729 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 730 731 if (!regmap) 732 return UNKNOWN_TYPE; 733 734 if (mxs_charger_data_contact_detect(mxs_phy)) 735 return chgr_type; 736 737 chgr_type = mxs_charger_primary_detection(mxs_phy); 738 739 if (chgr_type != SDP_TYPE) { 740 /* Pull up DP via test */ 741 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 742 base + HW_USBPHY_DEBUG_CLR); 743 regmap_write(regmap, ANADIG_USB1_LOOPBACK_SET, 744 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 745 746 chgr_type = mxs_charger_secondary_detection(mxs_phy); 747 748 /* Stop the test */ 749 regmap_write(regmap, ANADIG_USB1_LOOPBACK_CLR, 750 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 751 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 752 base + HW_USBPHY_DEBUG_SET); 753 } 754 755 return chgr_type; 756 } 757 758 static int mxs_phy_probe(struct platform_device *pdev) 759 { 760 void __iomem *base; 761 struct clk *clk; 762 struct mxs_phy *mxs_phy; 763 int ret; 764 struct device_node *np = pdev->dev.of_node; 765 u32 val; 766 767 base = devm_platform_ioremap_resource(pdev, 0); 768 if (IS_ERR(base)) 769 return PTR_ERR(base); 770 771 clk = devm_clk_get(&pdev->dev, NULL); 772 if (IS_ERR(clk)) { 773 dev_err(&pdev->dev, 774 "can't get the clock, err=%ld", PTR_ERR(clk)); 775 return PTR_ERR(clk); 776 } 777 778 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 779 if (!mxs_phy) 780 return -ENOMEM; 781 782 /* Some SoCs don't have anatop registers */ 783 if (of_property_present(np, "fsl,anatop")) { 784 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 785 (np, "fsl,anatop"); 786 if (IS_ERR(mxs_phy->regmap_anatop)) { 787 dev_dbg(&pdev->dev, 788 "failed to find regmap for anatop\n"); 789 return PTR_ERR(mxs_phy->regmap_anatop); 790 } 791 } 792 793 /* Currently, only imx7ulp has SIM module */ 794 if (of_get_property(np, "nxp,sim", NULL)) { 795 mxs_phy->regmap_sim = syscon_regmap_lookup_by_phandle 796 (np, "nxp,sim"); 797 if (IS_ERR(mxs_phy->regmap_sim)) { 798 dev_dbg(&pdev->dev, 799 "failed to find regmap for sim\n"); 800 return PTR_ERR(mxs_phy->regmap_sim); 801 } 802 } 803 804 /* Precompute which bits of the TX register are to be updated, if any */ 805 if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && 806 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 807 /* Scale to a 4-bit value */ 808 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 809 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 810 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); 811 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); 812 } 813 814 if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && 815 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 816 /* Scale to a 4-bit value. */ 817 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 818 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 819 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); 820 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); 821 } 822 823 if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && 824 val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) { 825 /* Scale to a 4-bit value. Round up the values and heavily 826 * weight the rounding by adding 2/3 of the denominator. 827 */ 828 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF 829 + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) 830 / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); 831 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); 832 mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); 833 } 834 835 ret = of_alias_get_id(np, "usbphy"); 836 if (ret < 0) 837 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); 838 mxs_phy->port_id = ret; 839 840 mxs_phy->phy.io_priv = base; 841 mxs_phy->phy.dev = &pdev->dev; 842 mxs_phy->phy.label = DRIVER_NAME; 843 mxs_phy->phy.init = mxs_phy_init; 844 mxs_phy->phy.shutdown = mxs_phy_shutdown; 845 mxs_phy->phy.set_suspend = mxs_phy_suspend; 846 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 847 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 848 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 849 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; 850 mxs_phy->phy.charger_detect = mxs_phy_charger_detect; 851 852 mxs_phy->clk = clk; 853 mxs_phy->data = of_device_get_match_data(&pdev->dev); 854 855 mxs_phy->phy_3p0 = devm_regulator_get(&pdev->dev, "phy-3p0"); 856 if (PTR_ERR(mxs_phy->phy_3p0) == -ENODEV) 857 /* not exist */ 858 mxs_phy->phy_3p0 = NULL; 859 else if (IS_ERR(mxs_phy->phy_3p0)) 860 return dev_err_probe(&pdev->dev, PTR_ERR(mxs_phy->phy_3p0), 861 "Getting regulator error\n"); 862 863 if (mxs_phy->phy_3p0) 864 regulator_set_voltage(mxs_phy->phy_3p0, 3200000, 3200000); 865 866 platform_set_drvdata(pdev, mxs_phy); 867 868 device_set_wakeup_capable(&pdev->dev, true); 869 870 return usb_add_phy_dev(&mxs_phy->phy); 871 } 872 873 static void mxs_phy_remove(struct platform_device *pdev) 874 { 875 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 876 877 usb_remove_phy(&mxs_phy->phy); 878 } 879 880 #ifdef CONFIG_PM_SLEEP 881 static void mxs_phy_wakeup_enable(struct mxs_phy *mxs_phy, bool on) 882 { 883 u32 mask = USB_PHY_VLLS_WAKEUP_EN; 884 885 /* If the SoCs don't have SIM, quit */ 886 if (!mxs_phy->regmap_sim) 887 return; 888 889 if (on) { 890 regmap_update_bits(mxs_phy->regmap_sim, SIM_GPR1, mask, mask); 891 udelay(500); 892 } else { 893 regmap_update_bits(mxs_phy->regmap_sim, SIM_GPR1, mask, 0); 894 } 895 } 896 897 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) 898 { 899 unsigned int reg; 900 u32 value; 901 902 /* If the SoCs don't have anatop, quit */ 903 if (!mxs_phy->regmap_anatop) 904 return; 905 906 if (is_imx6q_phy(mxs_phy)) { 907 reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 908 regmap_write(mxs_phy->regmap_anatop, reg, 909 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); 910 } else if (is_imx6sl_phy(mxs_phy)) { 911 reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 912 regmap_write(mxs_phy->regmap_anatop, 913 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); 914 } else if (is_imx6ul_phy(mxs_phy)) { 915 reg = on ? ANADIG_REG_1P1_SET : ANADIG_REG_1P1_CLR; 916 value = BM_ANADIG_REG_1P1_ENABLE_WEAK_LINREG | 917 BM_ANADIG_REG_1P1_TRACK_VDD_SOC_CAP; 918 if (mxs_phy_get_vbus_status(mxs_phy) && on) 919 regmap_write(mxs_phy->regmap_anatop, reg, value); 920 else if (!on) 921 regmap_write(mxs_phy->regmap_anatop, reg, value); 922 } 923 } 924 925 static int mxs_phy_system_suspend(struct device *dev) 926 { 927 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 928 929 if (device_may_wakeup(dev)) { 930 mxs_phy_enable_ldo_in_suspend(mxs_phy, true); 931 mxs_phy_wakeup_enable(mxs_phy, true); 932 } 933 934 return 0; 935 } 936 937 static int mxs_phy_system_resume(struct device *dev) 938 { 939 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 940 941 if (device_may_wakeup(dev)) { 942 mxs_phy_enable_ldo_in_suspend(mxs_phy, false); 943 mxs_phy_wakeup_enable(mxs_phy, false); 944 } 945 946 return 0; 947 } 948 #endif /* CONFIG_PM_SLEEP */ 949 950 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, 951 mxs_phy_system_resume); 952 953 static struct platform_driver mxs_phy_driver = { 954 .probe = mxs_phy_probe, 955 .remove_new = mxs_phy_remove, 956 .driver = { 957 .name = DRIVER_NAME, 958 .of_match_table = mxs_phy_dt_ids, 959 .pm = &mxs_phy_pm, 960 }, 961 }; 962 963 static int __init mxs_phy_module_init(void) 964 { 965 return platform_driver_register(&mxs_phy_driver); 966 } 967 postcore_initcall(mxs_phy_module_init); 968 969 static void __exit mxs_phy_module_exit(void) 970 { 971 platform_driver_unregister(&mxs_phy_driver); 972 } 973 module_exit(mxs_phy_module_exit); 974 975 MODULE_ALIAS("platform:mxs-usb-phy"); 976 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 977 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 978 MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 979 MODULE_LICENSE("GPL"); 980