1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2011 Marvell International Ltd. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __MV_USB_OTG_CONTROLLER__ 12 #define __MV_USB_OTG_CONTROLLER__ 13 14 #include <linux/types.h> 15 16 /* Command Register Bit Masks */ 17 #define USBCMD_RUN_STOP (0x00000001) 18 #define USBCMD_CTRL_RESET (0x00000002) 19 20 /* otgsc Register Bit Masks */ 21 #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 22 #define OTGSC_CTRL_VUSB_CHARGE 0x00000002 23 #define OTGSC_CTRL_OTG_TERM 0x00000008 24 #define OTGSC_CTRL_DATA_PULSING 0x00000010 25 #define OTGSC_STS_USB_ID 0x00000100 26 #define OTGSC_STS_A_VBUS_VALID 0x00000200 27 #define OTGSC_STS_A_SESSION_VALID 0x00000400 28 #define OTGSC_STS_B_SESSION_VALID 0x00000800 29 #define OTGSC_STS_B_SESSION_END 0x00001000 30 #define OTGSC_STS_1MS_TOGGLE 0x00002000 31 #define OTGSC_STS_DATA_PULSING 0x00004000 32 #define OTGSC_INTSTS_USB_ID 0x00010000 33 #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 34 #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 35 #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 36 #define OTGSC_INTSTS_B_SESSION_END 0x00100000 37 #define OTGSC_INTSTS_1MS 0x00200000 38 #define OTGSC_INTSTS_DATA_PULSING 0x00400000 39 #define OTGSC_INTR_USB_ID 0x01000000 40 #define OTGSC_INTR_A_VBUS_VALID 0x02000000 41 #define OTGSC_INTR_A_SESSION_VALID 0x04000000 42 #define OTGSC_INTR_B_SESSION_VALID 0x08000000 43 #define OTGSC_INTR_B_SESSION_END 0x10000000 44 #define OTGSC_INTR_1MS_TIMER 0x20000000 45 #define OTGSC_INTR_DATA_PULSING 0x40000000 46 47 #define CAPLENGTH_MASK (0xff) 48 49 /* Timer's interval, unit 10ms */ 50 #define T_A_WAIT_VRISE 100 51 #define T_A_WAIT_BCON 2000 52 #define T_A_AIDL_BDIS 100 53 #define T_A_BIDL_ADIS 20 54 #define T_B_ASE0_BRST 400 55 #define T_B_SE0_SRP 300 56 #define T_B_SRP_FAIL 2000 57 #define T_B_DATA_PLS 10 58 #define T_B_SRP_INIT 100 59 #define T_A_SRP_RSPNS 10 60 #define T_A_DRV_RSM 5 61 62 enum otg_function { 63 OTG_B_DEVICE = 0, 64 OTG_A_DEVICE 65 }; 66 67 enum mv_otg_timer { 68 A_WAIT_BCON_TIMER = 0, 69 OTG_TIMER_NUM 70 }; 71 72 /* PXA OTG state machine */ 73 struct mv_otg_ctrl { 74 /* internal variables */ 75 u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */ 76 u8 b_srp_done; 77 u8 b_hnp_en; 78 79 /* OTG inputs */ 80 u8 a_bus_drop; 81 u8 a_bus_req; 82 u8 a_clr_err; 83 u8 a_bus_resume; 84 u8 a_bus_suspend; 85 u8 a_conn; 86 u8 a_sess_vld; 87 u8 a_srp_det; 88 u8 a_vbus_vld; 89 u8 b_bus_req; /* B-Device Require Bus */ 90 u8 b_bus_resume; 91 u8 b_bus_suspend; 92 u8 b_conn; 93 u8 b_se0_srp; 94 u8 b_sess_end; 95 u8 b_sess_vld; 96 u8 id; 97 u8 a_suspend_req; 98 99 /*Timer event */ 100 u8 a_aidl_bdis_timeout; 101 u8 b_ase0_brst_timeout; 102 u8 a_bidl_adis_timeout; 103 u8 a_wait_bcon_timeout; 104 105 struct timer_list timer[OTG_TIMER_NUM]; 106 }; 107 108 #define VUSBHS_MAX_PORTS 8 109 110 struct mv_otg_regs { 111 u32 usbcmd; /* Command register */ 112 u32 usbsts; /* Status register */ 113 u32 usbintr; /* Interrupt enable */ 114 u32 frindex; /* Frame index */ 115 u32 reserved1[1]; 116 u32 deviceaddr; /* Device Address */ 117 u32 eplistaddr; /* Endpoint List Address */ 118 u32 ttctrl; /* HOST TT status and control */ 119 u32 burstsize; /* Programmable Burst Size */ 120 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */ 121 u32 reserved[4]; 122 u32 epnak; /* Endpoint NAK */ 123 u32 epnaken; /* Endpoint NAK Enable */ 124 u32 configflag; /* Configured Flag register */ 125 u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ 126 u32 otgsc; 127 u32 usbmode; /* USB Host/Device mode */ 128 u32 epsetupstat; /* Endpoint Setup Status */ 129 u32 epprime; /* Endpoint Initialize */ 130 u32 epflush; /* Endpoint De-initialize */ 131 u32 epstatus; /* Endpoint Status */ 132 u32 epcomplete; /* Endpoint Interrupt On Complete */ 133 u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */ 134 u32 mcr; /* Mux Control */ 135 u32 isr; /* Interrupt Status */ 136 u32 ier; /* Interrupt Enable */ 137 }; 138 139 struct mv_otg { 140 struct usb_phy phy; 141 struct mv_otg_ctrl otg_ctrl; 142 143 /* base address */ 144 void __iomem *phy_regs; 145 void __iomem *cap_regs; 146 struct mv_otg_regs __iomem *op_regs; 147 148 struct platform_device *pdev; 149 int irq; 150 u32 irq_status; 151 u32 irq_en; 152 153 struct delayed_work work; 154 struct workqueue_struct *qwork; 155 156 spinlock_t wq_lock; 157 158 struct mv_usb_platform_data *pdata; 159 160 unsigned int active; 161 unsigned int clock_gating; 162 struct clk *clk; 163 }; 164 165 #endif 166