1 /* 2 * drivers/usb/musb/ux500_dma.c 3 * 4 * U8500 DMA support code 5 * 6 * Copyright (C) 2009 STMicroelectronics 7 * Copyright (C) 2011 ST-Ericsson SA 8 * Authors: 9 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> 10 * Praveena Nadahally <praveen.nadahally@stericsson.com> 11 * Rajaram Regupathy <ragupathy.rajaram@stericsson.com> 12 * 13 * This program is free software: you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation, either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program. If not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include <linux/device.h> 28 #include <linux/interrupt.h> 29 #include <linux/platform_device.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/pfn.h> 33 #include <linux/sizes.h> 34 #include <linux/platform_data/usb-musb-ux500.h> 35 #include "musb_core.h" 36 37 static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12", 38 "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" }; 39 static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12", 40 "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" }; 41 42 struct ux500_dma_channel { 43 struct dma_channel channel; 44 struct ux500_dma_controller *controller; 45 struct musb_hw_ep *hw_ep; 46 struct dma_chan *dma_chan; 47 unsigned int cur_len; 48 dma_cookie_t cookie; 49 u8 ch_num; 50 u8 is_tx; 51 u8 is_allocated; 52 }; 53 54 struct ux500_dma_controller { 55 struct dma_controller controller; 56 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; 57 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; 58 void *private_data; 59 dma_addr_t phy_base; 60 }; 61 62 /* Work function invoked from DMA callback to handle rx transfers. */ 63 static void ux500_dma_callback(void *private_data) 64 { 65 struct dma_channel *channel = private_data; 66 struct ux500_dma_channel *ux500_channel = channel->private_data; 67 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 68 struct musb *musb = hw_ep->musb; 69 unsigned long flags; 70 71 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", 72 hw_ep->epnum); 73 74 spin_lock_irqsave(&musb->lock, flags); 75 ux500_channel->channel.actual_len = ux500_channel->cur_len; 76 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE; 77 musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx); 78 spin_unlock_irqrestore(&musb->lock, flags); 79 80 } 81 82 static bool ux500_configure_channel(struct dma_channel *channel, 83 u16 packet_sz, u8 mode, 84 dma_addr_t dma_addr, u32 len) 85 { 86 struct ux500_dma_channel *ux500_channel = channel->private_data; 87 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 88 struct dma_chan *dma_chan = ux500_channel->dma_chan; 89 struct dma_async_tx_descriptor *dma_desc; 90 enum dma_transfer_direction direction; 91 struct scatterlist sg; 92 struct dma_slave_config slave_conf; 93 enum dma_slave_buswidth addr_width; 94 struct musb *musb = ux500_channel->controller->private_data; 95 dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) + 96 ux500_channel->controller->phy_base); 97 98 dev_dbg(musb->controller, 99 "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n", 100 packet_sz, mode, (unsigned long long) dma_addr, 101 len, ux500_channel->is_tx); 102 103 ux500_channel->cur_len = len; 104 105 sg_init_table(&sg, 1); 106 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len, 107 offset_in_page(dma_addr)); 108 sg_dma_address(&sg) = dma_addr; 109 sg_dma_len(&sg) = len; 110 111 direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 112 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE : 113 DMA_SLAVE_BUSWIDTH_4_BYTES; 114 115 slave_conf.direction = direction; 116 slave_conf.src_addr = usb_fifo_addr; 117 slave_conf.src_addr_width = addr_width; 118 slave_conf.src_maxburst = 16; 119 slave_conf.dst_addr = usb_fifo_addr; 120 slave_conf.dst_addr_width = addr_width; 121 slave_conf.dst_maxburst = 16; 122 slave_conf.device_fc = false; 123 124 dmaengine_slave_config(dma_chan, &slave_conf); 125 126 dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction, 127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 128 if (!dma_desc) 129 return false; 130 131 dma_desc->callback = ux500_dma_callback; 132 dma_desc->callback_param = channel; 133 ux500_channel->cookie = dma_desc->tx_submit(dma_desc); 134 135 dma_async_issue_pending(dma_chan); 136 137 return true; 138 } 139 140 static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c, 141 struct musb_hw_ep *hw_ep, u8 is_tx) 142 { 143 struct ux500_dma_controller *controller = container_of(c, 144 struct ux500_dma_controller, controller); 145 struct ux500_dma_channel *ux500_channel = NULL; 146 struct musb *musb = controller->private_data; 147 u8 ch_num = hw_ep->epnum - 1; 148 149 /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated 150 * to specified hw_ep. For example DMA channel 0 can only be allocated 151 * to hw_ep 1 and 9. 152 */ 153 if (ch_num > 7) 154 ch_num -= 8; 155 156 if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS) 157 return NULL; 158 159 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : 160 &(controller->rx_channel[ch_num]) ; 161 162 /* Check if channel is already used. */ 163 if (ux500_channel->is_allocated) 164 return NULL; 165 166 ux500_channel->hw_ep = hw_ep; 167 ux500_channel->is_allocated = 1; 168 169 dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n", 170 hw_ep->epnum, is_tx, ch_num); 171 172 return &(ux500_channel->channel); 173 } 174 175 static void ux500_dma_channel_release(struct dma_channel *channel) 176 { 177 struct ux500_dma_channel *ux500_channel = channel->private_data; 178 struct musb *musb = ux500_channel->controller->private_data; 179 180 dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num); 181 182 if (ux500_channel->is_allocated) { 183 ux500_channel->is_allocated = 0; 184 channel->status = MUSB_DMA_STATUS_FREE; 185 channel->actual_len = 0; 186 } 187 } 188 189 static int ux500_dma_is_compatible(struct dma_channel *channel, 190 u16 maxpacket, void *buf, u32 length) 191 { 192 if ((maxpacket & 0x3) || 193 ((unsigned long int) buf & 0x3) || 194 (length < 512) || 195 (length & 0x3)) 196 return false; 197 else 198 return true; 199 } 200 201 static int ux500_dma_channel_program(struct dma_channel *channel, 202 u16 packet_sz, u8 mode, 203 dma_addr_t dma_addr, u32 len) 204 { 205 int ret; 206 207 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 208 channel->status == MUSB_DMA_STATUS_BUSY); 209 210 if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len)) 211 return false; 212 213 channel->status = MUSB_DMA_STATUS_BUSY; 214 channel->actual_len = 0; 215 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len); 216 if (!ret) 217 channel->status = MUSB_DMA_STATUS_FREE; 218 219 return ret; 220 } 221 222 static int ux500_dma_channel_abort(struct dma_channel *channel) 223 { 224 struct ux500_dma_channel *ux500_channel = channel->private_data; 225 struct ux500_dma_controller *controller = ux500_channel->controller; 226 struct musb *musb = controller->private_data; 227 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs; 228 u16 csr; 229 230 dev_dbg(musb->controller, "channel=%d, is_tx=%d\n", 231 ux500_channel->ch_num, ux500_channel->is_tx); 232 233 if (channel->status == MUSB_DMA_STATUS_BUSY) { 234 if (ux500_channel->is_tx) { 235 csr = musb_readw(epio, MUSB_TXCSR); 236 csr &= ~(MUSB_TXCSR_AUTOSET | 237 MUSB_TXCSR_DMAENAB | 238 MUSB_TXCSR_DMAMODE); 239 musb_writew(epio, MUSB_TXCSR, csr); 240 } else { 241 csr = musb_readw(epio, MUSB_RXCSR); 242 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 243 MUSB_RXCSR_DMAENAB | 244 MUSB_RXCSR_DMAMODE); 245 musb_writew(epio, MUSB_RXCSR, csr); 246 } 247 248 dmaengine_terminate_all(ux500_channel->dma_chan); 249 channel->status = MUSB_DMA_STATUS_FREE; 250 } 251 return 0; 252 } 253 254 static void ux500_dma_controller_stop(struct ux500_dma_controller *controller) 255 { 256 struct ux500_dma_channel *ux500_channel; 257 struct dma_channel *channel; 258 u8 ch_num; 259 260 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { 261 channel = &controller->rx_channel[ch_num].channel; 262 ux500_channel = channel->private_data; 263 264 ux500_dma_channel_release(channel); 265 266 if (ux500_channel->dma_chan) 267 dma_release_channel(ux500_channel->dma_chan); 268 } 269 270 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { 271 channel = &controller->tx_channel[ch_num].channel; 272 ux500_channel = channel->private_data; 273 274 ux500_dma_channel_release(channel); 275 276 if (ux500_channel->dma_chan) 277 dma_release_channel(ux500_channel->dma_chan); 278 } 279 } 280 281 static int ux500_dma_controller_start(struct ux500_dma_controller *controller) 282 { 283 struct ux500_dma_channel *ux500_channel = NULL; 284 struct musb *musb = controller->private_data; 285 struct device *dev = musb->controller; 286 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 287 struct ux500_musb_board_data *data; 288 struct dma_channel *dma_channel = NULL; 289 char **chan_names; 290 u32 ch_num; 291 u8 dir; 292 u8 is_tx = 0; 293 294 void **param_array; 295 struct ux500_dma_channel *channel_array; 296 dma_cap_mask_t mask; 297 298 if (!plat) { 299 dev_err(musb->controller, "No platform data\n"); 300 return -EINVAL; 301 } 302 303 data = plat->board_data; 304 305 dma_cap_zero(mask); 306 dma_cap_set(DMA_SLAVE, mask); 307 308 /* Prepare the loop for RX channels */ 309 channel_array = controller->rx_channel; 310 param_array = data ? data->dma_rx_param_array : NULL; 311 chan_names = (char **)iep_chan_names; 312 313 for (dir = 0; dir < 2; dir++) { 314 for (ch_num = 0; 315 ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; 316 ch_num++) { 317 ux500_channel = &channel_array[ch_num]; 318 ux500_channel->controller = controller; 319 ux500_channel->ch_num = ch_num; 320 ux500_channel->is_tx = is_tx; 321 322 dma_channel = &(ux500_channel->channel); 323 dma_channel->private_data = ux500_channel; 324 dma_channel->status = MUSB_DMA_STATUS_FREE; 325 dma_channel->max_len = SZ_16M; 326 327 ux500_channel->dma_chan = 328 dma_request_slave_channel(dev, chan_names[ch_num]); 329 330 if (!ux500_channel->dma_chan) 331 ux500_channel->dma_chan = 332 dma_request_channel(mask, 333 data ? 334 data->dma_filter : 335 NULL, 336 param_array ? 337 param_array[ch_num] : 338 NULL); 339 340 if (!ux500_channel->dma_chan) { 341 ERR("Dma pipe allocation error dir=%d ch=%d\n", 342 dir, ch_num); 343 344 /* Release already allocated channels */ 345 ux500_dma_controller_stop(controller); 346 347 return -EBUSY; 348 } 349 350 } 351 352 /* Prepare the loop for TX channels */ 353 channel_array = controller->tx_channel; 354 param_array = data ? data->dma_tx_param_array : NULL; 355 chan_names = (char **)oep_chan_names; 356 is_tx = 1; 357 } 358 359 return 0; 360 } 361 362 void ux500_dma_controller_destroy(struct dma_controller *c) 363 { 364 struct ux500_dma_controller *controller = container_of(c, 365 struct ux500_dma_controller, controller); 366 367 ux500_dma_controller_stop(controller); 368 kfree(controller); 369 } 370 EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy); 371 372 struct dma_controller * 373 ux500_dma_controller_create(struct musb *musb, void __iomem *base) 374 { 375 struct ux500_dma_controller *controller; 376 struct platform_device *pdev = to_platform_device(musb->controller); 377 struct resource *iomem; 378 int ret; 379 380 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 381 if (!controller) 382 goto kzalloc_fail; 383 384 controller->private_data = musb; 385 386 /* Save physical address for DMA controller. */ 387 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 388 if (!iomem) { 389 dev_err(musb->controller, "no memory resource defined\n"); 390 goto plat_get_fail; 391 } 392 393 controller->phy_base = (dma_addr_t) iomem->start; 394 395 controller->controller.channel_alloc = ux500_dma_channel_allocate; 396 controller->controller.channel_release = ux500_dma_channel_release; 397 controller->controller.channel_program = ux500_dma_channel_program; 398 controller->controller.channel_abort = ux500_dma_channel_abort; 399 controller->controller.is_compatible = ux500_dma_is_compatible; 400 401 ret = ux500_dma_controller_start(controller); 402 if (ret) 403 goto plat_get_fail; 404 return &controller->controller; 405 406 plat_get_fail: 407 kfree(controller); 408 kzalloc_fail: 409 return NULL; 410 } 411 EXPORT_SYMBOL_GPL(ux500_dma_controller_create); 412