1 /* 2 * drivers/usb/musb/ux500_dma.c 3 * 4 * U8500 and U5500 DMA support code 5 * 6 * Copyright (C) 2009 STMicroelectronics 7 * Copyright (C) 2011 ST-Ericsson SA 8 * Authors: 9 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> 10 * Praveena Nadahally <praveen.nadahally@stericsson.com> 11 * Rajaram Regupathy <ragupathy.rajaram@stericsson.com> 12 * 13 * This program is free software: you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation, either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program. If not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include <linux/device.h> 28 #include <linux/interrupt.h> 29 #include <linux/platform_device.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/pfn.h> 33 #include <mach/usb.h> 34 #include "musb_core.h" 35 36 struct ux500_dma_channel { 37 struct dma_channel channel; 38 struct ux500_dma_controller *controller; 39 struct musb_hw_ep *hw_ep; 40 struct dma_chan *dma_chan; 41 unsigned int cur_len; 42 dma_cookie_t cookie; 43 u8 ch_num; 44 u8 is_tx; 45 u8 is_allocated; 46 }; 47 48 struct ux500_dma_controller { 49 struct dma_controller controller; 50 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS]; 51 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS]; 52 u32 num_rx_channels; 53 u32 num_tx_channels; 54 void *private_data; 55 dma_addr_t phy_base; 56 }; 57 58 /* Work function invoked from DMA callback to handle rx transfers. */ 59 void ux500_dma_callback(void *private_data) 60 { 61 struct dma_channel *channel = private_data; 62 struct ux500_dma_channel *ux500_channel = channel->private_data; 63 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 64 struct musb *musb = hw_ep->musb; 65 unsigned long flags; 66 67 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", 68 hw_ep->epnum); 69 70 spin_lock_irqsave(&musb->lock, flags); 71 ux500_channel->channel.actual_len = ux500_channel->cur_len; 72 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE; 73 musb_dma_completion(musb, hw_ep->epnum, 74 ux500_channel->is_tx); 75 spin_unlock_irqrestore(&musb->lock, flags); 76 77 } 78 79 static bool ux500_configure_channel(struct dma_channel *channel, 80 u16 packet_sz, u8 mode, 81 dma_addr_t dma_addr, u32 len) 82 { 83 struct ux500_dma_channel *ux500_channel = channel->private_data; 84 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 85 struct dma_chan *dma_chan = ux500_channel->dma_chan; 86 struct dma_async_tx_descriptor *dma_desc; 87 enum dma_transfer_direction direction; 88 struct scatterlist sg; 89 struct dma_slave_config slave_conf; 90 enum dma_slave_buswidth addr_width; 91 dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) + 92 ux500_channel->controller->phy_base); 93 struct musb *musb = ux500_channel->controller->private_data; 94 95 dev_dbg(musb->controller, 96 "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n", 97 packet_sz, mode, dma_addr, len, ux500_channel->is_tx); 98 99 ux500_channel->cur_len = len; 100 101 sg_init_table(&sg, 1); 102 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len, 103 offset_in_page(dma_addr)); 104 sg_dma_address(&sg) = dma_addr; 105 sg_dma_len(&sg) = len; 106 107 direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 108 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE : 109 DMA_SLAVE_BUSWIDTH_4_BYTES; 110 111 slave_conf.direction = direction; 112 slave_conf.src_addr = usb_fifo_addr; 113 slave_conf.src_addr_width = addr_width; 114 slave_conf.src_maxburst = 16; 115 slave_conf.dst_addr = usb_fifo_addr; 116 slave_conf.dst_addr_width = addr_width; 117 slave_conf.dst_maxburst = 16; 118 slave_conf.device_fc = false; 119 120 dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG, 121 (unsigned long) &slave_conf); 122 123 dma_desc = dma_chan->device-> 124 device_prep_slave_sg(dma_chan, &sg, 1, direction, 125 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 126 if (!dma_desc) 127 return false; 128 129 dma_desc->callback = ux500_dma_callback; 130 dma_desc->callback_param = channel; 131 ux500_channel->cookie = dma_desc->tx_submit(dma_desc); 132 133 dma_async_issue_pending(dma_chan); 134 135 return true; 136 } 137 138 static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c, 139 struct musb_hw_ep *hw_ep, u8 is_tx) 140 { 141 struct ux500_dma_controller *controller = container_of(c, 142 struct ux500_dma_controller, controller); 143 struct ux500_dma_channel *ux500_channel = NULL; 144 struct musb *musb = controller->private_data; 145 u8 ch_num = hw_ep->epnum - 1; 146 u32 max_ch; 147 148 /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated 149 * to specified hw_ep. For example DMA channel 0 can only be allocated 150 * to hw_ep 1 and 9. 151 */ 152 if (ch_num > 7) 153 ch_num -= 8; 154 155 max_ch = is_tx ? controller->num_tx_channels : 156 controller->num_rx_channels; 157 158 if (ch_num >= max_ch) 159 return NULL; 160 161 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : 162 &(controller->rx_channel[ch_num]) ; 163 164 /* Check if channel is already used. */ 165 if (ux500_channel->is_allocated) 166 return NULL; 167 168 ux500_channel->hw_ep = hw_ep; 169 ux500_channel->is_allocated = 1; 170 171 dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n", 172 hw_ep->epnum, is_tx, ch_num); 173 174 return &(ux500_channel->channel); 175 } 176 177 static void ux500_dma_channel_release(struct dma_channel *channel) 178 { 179 struct ux500_dma_channel *ux500_channel = channel->private_data; 180 struct musb *musb = ux500_channel->controller->private_data; 181 182 dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num); 183 184 if (ux500_channel->is_allocated) { 185 ux500_channel->is_allocated = 0; 186 channel->status = MUSB_DMA_STATUS_FREE; 187 channel->actual_len = 0; 188 } 189 } 190 191 static int ux500_dma_is_compatible(struct dma_channel *channel, 192 u16 maxpacket, void *buf, u32 length) 193 { 194 if ((maxpacket & 0x3) || 195 ((int)buf & 0x3) || 196 (length < 512) || 197 (length & 0x3)) 198 return false; 199 else 200 return true; 201 } 202 203 static int ux500_dma_channel_program(struct dma_channel *channel, 204 u16 packet_sz, u8 mode, 205 dma_addr_t dma_addr, u32 len) 206 { 207 int ret; 208 209 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 210 channel->status == MUSB_DMA_STATUS_BUSY); 211 212 if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len)) 213 return false; 214 215 channel->status = MUSB_DMA_STATUS_BUSY; 216 channel->actual_len = 0; 217 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len); 218 if (!ret) 219 channel->status = MUSB_DMA_STATUS_FREE; 220 221 return ret; 222 } 223 224 static int ux500_dma_channel_abort(struct dma_channel *channel) 225 { 226 struct ux500_dma_channel *ux500_channel = channel->private_data; 227 struct ux500_dma_controller *controller = ux500_channel->controller; 228 struct musb *musb = controller->private_data; 229 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs; 230 u16 csr; 231 232 dev_dbg(musb->controller, "channel=%d, is_tx=%d\n", 233 ux500_channel->ch_num, ux500_channel->is_tx); 234 235 if (channel->status == MUSB_DMA_STATUS_BUSY) { 236 if (ux500_channel->is_tx) { 237 csr = musb_readw(epio, MUSB_TXCSR); 238 csr &= ~(MUSB_TXCSR_AUTOSET | 239 MUSB_TXCSR_DMAENAB | 240 MUSB_TXCSR_DMAMODE); 241 musb_writew(epio, MUSB_TXCSR, csr); 242 } else { 243 csr = musb_readw(epio, MUSB_RXCSR); 244 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 245 MUSB_RXCSR_DMAENAB | 246 MUSB_RXCSR_DMAMODE); 247 musb_writew(epio, MUSB_RXCSR, csr); 248 } 249 250 ux500_channel->dma_chan->device-> 251 device_control(ux500_channel->dma_chan, 252 DMA_TERMINATE_ALL, 0); 253 channel->status = MUSB_DMA_STATUS_FREE; 254 } 255 return 0; 256 } 257 258 static int ux500_dma_controller_stop(struct dma_controller *c) 259 { 260 struct ux500_dma_controller *controller = container_of(c, 261 struct ux500_dma_controller, controller); 262 struct ux500_dma_channel *ux500_channel; 263 struct dma_channel *channel; 264 u8 ch_num; 265 266 for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) { 267 channel = &controller->rx_channel[ch_num].channel; 268 ux500_channel = channel->private_data; 269 270 ux500_dma_channel_release(channel); 271 272 if (ux500_channel->dma_chan) 273 dma_release_channel(ux500_channel->dma_chan); 274 } 275 276 for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) { 277 channel = &controller->tx_channel[ch_num].channel; 278 ux500_channel = channel->private_data; 279 280 ux500_dma_channel_release(channel); 281 282 if (ux500_channel->dma_chan) 283 dma_release_channel(ux500_channel->dma_chan); 284 } 285 286 return 0; 287 } 288 289 static int ux500_dma_controller_start(struct dma_controller *c) 290 { 291 struct ux500_dma_controller *controller = container_of(c, 292 struct ux500_dma_controller, controller); 293 struct ux500_dma_channel *ux500_channel = NULL; 294 struct musb *musb = controller->private_data; 295 struct device *dev = musb->controller; 296 struct musb_hdrc_platform_data *plat = dev->platform_data; 297 struct ux500_musb_board_data *data = plat->board_data; 298 struct dma_channel *dma_channel = NULL; 299 u32 ch_num; 300 u8 dir; 301 u8 is_tx = 0; 302 303 void **param_array; 304 struct ux500_dma_channel *channel_array; 305 u32 ch_count; 306 dma_cap_mask_t mask; 307 308 if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) || 309 (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS)) 310 return -EINVAL; 311 312 controller->num_rx_channels = data->num_rx_channels; 313 controller->num_tx_channels = data->num_tx_channels; 314 315 dma_cap_zero(mask); 316 dma_cap_set(DMA_SLAVE, mask); 317 318 /* Prepare the loop for RX channels */ 319 channel_array = controller->rx_channel; 320 ch_count = data->num_rx_channels; 321 param_array = data->dma_rx_param_array; 322 323 for (dir = 0; dir < 2; dir++) { 324 for (ch_num = 0; ch_num < ch_count; ch_num++) { 325 ux500_channel = &channel_array[ch_num]; 326 ux500_channel->controller = controller; 327 ux500_channel->ch_num = ch_num; 328 ux500_channel->is_tx = is_tx; 329 330 dma_channel = &(ux500_channel->channel); 331 dma_channel->private_data = ux500_channel; 332 dma_channel->status = MUSB_DMA_STATUS_FREE; 333 dma_channel->max_len = SZ_16M; 334 335 ux500_channel->dma_chan = dma_request_channel(mask, 336 data->dma_filter, 337 param_array[ch_num]); 338 if (!ux500_channel->dma_chan) { 339 ERR("Dma pipe allocation error dir=%d ch=%d\n", 340 dir, ch_num); 341 342 /* Release already allocated channels */ 343 ux500_dma_controller_stop(c); 344 345 return -EBUSY; 346 } 347 348 } 349 350 /* Prepare the loop for TX channels */ 351 channel_array = controller->tx_channel; 352 ch_count = data->num_tx_channels; 353 param_array = data->dma_tx_param_array; 354 is_tx = 1; 355 } 356 357 return 0; 358 } 359 360 void dma_controller_destroy(struct dma_controller *c) 361 { 362 struct ux500_dma_controller *controller = container_of(c, 363 struct ux500_dma_controller, controller); 364 365 kfree(controller); 366 } 367 368 struct dma_controller *__init 369 dma_controller_create(struct musb *musb, void __iomem *base) 370 { 371 struct ux500_dma_controller *controller; 372 struct platform_device *pdev = to_platform_device(musb->controller); 373 struct resource *iomem; 374 375 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 376 if (!controller) 377 return NULL; 378 379 controller->private_data = musb; 380 381 /* Save physical address for DMA controller. */ 382 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 383 controller->phy_base = (dma_addr_t) iomem->start; 384 385 controller->controller.start = ux500_dma_controller_start; 386 controller->controller.stop = ux500_dma_controller_stop; 387 controller->controller.channel_alloc = ux500_dma_channel_allocate; 388 controller->controller.channel_release = ux500_dma_channel_release; 389 controller->controller.channel_program = ux500_dma_channel_program; 390 controller->controller.channel_abort = ux500_dma_channel_abort; 391 controller->controller.is_compatible = ux500_dma_is_compatible; 392 393 return &controller->controller; 394 } 395