1550a7375SFelipe Balbi /* 2550a7375SFelipe Balbi * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3550a7375SFelipe Balbi * 4550a7375SFelipe Balbi * Copyright (C) 2006 Nokia Corporation 5550a7375SFelipe Balbi * Tony Lindgren <tony@atomide.com> 6550a7375SFelipe Balbi * 7550a7375SFelipe Balbi * This program is free software; you can redistribute it and/or modify 8550a7375SFelipe Balbi * it under the terms of the GNU General Public License version 2 as 9550a7375SFelipe Balbi * published by the Free Software Foundation. 10550a7375SFelipe Balbi */ 11550a7375SFelipe Balbi #include <linux/module.h> 12550a7375SFelipe Balbi #include <linux/kernel.h> 13550a7375SFelipe Balbi #include <linux/errno.h> 14550a7375SFelipe Balbi #include <linux/usb.h> 15550a7375SFelipe Balbi #include <linux/platform_device.h> 16550a7375SFelipe Balbi #include <linux/dma-mapping.h> 175a0e3ad6STejun Heo #include <linux/slab.h> 1845c3eb7dSTony Lindgren #include <linux/omap-dma.h> 19550a7375SFelipe Balbi 20550a7375SFelipe Balbi #include "musb_core.h" 21240a16e2SFelipe Balbi #include "tusb6010.h" 22550a7375SFelipe Balbi 23550a7375SFelipe Balbi #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 24550a7375SFelipe Balbi 25550a7375SFelipe Balbi #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 26550a7375SFelipe Balbi 27d5e7c864SLokesh Vutla #define OMAP24XX_DMA_EXT_DMAREQ0 2 28d5e7c864SLokesh Vutla #define OMAP24XX_DMA_EXT_DMAREQ1 3 29d5e7c864SLokesh Vutla #define OMAP242X_DMA_EXT_DMAREQ2 14 30d5e7c864SLokesh Vutla #define OMAP242X_DMA_EXT_DMAREQ3 15 31d5e7c864SLokesh Vutla #define OMAP242X_DMA_EXT_DMAREQ4 16 32d5e7c864SLokesh Vutla #define OMAP242X_DMA_EXT_DMAREQ5 64 33d5e7c864SLokesh Vutla 34550a7375SFelipe Balbi struct tusb_omap_dma_ch { 35550a7375SFelipe Balbi struct musb *musb; 36550a7375SFelipe Balbi void __iomem *tbase; 37550a7375SFelipe Balbi unsigned long phys_offset; 38550a7375SFelipe Balbi int epnum; 39550a7375SFelipe Balbi u8 tx; 40550a7375SFelipe Balbi struct musb_hw_ep *hw_ep; 41550a7375SFelipe Balbi 42550a7375SFelipe Balbi int ch; 43550a7375SFelipe Balbi s8 dmareq; 44550a7375SFelipe Balbi s8 sync_dev; 45550a7375SFelipe Balbi 46550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma; 47550a7375SFelipe Balbi 481d0f11b3STony Lindgren dma_addr_t dma_addr; 49550a7375SFelipe Balbi 50550a7375SFelipe Balbi u32 len; 51550a7375SFelipe Balbi u16 packet_sz; 52550a7375SFelipe Balbi u16 transfer_packet_sz; 53550a7375SFelipe Balbi u32 transfer_len; 54550a7375SFelipe Balbi u32 completed_len; 55550a7375SFelipe Balbi }; 56550a7375SFelipe Balbi 57550a7375SFelipe Balbi struct tusb_omap_dma { 58550a7375SFelipe Balbi struct dma_controller controller; 59550a7375SFelipe Balbi void __iomem *tbase; 60550a7375SFelipe Balbi 61550a7375SFelipe Balbi int ch; 62550a7375SFelipe Balbi s8 dmareq; 63550a7375SFelipe Balbi s8 sync_dev; 64550a7375SFelipe Balbi unsigned multichannel:1; 65550a7375SFelipe Balbi }; 66550a7375SFelipe Balbi 67550a7375SFelipe Balbi /* 68550a7375SFelipe Balbi * Allocate dmareq0 to the current channel unless it's already taken 69550a7375SFelipe Balbi */ 70550a7375SFelipe Balbi static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 71550a7375SFelipe Balbi { 72550a7375SFelipe Balbi u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 73550a7375SFelipe Balbi 74550a7375SFelipe Balbi if (reg != 0) { 7574c6f3a4SSergei Trofimovich dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", 76550a7375SFelipe Balbi chdat->epnum, reg & 0xf); 77550a7375SFelipe Balbi return -EAGAIN; 78550a7375SFelipe Balbi } 79550a7375SFelipe Balbi 80550a7375SFelipe Balbi if (chdat->tx) 81550a7375SFelipe Balbi reg = (1 << 4) | chdat->epnum; 82550a7375SFelipe Balbi else 83550a7375SFelipe Balbi reg = chdat->epnum; 84550a7375SFelipe Balbi 85550a7375SFelipe Balbi musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 86550a7375SFelipe Balbi 87550a7375SFelipe Balbi return 0; 88550a7375SFelipe Balbi } 89550a7375SFelipe Balbi 90550a7375SFelipe Balbi static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 91550a7375SFelipe Balbi { 92550a7375SFelipe Balbi u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 93550a7375SFelipe Balbi 94550a7375SFelipe Balbi if ((reg & 0xf) != chdat->epnum) { 95550a7375SFelipe Balbi printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 96550a7375SFelipe Balbi chdat->epnum, reg & 0xf); 97550a7375SFelipe Balbi return; 98550a7375SFelipe Balbi } 99550a7375SFelipe Balbi musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 100550a7375SFelipe Balbi } 101550a7375SFelipe Balbi 102550a7375SFelipe Balbi /* 103550a7375SFelipe Balbi * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 104550a7375SFelipe Balbi * musb_gadget.c. 105550a7375SFelipe Balbi */ 106550a7375SFelipe Balbi static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 107550a7375SFelipe Balbi { 108550a7375SFelipe Balbi struct dma_channel *channel = (struct dma_channel *)data; 109550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat = to_chdat(channel); 110550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 111550a7375SFelipe Balbi struct musb *musb = chdat->musb; 1121d0f11b3STony Lindgren struct device *dev = musb->controller; 113550a7375SFelipe Balbi struct musb_hw_ep *hw_ep = chdat->hw_ep; 114550a7375SFelipe Balbi void __iomem *ep_conf = hw_ep->conf; 115550a7375SFelipe Balbi void __iomem *mbase = musb->mregs; 116550a7375SFelipe Balbi unsigned long remaining, flags, pio; 117550a7375SFelipe Balbi int ch; 118550a7375SFelipe Balbi 119550a7375SFelipe Balbi spin_lock_irqsave(&musb->lock, flags); 120550a7375SFelipe Balbi 121550a7375SFelipe Balbi if (tusb_dma->multichannel) 122550a7375SFelipe Balbi ch = chdat->ch; 123550a7375SFelipe Balbi else 124550a7375SFelipe Balbi ch = tusb_dma->ch; 125550a7375SFelipe Balbi 126550a7375SFelipe Balbi if (ch_status != OMAP_DMA_BLOCK_IRQ) 127550a7375SFelipe Balbi printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 128550a7375SFelipe Balbi 1295c8a86e1SFelipe Balbi dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", 130550a7375SFelipe Balbi chdat->epnum, chdat->tx ? "tx" : "rx", 131550a7375SFelipe Balbi ch, ch_status); 132550a7375SFelipe Balbi 133550a7375SFelipe Balbi if (chdat->tx) 134550a7375SFelipe Balbi remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 135550a7375SFelipe Balbi else 136550a7375SFelipe Balbi remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 137550a7375SFelipe Balbi 138550a7375SFelipe Balbi remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 139550a7375SFelipe Balbi 140550a7375SFelipe Balbi /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 141550a7375SFelipe Balbi if (unlikely(remaining > chdat->transfer_len)) { 1425c8a86e1SFelipe Balbi dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 143550a7375SFelipe Balbi chdat->tx ? "tx" : "rx", chdat->ch, 144550a7375SFelipe Balbi remaining); 145550a7375SFelipe Balbi remaining = 0; 146550a7375SFelipe Balbi } 147550a7375SFelipe Balbi 148550a7375SFelipe Balbi channel->actual_len = chdat->transfer_len - remaining; 149550a7375SFelipe Balbi pio = chdat->len - channel->actual_len; 150550a7375SFelipe Balbi 1515c8a86e1SFelipe Balbi dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 152550a7375SFelipe Balbi 153550a7375SFelipe Balbi /* Transfer remaining 1 - 31 bytes */ 154550a7375SFelipe Balbi if (pio > 0 && pio < 32) { 155550a7375SFelipe Balbi u8 *buf; 156550a7375SFelipe Balbi 1575c8a86e1SFelipe Balbi dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); 158550a7375SFelipe Balbi buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 159550a7375SFelipe Balbi if (chdat->tx) { 1601d0f11b3STony Lindgren dma_unmap_single(dev, chdat->dma_addr, 1611d0f11b3STony Lindgren chdat->transfer_len, 1621d0f11b3STony Lindgren DMA_TO_DEVICE); 163550a7375SFelipe Balbi musb_write_fifo(hw_ep, pio, buf); 164550a7375SFelipe Balbi } else { 1651d0f11b3STony Lindgren dma_unmap_single(dev, chdat->dma_addr, 1661d0f11b3STony Lindgren chdat->transfer_len, 1671d0f11b3STony Lindgren DMA_FROM_DEVICE); 168550a7375SFelipe Balbi musb_read_fifo(hw_ep, pio, buf); 169550a7375SFelipe Balbi } 170550a7375SFelipe Balbi channel->actual_len += pio; 171550a7375SFelipe Balbi } 172550a7375SFelipe Balbi 173550a7375SFelipe Balbi if (!tusb_dma->multichannel) 174550a7375SFelipe Balbi tusb_omap_free_shared_dmareq(chdat); 175550a7375SFelipe Balbi 176550a7375SFelipe Balbi channel->status = MUSB_DMA_STATUS_FREE; 177550a7375SFelipe Balbi 178550a7375SFelipe Balbi /* Handle only RX callbacks here. TX callbacks must be handled based 179550a7375SFelipe Balbi * on the TUSB DMA status interrupt. 180550a7375SFelipe Balbi * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 181550a7375SFelipe Balbi * interrupt for RX and TX. 182550a7375SFelipe Balbi */ 183550a7375SFelipe Balbi if (!chdat->tx) 184550a7375SFelipe Balbi musb_dma_completion(musb, chdat->epnum, chdat->tx); 185550a7375SFelipe Balbi 186550a7375SFelipe Balbi /* We must terminate short tx transfers manually by setting TXPKTRDY. 187550a7375SFelipe Balbi * REVISIT: This same problem may occur with other MUSB dma as well. 188550a7375SFelipe Balbi * Easy to test with g_ether by pinging the MUSB board with ping -s54. 189550a7375SFelipe Balbi */ 190550a7375SFelipe Balbi if ((chdat->transfer_len < chdat->packet_sz) 191550a7375SFelipe Balbi || (chdat->transfer_len % chdat->packet_sz != 0)) { 192550a7375SFelipe Balbi u16 csr; 193550a7375SFelipe Balbi 194550a7375SFelipe Balbi if (chdat->tx) { 1955c8a86e1SFelipe Balbi dev_dbg(musb->controller, "terminating short tx packet\n"); 196550a7375SFelipe Balbi musb_ep_select(mbase, chdat->epnum); 197550a7375SFelipe Balbi csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 198550a7375SFelipe Balbi csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 199550a7375SFelipe Balbi | MUSB_TXCSR_P_WZC_BITS; 200550a7375SFelipe Balbi musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 201550a7375SFelipe Balbi } 202550a7375SFelipe Balbi } 203550a7375SFelipe Balbi 204550a7375SFelipe Balbi spin_unlock_irqrestore(&musb->lock, flags); 205550a7375SFelipe Balbi } 206550a7375SFelipe Balbi 207550a7375SFelipe Balbi static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 208550a7375SFelipe Balbi u8 rndis_mode, dma_addr_t dma_addr, u32 len) 209550a7375SFelipe Balbi { 210550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat = to_chdat(channel); 211550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 212550a7375SFelipe Balbi struct musb *musb = chdat->musb; 2131d0f11b3STony Lindgren struct device *dev = musb->controller; 214550a7375SFelipe Balbi struct musb_hw_ep *hw_ep = chdat->hw_ep; 215550a7375SFelipe Balbi void __iomem *mbase = musb->mregs; 216550a7375SFelipe Balbi void __iomem *ep_conf = hw_ep->conf; 217550a7375SFelipe Balbi dma_addr_t fifo = hw_ep->fifo_sync; 218550a7375SFelipe Balbi struct omap_dma_channel_params dma_params; 219550a7375SFelipe Balbi u32 dma_remaining; 220550a7375SFelipe Balbi int src_burst, dst_burst; 221550a7375SFelipe Balbi u16 csr; 2226df2b42fSPeter Ujfalusi u32 psize; 223550a7375SFelipe Balbi int ch; 224550a7375SFelipe Balbi s8 dmareq; 225550a7375SFelipe Balbi s8 sync_dev; 226550a7375SFelipe Balbi 227550a7375SFelipe Balbi if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 228550a7375SFelipe Balbi return false; 229550a7375SFelipe Balbi 230550a7375SFelipe Balbi /* 231550a7375SFelipe Balbi * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 232550a7375SFelipe Balbi * register which will cause missed DMA interrupt. We could try to 233550a7375SFelipe Balbi * use a timer for the callback, but it is unsafe as the XFR_SIZE 234550a7375SFelipe Balbi * register is corrupt, and we won't know if the DMA worked. 235550a7375SFelipe Balbi */ 236550a7375SFelipe Balbi if (dma_addr & 0x2) 237550a7375SFelipe Balbi return false; 238550a7375SFelipe Balbi 239550a7375SFelipe Balbi /* 240550a7375SFelipe Balbi * Because of HW issue #10, it seems like mixing sync DMA and async 241550a7375SFelipe Balbi * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 242550a7375SFelipe Balbi * using the channel for DMA. 243550a7375SFelipe Balbi */ 244550a7375SFelipe Balbi if (chdat->tx) 245550a7375SFelipe Balbi dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 246550a7375SFelipe Balbi else 247550a7375SFelipe Balbi dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 248550a7375SFelipe Balbi 249550a7375SFelipe Balbi dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 250550a7375SFelipe Balbi if (dma_remaining) { 2515c8a86e1SFelipe Balbi dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", 252550a7375SFelipe Balbi chdat->tx ? "tx" : "rx", chdat->ch, 253550a7375SFelipe Balbi dma_remaining); 254550a7375SFelipe Balbi return false; 255550a7375SFelipe Balbi } 256550a7375SFelipe Balbi 257550a7375SFelipe Balbi chdat->transfer_len = len & ~0x1f; 258550a7375SFelipe Balbi 259550a7375SFelipe Balbi if (len < packet_sz) 260550a7375SFelipe Balbi chdat->transfer_packet_sz = chdat->transfer_len; 261550a7375SFelipe Balbi else 262550a7375SFelipe Balbi chdat->transfer_packet_sz = packet_sz; 263550a7375SFelipe Balbi 264550a7375SFelipe Balbi if (tusb_dma->multichannel) { 265550a7375SFelipe Balbi ch = chdat->ch; 266550a7375SFelipe Balbi dmareq = chdat->dmareq; 267550a7375SFelipe Balbi sync_dev = chdat->sync_dev; 268550a7375SFelipe Balbi } else { 269550a7375SFelipe Balbi if (tusb_omap_use_shared_dmareq(chdat) != 0) { 2705c8a86e1SFelipe Balbi dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); 271550a7375SFelipe Balbi return false; 272550a7375SFelipe Balbi } 273550a7375SFelipe Balbi if (tusb_dma->ch < 0) { 274550a7375SFelipe Balbi /* REVISIT: This should get blocked earlier, happens 275550a7375SFelipe Balbi * with MSC ErrorRecoveryTest 276550a7375SFelipe Balbi */ 277550a7375SFelipe Balbi WARN_ON(1); 278550a7375SFelipe Balbi return false; 279550a7375SFelipe Balbi } 280550a7375SFelipe Balbi 281550a7375SFelipe Balbi ch = tusb_dma->ch; 282550a7375SFelipe Balbi dmareq = tusb_dma->dmareq; 283550a7375SFelipe Balbi sync_dev = tusb_dma->sync_dev; 284550a7375SFelipe Balbi omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 285550a7375SFelipe Balbi } 286550a7375SFelipe Balbi 287550a7375SFelipe Balbi chdat->packet_sz = packet_sz; 288550a7375SFelipe Balbi chdat->len = len; 289550a7375SFelipe Balbi channel->actual_len = 0; 2901d0f11b3STony Lindgren chdat->dma_addr = dma_addr; 291550a7375SFelipe Balbi channel->status = MUSB_DMA_STATUS_BUSY; 292550a7375SFelipe Balbi 293550a7375SFelipe Balbi /* Since we're recycling dma areas, we need to clean or invalidate */ 294550a7375SFelipe Balbi if (chdat->tx) 2951d0f11b3STony Lindgren dma_map_single(dev, phys_to_virt(dma_addr), len, 2961d0f11b3STony Lindgren DMA_TO_DEVICE); 297550a7375SFelipe Balbi else 2981d0f11b3STony Lindgren dma_map_single(dev, phys_to_virt(dma_addr), len, 2991d0f11b3STony Lindgren DMA_FROM_DEVICE); 300550a7375SFelipe Balbi 301550a7375SFelipe Balbi /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 302550a7375SFelipe Balbi if ((dma_addr & 0x3) == 0) { 303550a7375SFelipe Balbi dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 304550a7375SFelipe Balbi dma_params.elem_count = 8; /* Elements in frame */ 305550a7375SFelipe Balbi } else { 306550a7375SFelipe Balbi dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 307550a7375SFelipe Balbi dma_params.elem_count = 16; /* Elements in frame */ 308550a7375SFelipe Balbi fifo = hw_ep->fifo_async; 309550a7375SFelipe Balbi } 310550a7375SFelipe Balbi 311550a7375SFelipe Balbi dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 312550a7375SFelipe Balbi 3133ec08ddfSArnd Bergmann dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n", 314550a7375SFelipe Balbi chdat->epnum, chdat->tx ? "tx" : "rx", 3153ec08ddfSArnd Bergmann ch, &dma_addr, chdat->transfer_len, len, 316550a7375SFelipe Balbi chdat->transfer_packet_sz, packet_sz); 317550a7375SFelipe Balbi 318550a7375SFelipe Balbi /* 319550a7375SFelipe Balbi * Prepare omap DMA for transfer 320550a7375SFelipe Balbi */ 321550a7375SFelipe Balbi if (chdat->tx) { 322550a7375SFelipe Balbi dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 323550a7375SFelipe Balbi dma_params.src_start = (unsigned long)dma_addr; 324550a7375SFelipe Balbi dma_params.src_ei = 0; 325550a7375SFelipe Balbi dma_params.src_fi = 0; 326550a7375SFelipe Balbi 327550a7375SFelipe Balbi dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 328550a7375SFelipe Balbi dma_params.dst_start = (unsigned long)fifo; 329550a7375SFelipe Balbi dma_params.dst_ei = 1; 330550a7375SFelipe Balbi dma_params.dst_fi = -31; /* Loop 32 byte window */ 331550a7375SFelipe Balbi 332550a7375SFelipe Balbi dma_params.trigger = sync_dev; 333550a7375SFelipe Balbi dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 334550a7375SFelipe Balbi dma_params.src_or_dst_synch = 0; /* Dest sync */ 335550a7375SFelipe Balbi 336550a7375SFelipe Balbi src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 337550a7375SFelipe Balbi dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 338550a7375SFelipe Balbi } else { 339550a7375SFelipe Balbi dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 340550a7375SFelipe Balbi dma_params.src_start = (unsigned long)fifo; 341550a7375SFelipe Balbi dma_params.src_ei = 1; 342550a7375SFelipe Balbi dma_params.src_fi = -31; /* Loop 32 byte window */ 343550a7375SFelipe Balbi 344550a7375SFelipe Balbi dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 345550a7375SFelipe Balbi dma_params.dst_start = (unsigned long)dma_addr; 346550a7375SFelipe Balbi dma_params.dst_ei = 0; 347550a7375SFelipe Balbi dma_params.dst_fi = 0; 348550a7375SFelipe Balbi 349550a7375SFelipe Balbi dma_params.trigger = sync_dev; 350550a7375SFelipe Balbi dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 351550a7375SFelipe Balbi dma_params.src_or_dst_synch = 1; /* Source sync */ 352550a7375SFelipe Balbi 353550a7375SFelipe Balbi src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 354550a7375SFelipe Balbi dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 355550a7375SFelipe Balbi } 356550a7375SFelipe Balbi 3575c8a86e1SFelipe Balbi dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 358550a7375SFelipe Balbi chdat->epnum, chdat->tx ? "tx" : "rx", 359550a7375SFelipe Balbi (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 360550a7375SFelipe Balbi ((dma_addr & 0x3) == 0) ? "sync" : "async", 361550a7375SFelipe Balbi dma_params.src_start, dma_params.dst_start); 362550a7375SFelipe Balbi 363550a7375SFelipe Balbi omap_set_dma_params(ch, &dma_params); 364550a7375SFelipe Balbi omap_set_dma_src_burst_mode(ch, src_burst); 365550a7375SFelipe Balbi omap_set_dma_dest_burst_mode(ch, dst_burst); 366550a7375SFelipe Balbi omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 367550a7375SFelipe Balbi 368550a7375SFelipe Balbi /* 369550a7375SFelipe Balbi * Prepare MUSB for DMA transfer 370550a7375SFelipe Balbi */ 371550a7375SFelipe Balbi musb_ep_select(mbase, chdat->epnum); 372*3565b787SPeter Ujfalusi if (chdat->tx) { 373550a7375SFelipe Balbi csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 374550a7375SFelipe Balbi csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 375550a7375SFelipe Balbi | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 376550a7375SFelipe Balbi csr &= ~MUSB_TXCSR_P_UNDERRUN; 377550a7375SFelipe Balbi musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 378550a7375SFelipe Balbi } else { 379550a7375SFelipe Balbi csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 380550a7375SFelipe Balbi csr |= MUSB_RXCSR_DMAENAB; 381550a7375SFelipe Balbi csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 382550a7375SFelipe Balbi musb_writew(hw_ep->regs, MUSB_RXCSR, 383550a7375SFelipe Balbi csr | MUSB_RXCSR_P_WZC_BITS); 384550a7375SFelipe Balbi } 385550a7375SFelipe Balbi 386550a7375SFelipe Balbi /* 387550a7375SFelipe Balbi * Start DMA transfer 388550a7375SFelipe Balbi */ 389550a7375SFelipe Balbi omap_start_dma(ch); 390550a7375SFelipe Balbi 391550a7375SFelipe Balbi if (chdat->tx) { 392550a7375SFelipe Balbi /* Send transfer_packet_sz packets at a time */ 3936df2b42fSPeter Ujfalusi psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); 3946df2b42fSPeter Ujfalusi psize &= ~0x7ff; 3956df2b42fSPeter Ujfalusi psize |= chdat->transfer_packet_sz; 3966df2b42fSPeter Ujfalusi musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); 397550a7375SFelipe Balbi 398550a7375SFelipe Balbi musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 399550a7375SFelipe Balbi TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 400550a7375SFelipe Balbi } else { 401550a7375SFelipe Balbi /* Receive transfer_packet_sz packets at a time */ 4026df2b42fSPeter Ujfalusi psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); 4036df2b42fSPeter Ujfalusi psize &= ~(0x7ff << 16); 4046df2b42fSPeter Ujfalusi psize |= (chdat->transfer_packet_sz << 16); 4056df2b42fSPeter Ujfalusi musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); 406550a7375SFelipe Balbi 407550a7375SFelipe Balbi musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 408550a7375SFelipe Balbi TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 409550a7375SFelipe Balbi } 410550a7375SFelipe Balbi 411550a7375SFelipe Balbi return true; 412550a7375SFelipe Balbi } 413550a7375SFelipe Balbi 414550a7375SFelipe Balbi static int tusb_omap_dma_abort(struct dma_channel *channel) 415550a7375SFelipe Balbi { 416550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat = to_chdat(channel); 417550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 418550a7375SFelipe Balbi 419550a7375SFelipe Balbi if (!tusb_dma->multichannel) { 420550a7375SFelipe Balbi if (tusb_dma->ch >= 0) { 421550a7375SFelipe Balbi omap_stop_dma(tusb_dma->ch); 422550a7375SFelipe Balbi omap_free_dma(tusb_dma->ch); 423550a7375SFelipe Balbi tusb_dma->ch = -1; 424550a7375SFelipe Balbi } 425550a7375SFelipe Balbi 426550a7375SFelipe Balbi tusb_dma->dmareq = -1; 427550a7375SFelipe Balbi tusb_dma->sync_dev = -1; 428550a7375SFelipe Balbi } 429550a7375SFelipe Balbi 430550a7375SFelipe Balbi channel->status = MUSB_DMA_STATUS_FREE; 431550a7375SFelipe Balbi 432550a7375SFelipe Balbi return 0; 433550a7375SFelipe Balbi } 434550a7375SFelipe Balbi 435550a7375SFelipe Balbi static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 436550a7375SFelipe Balbi { 437550a7375SFelipe Balbi u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 438550a7375SFelipe Balbi int i, dmareq_nr = -1; 439550a7375SFelipe Balbi 440550a7375SFelipe Balbi const int sync_dev[6] = { 441550a7375SFelipe Balbi OMAP24XX_DMA_EXT_DMAREQ0, 442550a7375SFelipe Balbi OMAP24XX_DMA_EXT_DMAREQ1, 443550a7375SFelipe Balbi OMAP242X_DMA_EXT_DMAREQ2, 444550a7375SFelipe Balbi OMAP242X_DMA_EXT_DMAREQ3, 445550a7375SFelipe Balbi OMAP242X_DMA_EXT_DMAREQ4, 446550a7375SFelipe Balbi OMAP242X_DMA_EXT_DMAREQ5, 447550a7375SFelipe Balbi }; 448550a7375SFelipe Balbi 449550a7375SFelipe Balbi for (i = 0; i < MAX_DMAREQ; i++) { 450550a7375SFelipe Balbi int cur = (reg & (0xf << (i * 5))) >> (i * 5); 451550a7375SFelipe Balbi if (cur == 0) { 452550a7375SFelipe Balbi dmareq_nr = i; 453550a7375SFelipe Balbi break; 454550a7375SFelipe Balbi } 455550a7375SFelipe Balbi } 456550a7375SFelipe Balbi 457550a7375SFelipe Balbi if (dmareq_nr == -1) 458550a7375SFelipe Balbi return -EAGAIN; 459550a7375SFelipe Balbi 460550a7375SFelipe Balbi reg |= (chdat->epnum << (dmareq_nr * 5)); 461550a7375SFelipe Balbi if (chdat->tx) 462550a7375SFelipe Balbi reg |= ((1 << 4) << (dmareq_nr * 5)); 463550a7375SFelipe Balbi musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 464550a7375SFelipe Balbi 465550a7375SFelipe Balbi chdat->dmareq = dmareq_nr; 466550a7375SFelipe Balbi chdat->sync_dev = sync_dev[chdat->dmareq]; 467550a7375SFelipe Balbi 468550a7375SFelipe Balbi return 0; 469550a7375SFelipe Balbi } 470550a7375SFelipe Balbi 471550a7375SFelipe Balbi static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 472550a7375SFelipe Balbi { 473550a7375SFelipe Balbi u32 reg; 474550a7375SFelipe Balbi 475550a7375SFelipe Balbi if (!chdat || chdat->dmareq < 0) 476550a7375SFelipe Balbi return; 477550a7375SFelipe Balbi 478550a7375SFelipe Balbi reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 479550a7375SFelipe Balbi reg &= ~(0x1f << (chdat->dmareq * 5)); 480550a7375SFelipe Balbi musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 481550a7375SFelipe Balbi 482550a7375SFelipe Balbi chdat->dmareq = -1; 483550a7375SFelipe Balbi chdat->sync_dev = -1; 484550a7375SFelipe Balbi } 485550a7375SFelipe Balbi 486550a7375SFelipe Balbi static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 487550a7375SFelipe Balbi 488550a7375SFelipe Balbi static struct dma_channel * 489550a7375SFelipe Balbi tusb_omap_dma_allocate(struct dma_controller *c, 490550a7375SFelipe Balbi struct musb_hw_ep *hw_ep, 491550a7375SFelipe Balbi u8 tx) 492550a7375SFelipe Balbi { 493550a7375SFelipe Balbi int ret, i; 494550a7375SFelipe Balbi const char *dev_name; 495550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma; 496550a7375SFelipe Balbi struct musb *musb; 497550a7375SFelipe Balbi void __iomem *tbase; 498550a7375SFelipe Balbi struct dma_channel *channel = NULL; 499550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat = NULL; 500550a7375SFelipe Balbi u32 reg; 501550a7375SFelipe Balbi 502550a7375SFelipe Balbi tusb_dma = container_of(c, struct tusb_omap_dma, controller); 503a96ca0d2SAlexandre Bailon musb = tusb_dma->controller.musb; 504550a7375SFelipe Balbi tbase = musb->ctrl_base; 505550a7375SFelipe Balbi 506550a7375SFelipe Balbi reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 507550a7375SFelipe Balbi if (tx) 508550a7375SFelipe Balbi reg &= ~(1 << hw_ep->epnum); 509550a7375SFelipe Balbi else 510550a7375SFelipe Balbi reg &= ~(1 << (hw_ep->epnum + 15)); 511550a7375SFelipe Balbi musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 512550a7375SFelipe Balbi 513550a7375SFelipe Balbi /* REVISIT: Why does dmareq5 not work? */ 514550a7375SFelipe Balbi if (hw_ep->epnum == 0) { 5155c8a86e1SFelipe Balbi dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 516550a7375SFelipe Balbi return NULL; 517550a7375SFelipe Balbi } 518550a7375SFelipe Balbi 519550a7375SFelipe Balbi for (i = 0; i < MAX_DMAREQ; i++) { 520550a7375SFelipe Balbi struct dma_channel *ch = dma_channel_pool[i]; 521550a7375SFelipe Balbi if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 522550a7375SFelipe Balbi ch->status = MUSB_DMA_STATUS_FREE; 523550a7375SFelipe Balbi channel = ch; 524550a7375SFelipe Balbi chdat = ch->private_data; 525550a7375SFelipe Balbi break; 526550a7375SFelipe Balbi } 527550a7375SFelipe Balbi } 528550a7375SFelipe Balbi 529550a7375SFelipe Balbi if (!channel) 530550a7375SFelipe Balbi return NULL; 531550a7375SFelipe Balbi 532550a7375SFelipe Balbi if (tx) { 533550a7375SFelipe Balbi chdat->tx = 1; 534550a7375SFelipe Balbi dev_name = "TUSB transmit"; 535550a7375SFelipe Balbi } else { 536550a7375SFelipe Balbi chdat->tx = 0; 537550a7375SFelipe Balbi dev_name = "TUSB receive"; 538550a7375SFelipe Balbi } 539550a7375SFelipe Balbi 540a96ca0d2SAlexandre Bailon chdat->musb = tusb_dma->controller.musb; 541550a7375SFelipe Balbi chdat->tbase = tusb_dma->tbase; 542550a7375SFelipe Balbi chdat->hw_ep = hw_ep; 543550a7375SFelipe Balbi chdat->epnum = hw_ep->epnum; 544550a7375SFelipe Balbi chdat->dmareq = -1; 545550a7375SFelipe Balbi chdat->completed_len = 0; 546550a7375SFelipe Balbi chdat->tusb_dma = tusb_dma; 547550a7375SFelipe Balbi 548550a7375SFelipe Balbi channel->max_len = 0x7fffffff; 549550a7375SFelipe Balbi channel->desired_mode = 0; 550550a7375SFelipe Balbi channel->actual_len = 0; 551550a7375SFelipe Balbi 552550a7375SFelipe Balbi if (tusb_dma->multichannel) { 553550a7375SFelipe Balbi ret = tusb_omap_dma_allocate_dmareq(chdat); 554550a7375SFelipe Balbi if (ret != 0) 555550a7375SFelipe Balbi goto free_dmareq; 556550a7375SFelipe Balbi 557550a7375SFelipe Balbi ret = omap_request_dma(chdat->sync_dev, dev_name, 558550a7375SFelipe Balbi tusb_omap_dma_cb, channel, &chdat->ch); 559550a7375SFelipe Balbi if (ret != 0) 560550a7375SFelipe Balbi goto free_dmareq; 561550a7375SFelipe Balbi } else if (tusb_dma->ch == -1) { 562550a7375SFelipe Balbi tusb_dma->dmareq = 0; 563550a7375SFelipe Balbi tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 564550a7375SFelipe Balbi 565550a7375SFelipe Balbi /* Callback data gets set later in the shared dmareq case */ 566550a7375SFelipe Balbi ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 567550a7375SFelipe Balbi tusb_omap_dma_cb, NULL, &tusb_dma->ch); 568550a7375SFelipe Balbi if (ret != 0) 569550a7375SFelipe Balbi goto free_dmareq; 570550a7375SFelipe Balbi 571550a7375SFelipe Balbi chdat->dmareq = -1; 572550a7375SFelipe Balbi chdat->ch = -1; 573550a7375SFelipe Balbi } 574550a7375SFelipe Balbi 5755c8a86e1SFelipe Balbi dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 576550a7375SFelipe Balbi chdat->epnum, 577550a7375SFelipe Balbi chdat->tx ? "tx" : "rx", 578550a7375SFelipe Balbi chdat->ch >= 0 ? "dedicated" : "shared", 579550a7375SFelipe Balbi chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 580550a7375SFelipe Balbi chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 581550a7375SFelipe Balbi chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 582550a7375SFelipe Balbi 583550a7375SFelipe Balbi return channel; 584550a7375SFelipe Balbi 585550a7375SFelipe Balbi free_dmareq: 586550a7375SFelipe Balbi tusb_omap_dma_free_dmareq(chdat); 587550a7375SFelipe Balbi 5885c8a86e1SFelipe Balbi dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); 589550a7375SFelipe Balbi channel->status = MUSB_DMA_STATUS_UNKNOWN; 590550a7375SFelipe Balbi 591550a7375SFelipe Balbi return NULL; 592550a7375SFelipe Balbi } 593550a7375SFelipe Balbi 594550a7375SFelipe Balbi static void tusb_omap_dma_release(struct dma_channel *channel) 595550a7375SFelipe Balbi { 596550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat = to_chdat(channel); 597550a7375SFelipe Balbi struct musb *musb = chdat->musb; 598550a7375SFelipe Balbi void __iomem *tbase = musb->ctrl_base; 599550a7375SFelipe Balbi u32 reg; 600550a7375SFelipe Balbi 6015c8a86e1SFelipe Balbi dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); 602550a7375SFelipe Balbi 603550a7375SFelipe Balbi reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 604550a7375SFelipe Balbi if (chdat->tx) 605550a7375SFelipe Balbi reg |= (1 << chdat->epnum); 606550a7375SFelipe Balbi else 607550a7375SFelipe Balbi reg |= (1 << (chdat->epnum + 15)); 608550a7375SFelipe Balbi musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 609550a7375SFelipe Balbi 610550a7375SFelipe Balbi reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 611550a7375SFelipe Balbi if (chdat->tx) 612550a7375SFelipe Balbi reg |= (1 << chdat->epnum); 613550a7375SFelipe Balbi else 614550a7375SFelipe Balbi reg |= (1 << (chdat->epnum + 15)); 615550a7375SFelipe Balbi musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 616550a7375SFelipe Balbi 617550a7375SFelipe Balbi channel->status = MUSB_DMA_STATUS_UNKNOWN; 618550a7375SFelipe Balbi 619550a7375SFelipe Balbi if (chdat->ch >= 0) { 620550a7375SFelipe Balbi omap_stop_dma(chdat->ch); 621550a7375SFelipe Balbi omap_free_dma(chdat->ch); 622550a7375SFelipe Balbi chdat->ch = -1; 623550a7375SFelipe Balbi } 624550a7375SFelipe Balbi 625550a7375SFelipe Balbi if (chdat->dmareq >= 0) 626550a7375SFelipe Balbi tusb_omap_dma_free_dmareq(chdat); 627550a7375SFelipe Balbi 628550a7375SFelipe Balbi channel = NULL; 629550a7375SFelipe Balbi } 630550a7375SFelipe Balbi 6317f6283edSTony Lindgren void tusb_dma_controller_destroy(struct dma_controller *c) 632550a7375SFelipe Balbi { 633550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma; 634550a7375SFelipe Balbi int i; 635550a7375SFelipe Balbi 636550a7375SFelipe Balbi tusb_dma = container_of(c, struct tusb_omap_dma, controller); 637550a7375SFelipe Balbi for (i = 0; i < MAX_DMAREQ; i++) { 638550a7375SFelipe Balbi struct dma_channel *ch = dma_channel_pool[i]; 639550a7375SFelipe Balbi if (ch) { 640550a7375SFelipe Balbi kfree(ch->private_data); 641550a7375SFelipe Balbi kfree(ch); 642550a7375SFelipe Balbi } 643550a7375SFelipe Balbi } 644550a7375SFelipe Balbi 64594089d56SRoel Kluin if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 646550a7375SFelipe Balbi omap_free_dma(tusb_dma->ch); 647550a7375SFelipe Balbi 648550a7375SFelipe Balbi kfree(tusb_dma); 649550a7375SFelipe Balbi } 6507f6283edSTony Lindgren EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy); 651550a7375SFelipe Balbi 6527f6283edSTony Lindgren struct dma_controller * 6537f6283edSTony Lindgren tusb_dma_controller_create(struct musb *musb, void __iomem *base) 654550a7375SFelipe Balbi { 655550a7375SFelipe Balbi void __iomem *tbase = musb->ctrl_base; 656550a7375SFelipe Balbi struct tusb_omap_dma *tusb_dma; 657550a7375SFelipe Balbi int i; 658550a7375SFelipe Balbi 659550a7375SFelipe Balbi /* REVISIT: Get dmareq lines used from board-*.c */ 660550a7375SFelipe Balbi 661550a7375SFelipe Balbi musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 662550a7375SFelipe Balbi musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 663550a7375SFelipe Balbi 664550a7375SFelipe Balbi musb_writel(tbase, TUSB_DMA_REQ_CONF, 665550a7375SFelipe Balbi TUSB_DMA_REQ_CONF_BURST_SIZE(2) 666550a7375SFelipe Balbi | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 667550a7375SFelipe Balbi | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 668550a7375SFelipe Balbi 669550a7375SFelipe Balbi tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 670550a7375SFelipe Balbi if (!tusb_dma) 671c88ba39cSHuzaifa Sidhpurwala goto out; 672550a7375SFelipe Balbi 673a96ca0d2SAlexandre Bailon tusb_dma->controller.musb = musb; 674550a7375SFelipe Balbi tusb_dma->tbase = musb->ctrl_base; 675550a7375SFelipe Balbi 676550a7375SFelipe Balbi tusb_dma->ch = -1; 677550a7375SFelipe Balbi tusb_dma->dmareq = -1; 678550a7375SFelipe Balbi tusb_dma->sync_dev = -1; 679550a7375SFelipe Balbi 680550a7375SFelipe Balbi tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 681550a7375SFelipe Balbi tusb_dma->controller.channel_release = tusb_omap_dma_release; 682550a7375SFelipe Balbi tusb_dma->controller.channel_program = tusb_omap_dma_program; 683550a7375SFelipe Balbi tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 684550a7375SFelipe Balbi 6857751b6fbSMatwey V. Kornilov if (musb->tusb_revision >= TUSB_REV_30) 686550a7375SFelipe Balbi tusb_dma->multichannel = 1; 687550a7375SFelipe Balbi 688550a7375SFelipe Balbi for (i = 0; i < MAX_DMAREQ; i++) { 689550a7375SFelipe Balbi struct dma_channel *ch; 690550a7375SFelipe Balbi struct tusb_omap_dma_ch *chdat; 691550a7375SFelipe Balbi 692550a7375SFelipe Balbi ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 693550a7375SFelipe Balbi if (!ch) 694550a7375SFelipe Balbi goto cleanup; 695550a7375SFelipe Balbi 696550a7375SFelipe Balbi dma_channel_pool[i] = ch; 697550a7375SFelipe Balbi 698550a7375SFelipe Balbi chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 699550a7375SFelipe Balbi if (!chdat) 700550a7375SFelipe Balbi goto cleanup; 701550a7375SFelipe Balbi 702550a7375SFelipe Balbi ch->status = MUSB_DMA_STATUS_UNKNOWN; 703550a7375SFelipe Balbi ch->private_data = chdat; 704550a7375SFelipe Balbi } 705550a7375SFelipe Balbi 706550a7375SFelipe Balbi return &tusb_dma->controller; 707550a7375SFelipe Balbi 708550a7375SFelipe Balbi cleanup: 7097f6283edSTony Lindgren musb_dma_controller_destroy(&tusb_dma->controller); 710c88ba39cSHuzaifa Sidhpurwala out: 711550a7375SFelipe Balbi return NULL; 712550a7375SFelipe Balbi } 7137f6283edSTony Lindgren EXPORT_SYMBOL_GPL(tusb_dma_controller_create); 714