1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller 4 * 5 * Copyright (C) 2006 Nokia Corporation 6 * Tony Lindgren <tony@atomide.com> 7 */ 8 9 #ifndef __TUSB6010_H__ 10 #define __TUSB6010_H__ 11 12 /* VLYNQ control register. 32-bit at offset 0x000 */ 13 #define TUSB_VLYNQ_CTRL 0x004 14 15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */ 16 #define TUSB_BASE_OFFSET 0x400 17 18 /* FIFO registers 32-bit at offset 0x600 */ 19 #define TUSB_FIFO_BASE 0x600 20 21 /* Device System & Control registers. 32-bit at offset 0x800 */ 22 #define TUSB_SYS_REG_BASE 0x800 23 24 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) 25 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) 26 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) 27 #define TUSB_DEV_CONF_SOFT_ID (1 << 1) 28 #define TUSB_DEV_CONF_ID_SEL (1 << 0) 29 30 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) 31 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) 32 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) 33 #define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23) 34 #define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19) 35 #define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18) 36 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) 37 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) 38 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) 39 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) 40 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) 41 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) 42 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) 43 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) 44 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) 45 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) 46 #define TUSB_PHY_OTG_CTRL_PD (1 << 6) 47 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) 48 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) 49 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) 50 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) 51 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) 52 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) 53 54 /*OTG status register */ 55 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) 56 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) 57 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) 58 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) 59 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) 60 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) 61 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) 62 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) 63 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) 64 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) 65 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) 66 67 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) 68 # define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) 69 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) 70 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) 71 72 /* PRCM configuration register */ 73 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) 74 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) 75 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) 76 77 /* PRCM management register */ 78 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) 79 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) 80 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) 81 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20) 82 #define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19) 83 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) 84 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) 85 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) 86 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) 87 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) 88 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) 89 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) 90 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) 91 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) 92 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) 93 94 /* Wake-up source clear and mask registers */ 95 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) 96 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) 97 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) 98 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) 99 #define TUSB_PRCM_WGPIO_7 (1 << 12) 100 #define TUSB_PRCM_WGPIO_6 (1 << 11) 101 #define TUSB_PRCM_WGPIO_5 (1 << 10) 102 #define TUSB_PRCM_WGPIO_4 (1 << 9) 103 #define TUSB_PRCM_WGPIO_3 (1 << 8) 104 #define TUSB_PRCM_WGPIO_2 (1 << 7) 105 #define TUSB_PRCM_WGPIO_1 (1 << 6) 106 #define TUSB_PRCM_WGPIO_0 (1 << 5) 107 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ 108 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ 109 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ 110 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ 111 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ 112 113 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) 114 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) 115 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) 116 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) 117 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) 118 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) 119 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) 120 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) 121 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) 122 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) 123 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) 124 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) 125 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) 126 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) 127 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) 128 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) 129 130 /* NOR flash interrupt source registers */ 131 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) 132 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) 133 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) 134 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) 135 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) 136 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) 137 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) 138 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) 139 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) 140 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) 141 #define TUSB_INT_SRC_DEV_READY (1 << 12) 142 #define TUSB_INT_SRC_USB_IP_TX (1 << 9) 143 #define TUSB_INT_SRC_USB_IP_RX (1 << 8) 144 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) 145 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) 146 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) 147 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) 148 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) 149 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) 150 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) 151 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) 152 153 /* NOR flash interrupt registers reserved bits. Must be written as 0 */ 154 #define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17) 155 #define TUSB_INT_MASK_RESERVED_13 (1 << 13) 156 #define TUSB_INT_MASK_RESERVED_8 (0xf << 8) 157 #define TUSB_INT_SRC_RESERVED_26 (0x1f << 26) 158 #define TUSB_INT_SRC_RESERVED_18 (0x3f << 18) 159 #define TUSB_INT_SRC_RESERVED_10 (0x03 << 10) 160 161 /* Reserved bits for NOR flash interrupt mask and clear register */ 162 #define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \ 163 TUSB_INT_MASK_RESERVED_13 | \ 164 TUSB_INT_MASK_RESERVED_8) 165 166 /* Reserved bits for NOR flash interrupt status register */ 167 #define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \ 168 TUSB_INT_SRC_RESERVED_18 | \ 169 TUSB_INT_SRC_RESERVED_10) 170 171 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) 172 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) 173 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) 174 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) 175 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) 176 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) 177 178 /* Offsets from each ep base register */ 179 #define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */ 180 #define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */ 181 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188 182 183 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) 184 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) 185 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) 186 187 /* Device System & Control register bitfields */ 188 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18) 189 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) 190 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) 191 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) 192 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) 193 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20) 194 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16) 195 #define TUSB_EP0_CONFIG_SW_EN (1 << 8) 196 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) 197 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) 198 #define TUSB_EP_CONFIG_SW_EN (1 << 31) 199 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) 200 #define TUSB_PROD_TEST_RESET_VAL 0xa596 201 #define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20) 202 203 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) 204 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) 205 #define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf) 206 #define TUSB_DIDR1_HI_REV_20 0 207 #define TUSB_DIDR1_HI_REV_30 1 208 #define TUSB_DIDR1_HI_REV_31 2 209 210 #define TUSB_REV_10 0x10 211 #define TUSB_REV_20 0x20 212 #define TUSB_REV_30 0x30 213 #define TUSB_REV_31 0x31 214 215 #endif /* __TUSB6010_H__ */ 216