1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/init.h> 21 #include <linux/usb.h> 22 #include <linux/irq.h> 23 #include <linux/platform_device.h> 24 25 #include "musb_core.h" 26 27 static void tusb_source_power(struct musb *musb, int is_on); 28 29 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 30 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 31 32 /* 33 * Checks the revision. We need to use the DMA register as 3.0 does not 34 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 35 */ 36 u8 tusb_get_revision(struct musb *musb) 37 { 38 void __iomem *tbase = musb->ctrl_base; 39 u32 die_id; 40 u8 rev; 41 42 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 43 if (TUSB_REV_MAJOR(rev) == 3) { 44 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 45 TUSB_DIDR1_HI)); 46 if (die_id >= TUSB_DIDR1_HI_REV_31) 47 rev |= 1; 48 } 49 50 return rev; 51 } 52 53 static int __init tusb_print_revision(struct musb *musb) 54 { 55 void __iomem *tbase = musb->ctrl_base; 56 u8 rev; 57 58 rev = tusb_get_revision(musb); 59 60 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 61 "prcm", 62 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 63 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 64 "int", 65 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 66 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 67 "gpio", 68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 70 "dma", 71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 73 "dieid", 74 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 75 "rev", 76 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 77 78 return tusb_get_revision(musb); 79 } 80 81 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 82 | TUSB_PHY_OTG_CTRL_TESTM0) 83 84 /* 85 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 86 * Disables power detection in PHY for the duration of idle. 87 */ 88 static void tusb_wbus_quirk(struct musb *musb, int enabled) 89 { 90 void __iomem *tbase = musb->ctrl_base; 91 static u32 phy_otg_ctrl, phy_otg_ena; 92 u32 tmp; 93 94 if (enabled) { 95 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 96 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 97 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 98 | phy_otg_ena | WBUS_QUIRK_MASK; 99 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 100 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 101 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 102 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 103 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 104 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 105 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 106 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 107 & TUSB_PHY_OTG_CTRL_TESTM2) { 108 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 109 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 110 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 111 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 112 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 113 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 114 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 115 phy_otg_ctrl = 0; 116 phy_otg_ena = 0; 117 } 118 } 119 120 /* 121 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 122 * so both loading and unloading FIFOs need explicit byte counts. 123 */ 124 125 static inline void 126 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 127 { 128 u32 val; 129 int i; 130 131 if (len > 4) { 132 for (i = 0; i < (len >> 2); i++) { 133 memcpy(&val, buf, 4); 134 musb_writel(fifo, 0, val); 135 buf += 4; 136 } 137 len %= 4; 138 } 139 if (len > 0) { 140 /* Write the rest 1 - 3 bytes to FIFO */ 141 memcpy(&val, buf, len); 142 musb_writel(fifo, 0, val); 143 } 144 } 145 146 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 147 void __iomem *buf, u16 len) 148 { 149 u32 val; 150 int i; 151 152 if (len > 4) { 153 for (i = 0; i < (len >> 2); i++) { 154 val = musb_readl(fifo, 0); 155 memcpy(buf, &val, 4); 156 buf += 4; 157 } 158 len %= 4; 159 } 160 if (len > 0) { 161 /* Read the rest 1 - 3 bytes from FIFO */ 162 val = musb_readl(fifo, 0); 163 memcpy(buf, &val, len); 164 } 165 } 166 167 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 168 { 169 void __iomem *ep_conf = hw_ep->conf; 170 void __iomem *fifo = hw_ep->fifo; 171 u8 epnum = hw_ep->epnum; 172 173 prefetch(buf); 174 175 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 176 'T', epnum, fifo, len, buf); 177 178 if (epnum) 179 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 180 TUSB_EP_CONFIG_XFR_SIZE(len)); 181 else 182 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 183 TUSB_EP0_CONFIG_XFR_SIZE(len)); 184 185 if (likely((0x01 & (unsigned long) buf) == 0)) { 186 187 /* Best case is 32bit-aligned destination address */ 188 if ((0x02 & (unsigned long) buf) == 0) { 189 if (len >= 4) { 190 writesl(fifo, buf, len >> 2); 191 buf += (len & ~0x03); 192 len &= 0x03; 193 } 194 } else { 195 if (len >= 2) { 196 u32 val; 197 int i; 198 199 /* Cannot use writesw, fifo is 32-bit */ 200 for (i = 0; i < (len >> 2); i++) { 201 val = (u32)(*(u16 *)buf); 202 buf += 2; 203 val |= (*(u16 *)buf) << 16; 204 buf += 2; 205 musb_writel(fifo, 0, val); 206 } 207 len &= 0x03; 208 } 209 } 210 } 211 212 if (len > 0) 213 tusb_fifo_write_unaligned(fifo, buf, len); 214 } 215 216 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 217 { 218 void __iomem *ep_conf = hw_ep->conf; 219 void __iomem *fifo = hw_ep->fifo; 220 u8 epnum = hw_ep->epnum; 221 222 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 223 'R', epnum, fifo, len, buf); 224 225 if (epnum) 226 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 227 TUSB_EP_CONFIG_XFR_SIZE(len)); 228 else 229 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 230 231 if (likely((0x01 & (unsigned long) buf) == 0)) { 232 233 /* Best case is 32bit-aligned destination address */ 234 if ((0x02 & (unsigned long) buf) == 0) { 235 if (len >= 4) { 236 readsl(fifo, buf, len >> 2); 237 buf += (len & ~0x03); 238 len &= 0x03; 239 } 240 } else { 241 if (len >= 2) { 242 u32 val; 243 int i; 244 245 /* Cannot use readsw, fifo is 32-bit */ 246 for (i = 0; i < (len >> 2); i++) { 247 val = musb_readl(fifo, 0); 248 *(u16 *)buf = (u16)(val & 0xffff); 249 buf += 2; 250 *(u16 *)buf = (u16)(val >> 16); 251 buf += 2; 252 } 253 len &= 0x03; 254 } 255 } 256 } 257 258 if (len > 0) 259 tusb_fifo_read_unaligned(fifo, buf, len); 260 } 261 262 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 263 264 /* This is used by gadget drivers, and OTG transceiver logic, allowing 265 * at most mA current to be drawn from VBUS during a Default-B session 266 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 267 * mode), or low power Default-B sessions, something else supplies power. 268 * Caller must take care of locking. 269 */ 270 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA) 271 { 272 struct musb *musb = container_of(x, struct musb, xceiv); 273 void __iomem *tbase = musb->ctrl_base; 274 u32 reg; 275 276 /* 277 * Keep clock active when enabled. Note that this is not tied to 278 * drawing VBUS, as with OTG mA can be less than musb->min_power. 279 */ 280 if (musb->set_clock) { 281 if (mA) 282 musb->set_clock(musb->clock, 1); 283 else 284 musb->set_clock(musb->clock, 0); 285 } 286 287 /* tps65030 seems to consume max 100mA, with maybe 60mA available 288 * (measured on one board) for things other than tps and tusb. 289 * 290 * Boards sharing the CPU clock with CLKIN will need to prevent 291 * certain idle sleep states while the USB link is active. 292 * 293 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 294 * The actual current usage would be very board-specific. For now, 295 * it's simpler to just use an aggregate (also board-specific). 296 */ 297 if (x->default_a || mA < (musb->min_power << 1)) 298 mA = 0; 299 300 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 301 if (mA) { 302 musb->is_bus_powered = 1; 303 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 304 } else { 305 musb->is_bus_powered = 0; 306 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 307 } 308 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 309 310 DBG(2, "draw max %d mA VBUS\n", mA); 311 return 0; 312 } 313 314 #else 315 #define tusb_draw_power NULL 316 #endif 317 318 /* workaround for issue 13: change clock during chip idle 319 * (to be fixed in rev3 silicon) ... symptoms include disconnect 320 * or looping suspend/resume cycles 321 */ 322 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 323 { 324 void __iomem *tbase = musb->ctrl_base; 325 u32 reg; 326 327 reg = musb_readl(tbase, TUSB_PRCM_CONF); 328 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 329 330 /* 0 = refclk (clkin, XI) 331 * 1 = PHY 60 MHz (internal PLL) 332 * 2 = not supported 333 * 3 = what? 334 */ 335 if (mode > 0) 336 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 337 338 musb_writel(tbase, TUSB_PRCM_CONF, reg); 339 340 /* FIXME tusb6010_platform_retime(mode == 0); */ 341 } 342 343 /* 344 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 345 * Other code ensures that we idle unless we're connected _and_ the 346 * USB link is not suspended ... and tells us the relevant wakeup 347 * events. SW_EN for voltage is handled separately. 348 */ 349 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 350 { 351 void __iomem *tbase = musb->ctrl_base; 352 u32 reg; 353 354 if ((wakeup_enables & TUSB_PRCM_WBUS) 355 && (tusb_get_revision(musb) == TUSB_REV_30)) 356 tusb_wbus_quirk(musb, 1); 357 358 tusb_set_clock_source(musb, 0); 359 360 wakeup_enables |= TUSB_PRCM_WNORCS; 361 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 362 363 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 364 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 365 * Presumably that's mostly to save power, hence WID is immaterial ... 366 */ 367 368 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 369 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 370 if (is_host_active(musb)) { 371 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 372 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 373 } else { 374 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 375 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 376 } 377 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 378 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 379 380 DBG(6, "idle, wake on %02x\n", wakeup_enables); 381 } 382 383 /* 384 * Updates cable VBUS status. Caller must take care of locking. 385 */ 386 int musb_platform_get_vbus_status(struct musb *musb) 387 { 388 void __iomem *tbase = musb->ctrl_base; 389 u32 otg_stat, prcm_mngmt; 390 int ret = 0; 391 392 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 393 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 394 395 /* Temporarily enable VBUS detection if it was disabled for 396 * suspend mode. Unless it's enabled otg_stat and devctl will 397 * not show correct VBUS state. 398 */ 399 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 400 u32 tmp = prcm_mngmt; 401 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 402 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 403 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 404 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 405 } 406 407 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 408 ret = 1; 409 410 return ret; 411 } 412 413 static struct timer_list musb_idle_timer; 414 415 static void musb_do_idle(unsigned long _musb) 416 { 417 struct musb *musb = (void *)_musb; 418 unsigned long flags; 419 420 spin_lock_irqsave(&musb->lock, flags); 421 422 switch (musb->xceiv.state) { 423 case OTG_STATE_A_WAIT_BCON: 424 if ((musb->a_wait_bcon != 0) 425 && (musb->idle_timeout == 0 426 || time_after(jiffies, musb->idle_timeout))) { 427 DBG(4, "Nothing connected %s, turning off VBUS\n", 428 otg_state_string(musb)); 429 } 430 /* FALLTHROUGH */ 431 case OTG_STATE_A_IDLE: 432 tusb_source_power(musb, 0); 433 default: 434 break; 435 } 436 437 if (!musb->is_active) { 438 u32 wakeups; 439 440 /* wait until khubd handles port change status */ 441 if (is_host_active(musb) && (musb->port1_status >> 16)) 442 goto done; 443 444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 445 if (is_peripheral_enabled(musb) && !musb->gadget_driver) 446 wakeups = 0; 447 else { 448 wakeups = TUSB_PRCM_WHOSTDISCON 449 | TUSB_PRCM_WBUS 450 | TUSB_PRCM_WVBUS; 451 if (is_otg_enabled(musb)) 452 wakeups |= TUSB_PRCM_WID; 453 } 454 #else 455 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS; 456 #endif 457 tusb_allow_idle(musb, wakeups); 458 } 459 done: 460 spin_unlock_irqrestore(&musb->lock, flags); 461 } 462 463 /* 464 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 465 * like "disconnected" or "suspended". We'll be woken out of it by 466 * connect, resume, or disconnect. 467 * 468 * Needs to be called as the last function everywhere where there is 469 * register access to TUSB6010 because of NOR flash wake-up. 470 * Caller should own controller spinlock. 471 * 472 * Delay because peripheral enables D+ pullup 3msec after SE0, and 473 * we don't want to treat that full speed J as a wakeup event. 474 * ... peripherals must draw only suspend current after 10 msec. 475 */ 476 void musb_platform_try_idle(struct musb *musb, unsigned long timeout) 477 { 478 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 479 static unsigned long last_timer; 480 481 if (timeout == 0) 482 timeout = default_timeout; 483 484 /* Never idle if active, or when VBUS timeout is not set as host */ 485 if (musb->is_active || ((musb->a_wait_bcon == 0) 486 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) { 487 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 488 del_timer(&musb_idle_timer); 489 last_timer = jiffies; 490 return; 491 } 492 493 if (time_after(last_timer, timeout)) { 494 if (!timer_pending(&musb_idle_timer)) 495 last_timer = timeout; 496 else { 497 DBG(4, "Longer idle timer already pending, ignoring\n"); 498 return; 499 } 500 } 501 last_timer = timeout; 502 503 DBG(4, "%s inactive, for idle timer for %lu ms\n", 504 otg_state_string(musb), 505 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 506 mod_timer(&musb_idle_timer, timeout); 507 } 508 509 /* ticks of 60 MHz clock */ 510 #define DEVCLOCK 60000000 511 #define OTG_TIMER_MS(msecs) ((msecs) \ 512 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 513 | TUSB_DEV_OTG_TIMER_ENABLE) \ 514 : 0) 515 516 static void tusb_source_power(struct musb *musb, int is_on) 517 { 518 void __iomem *tbase = musb->ctrl_base; 519 u32 conf, prcm, timer; 520 u8 devctl; 521 522 /* HDRC controls CPEN, but beware current surges during device 523 * connect. They can trigger transient overcurrent conditions 524 * that must be ignored. 525 */ 526 527 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 528 conf = musb_readl(tbase, TUSB_DEV_CONF); 529 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 530 531 if (is_on) { 532 if (musb->set_clock) 533 musb->set_clock(musb->clock, 1); 534 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 535 musb->xceiv.default_a = 1; 536 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 537 devctl |= MUSB_DEVCTL_SESSION; 538 539 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 540 MUSB_HST_MODE(musb); 541 } else { 542 u32 otg_stat; 543 544 timer = 0; 545 546 /* If ID pin is grounded, we want to be a_idle */ 547 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 548 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 549 switch (musb->xceiv.state) { 550 case OTG_STATE_A_WAIT_VRISE: 551 case OTG_STATE_A_WAIT_BCON: 552 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; 553 break; 554 case OTG_STATE_A_WAIT_VFALL: 555 musb->xceiv.state = OTG_STATE_A_IDLE; 556 break; 557 default: 558 musb->xceiv.state = OTG_STATE_A_IDLE; 559 } 560 musb->is_active = 0; 561 musb->xceiv.default_a = 1; 562 MUSB_HST_MODE(musb); 563 } else { 564 musb->is_active = 0; 565 musb->xceiv.default_a = 0; 566 musb->xceiv.state = OTG_STATE_B_IDLE; 567 MUSB_DEV_MODE(musb); 568 } 569 570 devctl &= ~MUSB_DEVCTL_SESSION; 571 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 572 if (musb->set_clock) 573 musb->set_clock(musb->clock, 0); 574 } 575 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 576 577 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 578 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 579 musb_writel(tbase, TUSB_DEV_CONF, conf); 580 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 581 582 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 583 otg_state_string(musb), 584 musb_readb(musb->mregs, MUSB_DEVCTL), 585 musb_readl(tbase, TUSB_DEV_OTG_STAT), 586 conf, prcm); 587 } 588 589 /* 590 * Sets the mode to OTG, peripheral or host by changing the ID detection. 591 * Caller must take care of locking. 592 * 593 * Note that if a mini-A cable is plugged in the ID line will stay down as 594 * the weak ID pull-up is not able to pull the ID up. 595 * 596 * REVISIT: It would be possible to add support for changing between host 597 * and peripheral modes in non-OTG configurations by reconfiguring hardware 598 * and then setting musb->board_mode. For now, only support OTG mode. 599 */ 600 int musb_platform_set_mode(struct musb *musb, u8 musb_mode) 601 { 602 void __iomem *tbase = musb->ctrl_base; 603 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 604 605 if (musb->board_mode != MUSB_OTG) { 606 ERR("Changing mode currently only supported in OTG mode\n"); 607 return -EINVAL; 608 } 609 610 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 611 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 612 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 613 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 614 615 switch (musb_mode) { 616 617 #ifdef CONFIG_USB_MUSB_HDRC_HCD 618 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 619 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 620 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 621 dev_conf |= TUSB_DEV_CONF_ID_SEL; 622 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 623 break; 624 #endif 625 626 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 627 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 628 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 629 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 630 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 631 break; 632 #endif 633 634 #ifdef CONFIG_USB_MUSB_OTG 635 case MUSB_OTG: /* Use PHY ID detection */ 636 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 637 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 638 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 639 break; 640 #endif 641 642 default: 643 DBG(2, "Trying to set mode %i\n", musb_mode); 644 return -EINVAL; 645 } 646 647 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 648 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 649 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 650 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 651 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 652 653 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 654 if ((musb_mode == MUSB_PERIPHERAL) && 655 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 656 INFO("Cannot be peripheral with mini-A cable " 657 "otg_stat: %08x\n", otg_stat); 658 659 return 0; 660 } 661 662 static inline unsigned long 663 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 664 { 665 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 666 unsigned long idle_timeout = 0; 667 668 /* ID pin */ 669 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 670 int default_a; 671 672 if (is_otg_enabled(musb)) 673 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 674 else 675 default_a = is_host_enabled(musb); 676 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 677 musb->xceiv.default_a = default_a; 678 tusb_source_power(musb, default_a); 679 680 /* Don't allow idling immediately */ 681 if (default_a) 682 idle_timeout = jiffies + (HZ * 3); 683 } 684 685 /* VBUS state change */ 686 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 687 688 /* B-dev state machine: no vbus ~= disconnect */ 689 if ((is_otg_enabled(musb) && !musb->xceiv.default_a) 690 || !is_host_enabled(musb)) { 691 #ifdef CONFIG_USB_MUSB_HDRC_HCD 692 /* ? musb_root_disconnect(musb); */ 693 musb->port1_status &= 694 ~(USB_PORT_STAT_CONNECTION 695 | USB_PORT_STAT_ENABLE 696 | USB_PORT_STAT_LOW_SPEED 697 | USB_PORT_STAT_HIGH_SPEED 698 | USB_PORT_STAT_TEST 699 ); 700 #endif 701 702 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 703 DBG(1, "Forcing disconnect (no interrupt)\n"); 704 if (musb->xceiv.state != OTG_STATE_B_IDLE) { 705 /* INTR_DISCONNECT can hide... */ 706 musb->xceiv.state = OTG_STATE_B_IDLE; 707 musb->int_usb |= MUSB_INTR_DISCONNECT; 708 } 709 musb->is_active = 0; 710 } 711 DBG(2, "vbus change, %s, otg %03x\n", 712 otg_state_string(musb), otg_stat); 713 idle_timeout = jiffies + (1 * HZ); 714 schedule_work(&musb->irq_work); 715 716 } else /* A-dev state machine */ { 717 DBG(2, "vbus change, %s, otg %03x\n", 718 otg_state_string(musb), otg_stat); 719 720 switch (musb->xceiv.state) { 721 case OTG_STATE_A_IDLE: 722 DBG(2, "Got SRP, turning on VBUS\n"); 723 musb_set_vbus(musb, 1); 724 725 /* CONNECT can wake if a_wait_bcon is set */ 726 if (musb->a_wait_bcon != 0) 727 musb->is_active = 0; 728 else 729 musb->is_active = 1; 730 731 /* 732 * OPT FS A TD.4.6 needs few seconds for 733 * A_WAIT_VRISE 734 */ 735 idle_timeout = jiffies + (2 * HZ); 736 737 break; 738 case OTG_STATE_A_WAIT_VRISE: 739 /* ignore; A-session-valid < VBUS_VALID/2, 740 * we monitor this with the timer 741 */ 742 break; 743 case OTG_STATE_A_WAIT_VFALL: 744 /* REVISIT this irq triggers during short 745 * spikes caused by enumeration ... 746 */ 747 if (musb->vbuserr_retry) { 748 musb->vbuserr_retry--; 749 tusb_source_power(musb, 1); 750 } else { 751 musb->vbuserr_retry 752 = VBUSERR_RETRY_COUNT; 753 tusb_source_power(musb, 0); 754 } 755 break; 756 default: 757 break; 758 } 759 } 760 } 761 762 /* OTG timer expiration */ 763 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 764 u8 devctl; 765 766 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 767 768 switch (musb->xceiv.state) { 769 case OTG_STATE_A_WAIT_VRISE: 770 /* VBUS has probably been valid for a while now, 771 * but may well have bounced out of range a bit 772 */ 773 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 774 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 775 if ((devctl & MUSB_DEVCTL_VBUS) 776 != MUSB_DEVCTL_VBUS) { 777 DBG(2, "devctl %02x\n", devctl); 778 break; 779 } 780 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 781 musb->is_active = 0; 782 idle_timeout = jiffies 783 + msecs_to_jiffies(musb->a_wait_bcon); 784 } else { 785 /* REVISIT report overcurrent to hub? */ 786 ERR("vbus too slow, devctl %02x\n", devctl); 787 tusb_source_power(musb, 0); 788 } 789 break; 790 case OTG_STATE_A_WAIT_BCON: 791 if (musb->a_wait_bcon != 0) 792 idle_timeout = jiffies 793 + msecs_to_jiffies(musb->a_wait_bcon); 794 break; 795 case OTG_STATE_A_SUSPEND: 796 break; 797 case OTG_STATE_B_WAIT_ACON: 798 break; 799 default: 800 break; 801 } 802 } 803 schedule_work(&musb->irq_work); 804 805 return idle_timeout; 806 } 807 808 static irqreturn_t tusb_interrupt(int irq, void *__hci) 809 { 810 struct musb *musb = __hci; 811 void __iomem *tbase = musb->ctrl_base; 812 unsigned long flags, idle_timeout = 0; 813 u32 int_mask, int_src; 814 815 spin_lock_irqsave(&musb->lock, flags); 816 817 /* Mask all interrupts to allow using both edge and level GPIO irq */ 818 int_mask = musb_readl(tbase, TUSB_INT_MASK); 819 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 820 821 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 822 DBG(3, "TUSB IRQ %08x\n", int_src); 823 824 musb->int_usb = (u8) int_src; 825 826 /* Acknowledge wake-up source interrupts */ 827 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 828 u32 reg; 829 u32 i; 830 831 if (tusb_get_revision(musb) == TUSB_REV_30) 832 tusb_wbus_quirk(musb, 0); 833 834 /* there are issues re-locking the PLL on wakeup ... */ 835 836 /* work around issue 8 */ 837 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 838 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 839 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 840 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 841 if (reg == i) 842 break; 843 DBG(6, "TUSB NOR not ready\n"); 844 } 845 846 /* work around issue 13 (2nd half) */ 847 tusb_set_clock_source(musb, 1); 848 849 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 850 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 851 if (reg & ~TUSB_PRCM_WNORCS) { 852 musb->is_active = 1; 853 schedule_work(&musb->irq_work); 854 } 855 DBG(3, "wake %sactive %02x\n", 856 musb->is_active ? "" : "in", reg); 857 858 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 859 } 860 861 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 862 del_timer(&musb_idle_timer); 863 864 /* OTG state change reports (annoyingly) not issued by Mentor core */ 865 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 866 | TUSB_INT_SRC_OTG_TIMEOUT 867 | TUSB_INT_SRC_ID_STATUS_CHNG)) 868 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 869 870 /* TX dma callback must be handled here, RX dma callback is 871 * handled in tusb_omap_dma_cb. 872 */ 873 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 874 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 875 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 876 877 DBG(3, "DMA IRQ %08x\n", dma_src); 878 real_dma_src = ~real_dma_src & dma_src; 879 if (tusb_dma_omap() && real_dma_src) { 880 int tx_source = (real_dma_src & 0xffff); 881 int i; 882 883 for (i = 1; i <= 15; i++) { 884 if (tx_source & (1 << i)) { 885 DBG(3, "completing ep%i %s\n", i, "tx"); 886 musb_dma_completion(musb, i, 1); 887 } 888 } 889 } 890 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 891 } 892 893 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 894 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 895 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 896 897 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 898 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 899 musb->int_tx = (musb_src & 0xffff); 900 } else { 901 musb->int_rx = 0; 902 musb->int_tx = 0; 903 } 904 905 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 906 musb_interrupt(musb); 907 908 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 909 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 910 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 911 912 musb_platform_try_idle(musb, idle_timeout); 913 914 musb_writel(tbase, TUSB_INT_MASK, int_mask); 915 spin_unlock_irqrestore(&musb->lock, flags); 916 917 return IRQ_HANDLED; 918 } 919 920 static int dma_off; 921 922 /* 923 * Enables TUSB6010. Caller must take care of locking. 924 * REVISIT: 925 * - Check what is unnecessary in MGC_HdrcStart() 926 */ 927 void musb_platform_enable(struct musb *musb) 928 { 929 void __iomem *tbase = musb->ctrl_base; 930 931 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 932 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 933 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 934 935 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 936 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 937 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 938 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 939 940 /* Clear all subsystem interrups */ 941 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 942 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 943 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 944 945 /* Acknowledge pending interrupt(s) */ 946 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 947 948 /* Only 0 clock cycles for minimum interrupt de-assertion time and 949 * interrupt polarity active low seems to work reliably here */ 950 musb_writel(tbase, TUSB_INT_CTRL_CONF, 951 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 952 953 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 954 955 /* maybe force into the Default-A OTG state machine */ 956 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 957 & TUSB_DEV_OTG_STAT_ID_STATUS)) 958 musb_writel(tbase, TUSB_INT_SRC_SET, 959 TUSB_INT_SRC_ID_STATUS_CHNG); 960 961 if (is_dma_capable() && dma_off) 962 printk(KERN_WARNING "%s %s: dma not reactivated\n", 963 __FILE__, __func__); 964 else 965 dma_off = 1; 966 } 967 968 /* 969 * Disables TUSB6010. Caller must take care of locking. 970 */ 971 void musb_platform_disable(struct musb *musb) 972 { 973 void __iomem *tbase = musb->ctrl_base; 974 975 /* FIXME stop DMA, IRQs, timers, ... */ 976 977 /* disable all IRQs */ 978 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 979 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 980 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 981 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 982 983 del_timer(&musb_idle_timer); 984 985 if (is_dma_capable() && !dma_off) { 986 printk(KERN_WARNING "%s %s: dma still active\n", 987 __FILE__, __func__); 988 dma_off = 1; 989 } 990 } 991 992 /* 993 * Sets up TUSB6010 CPU interface specific signals and registers 994 * Note: Settings optimized for OMAP24xx 995 */ 996 static void __init tusb_setup_cpu_interface(struct musb *musb) 997 { 998 void __iomem *tbase = musb->ctrl_base; 999 1000 /* 1001 * Disable GPIO[5:0] pullups (used as output DMA requests) 1002 * Don't disable GPIO[7:6] as they are needed for wake-up. 1003 */ 1004 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1005 1006 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1007 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1008 1009 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1010 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1011 1012 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1013 * de-assertion time 2 system clocks p 62 */ 1014 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1015 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1016 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1017 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1018 1019 /* Set 0 wait count for synchronous burst access */ 1020 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1021 } 1022 1023 static int __init tusb_start(struct musb *musb) 1024 { 1025 void __iomem *tbase = musb->ctrl_base; 1026 int ret = 0; 1027 unsigned long flags; 1028 u32 reg; 1029 1030 if (musb->board_set_power) 1031 ret = musb->board_set_power(1); 1032 if (ret != 0) { 1033 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1034 return ret; 1035 } 1036 1037 spin_lock_irqsave(&musb->lock, flags); 1038 1039 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1040 TUSB_PROD_TEST_RESET_VAL) { 1041 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1042 goto err; 1043 } 1044 1045 ret = tusb_print_revision(musb); 1046 if (ret < 2) { 1047 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1048 ret); 1049 goto err; 1050 } 1051 1052 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1053 * NOR FLASH interface is used */ 1054 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1055 1056 /* Select PHY free running 60MHz as a system clock */ 1057 tusb_set_clock_source(musb, 1); 1058 1059 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1060 * power saving, enable VBus detect and session end comparators, 1061 * enable IDpullup, enable VBus charging */ 1062 musb_writel(tbase, TUSB_PRCM_MNGMT, 1063 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1064 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1065 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1066 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1067 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1068 tusb_setup_cpu_interface(musb); 1069 1070 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1071 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1072 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1073 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1074 1075 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1076 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1077 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1078 1079 spin_unlock_irqrestore(&musb->lock, flags); 1080 1081 return 0; 1082 1083 err: 1084 spin_unlock_irqrestore(&musb->lock, flags); 1085 1086 if (musb->board_set_power) 1087 musb->board_set_power(0); 1088 1089 return -ENODEV; 1090 } 1091 1092 int __init musb_platform_init(struct musb *musb) 1093 { 1094 struct platform_device *pdev; 1095 struct resource *mem; 1096 void __iomem *sync; 1097 int ret; 1098 1099 pdev = to_platform_device(musb->controller); 1100 1101 /* dma address for async dma */ 1102 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1103 musb->async = mem->start; 1104 1105 /* dma address for sync dma */ 1106 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1107 if (!mem) { 1108 pr_debug("no sync dma resource?\n"); 1109 return -ENODEV; 1110 } 1111 musb->sync = mem->start; 1112 1113 sync = ioremap(mem->start, mem->end - mem->start + 1); 1114 if (!sync) { 1115 pr_debug("ioremap for sync failed\n"); 1116 return -ENOMEM; 1117 } 1118 musb->sync_va = sync; 1119 1120 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1121 * FIFOs at 0x600, TUSB at 0x800 1122 */ 1123 musb->mregs += TUSB_BASE_OFFSET; 1124 1125 ret = tusb_start(musb); 1126 if (ret) { 1127 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1128 ret); 1129 return -ENODEV; 1130 } 1131 musb->isr = tusb_interrupt; 1132 1133 if (is_host_enabled(musb)) 1134 musb->board_set_vbus = tusb_source_power; 1135 if (is_peripheral_enabled(musb)) 1136 musb->xceiv.set_power = tusb_draw_power; 1137 1138 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1139 1140 return ret; 1141 } 1142 1143 int musb_platform_exit(struct musb *musb) 1144 { 1145 del_timer_sync(&musb_idle_timer); 1146 1147 if (musb->board_set_power) 1148 musb->board_set_power(0); 1149 1150 iounmap(musb->sync_va); 1151 1152 return 0; 1153 } 1154