1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Jarkko Nikula <jarkko.nikula@nokia.com> 6 * Tony Lindgren <tony@atomide.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Notes: 13 * - Driver assumes that interface to external host (main CPU) is 14 * configured for NOR FLASH interface instead of VLYNQ serial 15 * interface. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/init.h> 22 #include <linux/usb.h> 23 #include <linux/irq.h> 24 #include <linux/platform_device.h> 25 26 #include "musb_core.h" 27 28 static void tusb_source_power(struct musb *musb, int is_on); 29 30 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 31 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 32 33 /* 34 * Checks the revision. We need to use the DMA register as 3.0 does not 35 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 36 */ 37 u8 tusb_get_revision(struct musb *musb) 38 { 39 void __iomem *tbase = musb->ctrl_base; 40 u32 die_id; 41 u8 rev; 42 43 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 44 if (TUSB_REV_MAJOR(rev) == 3) { 45 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 46 TUSB_DIDR1_HI)); 47 if (die_id >= TUSB_DIDR1_HI_REV_31) 48 rev |= 1; 49 } 50 51 return rev; 52 } 53 54 static int __init tusb_print_revision(struct musb *musb) 55 { 56 void __iomem *tbase = musb->ctrl_base; 57 u8 rev; 58 59 rev = tusb_get_revision(musb); 60 61 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 62 "prcm", 63 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 64 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 65 "int", 66 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 67 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 68 "gpio", 69 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 70 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 71 "dma", 72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 74 "dieid", 75 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 76 "rev", 77 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 78 79 return tusb_get_revision(musb); 80 } 81 82 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 83 | TUSB_PHY_OTG_CTRL_TESTM0) 84 85 /* 86 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 87 * Disables power detection in PHY for the duration of idle. 88 */ 89 static void tusb_wbus_quirk(struct musb *musb, int enabled) 90 { 91 void __iomem *tbase = musb->ctrl_base; 92 static u32 phy_otg_ctrl, phy_otg_ena; 93 u32 tmp; 94 95 if (enabled) { 96 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 97 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 98 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 99 | phy_otg_ena | WBUS_QUIRK_MASK; 100 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 101 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 102 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 103 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 104 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 105 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 106 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 107 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 108 & TUSB_PHY_OTG_CTRL_TESTM2) { 109 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 110 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 111 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 112 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 113 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 114 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 115 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 116 phy_otg_ctrl = 0; 117 phy_otg_ena = 0; 118 } 119 } 120 121 /* 122 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 123 * so both loading and unloading FIFOs need explicit byte counts. 124 */ 125 126 static inline void 127 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 128 { 129 u32 val; 130 int i; 131 132 if (len > 4) { 133 for (i = 0; i < (len >> 2); i++) { 134 memcpy(&val, buf, 4); 135 musb_writel(fifo, 0, val); 136 buf += 4; 137 } 138 len %= 4; 139 } 140 if (len > 0) { 141 /* Write the rest 1 - 3 bytes to FIFO */ 142 memcpy(&val, buf, len); 143 musb_writel(fifo, 0, val); 144 } 145 } 146 147 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 148 void __iomem *buf, u16 len) 149 { 150 u32 val; 151 int i; 152 153 if (len > 4) { 154 for (i = 0; i < (len >> 2); i++) { 155 val = musb_readl(fifo, 0); 156 memcpy(buf, &val, 4); 157 buf += 4; 158 } 159 len %= 4; 160 } 161 if (len > 0) { 162 /* Read the rest 1 - 3 bytes from FIFO */ 163 val = musb_readl(fifo, 0); 164 memcpy(buf, &val, len); 165 } 166 } 167 168 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 169 { 170 void __iomem *ep_conf = hw_ep->conf; 171 void __iomem *fifo = hw_ep->fifo; 172 u8 epnum = hw_ep->epnum; 173 174 prefetch(buf); 175 176 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 177 'T', epnum, fifo, len, buf); 178 179 if (epnum) 180 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 181 TUSB_EP_CONFIG_XFR_SIZE(len)); 182 else 183 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 184 TUSB_EP0_CONFIG_XFR_SIZE(len)); 185 186 if (likely((0x01 & (unsigned long) buf) == 0)) { 187 188 /* Best case is 32bit-aligned destination address */ 189 if ((0x02 & (unsigned long) buf) == 0) { 190 if (len >= 4) { 191 writesl(fifo, buf, len >> 2); 192 buf += (len & ~0x03); 193 len &= 0x03; 194 } 195 } else { 196 if (len >= 2) { 197 u32 val; 198 int i; 199 200 /* Cannot use writesw, fifo is 32-bit */ 201 for (i = 0; i < (len >> 2); i++) { 202 val = (u32)(*(u16 *)buf); 203 buf += 2; 204 val |= (*(u16 *)buf) << 16; 205 buf += 2; 206 musb_writel(fifo, 0, val); 207 } 208 len &= 0x03; 209 } 210 } 211 } 212 213 if (len > 0) 214 tusb_fifo_write_unaligned(fifo, buf, len); 215 } 216 217 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 218 { 219 void __iomem *ep_conf = hw_ep->conf; 220 void __iomem *fifo = hw_ep->fifo; 221 u8 epnum = hw_ep->epnum; 222 223 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 224 'R', epnum, fifo, len, buf); 225 226 if (epnum) 227 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 228 TUSB_EP_CONFIG_XFR_SIZE(len)); 229 else 230 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 231 232 if (likely((0x01 & (unsigned long) buf) == 0)) { 233 234 /* Best case is 32bit-aligned destination address */ 235 if ((0x02 & (unsigned long) buf) == 0) { 236 if (len >= 4) { 237 readsl(fifo, buf, len >> 2); 238 buf += (len & ~0x03); 239 len &= 0x03; 240 } 241 } else { 242 if (len >= 2) { 243 u32 val; 244 int i; 245 246 /* Cannot use readsw, fifo is 32-bit */ 247 for (i = 0; i < (len >> 2); i++) { 248 val = musb_readl(fifo, 0); 249 *(u16 *)buf = (u16)(val & 0xffff); 250 buf += 2; 251 *(u16 *)buf = (u16)(val >> 16); 252 buf += 2; 253 } 254 len &= 0x03; 255 } 256 } 257 } 258 259 if (len > 0) 260 tusb_fifo_read_unaligned(fifo, buf, len); 261 } 262 263 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 264 265 /* This is used by gadget drivers, and OTG transceiver logic, allowing 266 * at most mA current to be drawn from VBUS during a Default-B session 267 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 268 * mode), or low power Default-B sessions, something else supplies power. 269 * Caller must take care of locking. 270 */ 271 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA) 272 { 273 struct musb *musb = container_of(x, struct musb, xceiv); 274 void __iomem *tbase = musb->ctrl_base; 275 u32 reg; 276 277 /* 278 * Keep clock active when enabled. Note that this is not tied to 279 * drawing VBUS, as with OTG mA can be less than musb->min_power. 280 */ 281 if (musb->set_clock) { 282 if (mA) 283 musb->set_clock(musb->clock, 1); 284 else 285 musb->set_clock(musb->clock, 0); 286 } 287 288 /* tps65030 seems to consume max 100mA, with maybe 60mA available 289 * (measured on one board) for things other than tps and tusb. 290 * 291 * Boards sharing the CPU clock with CLKIN will need to prevent 292 * certain idle sleep states while the USB link is active. 293 * 294 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 295 * The actual current usage would be very board-specific. For now, 296 * it's simpler to just use an aggregate (also board-specific). 297 */ 298 if (x->default_a || mA < (musb->min_power << 1)) 299 mA = 0; 300 301 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 302 if (mA) { 303 musb->is_bus_powered = 1; 304 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 305 } else { 306 musb->is_bus_powered = 0; 307 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 308 } 309 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 310 311 DBG(2, "draw max %d mA VBUS\n", mA); 312 return 0; 313 } 314 315 #else 316 #define tusb_draw_power NULL 317 #endif 318 319 /* workaround for issue 13: change clock during chip idle 320 * (to be fixed in rev3 silicon) ... symptoms include disconnect 321 * or looping suspend/resume cycles 322 */ 323 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 324 { 325 void __iomem *tbase = musb->ctrl_base; 326 u32 reg; 327 328 reg = musb_readl(tbase, TUSB_PRCM_CONF); 329 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 330 331 /* 0 = refclk (clkin, XI) 332 * 1 = PHY 60 MHz (internal PLL) 333 * 2 = not supported 334 * 3 = what? 335 */ 336 if (mode > 0) 337 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 338 339 musb_writel(tbase, TUSB_PRCM_CONF, reg); 340 341 /* FIXME tusb6010_platform_retime(mode == 0); */ 342 } 343 344 /* 345 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 346 * Other code ensures that we idle unless we're connected _and_ the 347 * USB link is not suspended ... and tells us the relevant wakeup 348 * events. SW_EN for voltage is handled separately. 349 */ 350 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 351 { 352 void __iomem *tbase = musb->ctrl_base; 353 u32 reg; 354 355 if ((wakeup_enables & TUSB_PRCM_WBUS) 356 && (tusb_get_revision(musb) == TUSB_REV_30)) 357 tusb_wbus_quirk(musb, 1); 358 359 tusb_set_clock_source(musb, 0); 360 361 wakeup_enables |= TUSB_PRCM_WNORCS; 362 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 363 364 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 365 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 366 * Presumably that's mostly to save power, hence WID is immaterial ... 367 */ 368 369 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 370 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 371 if (is_host_active(musb)) { 372 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 373 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 374 } else { 375 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 376 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 377 } 378 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 379 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 380 381 DBG(6, "idle, wake on %02x\n", wakeup_enables); 382 } 383 384 /* 385 * Updates cable VBUS status. Caller must take care of locking. 386 */ 387 int musb_platform_get_vbus_status(struct musb *musb) 388 { 389 void __iomem *tbase = musb->ctrl_base; 390 u32 otg_stat, prcm_mngmt; 391 int ret = 0; 392 393 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 394 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 395 396 /* Temporarily enable VBUS detection if it was disabled for 397 * suspend mode. Unless it's enabled otg_stat and devctl will 398 * not show correct VBUS state. 399 */ 400 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 401 u32 tmp = prcm_mngmt; 402 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 403 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 404 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 405 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 406 } 407 408 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 409 ret = 1; 410 411 return ret; 412 } 413 414 static struct timer_list musb_idle_timer; 415 416 static void musb_do_idle(unsigned long _musb) 417 { 418 struct musb *musb = (void *)_musb; 419 unsigned long flags; 420 421 spin_lock_irqsave(&musb->lock, flags); 422 423 switch (musb->xceiv.state) { 424 case OTG_STATE_A_WAIT_BCON: 425 if ((musb->a_wait_bcon != 0) 426 && (musb->idle_timeout == 0 427 || time_after(jiffies, musb->idle_timeout))) { 428 DBG(4, "Nothing connected %s, turning off VBUS\n", 429 otg_state_string(musb)); 430 } 431 /* FALLTHROUGH */ 432 case OTG_STATE_A_IDLE: 433 tusb_source_power(musb, 0); 434 default: 435 break; 436 } 437 438 if (!musb->is_active) { 439 u32 wakeups; 440 441 /* wait until khubd handles port change status */ 442 if (is_host_active(musb) && (musb->port1_status >> 16)) 443 goto done; 444 445 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 446 if (is_peripheral_enabled(musb) && !musb->gadget_driver) 447 wakeups = 0; 448 else { 449 wakeups = TUSB_PRCM_WHOSTDISCON 450 | TUSB_PRCM_WBUS 451 | TUSB_PRCM_WVBUS; 452 if (is_otg_enabled(musb)) 453 wakeups |= TUSB_PRCM_WID; 454 } 455 #else 456 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS; 457 #endif 458 tusb_allow_idle(musb, wakeups); 459 } 460 done: 461 spin_unlock_irqrestore(&musb->lock, flags); 462 } 463 464 /* 465 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 466 * like "disconnected" or "suspended". We'll be woken out of it by 467 * connect, resume, or disconnect. 468 * 469 * Needs to be called as the last function everywhere where there is 470 * register access to TUSB6010 because of NOR flash wake-up. 471 * Caller should own controller spinlock. 472 * 473 * Delay because peripheral enables D+ pullup 3msec after SE0, and 474 * we don't want to treat that full speed J as a wakeup event. 475 * ... peripherals must draw only suspend current after 10 msec. 476 */ 477 void musb_platform_try_idle(struct musb *musb, unsigned long timeout) 478 { 479 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 480 static unsigned long last_timer; 481 482 if (timeout == 0) 483 timeout = default_timeout; 484 485 /* Never idle if active, or when VBUS timeout is not set as host */ 486 if (musb->is_active || ((musb->a_wait_bcon == 0) 487 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) { 488 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 489 del_timer(&musb_idle_timer); 490 last_timer = jiffies; 491 return; 492 } 493 494 if (time_after(last_timer, timeout)) { 495 if (!timer_pending(&musb_idle_timer)) 496 last_timer = timeout; 497 else { 498 DBG(4, "Longer idle timer already pending, ignoring\n"); 499 return; 500 } 501 } 502 last_timer = timeout; 503 504 DBG(4, "%s inactive, for idle timer for %lu ms\n", 505 otg_state_string(musb), 506 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 507 mod_timer(&musb_idle_timer, timeout); 508 } 509 510 /* ticks of 60 MHz clock */ 511 #define DEVCLOCK 60000000 512 #define OTG_TIMER_MS(msecs) ((msecs) \ 513 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 514 | TUSB_DEV_OTG_TIMER_ENABLE) \ 515 : 0) 516 517 static void tusb_source_power(struct musb *musb, int is_on) 518 { 519 void __iomem *tbase = musb->ctrl_base; 520 u32 conf, prcm, timer; 521 u8 devctl; 522 523 /* HDRC controls CPEN, but beware current surges during device 524 * connect. They can trigger transient overcurrent conditions 525 * that must be ignored. 526 */ 527 528 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 529 conf = musb_readl(tbase, TUSB_DEV_CONF); 530 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 531 532 if (is_on) { 533 if (musb->set_clock) 534 musb->set_clock(musb->clock, 1); 535 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 536 musb->xceiv.default_a = 1; 537 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 538 devctl |= MUSB_DEVCTL_SESSION; 539 540 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 541 MUSB_HST_MODE(musb); 542 } else { 543 u32 otg_stat; 544 545 timer = 0; 546 547 /* If ID pin is grounded, we want to be a_idle */ 548 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 549 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 550 switch (musb->xceiv.state) { 551 case OTG_STATE_A_WAIT_VRISE: 552 case OTG_STATE_A_WAIT_BCON: 553 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; 554 break; 555 case OTG_STATE_A_WAIT_VFALL: 556 musb->xceiv.state = OTG_STATE_A_IDLE; 557 break; 558 default: 559 musb->xceiv.state = OTG_STATE_A_IDLE; 560 } 561 musb->is_active = 0; 562 musb->xceiv.default_a = 1; 563 MUSB_HST_MODE(musb); 564 } else { 565 musb->is_active = 0; 566 musb->xceiv.default_a = 0; 567 musb->xceiv.state = OTG_STATE_B_IDLE; 568 MUSB_DEV_MODE(musb); 569 } 570 571 devctl &= ~MUSB_DEVCTL_SESSION; 572 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 573 if (musb->set_clock) 574 musb->set_clock(musb->clock, 0); 575 } 576 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 577 578 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 579 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 580 musb_writel(tbase, TUSB_DEV_CONF, conf); 581 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 582 583 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 584 otg_state_string(musb), 585 musb_readb(musb->mregs, MUSB_DEVCTL), 586 musb_readl(tbase, TUSB_DEV_OTG_STAT), 587 conf, prcm); 588 } 589 590 /* 591 * Sets the mode to OTG, peripheral or host by changing the ID detection. 592 * Caller must take care of locking. 593 * 594 * Note that if a mini-A cable is plugged in the ID line will stay down as 595 * the weak ID pull-up is not able to pull the ID up. 596 * 597 * REVISIT: It would be possible to add support for changing between host 598 * and peripheral modes in non-OTG configurations by reconfiguring hardware 599 * and then setting musb->board_mode. For now, only support OTG mode. 600 */ 601 void musb_platform_set_mode(struct musb *musb, u8 musb_mode) 602 { 603 void __iomem *tbase = musb->ctrl_base; 604 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 605 606 if (musb->board_mode != MUSB_OTG) { 607 ERR("Changing mode currently only supported in OTG mode\n"); 608 return; 609 } 610 611 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 612 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 613 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 614 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 615 616 switch (musb_mode) { 617 618 #ifdef CONFIG_USB_MUSB_HDRC_HCD 619 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 620 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 621 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 622 dev_conf |= TUSB_DEV_CONF_ID_SEL; 623 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 624 break; 625 #endif 626 627 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 628 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 629 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 630 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 631 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 632 break; 633 #endif 634 635 #ifdef CONFIG_USB_MUSB_OTG 636 case MUSB_OTG: /* Use PHY ID detection */ 637 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 638 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 639 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 640 break; 641 #endif 642 643 default: 644 DBG(2, "Trying to set unknown mode %i\n", musb_mode); 645 } 646 647 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 648 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 649 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 650 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 651 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 652 653 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 654 if ((musb_mode == MUSB_PERIPHERAL) && 655 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 656 INFO("Cannot be peripheral with mini-A cable " 657 "otg_stat: %08x\n", otg_stat); 658 } 659 660 static inline unsigned long 661 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 662 { 663 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 664 unsigned long idle_timeout = 0; 665 666 /* ID pin */ 667 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 668 int default_a; 669 670 if (is_otg_enabled(musb)) 671 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 672 else 673 default_a = is_host_enabled(musb); 674 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 675 musb->xceiv.default_a = default_a; 676 tusb_source_power(musb, default_a); 677 678 /* Don't allow idling immediately */ 679 if (default_a) 680 idle_timeout = jiffies + (HZ * 3); 681 } 682 683 /* VBUS state change */ 684 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 685 686 /* B-dev state machine: no vbus ~= disconnect */ 687 if ((is_otg_enabled(musb) && !musb->xceiv.default_a) 688 || !is_host_enabled(musb)) { 689 #ifdef CONFIG_USB_MUSB_HDRC_HCD 690 /* ? musb_root_disconnect(musb); */ 691 musb->port1_status &= 692 ~(USB_PORT_STAT_CONNECTION 693 | USB_PORT_STAT_ENABLE 694 | USB_PORT_STAT_LOW_SPEED 695 | USB_PORT_STAT_HIGH_SPEED 696 | USB_PORT_STAT_TEST 697 ); 698 #endif 699 700 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 701 DBG(1, "Forcing disconnect (no interrupt)\n"); 702 if (musb->xceiv.state != OTG_STATE_B_IDLE) { 703 /* INTR_DISCONNECT can hide... */ 704 musb->xceiv.state = OTG_STATE_B_IDLE; 705 musb->int_usb |= MUSB_INTR_DISCONNECT; 706 } 707 musb->is_active = 0; 708 } 709 DBG(2, "vbus change, %s, otg %03x\n", 710 otg_state_string(musb), otg_stat); 711 idle_timeout = jiffies + (1 * HZ); 712 schedule_work(&musb->irq_work); 713 714 } else /* A-dev state machine */ { 715 DBG(2, "vbus change, %s, otg %03x\n", 716 otg_state_string(musb), otg_stat); 717 718 switch (musb->xceiv.state) { 719 case OTG_STATE_A_IDLE: 720 DBG(2, "Got SRP, turning on VBUS\n"); 721 musb_set_vbus(musb, 1); 722 723 /* CONNECT can wake if a_wait_bcon is set */ 724 if (musb->a_wait_bcon != 0) 725 musb->is_active = 0; 726 else 727 musb->is_active = 1; 728 729 /* 730 * OPT FS A TD.4.6 needs few seconds for 731 * A_WAIT_VRISE 732 */ 733 idle_timeout = jiffies + (2 * HZ); 734 735 break; 736 case OTG_STATE_A_WAIT_VRISE: 737 /* ignore; A-session-valid < VBUS_VALID/2, 738 * we monitor this with the timer 739 */ 740 break; 741 case OTG_STATE_A_WAIT_VFALL: 742 /* REVISIT this irq triggers during short 743 * spikes caused by enumeration ... 744 */ 745 if (musb->vbuserr_retry) { 746 musb->vbuserr_retry--; 747 tusb_source_power(musb, 1); 748 } else { 749 musb->vbuserr_retry 750 = VBUSERR_RETRY_COUNT; 751 tusb_source_power(musb, 0); 752 } 753 break; 754 default: 755 break; 756 } 757 } 758 } 759 760 /* OTG timer expiration */ 761 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 762 u8 devctl; 763 764 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 765 766 switch (musb->xceiv.state) { 767 case OTG_STATE_A_WAIT_VRISE: 768 /* VBUS has probably been valid for a while now, 769 * but may well have bounced out of range a bit 770 */ 771 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 772 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 773 if ((devctl & MUSB_DEVCTL_VBUS) 774 != MUSB_DEVCTL_VBUS) { 775 DBG(2, "devctl %02x\n", devctl); 776 break; 777 } 778 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 779 musb->is_active = 0; 780 idle_timeout = jiffies 781 + msecs_to_jiffies(musb->a_wait_bcon); 782 } else { 783 /* REVISIT report overcurrent to hub? */ 784 ERR("vbus too slow, devctl %02x\n", devctl); 785 tusb_source_power(musb, 0); 786 } 787 break; 788 case OTG_STATE_A_WAIT_BCON: 789 if (musb->a_wait_bcon != 0) 790 idle_timeout = jiffies 791 + msecs_to_jiffies(musb->a_wait_bcon); 792 break; 793 case OTG_STATE_A_SUSPEND: 794 break; 795 case OTG_STATE_B_WAIT_ACON: 796 break; 797 default: 798 break; 799 } 800 } 801 schedule_work(&musb->irq_work); 802 803 return idle_timeout; 804 } 805 806 static irqreturn_t tusb_interrupt(int irq, void *__hci) 807 { 808 struct musb *musb = __hci; 809 void __iomem *tbase = musb->ctrl_base; 810 unsigned long flags, idle_timeout = 0; 811 u32 int_mask, int_src; 812 813 spin_lock_irqsave(&musb->lock, flags); 814 815 /* Mask all interrupts to allow using both edge and level GPIO irq */ 816 int_mask = musb_readl(tbase, TUSB_INT_MASK); 817 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 818 819 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 820 DBG(3, "TUSB IRQ %08x\n", int_src); 821 822 musb->int_usb = (u8) int_src; 823 824 /* Acknowledge wake-up source interrupts */ 825 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 826 u32 reg; 827 u32 i; 828 829 if (tusb_get_revision(musb) == TUSB_REV_30) 830 tusb_wbus_quirk(musb, 0); 831 832 /* there are issues re-locking the PLL on wakeup ... */ 833 834 /* work around issue 8 */ 835 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 836 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 837 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 838 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 839 if (reg == i) 840 break; 841 DBG(6, "TUSB NOR not ready\n"); 842 } 843 844 /* work around issue 13 (2nd half) */ 845 tusb_set_clock_source(musb, 1); 846 847 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 848 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 849 if (reg & ~TUSB_PRCM_WNORCS) { 850 musb->is_active = 1; 851 schedule_work(&musb->irq_work); 852 } 853 DBG(3, "wake %sactive %02x\n", 854 musb->is_active ? "" : "in", reg); 855 856 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 857 } 858 859 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 860 del_timer(&musb_idle_timer); 861 862 /* OTG state change reports (annoyingly) not issued by Mentor core */ 863 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 864 | TUSB_INT_SRC_OTG_TIMEOUT 865 | TUSB_INT_SRC_ID_STATUS_CHNG)) 866 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 867 868 /* TX dma callback must be handled here, RX dma callback is 869 * handled in tusb_omap_dma_cb. 870 */ 871 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 872 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 873 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 874 875 DBG(3, "DMA IRQ %08x\n", dma_src); 876 real_dma_src = ~real_dma_src & dma_src; 877 if (tusb_dma_omap() && real_dma_src) { 878 int tx_source = (real_dma_src & 0xffff); 879 int i; 880 881 for (i = 1; i <= 15; i++) { 882 if (tx_source & (1 << i)) { 883 DBG(3, "completing ep%i %s\n", i, "tx"); 884 musb_dma_completion(musb, i, 1); 885 } 886 } 887 } 888 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 889 } 890 891 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 892 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 893 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 894 895 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 896 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 897 musb->int_tx = (musb_src & 0xffff); 898 } else { 899 musb->int_rx = 0; 900 musb->int_tx = 0; 901 } 902 903 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 904 musb_interrupt(musb); 905 906 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 907 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 908 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 909 910 musb_platform_try_idle(musb, idle_timeout); 911 912 musb_writel(tbase, TUSB_INT_MASK, int_mask); 913 spin_unlock_irqrestore(&musb->lock, flags); 914 915 return IRQ_HANDLED; 916 } 917 918 static int dma_off; 919 920 /* 921 * Enables TUSB6010. Caller must take care of locking. 922 * REVISIT: 923 * - Check what is unnecessary in MGC_HdrcStart() 924 */ 925 void musb_platform_enable(struct musb *musb) 926 { 927 void __iomem *tbase = musb->ctrl_base; 928 929 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 930 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 931 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 932 933 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 934 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 935 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 936 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 937 938 /* Clear all subsystem interrups */ 939 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 940 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 941 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 942 943 /* Acknowledge pending interrupt(s) */ 944 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 945 946 /* Only 0 clock cycles for minimum interrupt de-assertion time and 947 * interrupt polarity active low seems to work reliably here */ 948 musb_writel(tbase, TUSB_INT_CTRL_CONF, 949 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 950 951 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 952 953 /* maybe force into the Default-A OTG state machine */ 954 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 955 & TUSB_DEV_OTG_STAT_ID_STATUS)) 956 musb_writel(tbase, TUSB_INT_SRC_SET, 957 TUSB_INT_SRC_ID_STATUS_CHNG); 958 959 if (is_dma_capable() && dma_off) 960 printk(KERN_WARNING "%s %s: dma not reactivated\n", 961 __FILE__, __func__); 962 else 963 dma_off = 1; 964 } 965 966 /* 967 * Disables TUSB6010. Caller must take care of locking. 968 */ 969 void musb_platform_disable(struct musb *musb) 970 { 971 void __iomem *tbase = musb->ctrl_base; 972 973 /* FIXME stop DMA, IRQs, timers, ... */ 974 975 /* disable all IRQs */ 976 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 977 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 978 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 979 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 980 981 del_timer(&musb_idle_timer); 982 983 if (is_dma_capable() && !dma_off) { 984 printk(KERN_WARNING "%s %s: dma still active\n", 985 __FILE__, __func__); 986 dma_off = 1; 987 } 988 } 989 990 /* 991 * Sets up TUSB6010 CPU interface specific signals and registers 992 * Note: Settings optimized for OMAP24xx 993 */ 994 static void __init tusb_setup_cpu_interface(struct musb *musb) 995 { 996 void __iomem *tbase = musb->ctrl_base; 997 998 /* 999 * Disable GPIO[5:0] pullups (used as output DMA requests) 1000 * Don't disable GPIO[7:6] as they are needed for wake-up. 1001 */ 1002 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1003 1004 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1005 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1006 1007 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1008 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1009 1010 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1011 * de-assertion time 2 system clocks p 62 */ 1012 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1013 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1014 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1015 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1016 1017 /* Set 0 wait count for synchronous burst access */ 1018 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1019 } 1020 1021 static int __init tusb_start(struct musb *musb) 1022 { 1023 void __iomem *tbase = musb->ctrl_base; 1024 int ret = 0; 1025 unsigned long flags; 1026 u32 reg; 1027 1028 if (musb->board_set_power) 1029 ret = musb->board_set_power(1); 1030 if (ret != 0) { 1031 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1032 return ret; 1033 } 1034 1035 spin_lock_irqsave(&musb->lock, flags); 1036 1037 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1038 TUSB_PROD_TEST_RESET_VAL) { 1039 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1040 goto err; 1041 } 1042 1043 ret = tusb_print_revision(musb); 1044 if (ret < 2) { 1045 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1046 ret); 1047 goto err; 1048 } 1049 1050 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1051 * NOR FLASH interface is used */ 1052 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1053 1054 /* Select PHY free running 60MHz as a system clock */ 1055 tusb_set_clock_source(musb, 1); 1056 1057 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1058 * power saving, enable VBus detect and session end comparators, 1059 * enable IDpullup, enable VBus charging */ 1060 musb_writel(tbase, TUSB_PRCM_MNGMT, 1061 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1062 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1063 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1064 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1065 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1066 tusb_setup_cpu_interface(musb); 1067 1068 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1069 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1070 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1071 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1072 1073 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1074 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1075 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1076 1077 spin_unlock_irqrestore(&musb->lock, flags); 1078 1079 return 0; 1080 1081 err: 1082 spin_unlock_irqrestore(&musb->lock, flags); 1083 1084 if (musb->board_set_power) 1085 musb->board_set_power(0); 1086 1087 return -ENODEV; 1088 } 1089 1090 int __init musb_platform_init(struct musb *musb) 1091 { 1092 struct platform_device *pdev; 1093 struct resource *mem; 1094 void __iomem *sync; 1095 int ret; 1096 1097 pdev = to_platform_device(musb->controller); 1098 1099 /* dma address for async dma */ 1100 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1101 musb->async = mem->start; 1102 1103 /* dma address for sync dma */ 1104 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1105 if (!mem) { 1106 pr_debug("no sync dma resource?\n"); 1107 return -ENODEV; 1108 } 1109 musb->sync = mem->start; 1110 1111 sync = ioremap(mem->start, mem->end - mem->start + 1); 1112 if (!sync) { 1113 pr_debug("ioremap for sync failed\n"); 1114 return -ENOMEM; 1115 } 1116 musb->sync_va = sync; 1117 1118 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1119 * FIFOs at 0x600, TUSB at 0x800 1120 */ 1121 musb->mregs += TUSB_BASE_OFFSET; 1122 1123 ret = tusb_start(musb); 1124 if (ret) { 1125 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1126 ret); 1127 return -ENODEV; 1128 } 1129 musb->isr = tusb_interrupt; 1130 1131 if (is_host_enabled(musb)) 1132 musb->board_set_vbus = tusb_source_power; 1133 if (is_peripheral_enabled(musb)) 1134 musb->xceiv.set_power = tusb_draw_power; 1135 1136 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1137 1138 return ret; 1139 } 1140 1141 int musb_platform_exit(struct musb *musb) 1142 { 1143 del_timer_sync(&musb_idle_timer); 1144 1145 if (musb->board_set_power) 1146 musb->board_set_power(0); 1147 1148 iounmap(musb->sync_va); 1149 1150 return 0; 1151 } 1152