1 /* 2 * MUSB OTG driver register defines 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 #ifndef __MUSB_REGS_H__ 36 #define __MUSB_REGS_H__ 37 38 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 39 40 /* 41 * Common USB registers 42 */ 43 44 #define MUSB_FADDR 0x00 /* 8-bit */ 45 #define MUSB_POWER 0x01 /* 8-bit */ 46 47 #define MUSB_INTRTX 0x02 /* 16-bit */ 48 #define MUSB_INTRRX 0x04 49 #define MUSB_INTRTXE 0x06 50 #define MUSB_INTRRXE 0x08 51 #define MUSB_INTRUSB 0x0A /* 8 bit */ 52 #define MUSB_INTRUSBE 0x0B /* 8 bit */ 53 #define MUSB_FRAME 0x0C 54 #define MUSB_INDEX 0x0E /* 8 bit */ 55 #define MUSB_TESTMODE 0x0F /* 8 bit */ 56 57 /* Get offset for a given FIFO from musb->mregs */ 58 #ifdef CONFIG_USB_TUSB6010 59 #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20)) 60 #else 61 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4)) 62 #endif 63 64 /* 65 * Additional Control Registers 66 */ 67 68 #define MUSB_DEVCTL 0x60 /* 8 bit */ 69 70 /* These are always controlled through the INDEX register */ 71 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ 72 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ 73 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ 74 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ 75 76 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ 77 #define MUSB_HWVERS 0x6C /* 8 bit */ 78 79 #define MUSB_EPINFO 0x78 /* 8 bit */ 80 #define MUSB_RAMINFO 0x79 /* 8 bit */ 81 #define MUSB_LINKINFO 0x7a /* 8 bit */ 82 #define MUSB_VPLEN 0x7b /* 8 bit */ 83 #define MUSB_HS_EOF1 0x7c /* 8 bit */ 84 #define MUSB_FS_EOF1 0x7d /* 8 bit */ 85 #define MUSB_LS_EOF1 0x7e /* 8 bit */ 86 87 /* Offsets to endpoint registers */ 88 #define MUSB_TXMAXP 0x00 89 #define MUSB_TXCSR 0x02 90 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ 91 #define MUSB_RXMAXP 0x04 92 #define MUSB_RXCSR 0x06 93 #define MUSB_RXCOUNT 0x08 94 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ 95 #define MUSB_TXTYPE 0x0A 96 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ 97 #define MUSB_TXINTERVAL 0x0B 98 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ 99 #define MUSB_RXTYPE 0x0C 100 #define MUSB_RXINTERVAL 0x0D 101 #define MUSB_FIFOSIZE 0x0F 102 #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ 103 104 /* Offsets to endpoint registers in indexed model (using INDEX register) */ 105 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ 106 (0x10 + (_offset)) 107 108 /* Offsets to endpoint registers in flat models */ 109 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ 110 (0x100 + (0x10*(_epnum)) + (_offset)) 111 112 #ifdef CONFIG_USB_TUSB6010 113 /* TUSB6010 EP0 configuration register is special */ 114 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ 115 (0x10 + _offset) 116 #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */ 117 #endif 118 119 /* "bus control"/target registers, for host side multipoint (external hubs) */ 120 #define MUSB_TXFUNCADDR 0x00 121 #define MUSB_TXHUBADDR 0x02 122 #define MUSB_TXHUBPORT 0x03 123 124 #define MUSB_RXFUNCADDR 0x04 125 #define MUSB_RXHUBADDR 0x06 126 #define MUSB_RXHUBPORT 0x07 127 128 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ 129 (0x80 + (8*(_epnum)) + (_offset)) 130 131 /* 132 * MUSB Register bits 133 */ 134 135 /* POWER */ 136 #define MUSB_POWER_ISOUPDATE 0x80 137 #define MUSB_POWER_SOFTCONN 0x40 138 #define MUSB_POWER_HSENAB 0x20 139 #define MUSB_POWER_HSMODE 0x10 140 #define MUSB_POWER_RESET 0x08 141 #define MUSB_POWER_RESUME 0x04 142 #define MUSB_POWER_SUSPENDM 0x02 143 #define MUSB_POWER_ENSUSPEND 0x01 144 145 /* INTRUSB */ 146 #define MUSB_INTR_SUSPEND 0x01 147 #define MUSB_INTR_RESUME 0x02 148 #define MUSB_INTR_RESET 0x04 149 #define MUSB_INTR_BABBLE 0x04 150 #define MUSB_INTR_SOF 0x08 151 #define MUSB_INTR_CONNECT 0x10 152 #define MUSB_INTR_DISCONNECT 0x20 153 #define MUSB_INTR_SESSREQ 0x40 154 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 155 156 /* DEVCTL */ 157 #define MUSB_DEVCTL_BDEVICE 0x80 158 #define MUSB_DEVCTL_FSDEV 0x40 159 #define MUSB_DEVCTL_LSDEV 0x20 160 #define MUSB_DEVCTL_VBUS 0x18 161 #define MUSB_DEVCTL_VBUS_SHIFT 3 162 #define MUSB_DEVCTL_HM 0x04 163 #define MUSB_DEVCTL_HR 0x02 164 #define MUSB_DEVCTL_SESSION 0x01 165 166 /* TESTMODE */ 167 #define MUSB_TEST_FORCE_HOST 0x80 168 #define MUSB_TEST_FIFO_ACCESS 0x40 169 #define MUSB_TEST_FORCE_FS 0x20 170 #define MUSB_TEST_FORCE_HS 0x10 171 #define MUSB_TEST_PACKET 0x08 172 #define MUSB_TEST_K 0x04 173 #define MUSB_TEST_J 0x02 174 #define MUSB_TEST_SE0_NAK 0x01 175 176 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 177 #define MUSB_FIFOSZ_DPB 0x10 178 /* Allocation size (8, 16, 32, ... 4096) */ 179 #define MUSB_FIFOSZ_SIZE 0x0f 180 181 /* CSR0 */ 182 #define MUSB_CSR0_FLUSHFIFO 0x0100 183 #define MUSB_CSR0_TXPKTRDY 0x0002 184 #define MUSB_CSR0_RXPKTRDY 0x0001 185 186 /* CSR0 in Peripheral mode */ 187 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 188 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 189 #define MUSB_CSR0_P_SENDSTALL 0x0020 190 #define MUSB_CSR0_P_SETUPEND 0x0010 191 #define MUSB_CSR0_P_DATAEND 0x0008 192 #define MUSB_CSR0_P_SENTSTALL 0x0004 193 194 /* CSR0 in Host mode */ 195 #define MUSB_CSR0_H_DIS_PING 0x0800 196 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 197 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 198 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 199 #define MUSB_CSR0_H_STATUSPKT 0x0040 200 #define MUSB_CSR0_H_REQPKT 0x0020 201 #define MUSB_CSR0_H_ERROR 0x0010 202 #define MUSB_CSR0_H_SETUPPKT 0x0008 203 #define MUSB_CSR0_H_RXSTALL 0x0004 204 205 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 206 #define MUSB_CSR0_P_WZC_BITS \ 207 (MUSB_CSR0_P_SENTSTALL) 208 #define MUSB_CSR0_H_WZC_BITS \ 209 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 210 | MUSB_CSR0_RXPKTRDY) 211 212 /* TxType/RxType */ 213 #define MUSB_TYPE_SPEED 0xc0 214 #define MUSB_TYPE_SPEED_SHIFT 6 215 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 216 #define MUSB_TYPE_PROTO_SHIFT 4 217 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 218 219 /* CONFIGDATA */ 220 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 221 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 222 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 223 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 224 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 225 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 226 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 227 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 228 229 /* TXCSR in Peripheral and Host mode */ 230 #define MUSB_TXCSR_AUTOSET 0x8000 231 #define MUSB_TXCSR_MODE 0x2000 232 #define MUSB_TXCSR_DMAENAB 0x1000 233 #define MUSB_TXCSR_FRCDATATOG 0x0800 234 #define MUSB_TXCSR_DMAMODE 0x0400 235 #define MUSB_TXCSR_CLRDATATOG 0x0040 236 #define MUSB_TXCSR_FLUSHFIFO 0x0008 237 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 238 #define MUSB_TXCSR_TXPKTRDY 0x0001 239 240 /* TXCSR in Peripheral mode */ 241 #define MUSB_TXCSR_P_ISO 0x4000 242 #define MUSB_TXCSR_P_INCOMPTX 0x0080 243 #define MUSB_TXCSR_P_SENTSTALL 0x0020 244 #define MUSB_TXCSR_P_SENDSTALL 0x0010 245 #define MUSB_TXCSR_P_UNDERRUN 0x0004 246 247 /* TXCSR in Host mode */ 248 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 249 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 250 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 251 #define MUSB_TXCSR_H_RXSTALL 0x0020 252 #define MUSB_TXCSR_H_ERROR 0x0004 253 254 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 255 #define MUSB_TXCSR_P_WZC_BITS \ 256 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 257 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 258 #define MUSB_TXCSR_H_WZC_BITS \ 259 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 260 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 261 262 /* RXCSR in Peripheral and Host mode */ 263 #define MUSB_RXCSR_AUTOCLEAR 0x8000 264 #define MUSB_RXCSR_DMAENAB 0x2000 265 #define MUSB_RXCSR_DISNYET 0x1000 266 #define MUSB_RXCSR_PID_ERR 0x1000 267 #define MUSB_RXCSR_DMAMODE 0x0800 268 #define MUSB_RXCSR_INCOMPRX 0x0100 269 #define MUSB_RXCSR_CLRDATATOG 0x0080 270 #define MUSB_RXCSR_FLUSHFIFO 0x0010 271 #define MUSB_RXCSR_DATAERROR 0x0008 272 #define MUSB_RXCSR_FIFOFULL 0x0002 273 #define MUSB_RXCSR_RXPKTRDY 0x0001 274 275 /* RXCSR in Peripheral mode */ 276 #define MUSB_RXCSR_P_ISO 0x4000 277 #define MUSB_RXCSR_P_SENTSTALL 0x0040 278 #define MUSB_RXCSR_P_SENDSTALL 0x0020 279 #define MUSB_RXCSR_P_OVERRUN 0x0004 280 281 /* RXCSR in Host mode */ 282 #define MUSB_RXCSR_H_AUTOREQ 0x4000 283 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 284 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 285 #define MUSB_RXCSR_H_RXSTALL 0x0040 286 #define MUSB_RXCSR_H_REQPKT 0x0020 287 #define MUSB_RXCSR_H_ERROR 0x0004 288 289 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 290 #define MUSB_RXCSR_P_WZC_BITS \ 291 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 292 | MUSB_RXCSR_RXPKTRDY) 293 #define MUSB_RXCSR_H_WZC_BITS \ 294 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 295 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 296 297 /* HUBADDR */ 298 #define MUSB_HUBADDR_MULTI_TT 0x80 299 300 #endif /* __MUSB_REGS_H__ */ 301