1 /* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/sched.h> 40 #include <linux/slab.h> 41 #include <linux/errno.h> 42 #include <linux/list.h> 43 #include <linux/dma-mapping.h> 44 45 #include "musb_core.h" 46 #include "musb_host.h" 47 48 /* MUSB HOST status 22-mar-2006 49 * 50 * - There's still lots of partial code duplication for fault paths, so 51 * they aren't handled as consistently as they need to be. 52 * 53 * - PIO mostly behaved when last tested. 54 * + including ep0, with all usbtest cases 9, 10 55 * + usbtest 14 (ep0out) doesn't seem to run at all 56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 57 * configurations, but otherwise double buffering passes basic tests. 58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 59 * 60 * - DMA (CPPI) ... partially behaves, not currently recommended 61 * + about 1/15 the speed of typical EHCI implementations (PCI) 62 * + RX, all too often reqpkt seems to misbehave after tx 63 * + TX, no known issues (other than evident silicon issue) 64 * 65 * - DMA (Mentor/OMAP) ...has at least toggle update problems 66 * 67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 68 * starvation ... nothing yet for TX, interrupt, or bulk. 69 * 70 * - Not tested with HNP, but some SRP paths seem to behave. 71 * 72 * NOTE 24-August-2006: 73 * 74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 75 * extra endpoint for periodic use enabling hub + keybd + mouse. That 76 * mostly works, except that with "usbnet" it's easy to trigger cases 77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 79 * although ARP RX wins. (That test was done with a full speed link.) 80 */ 81 82 83 /* 84 * NOTE on endpoint usage: 85 * 86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 88 * (Yes, bulk _could_ use more of the endpoints than that, and would even 89 * benefit from it.) 90 * 91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 92 * So far that scheduling is both dumb and optimistic: the endpoint will be 93 * "claimed" until its software queue is no longer refilled. No multiplexing 94 * of transfers between endpoints, or anything clever. 95 */ 96 97 struct musb *hcd_to_musb(struct usb_hcd *hcd) 98 { 99 return *(struct musb **) hcd->hcd_priv; 100 } 101 102 103 static void musb_ep_program(struct musb *musb, u8 epnum, 104 struct urb *urb, int is_out, 105 u8 *buf, u32 offset, u32 len); 106 107 /* 108 * Clear TX fifo. Needed to avoid BABBLE errors. 109 */ 110 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 111 { 112 struct musb *musb = ep->musb; 113 void __iomem *epio = ep->regs; 114 u16 csr; 115 u16 lastcsr = 0; 116 int retries = 1000; 117 118 csr = musb_readw(epio, MUSB_TXCSR); 119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 120 if (csr != lastcsr) 121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 122 lastcsr = csr; 123 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; 124 musb_writew(epio, MUSB_TXCSR, csr); 125 csr = musb_readw(epio, MUSB_TXCSR); 126 if (WARN(retries-- < 1, 127 "Could not flush host TX%d fifo: csr: %04x\n", 128 ep->epnum, csr)) 129 return; 130 mdelay(1); 131 } 132 } 133 134 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 135 { 136 void __iomem *epio = ep->regs; 137 u16 csr; 138 int retries = 5; 139 140 /* scrub any data left in the fifo */ 141 do { 142 csr = musb_readw(epio, MUSB_TXCSR); 143 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 144 break; 145 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 146 csr = musb_readw(epio, MUSB_TXCSR); 147 udelay(10); 148 } while (--retries); 149 150 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 151 ep->epnum, csr); 152 153 /* and reset for the next transfer */ 154 musb_writew(epio, MUSB_TXCSR, 0); 155 } 156 157 /* 158 * Start transmit. Caller is responsible for locking shared resources. 159 * musb must be locked. 160 */ 161 static inline void musb_h_tx_start(struct musb_hw_ep *ep) 162 { 163 u16 txcsr; 164 165 /* NOTE: no locks here; caller should lock and select EP */ 166 if (ep->epnum) { 167 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 168 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 169 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 170 } else { 171 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 172 musb_writew(ep->regs, MUSB_CSR0, txcsr); 173 } 174 175 } 176 177 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 178 { 179 u16 txcsr; 180 181 /* NOTE: no locks here; caller should lock and select EP */ 182 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 183 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 184 if (is_cppi_enabled(ep->musb)) 185 txcsr |= MUSB_TXCSR_DMAMODE; 186 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 187 } 188 189 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 190 { 191 if (is_in != 0 || ep->is_shared_fifo) 192 ep->in_qh = qh; 193 if (is_in == 0 || ep->is_shared_fifo) 194 ep->out_qh = qh; 195 } 196 197 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 198 { 199 return is_in ? ep->in_qh : ep->out_qh; 200 } 201 202 /* 203 * Start the URB at the front of an endpoint's queue 204 * end must be claimed from the caller. 205 * 206 * Context: controller locked, irqs blocked 207 */ 208 static void 209 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 210 { 211 u16 frame; 212 u32 len; 213 void __iomem *mbase = musb->mregs; 214 struct urb *urb = next_urb(qh); 215 void *buf = urb->transfer_buffer; 216 u32 offset = 0; 217 struct musb_hw_ep *hw_ep = qh->hw_ep; 218 unsigned pipe = urb->pipe; 219 u8 address = usb_pipedevice(pipe); 220 int epnum = hw_ep->epnum; 221 222 /* initialize software qh state */ 223 qh->offset = 0; 224 qh->segsize = 0; 225 226 /* gather right source of data */ 227 switch (qh->type) { 228 case USB_ENDPOINT_XFER_CONTROL: 229 /* control transfers always start with SETUP */ 230 is_in = 0; 231 musb->ep0_stage = MUSB_EP0_START; 232 buf = urb->setup_packet; 233 len = 8; 234 break; 235 case USB_ENDPOINT_XFER_ISOC: 236 qh->iso_idx = 0; 237 qh->frame = 0; 238 offset = urb->iso_frame_desc[0].offset; 239 len = urb->iso_frame_desc[0].length; 240 break; 241 default: /* bulk, interrupt */ 242 /* actual_length may be nonzero on retry paths */ 243 buf = urb->transfer_buffer + urb->actual_length; 244 len = urb->transfer_buffer_length - urb->actual_length; 245 } 246 247 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 248 qh, urb, address, qh->epnum, 249 is_in ? "in" : "out", 250 ({char *s; switch (qh->type) { 251 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 252 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 253 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 254 default: s = "-intr"; break; 255 } s; }), 256 epnum, buf + offset, len); 257 258 /* Configure endpoint */ 259 musb_ep_set_qh(hw_ep, is_in, qh); 260 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 261 262 /* transmit may have more work: start it when it is time */ 263 if (is_in) 264 return; 265 266 /* determine if the time is right for a periodic transfer */ 267 switch (qh->type) { 268 case USB_ENDPOINT_XFER_ISOC: 269 case USB_ENDPOINT_XFER_INT: 270 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); 271 frame = musb_readw(mbase, MUSB_FRAME); 272 /* FIXME this doesn't implement that scheduling policy ... 273 * or handle framecounter wrapping 274 */ 275 if (1) { /* Always assume URB_ISO_ASAP */ 276 /* REVISIT the SOF irq handler shouldn't duplicate 277 * this code; and we don't init urb->start_frame... 278 */ 279 qh->frame = 0; 280 goto start; 281 } else { 282 qh->frame = urb->start_frame; 283 /* enable SOF interrupt so we can count down */ 284 dev_dbg(musb->controller, "SOF for %d\n", epnum); 285 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 286 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 287 #endif 288 } 289 break; 290 default: 291 start: 292 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, 293 hw_ep->tx_channel ? "dma" : "pio"); 294 295 if (!hw_ep->tx_channel) 296 musb_h_tx_start(hw_ep); 297 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) 298 musb_h_tx_dma_start(hw_ep); 299 } 300 } 301 302 /* Context: caller owns controller lock, IRQs are blocked */ 303 static void musb_giveback(struct musb *musb, struct urb *urb, int status) 304 __releases(musb->lock) 305 __acquires(musb->lock) 306 { 307 dev_dbg(musb->controller, 308 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 309 urb, urb->complete, status, 310 usb_pipedevice(urb->pipe), 311 usb_pipeendpoint(urb->pipe), 312 usb_pipein(urb->pipe) ? "in" : "out", 313 urb->actual_length, urb->transfer_buffer_length 314 ); 315 316 usb_hcd_unlink_urb_from_ep(musb->hcd, urb); 317 spin_unlock(&musb->lock); 318 usb_hcd_giveback_urb(musb->hcd, urb, status); 319 spin_lock(&musb->lock); 320 } 321 322 /* For bulk/interrupt endpoints only */ 323 static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 324 struct urb *urb) 325 { 326 void __iomem *epio = qh->hw_ep->regs; 327 u16 csr; 328 329 /* 330 * FIXME: the current Mentor DMA code seems to have 331 * problems getting toggle correct. 332 */ 333 334 if (is_in) 335 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 336 else 337 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 338 339 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 340 } 341 342 /* 343 * Advance this hardware endpoint's queue, completing the specified URB and 344 * advancing to either the next URB queued to that qh, or else invalidating 345 * that qh and advancing to the next qh scheduled after the current one. 346 * 347 * Context: caller owns controller lock, IRQs are blocked 348 */ 349 static void musb_advance_schedule(struct musb *musb, struct urb *urb, 350 struct musb_hw_ep *hw_ep, int is_in) 351 { 352 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 353 struct musb_hw_ep *ep = qh->hw_ep; 354 int ready = qh->is_ready; 355 int status; 356 357 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 358 359 /* save toggle eagerly, for paranoia */ 360 switch (qh->type) { 361 case USB_ENDPOINT_XFER_BULK: 362 case USB_ENDPOINT_XFER_INT: 363 musb_save_toggle(qh, is_in, urb); 364 break; 365 case USB_ENDPOINT_XFER_ISOC: 366 if (status == 0 && urb->error_count) 367 status = -EXDEV; 368 break; 369 } 370 371 qh->is_ready = 0; 372 musb_giveback(musb, urb, status); 373 qh->is_ready = ready; 374 375 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 376 * invalidate qh as soon as list_empty(&hep->urb_list) 377 */ 378 if (list_empty(&qh->hep->urb_list)) { 379 struct list_head *head; 380 struct dma_controller *dma = musb->dma_controller; 381 382 if (is_in) { 383 ep->rx_reinit = 1; 384 if (ep->rx_channel) { 385 dma->channel_release(ep->rx_channel); 386 ep->rx_channel = NULL; 387 } 388 } else { 389 ep->tx_reinit = 1; 390 if (ep->tx_channel) { 391 dma->channel_release(ep->tx_channel); 392 ep->tx_channel = NULL; 393 } 394 } 395 396 /* Clobber old pointers to this qh */ 397 musb_ep_set_qh(ep, is_in, NULL); 398 qh->hep->hcpriv = NULL; 399 400 switch (qh->type) { 401 402 case USB_ENDPOINT_XFER_CONTROL: 403 case USB_ENDPOINT_XFER_BULK: 404 /* fifo policy for these lists, except that NAKing 405 * should rotate a qh to the end (for fairness). 406 */ 407 if (qh->mux == 1) { 408 head = qh->ring.prev; 409 list_del(&qh->ring); 410 kfree(qh); 411 qh = first_qh(head); 412 break; 413 } 414 415 case USB_ENDPOINT_XFER_ISOC: 416 case USB_ENDPOINT_XFER_INT: 417 /* this is where periodic bandwidth should be 418 * de-allocated if it's tracked and allocated; 419 * and where we'd update the schedule tree... 420 */ 421 kfree(qh); 422 qh = NULL; 423 break; 424 } 425 } 426 427 if (qh != NULL && qh->is_ready) { 428 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", 429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 430 musb_start_urb(musb, is_in, qh); 431 } 432 } 433 434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 435 { 436 /* we don't want fifo to fill itself again; 437 * ignore dma (various models), 438 * leave toggle alone (may not have been saved yet) 439 */ 440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 441 csr &= ~(MUSB_RXCSR_H_REQPKT 442 | MUSB_RXCSR_H_AUTOREQ 443 | MUSB_RXCSR_AUTOCLEAR); 444 445 /* write 2x to allow double buffering */ 446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 448 449 /* flush writebuffer */ 450 return musb_readw(hw_ep->regs, MUSB_RXCSR); 451 } 452 453 /* 454 * PIO RX for a packet (or part of it). 455 */ 456 static bool 457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 458 { 459 u16 rx_count; 460 u8 *buf; 461 u16 csr; 462 bool done = false; 463 u32 length; 464 int do_flush = 0; 465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 466 void __iomem *epio = hw_ep->regs; 467 struct musb_qh *qh = hw_ep->in_qh; 468 int pipe = urb->pipe; 469 void *buffer = urb->transfer_buffer; 470 471 /* musb_ep_select(mbase, epnum); */ 472 rx_count = musb_readw(epio, MUSB_RXCOUNT); 473 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 474 urb->transfer_buffer, qh->offset, 475 urb->transfer_buffer_length); 476 477 /* unload FIFO */ 478 if (usb_pipeisoc(pipe)) { 479 int status = 0; 480 struct usb_iso_packet_descriptor *d; 481 482 if (iso_err) { 483 status = -EILSEQ; 484 urb->error_count++; 485 } 486 487 d = urb->iso_frame_desc + qh->iso_idx; 488 buf = buffer + d->offset; 489 length = d->length; 490 if (rx_count > length) { 491 if (status == 0) { 492 status = -EOVERFLOW; 493 urb->error_count++; 494 } 495 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 496 do_flush = 1; 497 } else 498 length = rx_count; 499 urb->actual_length += length; 500 d->actual_length = length; 501 502 d->status = status; 503 504 /* see if we are done */ 505 done = (++qh->iso_idx >= urb->number_of_packets); 506 } else { 507 /* non-isoch */ 508 buf = buffer + qh->offset; 509 length = urb->transfer_buffer_length - qh->offset; 510 if (rx_count > length) { 511 if (urb->status == -EINPROGRESS) 512 urb->status = -EOVERFLOW; 513 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 514 do_flush = 1; 515 } else 516 length = rx_count; 517 urb->actual_length += length; 518 qh->offset += length; 519 520 /* see if we are done */ 521 done = (urb->actual_length == urb->transfer_buffer_length) 522 || (rx_count < qh->maxpacket) 523 || (urb->status != -EINPROGRESS); 524 if (done 525 && (urb->status == -EINPROGRESS) 526 && (urb->transfer_flags & URB_SHORT_NOT_OK) 527 && (urb->actual_length 528 < urb->transfer_buffer_length)) 529 urb->status = -EREMOTEIO; 530 } 531 532 musb_read_fifo(hw_ep, length, buf); 533 534 csr = musb_readw(epio, MUSB_RXCSR); 535 csr |= MUSB_RXCSR_H_WZC_BITS; 536 if (unlikely(do_flush)) 537 musb_h_flush_rxfifo(hw_ep, csr); 538 else { 539 /* REVISIT this assumes AUTOCLEAR is never set */ 540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 541 if (!done) 542 csr |= MUSB_RXCSR_H_REQPKT; 543 musb_writew(epio, MUSB_RXCSR, csr); 544 } 545 546 return done; 547 } 548 549 /* we don't always need to reinit a given side of an endpoint... 550 * when we do, use tx/rx reinit routine and then construct a new CSR 551 * to address data toggle, NYET, and DMA or PIO. 552 * 553 * it's possible that driver bugs (especially for DMA) or aborting a 554 * transfer might have left the endpoint busier than it should be. 555 * the busy/not-empty tests are basically paranoia. 556 */ 557 static void 558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum) 559 { 560 struct musb_hw_ep *ep = musb->endpoints + epnum; 561 u16 csr; 562 563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 564 * That always uses tx_reinit since ep0 repurposes TX register 565 * offsets; the initial SETUP packet is also a kind of OUT. 566 */ 567 568 /* if programmed for Tx, put it in RX mode */ 569 if (ep->is_shared_fifo) { 570 csr = musb_readw(ep->regs, MUSB_TXCSR); 571 if (csr & MUSB_TXCSR_MODE) { 572 musb_h_tx_flush_fifo(ep); 573 csr = musb_readw(ep->regs, MUSB_TXCSR); 574 musb_writew(ep->regs, MUSB_TXCSR, 575 csr | MUSB_TXCSR_FRCDATATOG); 576 } 577 578 /* 579 * Clear the MODE bit (and everything else) to enable Rx. 580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 581 */ 582 if (csr & MUSB_TXCSR_DMAMODE) 583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 584 musb_writew(ep->regs, MUSB_TXCSR, 0); 585 586 /* scrub all previous state, clearing toggle */ 587 } else { 588 csr = musb_readw(ep->regs, MUSB_RXCSR); 589 if (csr & MUSB_RXCSR_RXPKTRDY) 590 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 591 musb_readw(ep->regs, MUSB_RXCOUNT)); 592 593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 594 } 595 596 /* target addr and (for multipoint) hub addr/port */ 597 if (musb->is_multipoint) { 598 musb_write_rxfunaddr(musb, epnum, qh->addr_reg); 599 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg); 600 musb_write_rxhubport(musb, epnum, qh->h_port_reg); 601 } else 602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 603 604 /* protocol/endpoint, interval/NAKlimit, i/o size */ 605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 607 /* NOTE: bulk combining rewrites high bits of maxpacket */ 608 /* Set RXMAXP with the FIFO size of the endpoint 609 * to disable double buffer mode. 610 */ 611 if (musb->double_buffer_not_ok) 612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 613 else 614 musb_writew(ep->regs, MUSB_RXMAXP, 615 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 616 617 ep->rx_reinit = 0; 618 } 619 620 static int musb_tx_dma_set_mode_mentor(struct dma_controller *dma, 621 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 622 struct urb *urb, u32 offset, 623 u32 *length, u8 *mode) 624 { 625 struct dma_channel *channel = hw_ep->tx_channel; 626 void __iomem *epio = hw_ep->regs; 627 u16 pkt_size = qh->maxpacket; 628 u16 csr; 629 630 if (*length > channel->max_len) 631 *length = channel->max_len; 632 633 csr = musb_readw(epio, MUSB_TXCSR); 634 if (*length > pkt_size) { 635 *mode = 1; 636 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 637 /* autoset shouldn't be set in high bandwidth */ 638 /* 639 * Enable Autoset according to table 640 * below 641 * bulk_split hb_mult Autoset_Enable 642 * 0 1 Yes(Normal) 643 * 0 >1 No(High BW ISO) 644 * 1 1 Yes(HS bulk) 645 * 1 >1 Yes(FS bulk) 646 */ 647 if (qh->hb_mult == 1 || (qh->hb_mult > 1 && 648 can_bulk_split(hw_ep->musb, qh->type))) 649 csr |= MUSB_TXCSR_AUTOSET; 650 } else { 651 *mode = 0; 652 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 653 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 654 } 655 channel->desired_mode = mode; 656 musb_writew(epio, MUSB_TXCSR, csr); 657 658 return 0; 659 } 660 661 static int musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma, 662 struct musb_hw_ep *hw_ep, 663 struct musb_qh *qh, 664 struct urb *urb, 665 u32 offset, 666 u32 *length, 667 u8 *mode) 668 { 669 struct dma_channel *channel = hw_ep->tx_channel; 670 671 if (!is_cppi_enabled(hw_ep->musb) && !tusb_dma_omap(hw_ep->musb)) 672 return -ENODEV; 673 674 channel->actual_len = 0; 675 676 /* 677 * TX uses "RNDIS" mode automatically but needs help 678 * to identify the zero-length-final-packet case. 679 */ 680 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 681 682 return 0; 683 } 684 685 static bool musb_tx_dma_program(struct dma_controller *dma, 686 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 687 struct urb *urb, u32 offset, u32 length) 688 { 689 struct dma_channel *channel = hw_ep->tx_channel; 690 u16 pkt_size = qh->maxpacket; 691 u8 mode; 692 int res; 693 694 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb)) 695 res = musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb, 696 offset, &length, &mode); 697 else 698 res = musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb, 699 offset, &length, &mode); 700 if (res) 701 return false; 702 703 qh->segsize = length; 704 705 /* 706 * Ensure the data reaches to main memory before starting 707 * DMA transfer 708 */ 709 wmb(); 710 711 if (!dma->channel_program(channel, pkt_size, mode, 712 urb->transfer_dma + offset, length)) { 713 void __iomem *epio = hw_ep->regs; 714 u16 csr; 715 716 dma->channel_release(channel); 717 hw_ep->tx_channel = NULL; 718 719 csr = musb_readw(epio, MUSB_TXCSR); 720 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 721 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 722 return false; 723 } 724 return true; 725 } 726 727 /* 728 * Program an HDRC endpoint as per the given URB 729 * Context: irqs blocked, controller lock held 730 */ 731 static void musb_ep_program(struct musb *musb, u8 epnum, 732 struct urb *urb, int is_out, 733 u8 *buf, u32 offset, u32 len) 734 { 735 struct dma_controller *dma_controller; 736 struct dma_channel *dma_channel; 737 u8 dma_ok; 738 void __iomem *mbase = musb->mregs; 739 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 740 void __iomem *epio = hw_ep->regs; 741 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 742 u16 packet_sz = qh->maxpacket; 743 u8 use_dma = 1; 744 u16 csr; 745 746 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " 747 "h_addr%02x h_port%02x bytes %d\n", 748 is_out ? "-->" : "<--", 749 epnum, urb, urb->dev->speed, 750 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 751 qh->h_addr_reg, qh->h_port_reg, 752 len); 753 754 musb_ep_select(mbase, epnum); 755 756 if (is_out && !len) { 757 use_dma = 0; 758 csr = musb_readw(epio, MUSB_TXCSR); 759 csr &= ~MUSB_TXCSR_DMAENAB; 760 musb_writew(epio, MUSB_TXCSR, csr); 761 hw_ep->tx_channel = NULL; 762 } 763 764 /* candidate for DMA? */ 765 dma_controller = musb->dma_controller; 766 if (use_dma && is_dma_capable() && epnum && dma_controller) { 767 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 768 if (!dma_channel) { 769 dma_channel = dma_controller->channel_alloc( 770 dma_controller, hw_ep, is_out); 771 if (is_out) 772 hw_ep->tx_channel = dma_channel; 773 else 774 hw_ep->rx_channel = dma_channel; 775 } 776 } else 777 dma_channel = NULL; 778 779 /* make sure we clear DMAEnab, autoSet bits from previous run */ 780 781 /* OUT/transmit/EP0 or IN/receive? */ 782 if (is_out) { 783 u16 csr; 784 u16 int_txe; 785 u16 load_count; 786 787 csr = musb_readw(epio, MUSB_TXCSR); 788 789 /* disable interrupt in case we flush */ 790 int_txe = musb->intrtxe; 791 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 792 793 /* general endpoint setup */ 794 if (epnum) { 795 /* flush all old state, set default */ 796 /* 797 * We could be flushing valid 798 * packets in double buffering 799 * case 800 */ 801 if (!hw_ep->tx_double_buffered) 802 musb_h_tx_flush_fifo(hw_ep); 803 804 /* 805 * We must not clear the DMAMODE bit before or in 806 * the same cycle with the DMAENAB bit, so we clear 807 * the latter first... 808 */ 809 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 810 | MUSB_TXCSR_AUTOSET 811 | MUSB_TXCSR_DMAENAB 812 | MUSB_TXCSR_FRCDATATOG 813 | MUSB_TXCSR_H_RXSTALL 814 | MUSB_TXCSR_H_ERROR 815 | MUSB_TXCSR_TXPKTRDY 816 ); 817 csr |= MUSB_TXCSR_MODE; 818 819 if (!hw_ep->tx_double_buffered) { 820 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 821 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 822 | MUSB_TXCSR_H_DATATOGGLE; 823 else 824 csr |= MUSB_TXCSR_CLRDATATOG; 825 } 826 827 musb_writew(epio, MUSB_TXCSR, csr); 828 /* REVISIT may need to clear FLUSHFIFO ... */ 829 csr &= ~MUSB_TXCSR_DMAMODE; 830 musb_writew(epio, MUSB_TXCSR, csr); 831 csr = musb_readw(epio, MUSB_TXCSR); 832 } else { 833 /* endpoint 0: just flush */ 834 musb_h_ep0_flush_fifo(hw_ep); 835 } 836 837 /* target addr and (for multipoint) hub addr/port */ 838 if (musb->is_multipoint) { 839 musb_write_txfunaddr(musb, epnum, qh->addr_reg); 840 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg); 841 musb_write_txhubport(musb, epnum, qh->h_port_reg); 842 /* FIXME if !epnum, do the same for RX ... */ 843 } else 844 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 845 846 /* protocol/endpoint/interval/NAKlimit */ 847 if (epnum) { 848 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 849 if (musb->double_buffer_not_ok) { 850 musb_writew(epio, MUSB_TXMAXP, 851 hw_ep->max_packet_sz_tx); 852 } else if (can_bulk_split(musb, qh->type)) { 853 qh->hb_mult = hw_ep->max_packet_sz_tx 854 / packet_sz; 855 musb_writew(epio, MUSB_TXMAXP, packet_sz 856 | ((qh->hb_mult) - 1) << 11); 857 } else { 858 musb_writew(epio, MUSB_TXMAXP, 859 qh->maxpacket | 860 ((qh->hb_mult - 1) << 11)); 861 } 862 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 863 } else { 864 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 865 if (musb->is_multipoint) 866 musb_writeb(epio, MUSB_TYPE0, 867 qh->type_reg); 868 } 869 870 if (can_bulk_split(musb, qh->type)) 871 load_count = min((u32) hw_ep->max_packet_sz_tx, 872 len); 873 else 874 load_count = min((u32) packet_sz, len); 875 876 if (dma_channel && musb_tx_dma_program(dma_controller, 877 hw_ep, qh, urb, offset, len)) 878 load_count = 0; 879 880 if (load_count) { 881 /* PIO to load FIFO */ 882 qh->segsize = load_count; 883 if (!buf) { 884 sg_miter_start(&qh->sg_miter, urb->sg, 1, 885 SG_MITER_ATOMIC 886 | SG_MITER_FROM_SG); 887 if (!sg_miter_next(&qh->sg_miter)) { 888 dev_err(musb->controller, 889 "error: sg" 890 "list empty\n"); 891 sg_miter_stop(&qh->sg_miter); 892 goto finish; 893 } 894 buf = qh->sg_miter.addr + urb->sg->offset + 895 urb->actual_length; 896 load_count = min_t(u32, load_count, 897 qh->sg_miter.length); 898 musb_write_fifo(hw_ep, load_count, buf); 899 qh->sg_miter.consumed = load_count; 900 sg_miter_stop(&qh->sg_miter); 901 } else 902 musb_write_fifo(hw_ep, load_count, buf); 903 } 904 finish: 905 /* re-enable interrupt */ 906 musb_writew(mbase, MUSB_INTRTXE, int_txe); 907 908 /* IN/receive */ 909 } else { 910 u16 csr; 911 912 if (hw_ep->rx_reinit) { 913 musb_rx_reinit(musb, qh, epnum); 914 915 /* init new state: toggle and NYET, maybe DMA later */ 916 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 917 csr = MUSB_RXCSR_H_WR_DATATOGGLE 918 | MUSB_RXCSR_H_DATATOGGLE; 919 else 920 csr = 0; 921 if (qh->type == USB_ENDPOINT_XFER_INT) 922 csr |= MUSB_RXCSR_DISNYET; 923 924 } else { 925 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 926 927 if (csr & (MUSB_RXCSR_RXPKTRDY 928 | MUSB_RXCSR_DMAENAB 929 | MUSB_RXCSR_H_REQPKT)) 930 ERR("broken !rx_reinit, ep%d csr %04x\n", 931 hw_ep->epnum, csr); 932 933 /* scrub any stale state, leaving toggle alone */ 934 csr &= MUSB_RXCSR_DISNYET; 935 } 936 937 /* kick things off */ 938 939 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) { 940 /* Candidate for DMA */ 941 dma_channel->actual_len = 0L; 942 qh->segsize = len; 943 944 /* AUTOREQ is in a DMA register */ 945 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 946 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 947 948 /* 949 * Unless caller treats short RX transfers as 950 * errors, we dare not queue multiple transfers. 951 */ 952 dma_ok = dma_controller->channel_program(dma_channel, 953 packet_sz, !(urb->transfer_flags & 954 URB_SHORT_NOT_OK), 955 urb->transfer_dma + offset, 956 qh->segsize); 957 if (!dma_ok) { 958 dma_controller->channel_release(dma_channel); 959 hw_ep->rx_channel = dma_channel = NULL; 960 } else 961 csr |= MUSB_RXCSR_DMAENAB; 962 } 963 964 csr |= MUSB_RXCSR_H_REQPKT; 965 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); 966 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 967 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 968 } 969 } 970 971 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to 972 * the end; avoids starvation for other endpoints. 973 */ 974 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, 975 int is_in) 976 { 977 struct dma_channel *dma; 978 struct urb *urb; 979 void __iomem *mbase = musb->mregs; 980 void __iomem *epio = ep->regs; 981 struct musb_qh *cur_qh, *next_qh; 982 u16 rx_csr, tx_csr; 983 984 musb_ep_select(mbase, ep->epnum); 985 if (is_in) { 986 dma = is_dma_capable() ? ep->rx_channel : NULL; 987 988 /* clear nak timeout bit */ 989 rx_csr = musb_readw(epio, MUSB_RXCSR); 990 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 991 rx_csr &= ~MUSB_RXCSR_DATAERROR; 992 musb_writew(epio, MUSB_RXCSR, rx_csr); 993 994 cur_qh = first_qh(&musb->in_bulk); 995 } else { 996 dma = is_dma_capable() ? ep->tx_channel : NULL; 997 998 /* clear nak timeout bit */ 999 tx_csr = musb_readw(epio, MUSB_TXCSR); 1000 tx_csr |= MUSB_TXCSR_H_WZC_BITS; 1001 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; 1002 musb_writew(epio, MUSB_TXCSR, tx_csr); 1003 1004 cur_qh = first_qh(&musb->out_bulk); 1005 } 1006 if (cur_qh) { 1007 urb = next_urb(cur_qh); 1008 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1009 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1010 musb->dma_controller->channel_abort(dma); 1011 urb->actual_length += dma->actual_len; 1012 dma->actual_len = 0L; 1013 } 1014 musb_save_toggle(cur_qh, is_in, urb); 1015 1016 if (is_in) { 1017 /* move cur_qh to end of queue */ 1018 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1019 1020 /* get the next qh from musb->in_bulk */ 1021 next_qh = first_qh(&musb->in_bulk); 1022 1023 /* set rx_reinit and schedule the next qh */ 1024 ep->rx_reinit = 1; 1025 } else { 1026 /* move cur_qh to end of queue */ 1027 list_move_tail(&cur_qh->ring, &musb->out_bulk); 1028 1029 /* get the next qh from musb->out_bulk */ 1030 next_qh = first_qh(&musb->out_bulk); 1031 1032 /* set tx_reinit and schedule the next qh */ 1033 ep->tx_reinit = 1; 1034 } 1035 musb_start_urb(musb, is_in, next_qh); 1036 } 1037 } 1038 1039 /* 1040 * Service the default endpoint (ep0) as host. 1041 * Return true until it's time to start the status stage. 1042 */ 1043 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 1044 { 1045 bool more = false; 1046 u8 *fifo_dest = NULL; 1047 u16 fifo_count = 0; 1048 struct musb_hw_ep *hw_ep = musb->control_ep; 1049 struct musb_qh *qh = hw_ep->in_qh; 1050 struct usb_ctrlrequest *request; 1051 1052 switch (musb->ep0_stage) { 1053 case MUSB_EP0_IN: 1054 fifo_dest = urb->transfer_buffer + urb->actual_length; 1055 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 1056 urb->actual_length); 1057 if (fifo_count < len) 1058 urb->status = -EOVERFLOW; 1059 1060 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 1061 1062 urb->actual_length += fifo_count; 1063 if (len < qh->maxpacket) { 1064 /* always terminate on short read; it's 1065 * rarely reported as an error. 1066 */ 1067 } else if (urb->actual_length < 1068 urb->transfer_buffer_length) 1069 more = true; 1070 break; 1071 case MUSB_EP0_START: 1072 request = (struct usb_ctrlrequest *) urb->setup_packet; 1073 1074 if (!request->wLength) { 1075 dev_dbg(musb->controller, "start no-DATA\n"); 1076 break; 1077 } else if (request->bRequestType & USB_DIR_IN) { 1078 dev_dbg(musb->controller, "start IN-DATA\n"); 1079 musb->ep0_stage = MUSB_EP0_IN; 1080 more = true; 1081 break; 1082 } else { 1083 dev_dbg(musb->controller, "start OUT-DATA\n"); 1084 musb->ep0_stage = MUSB_EP0_OUT; 1085 more = true; 1086 } 1087 /* FALLTHROUGH */ 1088 case MUSB_EP0_OUT: 1089 fifo_count = min_t(size_t, qh->maxpacket, 1090 urb->transfer_buffer_length - 1091 urb->actual_length); 1092 if (fifo_count) { 1093 fifo_dest = (u8 *) (urb->transfer_buffer 1094 + urb->actual_length); 1095 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", 1096 fifo_count, 1097 (fifo_count == 1) ? "" : "s", 1098 fifo_dest); 1099 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 1100 1101 urb->actual_length += fifo_count; 1102 more = true; 1103 } 1104 break; 1105 default: 1106 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 1107 break; 1108 } 1109 1110 return more; 1111 } 1112 1113 /* 1114 * Handle default endpoint interrupt as host. Only called in IRQ time 1115 * from musb_interrupt(). 1116 * 1117 * called with controller irqlocked 1118 */ 1119 irqreturn_t musb_h_ep0_irq(struct musb *musb) 1120 { 1121 struct urb *urb; 1122 u16 csr, len; 1123 int status = 0; 1124 void __iomem *mbase = musb->mregs; 1125 struct musb_hw_ep *hw_ep = musb->control_ep; 1126 void __iomem *epio = hw_ep->regs; 1127 struct musb_qh *qh = hw_ep->in_qh; 1128 bool complete = false; 1129 irqreturn_t retval = IRQ_NONE; 1130 1131 /* ep0 only has one queue, "in" */ 1132 urb = next_urb(qh); 1133 1134 musb_ep_select(mbase, 0); 1135 csr = musb_readw(epio, MUSB_CSR0); 1136 len = (csr & MUSB_CSR0_RXPKTRDY) 1137 ? musb_readb(epio, MUSB_COUNT0) 1138 : 0; 1139 1140 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 1141 csr, qh, len, urb, musb->ep0_stage); 1142 1143 /* if we just did status stage, we are done */ 1144 if (MUSB_EP0_STATUS == musb->ep0_stage) { 1145 retval = IRQ_HANDLED; 1146 complete = true; 1147 } 1148 1149 /* prepare status */ 1150 if (csr & MUSB_CSR0_H_RXSTALL) { 1151 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); 1152 status = -EPIPE; 1153 1154 } else if (csr & MUSB_CSR0_H_ERROR) { 1155 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); 1156 status = -EPROTO; 1157 1158 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1159 dev_dbg(musb->controller, "control NAK timeout\n"); 1160 1161 /* NOTE: this code path would be a good place to PAUSE a 1162 * control transfer, if another one is queued, so that 1163 * ep0 is more likely to stay busy. That's already done 1164 * for bulk RX transfers. 1165 * 1166 * if (qh->ring.next != &musb->control), then 1167 * we have a candidate... NAKing is *NOT* an error 1168 */ 1169 musb_writew(epio, MUSB_CSR0, 0); 1170 retval = IRQ_HANDLED; 1171 } 1172 1173 if (status) { 1174 dev_dbg(musb->controller, "aborting\n"); 1175 retval = IRQ_HANDLED; 1176 if (urb) 1177 urb->status = status; 1178 complete = true; 1179 1180 /* use the proper sequence to abort the transfer */ 1181 if (csr & MUSB_CSR0_H_REQPKT) { 1182 csr &= ~MUSB_CSR0_H_REQPKT; 1183 musb_writew(epio, MUSB_CSR0, csr); 1184 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1185 musb_writew(epio, MUSB_CSR0, csr); 1186 } else { 1187 musb_h_ep0_flush_fifo(hw_ep); 1188 } 1189 1190 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1191 1192 /* clear it */ 1193 musb_writew(epio, MUSB_CSR0, 0); 1194 } 1195 1196 if (unlikely(!urb)) { 1197 /* stop endpoint since we have no place for its data, this 1198 * SHOULD NEVER HAPPEN! */ 1199 ERR("no URB for end 0\n"); 1200 1201 musb_h_ep0_flush_fifo(hw_ep); 1202 goto done; 1203 } 1204 1205 if (!complete) { 1206 /* call common logic and prepare response */ 1207 if (musb_h_ep0_continue(musb, len, urb)) { 1208 /* more packets required */ 1209 csr = (MUSB_EP0_IN == musb->ep0_stage) 1210 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1211 } else { 1212 /* data transfer complete; perform status phase */ 1213 if (usb_pipeout(urb->pipe) 1214 || !urb->transfer_buffer_length) 1215 csr = MUSB_CSR0_H_STATUSPKT 1216 | MUSB_CSR0_H_REQPKT; 1217 else 1218 csr = MUSB_CSR0_H_STATUSPKT 1219 | MUSB_CSR0_TXPKTRDY; 1220 1221 /* disable ping token in status phase */ 1222 csr |= MUSB_CSR0_H_DIS_PING; 1223 1224 /* flag status stage */ 1225 musb->ep0_stage = MUSB_EP0_STATUS; 1226 1227 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); 1228 1229 } 1230 musb_writew(epio, MUSB_CSR0, csr); 1231 retval = IRQ_HANDLED; 1232 } else 1233 musb->ep0_stage = MUSB_EP0_IDLE; 1234 1235 /* call completion handler if done */ 1236 if (complete) 1237 musb_advance_schedule(musb, urb, hw_ep, 1); 1238 done: 1239 return retval; 1240 } 1241 1242 1243 #ifdef CONFIG_USB_INVENTRA_DMA 1244 1245 /* Host side TX (OUT) using Mentor DMA works as follows: 1246 submit_urb -> 1247 - if queue was empty, Program Endpoint 1248 - ... which starts DMA to fifo in mode 1 or 0 1249 1250 DMA Isr (transfer complete) -> TxAvail() 1251 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1252 only in musb_cleanup_urb) 1253 - TxPktRdy has to be set in mode 0 or for 1254 short packets in mode 1. 1255 */ 1256 1257 #endif 1258 1259 /* Service a Tx-Available or dma completion irq for the endpoint */ 1260 void musb_host_tx(struct musb *musb, u8 epnum) 1261 { 1262 int pipe; 1263 bool done = false; 1264 u16 tx_csr; 1265 size_t length = 0; 1266 size_t offset = 0; 1267 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1268 void __iomem *epio = hw_ep->regs; 1269 struct musb_qh *qh = hw_ep->out_qh; 1270 struct urb *urb = next_urb(qh); 1271 u32 status = 0; 1272 void __iomem *mbase = musb->mregs; 1273 struct dma_channel *dma; 1274 bool transfer_pending = false; 1275 1276 musb_ep_select(mbase, epnum); 1277 tx_csr = musb_readw(epio, MUSB_TXCSR); 1278 1279 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1280 if (!urb) { 1281 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1282 return; 1283 } 1284 1285 pipe = urb->pipe; 1286 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1287 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1288 dma ? ", dma" : ""); 1289 1290 /* check for errors */ 1291 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1292 /* dma was disabled, fifo flushed */ 1293 dev_dbg(musb->controller, "TX end %d stall\n", epnum); 1294 1295 /* stall; record URB status */ 1296 status = -EPIPE; 1297 1298 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1299 /* (NON-ISO) dma was disabled, fifo flushed */ 1300 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); 1301 1302 status = -ETIMEDOUT; 1303 1304 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1305 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 1306 && !list_is_singular(&musb->out_bulk)) { 1307 dev_dbg(musb->controller, 1308 "NAK timeout on TX%d ep\n", epnum); 1309 musb_bulk_nak_timeout(musb, hw_ep, 0); 1310 } else { 1311 dev_dbg(musb->controller, 1312 "TX end=%d device not responding\n", epnum); 1313 /* NOTE: this code path would be a good place to PAUSE a 1314 * transfer, if there's some other (nonperiodic) tx urb 1315 * that could use this fifo. (dma complicates it...) 1316 * That's already done for bulk RX transfers. 1317 * 1318 * if (bulk && qh->ring.next != &musb->out_bulk), then 1319 * we have a candidate... NAKing is *NOT* an error 1320 */ 1321 musb_ep_select(mbase, epnum); 1322 musb_writew(epio, MUSB_TXCSR, 1323 MUSB_TXCSR_H_WZC_BITS 1324 | MUSB_TXCSR_TXPKTRDY); 1325 } 1326 return; 1327 } 1328 1329 done: 1330 if (status) { 1331 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1332 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1333 musb->dma_controller->channel_abort(dma); 1334 } 1335 1336 /* do the proper sequence to abort the transfer in the 1337 * usb core; the dma engine should already be stopped. 1338 */ 1339 musb_h_tx_flush_fifo(hw_ep); 1340 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1341 | MUSB_TXCSR_DMAENAB 1342 | MUSB_TXCSR_H_ERROR 1343 | MUSB_TXCSR_H_RXSTALL 1344 | MUSB_TXCSR_H_NAKTIMEOUT 1345 ); 1346 1347 musb_ep_select(mbase, epnum); 1348 musb_writew(epio, MUSB_TXCSR, tx_csr); 1349 /* REVISIT may need to clear FLUSHFIFO ... */ 1350 musb_writew(epio, MUSB_TXCSR, tx_csr); 1351 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1352 1353 done = true; 1354 } 1355 1356 /* second cppi case */ 1357 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1358 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1359 return; 1360 } 1361 1362 if (is_dma_capable() && dma && !status) { 1363 /* 1364 * DMA has completed. But if we're using DMA mode 1 (multi 1365 * packet DMA), we need a terminal TXPKTRDY interrupt before 1366 * we can consider this transfer completed, lest we trash 1367 * its last packet when writing the next URB's data. So we 1368 * switch back to mode 0 to get that interrupt; we'll come 1369 * back here once it happens. 1370 */ 1371 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1372 /* 1373 * We shouldn't clear DMAMODE with DMAENAB set; so 1374 * clear them in a safe order. That should be OK 1375 * once TXPKTRDY has been set (and I've never seen 1376 * it being 0 at this moment -- DMA interrupt latency 1377 * is significant) but if it hasn't been then we have 1378 * no choice but to stop being polite and ignore the 1379 * programmer's guide... :-) 1380 * 1381 * Note that we must write TXCSR with TXPKTRDY cleared 1382 * in order not to re-trigger the packet send (this bit 1383 * can't be cleared by CPU), and there's another caveat: 1384 * TXPKTRDY may be set shortly and then cleared in the 1385 * double-buffered FIFO mode, so we do an extra TXCSR 1386 * read for debouncing... 1387 */ 1388 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1389 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1390 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1391 MUSB_TXCSR_TXPKTRDY); 1392 musb_writew(epio, MUSB_TXCSR, 1393 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1394 } 1395 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1396 MUSB_TXCSR_TXPKTRDY); 1397 musb_writew(epio, MUSB_TXCSR, 1398 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1399 1400 /* 1401 * There is no guarantee that we'll get an interrupt 1402 * after clearing DMAMODE as we might have done this 1403 * too late (after TXPKTRDY was cleared by controller). 1404 * Re-read TXCSR as we have spoiled its previous value. 1405 */ 1406 tx_csr = musb_readw(epio, MUSB_TXCSR); 1407 } 1408 1409 /* 1410 * We may get here from a DMA completion or TXPKTRDY interrupt. 1411 * In any case, we must check the FIFO status here and bail out 1412 * only if the FIFO still has data -- that should prevent the 1413 * "missed" TXPKTRDY interrupts and deal with double-buffered 1414 * FIFO mode too... 1415 */ 1416 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1417 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " 1418 "CSR %04x\n", tx_csr); 1419 return; 1420 } 1421 } 1422 1423 if (!status || dma || usb_pipeisoc(pipe)) { 1424 if (dma) 1425 length = dma->actual_len; 1426 else 1427 length = qh->segsize; 1428 qh->offset += length; 1429 1430 if (usb_pipeisoc(pipe)) { 1431 struct usb_iso_packet_descriptor *d; 1432 1433 d = urb->iso_frame_desc + qh->iso_idx; 1434 d->actual_length = length; 1435 d->status = status; 1436 if (++qh->iso_idx >= urb->number_of_packets) { 1437 done = true; 1438 } else { 1439 d++; 1440 offset = d->offset; 1441 length = d->length; 1442 } 1443 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1444 done = true; 1445 } else { 1446 /* see if we need to send more data, or ZLP */ 1447 if (qh->segsize < qh->maxpacket) 1448 done = true; 1449 else if (qh->offset == urb->transfer_buffer_length 1450 && !(urb->transfer_flags 1451 & URB_ZERO_PACKET)) 1452 done = true; 1453 if (!done) { 1454 offset = qh->offset; 1455 length = urb->transfer_buffer_length - offset; 1456 transfer_pending = true; 1457 } 1458 } 1459 } 1460 1461 /* urb->status != -EINPROGRESS means request has been faulted, 1462 * so we must abort this transfer after cleanup 1463 */ 1464 if (urb->status != -EINPROGRESS) { 1465 done = true; 1466 if (status == 0) 1467 status = urb->status; 1468 } 1469 1470 if (done) { 1471 /* set status */ 1472 urb->status = status; 1473 urb->actual_length = qh->offset; 1474 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1475 return; 1476 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1477 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1478 offset, length)) { 1479 if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) 1480 musb_h_tx_dma_start(hw_ep); 1481 return; 1482 } 1483 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1484 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); 1485 return; 1486 } 1487 1488 /* 1489 * PIO: start next packet in this URB. 1490 * 1491 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1492 * (and presumably, FIFO is not half-full) we should write *two* 1493 * packets before updating TXCSR; other docs disagree... 1494 */ 1495 if (length > qh->maxpacket) 1496 length = qh->maxpacket; 1497 /* Unmap the buffer so that CPU can use it */ 1498 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 1499 1500 /* 1501 * We need to map sg if the transfer_buffer is 1502 * NULL. 1503 */ 1504 if (!urb->transfer_buffer) 1505 qh->use_sg = true; 1506 1507 if (qh->use_sg) { 1508 /* sg_miter_start is already done in musb_ep_program */ 1509 if (!sg_miter_next(&qh->sg_miter)) { 1510 dev_err(musb->controller, "error: sg list empty\n"); 1511 sg_miter_stop(&qh->sg_miter); 1512 status = -EINVAL; 1513 goto done; 1514 } 1515 urb->transfer_buffer = qh->sg_miter.addr; 1516 length = min_t(u32, length, qh->sg_miter.length); 1517 musb_write_fifo(hw_ep, length, urb->transfer_buffer); 1518 qh->sg_miter.consumed = length; 1519 sg_miter_stop(&qh->sg_miter); 1520 } else { 1521 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1522 } 1523 1524 qh->segsize = length; 1525 1526 if (qh->use_sg) { 1527 if (offset + length >= urb->transfer_buffer_length) 1528 qh->use_sg = false; 1529 } 1530 1531 musb_ep_select(mbase, epnum); 1532 musb_writew(epio, MUSB_TXCSR, 1533 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1534 } 1535 1536 #ifdef CONFIG_USB_TI_CPPI41_DMA 1537 /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */ 1538 static int musb_rx_dma_iso_cppi41(struct dma_controller *dma, 1539 struct musb_hw_ep *hw_ep, 1540 struct musb_qh *qh, 1541 struct urb *urb, 1542 size_t len) 1543 { 1544 struct dma_channel *channel = hw_ep->tx_channel; 1545 void __iomem *epio = hw_ep->regs; 1546 dma_addr_t *buf; 1547 u32 length, res; 1548 u16 val; 1549 1550 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset + 1551 (u32)urb->transfer_dma; 1552 1553 length = urb->iso_frame_desc[qh->iso_idx].length; 1554 1555 val = musb_readw(epio, MUSB_RXCSR); 1556 val |= MUSB_RXCSR_DMAENAB; 1557 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1558 1559 res = dma->channel_program(channel, qh->maxpacket, 0, 1560 (u32)buf, length); 1561 1562 return res; 1563 } 1564 #else 1565 static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma, 1566 struct musb_hw_ep *hw_ep, 1567 struct musb_qh *qh, 1568 struct urb *urb, 1569 size_t len) 1570 { 1571 return false; 1572 } 1573 #endif 1574 1575 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \ 1576 defined(CONFIG_USB_TI_CPPI41_DMA) 1577 /* Host side RX (IN) using Mentor DMA works as follows: 1578 submit_urb -> 1579 - if queue was empty, ProgramEndpoint 1580 - first IN token is sent out (by setting ReqPkt) 1581 LinuxIsr -> RxReady() 1582 /\ => first packet is received 1583 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1584 | -> DMA Isr (transfer complete) -> RxReady() 1585 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1586 | - if urb not complete, send next IN token (ReqPkt) 1587 | | else complete urb. 1588 | | 1589 --------------------------- 1590 * 1591 * Nuances of mode 1: 1592 * For short packets, no ack (+RxPktRdy) is sent automatically 1593 * (even if AutoClear is ON) 1594 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1595 * automatically => major problem, as collecting the next packet becomes 1596 * difficult. Hence mode 1 is not used. 1597 * 1598 * REVISIT 1599 * All we care about at this driver level is that 1600 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1601 * (b) termination conditions are: short RX, or buffer full; 1602 * (c) fault modes include 1603 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1604 * (and that endpoint's dma queue stops immediately) 1605 * - overflow (full, PLUS more bytes in the terminal packet) 1606 * 1607 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1608 * thus be a great candidate for using mode 1 ... for all but the 1609 * last packet of one URB's transfer. 1610 */ 1611 static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, 1612 struct musb_hw_ep *hw_ep, 1613 struct musb_qh *qh, 1614 struct urb *urb, 1615 size_t len) 1616 { 1617 struct dma_channel *channel = hw_ep->rx_channel; 1618 void __iomem *epio = hw_ep->regs; 1619 u16 val; 1620 int pipe; 1621 bool done; 1622 1623 pipe = urb->pipe; 1624 1625 if (usb_pipeisoc(pipe)) { 1626 struct usb_iso_packet_descriptor *d; 1627 1628 d = urb->iso_frame_desc + qh->iso_idx; 1629 d->actual_length = len; 1630 1631 /* even if there was an error, we did the dma 1632 * for iso_frame_desc->length 1633 */ 1634 if (d->status != -EILSEQ && d->status != -EOVERFLOW) 1635 d->status = 0; 1636 1637 if (++qh->iso_idx >= urb->number_of_packets) { 1638 done = true; 1639 } else { 1640 /* REVISIT: Why ignore return value here? */ 1641 if (musb_dma_cppi41(hw_ep->musb)) 1642 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh, 1643 urb, len); 1644 done = false; 1645 } 1646 1647 } else { 1648 /* done if urb buffer is full or short packet is recd */ 1649 done = (urb->actual_length + len >= 1650 urb->transfer_buffer_length 1651 || channel->actual_len < qh->maxpacket 1652 || channel->rx_packet_done); 1653 } 1654 1655 /* send IN token for next packet, without AUTOREQ */ 1656 if (!done) { 1657 val = musb_readw(epio, MUSB_RXCSR); 1658 val |= MUSB_RXCSR_H_REQPKT; 1659 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); 1660 } 1661 1662 return done; 1663 } 1664 1665 /* Disadvantage of using mode 1: 1666 * It's basically usable only for mass storage class; essentially all 1667 * other protocols also terminate transfers on short packets. 1668 * 1669 * Details: 1670 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1671 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1672 * to use the extra IN token to grab the last packet using mode 0, then 1673 * the problem is that you cannot be sure when the device will send the 1674 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1675 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1676 * transfer, while sometimes it is recd just a little late so that if you 1677 * try to configure for mode 0 soon after the mode 1 transfer is 1678 * completed, you will find rxcount 0. Okay, so you might think why not 1679 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1680 */ 1681 static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, 1682 struct musb_hw_ep *hw_ep, 1683 struct musb_qh *qh, 1684 struct urb *urb, 1685 size_t len, 1686 u8 iso_err) 1687 { 1688 struct musb *musb = hw_ep->musb; 1689 void __iomem *epio = hw_ep->regs; 1690 struct dma_channel *channel = hw_ep->rx_channel; 1691 u16 rx_count, val; 1692 int length, pipe, done; 1693 dma_addr_t buf; 1694 1695 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1696 pipe = urb->pipe; 1697 1698 if (usb_pipeisoc(pipe)) { 1699 int d_status = 0; 1700 struct usb_iso_packet_descriptor *d; 1701 1702 d = urb->iso_frame_desc + qh->iso_idx; 1703 1704 if (iso_err) { 1705 d_status = -EILSEQ; 1706 urb->error_count++; 1707 } 1708 if (rx_count > d->length) { 1709 if (d_status == 0) { 1710 d_status = -EOVERFLOW; 1711 urb->error_count++; 1712 } 1713 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", 1714 rx_count, d->length); 1715 1716 length = d->length; 1717 } else 1718 length = rx_count; 1719 d->status = d_status; 1720 buf = urb->transfer_dma + d->offset; 1721 } else { 1722 length = rx_count; 1723 buf = urb->transfer_dma + urb->actual_length; 1724 } 1725 1726 channel->desired_mode = 0; 1727 #ifdef USE_MODE1 1728 /* because of the issue below, mode 1 will 1729 * only rarely behave with correct semantics. 1730 */ 1731 if ((urb->transfer_flags & URB_SHORT_NOT_OK) 1732 && (urb->transfer_buffer_length - urb->actual_length) 1733 > qh->maxpacket) 1734 channel->desired_mode = 1; 1735 if (rx_count < hw_ep->max_packet_sz_rx) { 1736 length = rx_count; 1737 channel->desired_mode = 0; 1738 } else { 1739 length = urb->transfer_buffer_length; 1740 } 1741 #endif 1742 1743 /* See comments above on disadvantages of using mode 1 */ 1744 val = musb_readw(epio, MUSB_RXCSR); 1745 val &= ~MUSB_RXCSR_H_REQPKT; 1746 1747 if (channel->desired_mode == 0) 1748 val &= ~MUSB_RXCSR_H_AUTOREQ; 1749 else 1750 val |= MUSB_RXCSR_H_AUTOREQ; 1751 val |= MUSB_RXCSR_DMAENAB; 1752 1753 /* autoclear shouldn't be set in high bandwidth */ 1754 if (qh->hb_mult == 1) 1755 val |= MUSB_RXCSR_AUTOCLEAR; 1756 1757 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); 1758 1759 /* REVISIT if when actual_length != 0, 1760 * transfer_buffer_length needs to be 1761 * adjusted first... 1762 */ 1763 done = dma->channel_program(channel, qh->maxpacket, 1764 channel->desired_mode, 1765 buf, length); 1766 1767 if (!done) { 1768 dma->channel_release(channel); 1769 hw_ep->rx_channel = NULL; 1770 channel = NULL; 1771 val = musb_readw(epio, MUSB_RXCSR); 1772 val &= ~(MUSB_RXCSR_DMAENAB 1773 | MUSB_RXCSR_H_AUTOREQ 1774 | MUSB_RXCSR_AUTOCLEAR); 1775 musb_writew(epio, MUSB_RXCSR, val); 1776 } 1777 1778 return done; 1779 } 1780 #else 1781 static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, 1782 struct musb_hw_ep *hw_ep, 1783 struct musb_qh *qh, 1784 struct urb *urb, 1785 size_t len) 1786 { 1787 return false; 1788 } 1789 1790 static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, 1791 struct musb_hw_ep *hw_ep, 1792 struct musb_qh *qh, 1793 struct urb *urb, 1794 size_t len, 1795 u8 iso_err) 1796 { 1797 return false; 1798 } 1799 #endif 1800 1801 /* 1802 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1803 * and high-bandwidth IN transfer cases. 1804 */ 1805 void musb_host_rx(struct musb *musb, u8 epnum) 1806 { 1807 struct urb *urb; 1808 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1809 struct dma_controller *c = musb->dma_controller; 1810 void __iomem *epio = hw_ep->regs; 1811 struct musb_qh *qh = hw_ep->in_qh; 1812 size_t xfer_len; 1813 void __iomem *mbase = musb->mregs; 1814 int pipe; 1815 u16 rx_csr, val; 1816 bool iso_err = false; 1817 bool done = false; 1818 u32 status; 1819 struct dma_channel *dma; 1820 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; 1821 1822 musb_ep_select(mbase, epnum); 1823 1824 urb = next_urb(qh); 1825 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1826 status = 0; 1827 xfer_len = 0; 1828 1829 rx_csr = musb_readw(epio, MUSB_RXCSR); 1830 val = rx_csr; 1831 1832 if (unlikely(!urb)) { 1833 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1834 * usbtest #11 (unlinks) triggers it regularly, sometimes 1835 * with fifo full. (Only with DMA??) 1836 */ 1837 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1838 musb_readw(epio, MUSB_RXCOUNT)); 1839 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1840 return; 1841 } 1842 1843 pipe = urb->pipe; 1844 1845 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1846 epnum, rx_csr, urb->actual_length, 1847 dma ? dma->actual_len : 0); 1848 1849 /* check for errors, concurrent stall & unlink is not really 1850 * handled yet! */ 1851 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1852 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); 1853 1854 /* stall; record URB status */ 1855 status = -EPIPE; 1856 1857 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1858 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); 1859 1860 status = -EPROTO; 1861 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1862 1863 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1864 1865 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1866 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); 1867 1868 /* NOTE: NAKing is *NOT* an error, so we want to 1869 * continue. Except ... if there's a request for 1870 * another QH, use that instead of starving it. 1871 * 1872 * Devices like Ethernet and serial adapters keep 1873 * reads posted at all times, which will starve 1874 * other devices without this logic. 1875 */ 1876 if (usb_pipebulk(urb->pipe) 1877 && qh->mux == 1 1878 && !list_is_singular(&musb->in_bulk)) { 1879 musb_bulk_nak_timeout(musb, hw_ep, 1); 1880 return; 1881 } 1882 musb_ep_select(mbase, epnum); 1883 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1884 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1885 musb_writew(epio, MUSB_RXCSR, rx_csr); 1886 1887 goto finish; 1888 } else { 1889 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); 1890 /* packet error reported later */ 1891 iso_err = true; 1892 } 1893 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1894 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", 1895 epnum); 1896 status = -EPROTO; 1897 } 1898 1899 /* faults abort the transfer */ 1900 if (status) { 1901 /* clean up dma and collect transfer count */ 1902 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1903 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1904 musb->dma_controller->channel_abort(dma); 1905 xfer_len = dma->actual_len; 1906 } 1907 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1908 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1909 done = true; 1910 goto finish; 1911 } 1912 1913 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1914 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1915 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1916 goto finish; 1917 } 1918 1919 /* thorough shutdown for now ... given more precise fault handling 1920 * and better queueing support, we might keep a DMA pipeline going 1921 * while processing this irq for earlier completions. 1922 */ 1923 1924 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1925 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) && 1926 (rx_csr & MUSB_RXCSR_H_REQPKT)) { 1927 /* REVISIT this happened for a while on some short reads... 1928 * the cleanup still needs investigation... looks bad... 1929 * and also duplicates dma cleanup code above ... plus, 1930 * shouldn't this be the "half full" double buffer case? 1931 */ 1932 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1933 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1934 musb->dma_controller->channel_abort(dma); 1935 xfer_len = dma->actual_len; 1936 done = true; 1937 } 1938 1939 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1940 xfer_len, dma ? ", dma" : ""); 1941 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1942 1943 musb_ep_select(mbase, epnum); 1944 musb_writew(epio, MUSB_RXCSR, 1945 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1946 } 1947 1948 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1949 xfer_len = dma->actual_len; 1950 1951 val &= ~(MUSB_RXCSR_DMAENAB 1952 | MUSB_RXCSR_H_AUTOREQ 1953 | MUSB_RXCSR_AUTOCLEAR 1954 | MUSB_RXCSR_RXPKTRDY); 1955 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1956 1957 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) || 1958 musb_dma_cppi41(musb)) { 1959 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len); 1960 dev_dbg(hw_ep->musb->controller, 1961 "ep %d dma %s, rxcsr %04x, rxcount %d\n", 1962 epnum, done ? "off" : "reset", 1963 musb_readw(epio, MUSB_RXCSR), 1964 musb_readw(epio, MUSB_RXCOUNT)); 1965 } else { 1966 done = true; 1967 } 1968 1969 } else if (urb->status == -EINPROGRESS) { 1970 /* if no errors, be sure a packet is ready for unloading */ 1971 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1972 status = -EPROTO; 1973 ERR("Rx interrupt with no errors or packet!\n"); 1974 1975 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1976 1977 /* SCRUB (RX) */ 1978 /* do the proper sequence to abort the transfer */ 1979 musb_ep_select(mbase, epnum); 1980 val &= ~MUSB_RXCSR_H_REQPKT; 1981 musb_writew(epio, MUSB_RXCSR, val); 1982 goto finish; 1983 } 1984 1985 /* we are expecting IN packets */ 1986 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) || 1987 musb_dma_cppi41(musb)) && dma) { 1988 dev_dbg(hw_ep->musb->controller, 1989 "RX%d count %d, buffer 0x%llx len %d/%d\n", 1990 epnum, musb_readw(epio, MUSB_RXCOUNT), 1991 (unsigned long long) urb->transfer_dma 1992 + urb->actual_length, 1993 qh->offset, 1994 urb->transfer_buffer_length); 1995 1996 done = musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, 1997 urb, xfer_len, 1998 iso_err); 1999 if (done) 2000 goto finish; 2001 else 2002 dev_err(musb->controller, "error: rx_dma failed\n"); 2003 } 2004 2005 if (!dma) { 2006 unsigned int received_len; 2007 2008 /* Unmap the buffer so that CPU can use it */ 2009 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 2010 2011 /* 2012 * We need to map sg if the transfer_buffer is 2013 * NULL. 2014 */ 2015 if (!urb->transfer_buffer) { 2016 qh->use_sg = true; 2017 sg_miter_start(&qh->sg_miter, urb->sg, 1, 2018 sg_flags); 2019 } 2020 2021 if (qh->use_sg) { 2022 if (!sg_miter_next(&qh->sg_miter)) { 2023 dev_err(musb->controller, "error: sg list empty\n"); 2024 sg_miter_stop(&qh->sg_miter); 2025 status = -EINVAL; 2026 done = true; 2027 goto finish; 2028 } 2029 urb->transfer_buffer = qh->sg_miter.addr; 2030 received_len = urb->actual_length; 2031 qh->offset = 0x0; 2032 done = musb_host_packet_rx(musb, urb, epnum, 2033 iso_err); 2034 /* Calculate the number of bytes received */ 2035 received_len = urb->actual_length - 2036 received_len; 2037 qh->sg_miter.consumed = received_len; 2038 sg_miter_stop(&qh->sg_miter); 2039 } else { 2040 done = musb_host_packet_rx(musb, urb, 2041 epnum, iso_err); 2042 } 2043 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); 2044 } 2045 } 2046 2047 finish: 2048 urb->actual_length += xfer_len; 2049 qh->offset += xfer_len; 2050 if (done) { 2051 if (qh->use_sg) 2052 qh->use_sg = false; 2053 2054 if (urb->status == -EINPROGRESS) 2055 urb->status = status; 2056 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 2057 } 2058 } 2059 2060 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 2061 * the software schedule associates multiple such nodes with a given 2062 * host side hardware endpoint + direction; scheduling may activate 2063 * that hardware endpoint. 2064 */ 2065 static int musb_schedule( 2066 struct musb *musb, 2067 struct musb_qh *qh, 2068 int is_in) 2069 { 2070 int idle = 0; 2071 int best_diff; 2072 int best_end, epnum; 2073 struct musb_hw_ep *hw_ep = NULL; 2074 struct list_head *head = NULL; 2075 u8 toggle; 2076 u8 txtype; 2077 struct urb *urb = next_urb(qh); 2078 2079 /* use fixed hardware for control and bulk */ 2080 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 2081 head = &musb->control; 2082 hw_ep = musb->control_ep; 2083 goto success; 2084 } 2085 2086 /* else, periodic transfers get muxed to other endpoints */ 2087 2088 /* 2089 * We know this qh hasn't been scheduled, so all we need to do 2090 * is choose which hardware endpoint to put it on ... 2091 * 2092 * REVISIT what we really want here is a regular schedule tree 2093 * like e.g. OHCI uses. 2094 */ 2095 best_diff = 4096; 2096 best_end = -1; 2097 2098 for (epnum = 1, hw_ep = musb->endpoints + 1; 2099 epnum < musb->nr_endpoints; 2100 epnum++, hw_ep++) { 2101 int diff; 2102 2103 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 2104 continue; 2105 2106 if (hw_ep == musb->bulk_ep) 2107 continue; 2108 2109 if (is_in) 2110 diff = hw_ep->max_packet_sz_rx; 2111 else 2112 diff = hw_ep->max_packet_sz_tx; 2113 diff -= (qh->maxpacket * qh->hb_mult); 2114 2115 if (diff >= 0 && best_diff > diff) { 2116 2117 /* 2118 * Mentor controller has a bug in that if we schedule 2119 * a BULK Tx transfer on an endpoint that had earlier 2120 * handled ISOC then the BULK transfer has to start on 2121 * a zero toggle. If the BULK transfer starts on a 1 2122 * toggle then this transfer will fail as the mentor 2123 * controller starts the Bulk transfer on a 0 toggle 2124 * irrespective of the programming of the toggle bits 2125 * in the TXCSR register. Check for this condition 2126 * while allocating the EP for a Tx Bulk transfer. If 2127 * so skip this EP. 2128 */ 2129 hw_ep = musb->endpoints + epnum; 2130 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 2131 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 2132 >> 4) & 0x3; 2133 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 2134 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 2135 continue; 2136 2137 best_diff = diff; 2138 best_end = epnum; 2139 } 2140 } 2141 /* use bulk reserved ep1 if no other ep is free */ 2142 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 2143 hw_ep = musb->bulk_ep; 2144 if (is_in) 2145 head = &musb->in_bulk; 2146 else 2147 head = &musb->out_bulk; 2148 2149 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are 2150 * multiplexed. This scheme does not work in high speed to full 2151 * speed scenario as NAK interrupts are not coming from a 2152 * full speed device connected to a high speed device. 2153 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 2154 * 4 (8 frame or 8ms) for FS device. 2155 */ 2156 if (qh->dev) 2157 qh->intv_reg = 2158 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 2159 goto success; 2160 } else if (best_end < 0) { 2161 return -ENOSPC; 2162 } 2163 2164 idle = 1; 2165 qh->mux = 0; 2166 hw_ep = musb->endpoints + best_end; 2167 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); 2168 success: 2169 if (head) { 2170 idle = list_empty(head); 2171 list_add_tail(&qh->ring, head); 2172 qh->mux = 1; 2173 } 2174 qh->hw_ep = hw_ep; 2175 qh->hep->hcpriv = qh; 2176 if (idle) 2177 musb_start_urb(musb, is_in, qh); 2178 return 0; 2179 } 2180 2181 static int musb_urb_enqueue( 2182 struct usb_hcd *hcd, 2183 struct urb *urb, 2184 gfp_t mem_flags) 2185 { 2186 unsigned long flags; 2187 struct musb *musb = hcd_to_musb(hcd); 2188 struct usb_host_endpoint *hep = urb->ep; 2189 struct musb_qh *qh; 2190 struct usb_endpoint_descriptor *epd = &hep->desc; 2191 int ret; 2192 unsigned type_reg; 2193 unsigned interval; 2194 2195 /* host role must be active */ 2196 if (!is_host_active(musb) || !musb->is_active) 2197 return -ENODEV; 2198 2199 spin_lock_irqsave(&musb->lock, flags); 2200 ret = usb_hcd_link_urb_to_ep(hcd, urb); 2201 qh = ret ? NULL : hep->hcpriv; 2202 if (qh) 2203 urb->hcpriv = qh; 2204 spin_unlock_irqrestore(&musb->lock, flags); 2205 2206 /* DMA mapping was already done, if needed, and this urb is on 2207 * hep->urb_list now ... so we're done, unless hep wasn't yet 2208 * scheduled onto a live qh. 2209 * 2210 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 2211 * disabled, testing for empty qh->ring and avoiding qh setup costs 2212 * except for the first urb queued after a config change. 2213 */ 2214 if (qh || ret) 2215 return ret; 2216 2217 /* Allocate and initialize qh, minimizing the work done each time 2218 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 2219 * 2220 * REVISIT consider a dedicated qh kmem_cache, so it's harder 2221 * for bugs in other kernel code to break this driver... 2222 */ 2223 qh = kzalloc(sizeof *qh, mem_flags); 2224 if (!qh) { 2225 spin_lock_irqsave(&musb->lock, flags); 2226 usb_hcd_unlink_urb_from_ep(hcd, urb); 2227 spin_unlock_irqrestore(&musb->lock, flags); 2228 return -ENOMEM; 2229 } 2230 2231 qh->hep = hep; 2232 qh->dev = urb->dev; 2233 INIT_LIST_HEAD(&qh->ring); 2234 qh->is_ready = 1; 2235 2236 qh->maxpacket = usb_endpoint_maxp(epd); 2237 qh->type = usb_endpoint_type(epd); 2238 2239 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 2240 * Some musb cores don't support high bandwidth ISO transfers; and 2241 * we don't (yet!) support high bandwidth interrupt transfers. 2242 */ 2243 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 2244 if (qh->hb_mult > 1) { 2245 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 2246 2247 if (ok) 2248 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 2249 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 2250 if (!ok) { 2251 ret = -EMSGSIZE; 2252 goto done; 2253 } 2254 qh->maxpacket &= 0x7ff; 2255 } 2256 2257 qh->epnum = usb_endpoint_num(epd); 2258 2259 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 2260 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 2261 2262 /* precompute rxtype/txtype/type0 register */ 2263 type_reg = (qh->type << 4) | qh->epnum; 2264 switch (urb->dev->speed) { 2265 case USB_SPEED_LOW: 2266 type_reg |= 0xc0; 2267 break; 2268 case USB_SPEED_FULL: 2269 type_reg |= 0x80; 2270 break; 2271 default: 2272 type_reg |= 0x40; 2273 } 2274 qh->type_reg = type_reg; 2275 2276 /* Precompute RXINTERVAL/TXINTERVAL register */ 2277 switch (qh->type) { 2278 case USB_ENDPOINT_XFER_INT: 2279 /* 2280 * Full/low speeds use the linear encoding, 2281 * high speed uses the logarithmic encoding. 2282 */ 2283 if (urb->dev->speed <= USB_SPEED_FULL) { 2284 interval = max_t(u8, epd->bInterval, 1); 2285 break; 2286 } 2287 /* FALLTHROUGH */ 2288 case USB_ENDPOINT_XFER_ISOC: 2289 /* ISO always uses logarithmic encoding */ 2290 interval = min_t(u8, epd->bInterval, 16); 2291 break; 2292 default: 2293 /* REVISIT we actually want to use NAK limits, hinting to the 2294 * transfer scheduling logic to try some other qh, e.g. try 2295 * for 2 msec first: 2296 * 2297 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2298 * 2299 * The downside of disabling this is that transfer scheduling 2300 * gets VERY unfair for nonperiodic transfers; a misbehaving 2301 * peripheral could make that hurt. That's perfectly normal 2302 * for reads from network or serial adapters ... so we have 2303 * partial NAKlimit support for bulk RX. 2304 * 2305 * The upside of disabling it is simpler transfer scheduling. 2306 */ 2307 interval = 0; 2308 } 2309 qh->intv_reg = interval; 2310 2311 /* precompute addressing for external hub/tt ports */ 2312 if (musb->is_multipoint) { 2313 struct usb_device *parent = urb->dev->parent; 2314 2315 if (parent != hcd->self.root_hub) { 2316 qh->h_addr_reg = (u8) parent->devnum; 2317 2318 /* set up tt info if needed */ 2319 if (urb->dev->tt) { 2320 qh->h_port_reg = (u8) urb->dev->ttport; 2321 if (urb->dev->tt->hub) 2322 qh->h_addr_reg = 2323 (u8) urb->dev->tt->hub->devnum; 2324 if (urb->dev->tt->multi) 2325 qh->h_addr_reg |= 0x80; 2326 } 2327 } 2328 } 2329 2330 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2331 * until we get real dma queues (with an entry for each urb/buffer), 2332 * we only have work to do in the former case. 2333 */ 2334 spin_lock_irqsave(&musb->lock, flags); 2335 if (hep->hcpriv || !next_urb(qh)) { 2336 /* some concurrent activity submitted another urb to hep... 2337 * odd, rare, error prone, but legal. 2338 */ 2339 kfree(qh); 2340 qh = NULL; 2341 ret = 0; 2342 } else 2343 ret = musb_schedule(musb, qh, 2344 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2345 2346 if (ret == 0) { 2347 urb->hcpriv = qh; 2348 /* FIXME set urb->start_frame for iso/intr, it's tested in 2349 * musb_start_urb(), but otherwise only konicawc cares ... 2350 */ 2351 } 2352 spin_unlock_irqrestore(&musb->lock, flags); 2353 2354 done: 2355 if (ret != 0) { 2356 spin_lock_irqsave(&musb->lock, flags); 2357 usb_hcd_unlink_urb_from_ep(hcd, urb); 2358 spin_unlock_irqrestore(&musb->lock, flags); 2359 kfree(qh); 2360 } 2361 return ret; 2362 } 2363 2364 2365 /* 2366 * abort a transfer that's at the head of a hardware queue. 2367 * called with controller locked, irqs blocked 2368 * that hardware queue advances to the next transfer, unless prevented 2369 */ 2370 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2371 { 2372 struct musb_hw_ep *ep = qh->hw_ep; 2373 struct musb *musb = ep->musb; 2374 void __iomem *epio = ep->regs; 2375 unsigned hw_end = ep->epnum; 2376 void __iomem *regs = ep->musb->mregs; 2377 int is_in = usb_pipein(urb->pipe); 2378 int status = 0; 2379 u16 csr; 2380 2381 musb_ep_select(regs, hw_end); 2382 2383 if (is_dma_capable()) { 2384 struct dma_channel *dma; 2385 2386 dma = is_in ? ep->rx_channel : ep->tx_channel; 2387 if (dma) { 2388 status = ep->musb->dma_controller->channel_abort(dma); 2389 dev_dbg(musb->controller, 2390 "abort %cX%d DMA for urb %p --> %d\n", 2391 is_in ? 'R' : 'T', ep->epnum, 2392 urb, status); 2393 urb->actual_length += dma->actual_len; 2394 } 2395 } 2396 2397 /* turn off DMA requests, discard state, stop polling ... */ 2398 if (ep->epnum && is_in) { 2399 /* giveback saves bulk toggle */ 2400 csr = musb_h_flush_rxfifo(ep, 0); 2401 2402 /* REVISIT we still get an irq; should likely clear the 2403 * endpoint's irq status here to avoid bogus irqs. 2404 * clearing that status is platform-specific... 2405 */ 2406 } else if (ep->epnum) { 2407 musb_h_tx_flush_fifo(ep); 2408 csr = musb_readw(epio, MUSB_TXCSR); 2409 csr &= ~(MUSB_TXCSR_AUTOSET 2410 | MUSB_TXCSR_DMAENAB 2411 | MUSB_TXCSR_H_RXSTALL 2412 | MUSB_TXCSR_H_NAKTIMEOUT 2413 | MUSB_TXCSR_H_ERROR 2414 | MUSB_TXCSR_TXPKTRDY); 2415 musb_writew(epio, MUSB_TXCSR, csr); 2416 /* REVISIT may need to clear FLUSHFIFO ... */ 2417 musb_writew(epio, MUSB_TXCSR, csr); 2418 /* flush cpu writebuffer */ 2419 csr = musb_readw(epio, MUSB_TXCSR); 2420 } else { 2421 musb_h_ep0_flush_fifo(ep); 2422 } 2423 if (status == 0) 2424 musb_advance_schedule(ep->musb, urb, ep, is_in); 2425 return status; 2426 } 2427 2428 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2429 { 2430 struct musb *musb = hcd_to_musb(hcd); 2431 struct musb_qh *qh; 2432 unsigned long flags; 2433 int is_in = usb_pipein(urb->pipe); 2434 int ret; 2435 2436 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, 2437 usb_pipedevice(urb->pipe), 2438 usb_pipeendpoint(urb->pipe), 2439 is_in ? "in" : "out"); 2440 2441 spin_lock_irqsave(&musb->lock, flags); 2442 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2443 if (ret) 2444 goto done; 2445 2446 qh = urb->hcpriv; 2447 if (!qh) 2448 goto done; 2449 2450 /* 2451 * Any URB not actively programmed into endpoint hardware can be 2452 * immediately given back; that's any URB not at the head of an 2453 * endpoint queue, unless someday we get real DMA queues. And even 2454 * if it's at the head, it might not be known to the hardware... 2455 * 2456 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2457 * has already been updated. This is a synchronous abort; it'd be 2458 * OK to hold off until after some IRQ, though. 2459 * 2460 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2461 */ 2462 if (!qh->is_ready 2463 || urb->urb_list.prev != &qh->hep->urb_list 2464 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2465 int ready = qh->is_ready; 2466 2467 qh->is_ready = 0; 2468 musb_giveback(musb, urb, 0); 2469 qh->is_ready = ready; 2470 2471 /* If nothing else (usually musb_giveback) is using it 2472 * and its URB list has emptied, recycle this qh. 2473 */ 2474 if (ready && list_empty(&qh->hep->urb_list)) { 2475 qh->hep->hcpriv = NULL; 2476 list_del(&qh->ring); 2477 kfree(qh); 2478 } 2479 } else 2480 ret = musb_cleanup_urb(urb, qh); 2481 done: 2482 spin_unlock_irqrestore(&musb->lock, flags); 2483 return ret; 2484 } 2485 2486 /* disable an endpoint */ 2487 static void 2488 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2489 { 2490 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2491 unsigned long flags; 2492 struct musb *musb = hcd_to_musb(hcd); 2493 struct musb_qh *qh; 2494 struct urb *urb; 2495 2496 spin_lock_irqsave(&musb->lock, flags); 2497 2498 qh = hep->hcpriv; 2499 if (qh == NULL) 2500 goto exit; 2501 2502 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2503 2504 /* Kick the first URB off the hardware, if needed */ 2505 qh->is_ready = 0; 2506 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2507 urb = next_urb(qh); 2508 2509 /* make software (then hardware) stop ASAP */ 2510 if (!urb->unlinked) 2511 urb->status = -ESHUTDOWN; 2512 2513 /* cleanup */ 2514 musb_cleanup_urb(urb, qh); 2515 2516 /* Then nuke all the others ... and advance the 2517 * queue on hw_ep (e.g. bulk ring) when we're done. 2518 */ 2519 while (!list_empty(&hep->urb_list)) { 2520 urb = next_urb(qh); 2521 urb->status = -ESHUTDOWN; 2522 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2523 } 2524 } else { 2525 /* Just empty the queue; the hardware is busy with 2526 * other transfers, and since !qh->is_ready nothing 2527 * will activate any of these as it advances. 2528 */ 2529 while (!list_empty(&hep->urb_list)) 2530 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2531 2532 hep->hcpriv = NULL; 2533 list_del(&qh->ring); 2534 kfree(qh); 2535 } 2536 exit: 2537 spin_unlock_irqrestore(&musb->lock, flags); 2538 } 2539 2540 static int musb_h_get_frame_number(struct usb_hcd *hcd) 2541 { 2542 struct musb *musb = hcd_to_musb(hcd); 2543 2544 return musb_readw(musb->mregs, MUSB_FRAME); 2545 } 2546 2547 static int musb_h_start(struct usb_hcd *hcd) 2548 { 2549 struct musb *musb = hcd_to_musb(hcd); 2550 2551 /* NOTE: musb_start() is called when the hub driver turns 2552 * on port power, or when (OTG) peripheral starts. 2553 */ 2554 hcd->state = HC_STATE_RUNNING; 2555 musb->port1_status = 0; 2556 return 0; 2557 } 2558 2559 static void musb_h_stop(struct usb_hcd *hcd) 2560 { 2561 musb_stop(hcd_to_musb(hcd)); 2562 hcd->state = HC_STATE_HALT; 2563 } 2564 2565 static int musb_bus_suspend(struct usb_hcd *hcd) 2566 { 2567 struct musb *musb = hcd_to_musb(hcd); 2568 u8 devctl; 2569 2570 musb_port_suspend(musb, true); 2571 2572 if (!is_host_active(musb)) 2573 return 0; 2574 2575 switch (musb->xceiv->otg->state) { 2576 case OTG_STATE_A_SUSPEND: 2577 return 0; 2578 case OTG_STATE_A_WAIT_VRISE: 2579 /* ID could be grounded even if there's no device 2580 * on the other end of the cable. NOTE that the 2581 * A_WAIT_VRISE timers are messy with MUSB... 2582 */ 2583 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2584 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2585 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 2586 break; 2587 default: 2588 break; 2589 } 2590 2591 if (musb->is_active) { 2592 WARNING("trying to suspend as %s while active\n", 2593 usb_otg_state_string(musb->xceiv->otg->state)); 2594 return -EBUSY; 2595 } else 2596 return 0; 2597 } 2598 2599 static int musb_bus_resume(struct usb_hcd *hcd) 2600 { 2601 struct musb *musb = hcd_to_musb(hcd); 2602 2603 if (musb->config && 2604 musb->config->host_port_deassert_reset_at_resume) 2605 musb_port_reset(musb, false); 2606 2607 return 0; 2608 } 2609 2610 #ifndef CONFIG_MUSB_PIO_ONLY 2611 2612 #define MUSB_USB_DMA_ALIGN 4 2613 2614 struct musb_temp_buffer { 2615 void *kmalloc_ptr; 2616 void *old_xfer_buffer; 2617 u8 data[0]; 2618 }; 2619 2620 static void musb_free_temp_buffer(struct urb *urb) 2621 { 2622 enum dma_data_direction dir; 2623 struct musb_temp_buffer *temp; 2624 size_t length; 2625 2626 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2627 return; 2628 2629 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2630 2631 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, 2632 data); 2633 2634 if (dir == DMA_FROM_DEVICE) { 2635 if (usb_pipeisoc(urb->pipe)) 2636 length = urb->transfer_buffer_length; 2637 else 2638 length = urb->actual_length; 2639 2640 memcpy(temp->old_xfer_buffer, temp->data, length); 2641 } 2642 urb->transfer_buffer = temp->old_xfer_buffer; 2643 kfree(temp->kmalloc_ptr); 2644 2645 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2646 } 2647 2648 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 2649 { 2650 enum dma_data_direction dir; 2651 struct musb_temp_buffer *temp; 2652 void *kmalloc_ptr; 2653 size_t kmalloc_size; 2654 2655 if (urb->num_sgs || urb->sg || 2656 urb->transfer_buffer_length == 0 || 2657 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) 2658 return 0; 2659 2660 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2661 2662 /* Allocate a buffer with enough padding for alignment */ 2663 kmalloc_size = urb->transfer_buffer_length + 2664 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; 2665 2666 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2667 if (!kmalloc_ptr) 2668 return -ENOMEM; 2669 2670 /* Position our struct temp_buffer such that data is aligned */ 2671 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); 2672 2673 2674 temp->kmalloc_ptr = kmalloc_ptr; 2675 temp->old_xfer_buffer = urb->transfer_buffer; 2676 if (dir == DMA_TO_DEVICE) 2677 memcpy(temp->data, urb->transfer_buffer, 2678 urb->transfer_buffer_length); 2679 urb->transfer_buffer = temp->data; 2680 2681 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2682 2683 return 0; 2684 } 2685 2686 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2687 gfp_t mem_flags) 2688 { 2689 struct musb *musb = hcd_to_musb(hcd); 2690 int ret; 2691 2692 /* 2693 * The DMA engine in RTL1.8 and above cannot handle 2694 * DMA addresses that are not aligned to a 4 byte boundary. 2695 * For such engine implemented (un)map_urb_for_dma hooks. 2696 * Do not use these hooks for RTL<1.8 2697 */ 2698 if (musb->hwvers < MUSB_HWVERS_1800) 2699 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2700 2701 ret = musb_alloc_temp_buffer(urb, mem_flags); 2702 if (ret) 2703 return ret; 2704 2705 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2706 if (ret) 2707 musb_free_temp_buffer(urb); 2708 2709 return ret; 2710 } 2711 2712 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2713 { 2714 struct musb *musb = hcd_to_musb(hcd); 2715 2716 usb_hcd_unmap_urb_for_dma(hcd, urb); 2717 2718 /* Do not use this hook for RTL<1.8 (see description above) */ 2719 if (musb->hwvers < MUSB_HWVERS_1800) 2720 return; 2721 2722 musb_free_temp_buffer(urb); 2723 } 2724 #endif /* !CONFIG_MUSB_PIO_ONLY */ 2725 2726 static const struct hc_driver musb_hc_driver = { 2727 .description = "musb-hcd", 2728 .product_desc = "MUSB HDRC host driver", 2729 .hcd_priv_size = sizeof(struct musb *), 2730 .flags = HCD_USB2 | HCD_MEMORY | HCD_BH, 2731 2732 /* not using irq handler or reset hooks from usbcore, since 2733 * those must be shared with peripheral code for OTG configs 2734 */ 2735 2736 .start = musb_h_start, 2737 .stop = musb_h_stop, 2738 2739 .get_frame_number = musb_h_get_frame_number, 2740 2741 .urb_enqueue = musb_urb_enqueue, 2742 .urb_dequeue = musb_urb_dequeue, 2743 .endpoint_disable = musb_h_disable, 2744 2745 #ifndef CONFIG_MUSB_PIO_ONLY 2746 .map_urb_for_dma = musb_map_urb_for_dma, 2747 .unmap_urb_for_dma = musb_unmap_urb_for_dma, 2748 #endif 2749 2750 .hub_status_data = musb_hub_status_data, 2751 .hub_control = musb_hub_control, 2752 .bus_suspend = musb_bus_suspend, 2753 .bus_resume = musb_bus_resume, 2754 /* .start_port_reset = NULL, */ 2755 /* .hub_irq_enable = NULL, */ 2756 }; 2757 2758 int musb_host_alloc(struct musb *musb) 2759 { 2760 struct device *dev = musb->controller; 2761 2762 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 2763 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 2764 if (!musb->hcd) 2765 return -EINVAL; 2766 2767 *musb->hcd->hcd_priv = (unsigned long) musb; 2768 musb->hcd->self.uses_pio_for_control = 1; 2769 musb->hcd->uses_new_polling = 1; 2770 musb->hcd->has_tt = 1; 2771 2772 return 0; 2773 } 2774 2775 void musb_host_cleanup(struct musb *musb) 2776 { 2777 if (musb->port_mode == MUSB_PORT_MODE_GADGET) 2778 return; 2779 usb_remove_hcd(musb->hcd); 2780 } 2781 2782 void musb_host_free(struct musb *musb) 2783 { 2784 usb_put_hcd(musb->hcd); 2785 } 2786 2787 int musb_host_setup(struct musb *musb, int power_budget) 2788 { 2789 int ret; 2790 struct usb_hcd *hcd = musb->hcd; 2791 2792 MUSB_HST_MODE(musb); 2793 musb->xceiv->otg->default_a = 1; 2794 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 2795 2796 otg_set_host(musb->xceiv->otg, &hcd->self); 2797 hcd->self.otg_port = 1; 2798 musb->xceiv->otg->host = &hcd->self; 2799 hcd->power_budget = 2 * (power_budget ? : 250); 2800 2801 ret = usb_add_hcd(hcd, 0, 0); 2802 if (ret < 0) 2803 return ret; 2804 2805 device_wakeup_enable(hcd->self.controller); 2806 return 0; 2807 } 2808 2809 void musb_host_resume_root_hub(struct musb *musb) 2810 { 2811 usb_hcd_resume_root_hub(musb->hcd); 2812 } 2813 2814 void musb_host_poke_root_hub(struct musb *musb) 2815 { 2816 MUSB_HST_MODE(musb); 2817 if (musb->hcd->status_urb) 2818 usb_hcd_poll_rh_status(musb->hcd); 2819 else 2820 usb_hcd_resume_root_hub(musb->hcd); 2821 } 2822