1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MUSB OTG driver host support 4 * 5 * Copyright 2005 Mentor Graphics Corporation 6 * Copyright (C) 2005-2006 by Texas Instruments 7 * Copyright (C) 2006-2007 Nokia Corporation 8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/sched.h> 15 #include <linux/slab.h> 16 #include <linux/errno.h> 17 #include <linux/list.h> 18 #include <linux/dma-mapping.h> 19 20 #include "musb_core.h" 21 #include "musb_host.h" 22 #include "musb_trace.h" 23 24 /* MUSB HOST status 22-mar-2006 25 * 26 * - There's still lots of partial code duplication for fault paths, so 27 * they aren't handled as consistently as they need to be. 28 * 29 * - PIO mostly behaved when last tested. 30 * + including ep0, with all usbtest cases 9, 10 31 * + usbtest 14 (ep0out) doesn't seem to run at all 32 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 33 * configurations, but otherwise double buffering passes basic tests. 34 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 35 * 36 * - DMA (CPPI) ... partially behaves, not currently recommended 37 * + about 1/15 the speed of typical EHCI implementations (PCI) 38 * + RX, all too often reqpkt seems to misbehave after tx 39 * + TX, no known issues (other than evident silicon issue) 40 * 41 * - DMA (Mentor/OMAP) ...has at least toggle update problems 42 * 43 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 44 * starvation ... nothing yet for TX, interrupt, or bulk. 45 * 46 * - Not tested with HNP, but some SRP paths seem to behave. 47 * 48 * NOTE 24-August-2006: 49 * 50 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 51 * extra endpoint for periodic use enabling hub + keybd + mouse. That 52 * mostly works, except that with "usbnet" it's easy to trigger cases 53 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 54 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 55 * although ARP RX wins. (That test was done with a full speed link.) 56 */ 57 58 59 /* 60 * NOTE on endpoint usage: 61 * 62 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 63 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 64 * (Yes, bulk _could_ use more of the endpoints than that, and would even 65 * benefit from it.) 66 * 67 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 68 * So far that scheduling is both dumb and optimistic: the endpoint will be 69 * "claimed" until its software queue is no longer refilled. No multiplexing 70 * of transfers between endpoints, or anything clever. 71 */ 72 73 struct musb *hcd_to_musb(struct usb_hcd *hcd) 74 { 75 return *(struct musb **) hcd->hcd_priv; 76 } 77 78 79 static void musb_ep_program(struct musb *musb, u8 epnum, 80 struct urb *urb, int is_out, 81 u8 *buf, u32 offset, u32 len); 82 83 /* 84 * Clear TX fifo. Needed to avoid BABBLE errors. 85 */ 86 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 87 { 88 struct musb *musb = ep->musb; 89 void __iomem *epio = ep->regs; 90 u16 csr; 91 int retries = 1000; 92 93 csr = musb_readw(epio, MUSB_TXCSR); 94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; 96 musb_writew(epio, MUSB_TXCSR, csr); 97 csr = musb_readw(epio, MUSB_TXCSR); 98 99 /* 100 * FIXME: sometimes the tx fifo flush failed, it has been 101 * observed during device disconnect on AM335x. 102 * 103 * To reproduce the issue, ensure tx urb(s) are queued when 104 * unplug the usb device which is connected to AM335x usb 105 * host port. 106 * 107 * I found using a usb-ethernet device and running iperf 108 * (client on AM335x) has very high chance to trigger it. 109 * 110 * Better to turn on musb_dbg() in musb_cleanup_urb() with 111 * CPPI enabled to see the issue when aborting the tx channel. 112 */ 113 if (dev_WARN_ONCE(musb->controller, retries-- < 1, 114 "Could not flush host TX%d fifo: csr: %04x\n", 115 ep->epnum, csr)) 116 return; 117 mdelay(1); 118 } 119 } 120 121 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 122 { 123 void __iomem *epio = ep->regs; 124 u16 csr; 125 int retries = 5; 126 127 /* scrub any data left in the fifo */ 128 do { 129 csr = musb_readw(epio, MUSB_TXCSR); 130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 131 break; 132 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 133 csr = musb_readw(epio, MUSB_TXCSR); 134 udelay(10); 135 } while (--retries); 136 137 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 138 ep->epnum, csr); 139 140 /* and reset for the next transfer */ 141 musb_writew(epio, MUSB_TXCSR, 0); 142 } 143 144 /* 145 * Start transmit. Caller is responsible for locking shared resources. 146 * musb must be locked. 147 */ 148 static inline void musb_h_tx_start(struct musb_hw_ep *ep) 149 { 150 u16 txcsr; 151 152 /* NOTE: no locks here; caller should lock and select EP */ 153 if (ep->epnum) { 154 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 155 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 156 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 157 } else { 158 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 159 musb_writew(ep->regs, MUSB_CSR0, txcsr); 160 } 161 162 } 163 164 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 165 { 166 u16 txcsr; 167 168 /* NOTE: no locks here; caller should lock and select EP */ 169 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 170 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 171 if (is_cppi_enabled(ep->musb)) 172 txcsr |= MUSB_TXCSR_DMAMODE; 173 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 174 } 175 176 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 177 { 178 if (is_in != 0 || ep->is_shared_fifo) 179 ep->in_qh = qh; 180 if (is_in == 0 || ep->is_shared_fifo) 181 ep->out_qh = qh; 182 } 183 184 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 185 { 186 return is_in ? ep->in_qh : ep->out_qh; 187 } 188 189 /* 190 * Start the URB at the front of an endpoint's queue 191 * end must be claimed from the caller. 192 * 193 * Context: controller locked, irqs blocked 194 */ 195 static void 196 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 197 { 198 u32 len; 199 void __iomem *mbase = musb->mregs; 200 struct urb *urb = next_urb(qh); 201 void *buf = urb->transfer_buffer; 202 u32 offset = 0; 203 struct musb_hw_ep *hw_ep = qh->hw_ep; 204 int epnum = hw_ep->epnum; 205 206 /* initialize software qh state */ 207 qh->offset = 0; 208 qh->segsize = 0; 209 210 /* gather right source of data */ 211 switch (qh->type) { 212 case USB_ENDPOINT_XFER_CONTROL: 213 /* control transfers always start with SETUP */ 214 is_in = 0; 215 musb->ep0_stage = MUSB_EP0_START; 216 buf = urb->setup_packet; 217 len = 8; 218 break; 219 case USB_ENDPOINT_XFER_ISOC: 220 qh->iso_idx = 0; 221 qh->frame = 0; 222 offset = urb->iso_frame_desc[0].offset; 223 len = urb->iso_frame_desc[0].length; 224 break; 225 default: /* bulk, interrupt */ 226 /* actual_length may be nonzero on retry paths */ 227 buf = urb->transfer_buffer + urb->actual_length; 228 len = urb->transfer_buffer_length - urb->actual_length; 229 } 230 231 trace_musb_urb_start(musb, urb); 232 233 /* Configure endpoint */ 234 musb_ep_set_qh(hw_ep, is_in, qh); 235 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 236 237 /* transmit may have more work: start it when it is time */ 238 if (is_in) 239 return; 240 241 /* determine if the time is right for a periodic transfer */ 242 switch (qh->type) { 243 case USB_ENDPOINT_XFER_ISOC: 244 case USB_ENDPOINT_XFER_INT: 245 musb_dbg(musb, "check whether there's still time for periodic Tx"); 246 /* FIXME this doesn't implement that scheduling policy ... 247 * or handle framecounter wrapping 248 */ 249 if (1) { /* Always assume URB_ISO_ASAP */ 250 /* REVISIT the SOF irq handler shouldn't duplicate 251 * this code; and we don't init urb->start_frame... 252 */ 253 qh->frame = 0; 254 goto start; 255 } else { 256 qh->frame = urb->start_frame; 257 /* enable SOF interrupt so we can count down */ 258 musb_dbg(musb, "SOF for %d", epnum); 259 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 260 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 261 #endif 262 } 263 break; 264 default: 265 start: 266 musb_dbg(musb, "Start TX%d %s", epnum, 267 hw_ep->tx_channel ? "dma" : "pio"); 268 269 if (!hw_ep->tx_channel) 270 musb_h_tx_start(hw_ep); 271 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) 272 musb_h_tx_dma_start(hw_ep); 273 } 274 } 275 276 /* Context: caller owns controller lock, IRQs are blocked */ 277 static void musb_giveback(struct musb *musb, struct urb *urb, int status) 278 __releases(musb->lock) 279 __acquires(musb->lock) 280 { 281 trace_musb_urb_gb(musb, urb); 282 283 usb_hcd_unlink_urb_from_ep(musb->hcd, urb); 284 spin_unlock(&musb->lock); 285 usb_hcd_giveback_urb(musb->hcd, urb, status); 286 spin_lock(&musb->lock); 287 } 288 289 /* 290 * Advance this hardware endpoint's queue, completing the specified URB and 291 * advancing to either the next URB queued to that qh, or else invalidating 292 * that qh and advancing to the next qh scheduled after the current one. 293 * 294 * Context: caller owns controller lock, IRQs are blocked 295 */ 296 static void musb_advance_schedule(struct musb *musb, struct urb *urb, 297 struct musb_hw_ep *hw_ep, int is_in) 298 { 299 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 300 struct musb_hw_ep *ep = qh->hw_ep; 301 int ready = qh->is_ready; 302 int status; 303 u16 toggle; 304 305 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 306 307 /* save toggle eagerly, for paranoia */ 308 switch (qh->type) { 309 case USB_ENDPOINT_XFER_BULK: 310 case USB_ENDPOINT_XFER_INT: 311 toggle = musb->io.get_toggle(qh, !is_in); 312 usb_settoggle(urb->dev, qh->epnum, !is_in, toggle ? 1 : 0); 313 break; 314 case USB_ENDPOINT_XFER_ISOC: 315 if (status == 0 && urb->error_count) 316 status = -EXDEV; 317 break; 318 } 319 320 qh->is_ready = 0; 321 musb_giveback(musb, urb, status); 322 qh->is_ready = ready; 323 324 /* 325 * musb->lock had been unlocked in musb_giveback, so qh may 326 * be freed, need to get it again 327 */ 328 qh = musb_ep_get_qh(hw_ep, is_in); 329 330 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 331 * invalidate qh as soon as list_empty(&hep->urb_list) 332 */ 333 if (qh && list_empty(&qh->hep->urb_list)) { 334 struct list_head *head; 335 struct dma_controller *dma = musb->dma_controller; 336 337 if (is_in) { 338 ep->rx_reinit = 1; 339 if (ep->rx_channel) { 340 dma->channel_release(ep->rx_channel); 341 ep->rx_channel = NULL; 342 } 343 } else { 344 ep->tx_reinit = 1; 345 if (ep->tx_channel) { 346 dma->channel_release(ep->tx_channel); 347 ep->tx_channel = NULL; 348 } 349 } 350 351 /* Clobber old pointers to this qh */ 352 musb_ep_set_qh(ep, is_in, NULL); 353 qh->hep->hcpriv = NULL; 354 355 switch (qh->type) { 356 357 case USB_ENDPOINT_XFER_CONTROL: 358 case USB_ENDPOINT_XFER_BULK: 359 /* fifo policy for these lists, except that NAKing 360 * should rotate a qh to the end (for fairness). 361 */ 362 if (qh->mux == 1) { 363 head = qh->ring.prev; 364 list_del(&qh->ring); 365 kfree(qh); 366 qh = first_qh(head); 367 break; 368 } 369 fallthrough; 370 371 case USB_ENDPOINT_XFER_ISOC: 372 case USB_ENDPOINT_XFER_INT: 373 /* this is where periodic bandwidth should be 374 * de-allocated if it's tracked and allocated; 375 * and where we'd update the schedule tree... 376 */ 377 kfree(qh); 378 qh = NULL; 379 break; 380 } 381 } 382 383 if (qh != NULL && qh->is_ready) { 384 musb_dbg(musb, "... next ep%d %cX urb %p", 385 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 386 musb_start_urb(musb, is_in, qh); 387 } 388 } 389 390 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 391 { 392 /* we don't want fifo to fill itself again; 393 * ignore dma (various models), 394 * leave toggle alone (may not have been saved yet) 395 */ 396 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 397 csr &= ~(MUSB_RXCSR_H_REQPKT 398 | MUSB_RXCSR_H_AUTOREQ 399 | MUSB_RXCSR_AUTOCLEAR); 400 401 /* write 2x to allow double buffering */ 402 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 403 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 404 405 /* flush writebuffer */ 406 return musb_readw(hw_ep->regs, MUSB_RXCSR); 407 } 408 409 /* 410 * PIO RX for a packet (or part of it). 411 */ 412 static bool 413 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 414 { 415 u16 rx_count; 416 u8 *buf; 417 u16 csr; 418 bool done = false; 419 u32 length; 420 int do_flush = 0; 421 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 422 void __iomem *epio = hw_ep->regs; 423 struct musb_qh *qh = hw_ep->in_qh; 424 int pipe = urb->pipe; 425 void *buffer = urb->transfer_buffer; 426 427 /* musb_ep_select(mbase, epnum); */ 428 rx_count = musb_readw(epio, MUSB_RXCOUNT); 429 musb_dbg(musb, "RX%d count %d, buffer %p len %d/%d", epnum, rx_count, 430 urb->transfer_buffer, qh->offset, 431 urb->transfer_buffer_length); 432 433 /* unload FIFO */ 434 if (usb_pipeisoc(pipe)) { 435 int status = 0; 436 struct usb_iso_packet_descriptor *d; 437 438 if (iso_err) { 439 status = -EILSEQ; 440 urb->error_count++; 441 } 442 443 d = urb->iso_frame_desc + qh->iso_idx; 444 buf = buffer + d->offset; 445 length = d->length; 446 if (rx_count > length) { 447 if (status == 0) { 448 status = -EOVERFLOW; 449 urb->error_count++; 450 } 451 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length); 452 do_flush = 1; 453 } else 454 length = rx_count; 455 urb->actual_length += length; 456 d->actual_length = length; 457 458 d->status = status; 459 460 /* see if we are done */ 461 done = (++qh->iso_idx >= urb->number_of_packets); 462 } else { 463 /* non-isoch */ 464 buf = buffer + qh->offset; 465 length = urb->transfer_buffer_length - qh->offset; 466 if (rx_count > length) { 467 if (urb->status == -EINPROGRESS) 468 urb->status = -EOVERFLOW; 469 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length); 470 do_flush = 1; 471 } else 472 length = rx_count; 473 urb->actual_length += length; 474 qh->offset += length; 475 476 /* see if we are done */ 477 done = (urb->actual_length == urb->transfer_buffer_length) 478 || (rx_count < qh->maxpacket) 479 || (urb->status != -EINPROGRESS); 480 if (done 481 && (urb->status == -EINPROGRESS) 482 && (urb->transfer_flags & URB_SHORT_NOT_OK) 483 && (urb->actual_length 484 < urb->transfer_buffer_length)) 485 urb->status = -EREMOTEIO; 486 } 487 488 musb_read_fifo(hw_ep, length, buf); 489 490 csr = musb_readw(epio, MUSB_RXCSR); 491 csr |= MUSB_RXCSR_H_WZC_BITS; 492 if (unlikely(do_flush)) 493 musb_h_flush_rxfifo(hw_ep, csr); 494 else { 495 /* REVISIT this assumes AUTOCLEAR is never set */ 496 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 497 if (!done) 498 csr |= MUSB_RXCSR_H_REQPKT; 499 musb_writew(epio, MUSB_RXCSR, csr); 500 } 501 502 return done; 503 } 504 505 /* we don't always need to reinit a given side of an endpoint... 506 * when we do, use tx/rx reinit routine and then construct a new CSR 507 * to address data toggle, NYET, and DMA or PIO. 508 * 509 * it's possible that driver bugs (especially for DMA) or aborting a 510 * transfer might have left the endpoint busier than it should be. 511 * the busy/not-empty tests are basically paranoia. 512 */ 513 static void 514 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum) 515 { 516 struct musb_hw_ep *ep = musb->endpoints + epnum; 517 u16 csr; 518 519 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 520 * That always uses tx_reinit since ep0 repurposes TX register 521 * offsets; the initial SETUP packet is also a kind of OUT. 522 */ 523 524 /* if programmed for Tx, put it in RX mode */ 525 if (ep->is_shared_fifo) { 526 csr = musb_readw(ep->regs, MUSB_TXCSR); 527 if (csr & MUSB_TXCSR_MODE) { 528 musb_h_tx_flush_fifo(ep); 529 csr = musb_readw(ep->regs, MUSB_TXCSR); 530 musb_writew(ep->regs, MUSB_TXCSR, 531 csr | MUSB_TXCSR_FRCDATATOG); 532 } 533 534 /* 535 * Clear the MODE bit (and everything else) to enable Rx. 536 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 537 */ 538 if (csr & MUSB_TXCSR_DMAMODE) 539 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 540 musb_writew(ep->regs, MUSB_TXCSR, 0); 541 542 /* scrub all previous state, clearing toggle */ 543 } 544 csr = musb_readw(ep->regs, MUSB_RXCSR); 545 if (csr & MUSB_RXCSR_RXPKTRDY) 546 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 547 musb_readw(ep->regs, MUSB_RXCOUNT)); 548 549 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 550 551 /* target addr and (for multipoint) hub addr/port */ 552 if (musb->is_multipoint) { 553 musb_write_rxfunaddr(musb, epnum, qh->addr_reg); 554 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg); 555 musb_write_rxhubport(musb, epnum, qh->h_port_reg); 556 } else 557 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 558 559 /* protocol/endpoint, interval/NAKlimit, i/o size */ 560 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 561 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 562 /* NOTE: bulk combining rewrites high bits of maxpacket */ 563 /* Set RXMAXP with the FIFO size of the endpoint 564 * to disable double buffer mode. 565 */ 566 musb_writew(ep->regs, MUSB_RXMAXP, 567 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 568 569 ep->rx_reinit = 0; 570 } 571 572 static void musb_tx_dma_set_mode_mentor(struct musb_hw_ep *hw_ep, 573 struct musb_qh *qh, 574 u32 *length, u8 *mode) 575 { 576 struct dma_channel *channel = hw_ep->tx_channel; 577 void __iomem *epio = hw_ep->regs; 578 u16 pkt_size = qh->maxpacket; 579 u16 csr; 580 581 if (*length > channel->max_len) 582 *length = channel->max_len; 583 584 csr = musb_readw(epio, MUSB_TXCSR); 585 if (*length > pkt_size) { 586 *mode = 1; 587 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 588 /* autoset shouldn't be set in high bandwidth */ 589 /* 590 * Enable Autoset according to table 591 * below 592 * bulk_split hb_mult Autoset_Enable 593 * 0 1 Yes(Normal) 594 * 0 >1 No(High BW ISO) 595 * 1 1 Yes(HS bulk) 596 * 1 >1 Yes(FS bulk) 597 */ 598 if (qh->hb_mult == 1 || (qh->hb_mult > 1 && 599 can_bulk_split(hw_ep->musb, qh->type))) 600 csr |= MUSB_TXCSR_AUTOSET; 601 } else { 602 *mode = 0; 603 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 604 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 605 } 606 channel->desired_mode = *mode; 607 musb_writew(epio, MUSB_TXCSR, csr); 608 } 609 610 static void musb_tx_dma_set_mode_cppi_tusb(struct musb_hw_ep *hw_ep, 611 struct urb *urb, 612 u8 *mode) 613 { 614 struct dma_channel *channel = hw_ep->tx_channel; 615 616 channel->actual_len = 0; 617 618 /* 619 * TX uses "RNDIS" mode automatically but needs help 620 * to identify the zero-length-final-packet case. 621 */ 622 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 623 } 624 625 static bool musb_tx_dma_program(struct dma_controller *dma, 626 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 627 struct urb *urb, u32 offset, u32 length) 628 { 629 struct dma_channel *channel = hw_ep->tx_channel; 630 u16 pkt_size = qh->maxpacket; 631 u8 mode; 632 633 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb)) 634 musb_tx_dma_set_mode_mentor(hw_ep, qh, 635 &length, &mode); 636 else if (is_cppi_enabled(hw_ep->musb) || tusb_dma_omap(hw_ep->musb)) 637 musb_tx_dma_set_mode_cppi_tusb(hw_ep, urb, &mode); 638 else 639 return false; 640 641 qh->segsize = length; 642 643 /* 644 * Ensure the data reaches to main memory before starting 645 * DMA transfer 646 */ 647 wmb(); 648 649 if (!dma->channel_program(channel, pkt_size, mode, 650 urb->transfer_dma + offset, length)) { 651 void __iomem *epio = hw_ep->regs; 652 u16 csr; 653 654 dma->channel_release(channel); 655 hw_ep->tx_channel = NULL; 656 657 csr = musb_readw(epio, MUSB_TXCSR); 658 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 659 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 660 return false; 661 } 662 return true; 663 } 664 665 /* 666 * Program an HDRC endpoint as per the given URB 667 * Context: irqs blocked, controller lock held 668 */ 669 static void musb_ep_program(struct musb *musb, u8 epnum, 670 struct urb *urb, int is_out, 671 u8 *buf, u32 offset, u32 len) 672 { 673 struct dma_controller *dma_controller; 674 struct dma_channel *dma_channel; 675 u8 dma_ok; 676 void __iomem *mbase = musb->mregs; 677 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 678 void __iomem *epio = hw_ep->regs; 679 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 680 u16 packet_sz = qh->maxpacket; 681 u8 use_dma = 1; 682 u16 csr; 683 684 musb_dbg(musb, "%s hw%d urb %p spd%d dev%d ep%d%s " 685 "h_addr%02x h_port%02x bytes %d", 686 is_out ? "-->" : "<--", 687 epnum, urb, urb->dev->speed, 688 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 689 qh->h_addr_reg, qh->h_port_reg, 690 len); 691 692 musb_ep_select(mbase, epnum); 693 694 if (is_out && !len) { 695 use_dma = 0; 696 csr = musb_readw(epio, MUSB_TXCSR); 697 csr &= ~MUSB_TXCSR_DMAENAB; 698 musb_writew(epio, MUSB_TXCSR, csr); 699 hw_ep->tx_channel = NULL; 700 } 701 702 /* candidate for DMA? */ 703 dma_controller = musb->dma_controller; 704 if (use_dma && is_dma_capable() && epnum && dma_controller) { 705 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 706 if (!dma_channel) { 707 dma_channel = dma_controller->channel_alloc( 708 dma_controller, hw_ep, is_out); 709 if (is_out) 710 hw_ep->tx_channel = dma_channel; 711 else 712 hw_ep->rx_channel = dma_channel; 713 } 714 } else 715 dma_channel = NULL; 716 717 /* make sure we clear DMAEnab, autoSet bits from previous run */ 718 719 /* OUT/transmit/EP0 or IN/receive? */ 720 if (is_out) { 721 u16 csr; 722 u16 int_txe; 723 u16 load_count; 724 725 csr = musb_readw(epio, MUSB_TXCSR); 726 727 /* disable interrupt in case we flush */ 728 int_txe = musb->intrtxe; 729 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 730 731 /* general endpoint setup */ 732 if (epnum) { 733 /* flush all old state, set default */ 734 /* 735 * We could be flushing valid 736 * packets in double buffering 737 * case 738 */ 739 if (!hw_ep->tx_double_buffered) 740 musb_h_tx_flush_fifo(hw_ep); 741 742 /* 743 * We must not clear the DMAMODE bit before or in 744 * the same cycle with the DMAENAB bit, so we clear 745 * the latter first... 746 */ 747 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 748 | MUSB_TXCSR_AUTOSET 749 | MUSB_TXCSR_DMAENAB 750 | MUSB_TXCSR_FRCDATATOG 751 | MUSB_TXCSR_H_RXSTALL 752 | MUSB_TXCSR_H_ERROR 753 | MUSB_TXCSR_TXPKTRDY 754 ); 755 csr |= MUSB_TXCSR_MODE; 756 757 if (!hw_ep->tx_double_buffered) 758 csr |= musb->io.set_toggle(qh, is_out, urb); 759 760 musb_writew(epio, MUSB_TXCSR, csr); 761 /* REVISIT may need to clear FLUSHFIFO ... */ 762 csr &= ~MUSB_TXCSR_DMAMODE; 763 musb_writew(epio, MUSB_TXCSR, csr); 764 csr = musb_readw(epio, MUSB_TXCSR); 765 } else { 766 /* endpoint 0: just flush */ 767 musb_h_ep0_flush_fifo(hw_ep); 768 } 769 770 /* target addr and (for multipoint) hub addr/port */ 771 if (musb->is_multipoint) { 772 musb_write_txfunaddr(musb, epnum, qh->addr_reg); 773 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg); 774 musb_write_txhubport(musb, epnum, qh->h_port_reg); 775 /* FIXME if !epnum, do the same for RX ... */ 776 } else 777 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 778 779 /* protocol/endpoint/interval/NAKlimit */ 780 if (epnum) { 781 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 782 if (can_bulk_split(musb, qh->type)) { 783 qh->hb_mult = hw_ep->max_packet_sz_tx 784 / packet_sz; 785 musb_writew(epio, MUSB_TXMAXP, packet_sz 786 | ((qh->hb_mult) - 1) << 11); 787 } else { 788 musb_writew(epio, MUSB_TXMAXP, 789 qh->maxpacket | 790 ((qh->hb_mult - 1) << 11)); 791 } 792 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 793 } else { 794 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 795 if (musb->is_multipoint) 796 musb_writeb(epio, MUSB_TYPE0, 797 qh->type_reg); 798 } 799 800 if (can_bulk_split(musb, qh->type)) 801 load_count = min_t(u32, hw_ep->max_packet_sz_tx, len); 802 else 803 load_count = min_t(u32, packet_sz, len); 804 805 if (dma_channel && musb_tx_dma_program(dma_controller, 806 hw_ep, qh, urb, offset, len)) 807 load_count = 0; 808 809 if (load_count) { 810 /* PIO to load FIFO */ 811 qh->segsize = load_count; 812 if (!buf) { 813 sg_miter_start(&qh->sg_miter, urb->sg, 1, 814 SG_MITER_ATOMIC 815 | SG_MITER_FROM_SG); 816 if (!sg_miter_next(&qh->sg_miter)) { 817 dev_err(musb->controller, 818 "error: sg" 819 "list empty\n"); 820 sg_miter_stop(&qh->sg_miter); 821 goto finish; 822 } 823 buf = qh->sg_miter.addr + urb->sg->offset + 824 urb->actual_length; 825 load_count = min_t(u32, load_count, 826 qh->sg_miter.length); 827 musb_write_fifo(hw_ep, load_count, buf); 828 qh->sg_miter.consumed = load_count; 829 sg_miter_stop(&qh->sg_miter); 830 } else 831 musb_write_fifo(hw_ep, load_count, buf); 832 } 833 finish: 834 /* re-enable interrupt */ 835 musb_writew(mbase, MUSB_INTRTXE, int_txe); 836 837 /* IN/receive */ 838 } else { 839 u16 csr = 0; 840 841 if (hw_ep->rx_reinit) { 842 musb_rx_reinit(musb, qh, epnum); 843 csr |= musb->io.set_toggle(qh, is_out, urb); 844 845 if (qh->type == USB_ENDPOINT_XFER_INT) 846 csr |= MUSB_RXCSR_DISNYET; 847 848 } else { 849 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 850 851 if (csr & (MUSB_RXCSR_RXPKTRDY 852 | MUSB_RXCSR_DMAENAB 853 | MUSB_RXCSR_H_REQPKT)) 854 ERR("broken !rx_reinit, ep%d csr %04x\n", 855 hw_ep->epnum, csr); 856 857 /* scrub any stale state, leaving toggle alone */ 858 csr &= MUSB_RXCSR_DISNYET; 859 } 860 861 /* kick things off */ 862 863 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) { 864 /* Candidate for DMA */ 865 dma_channel->actual_len = 0L; 866 qh->segsize = len; 867 868 /* AUTOREQ is in a DMA register */ 869 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 870 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 871 872 /* 873 * Unless caller treats short RX transfers as 874 * errors, we dare not queue multiple transfers. 875 */ 876 dma_ok = dma_controller->channel_program(dma_channel, 877 packet_sz, !(urb->transfer_flags & 878 URB_SHORT_NOT_OK), 879 urb->transfer_dma + offset, 880 qh->segsize); 881 if (!dma_ok) { 882 dma_controller->channel_release(dma_channel); 883 hw_ep->rx_channel = dma_channel = NULL; 884 } else 885 csr |= MUSB_RXCSR_DMAENAB; 886 } 887 888 csr |= MUSB_RXCSR_H_REQPKT; 889 musb_dbg(musb, "RXCSR%d := %04x", epnum, csr); 890 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 891 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 892 } 893 } 894 895 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to 896 * the end; avoids starvation for other endpoints. 897 */ 898 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, 899 int is_in) 900 { 901 struct dma_channel *dma; 902 struct urb *urb; 903 void __iomem *mbase = musb->mregs; 904 void __iomem *epio = ep->regs; 905 struct musb_qh *cur_qh, *next_qh; 906 u16 rx_csr, tx_csr; 907 u16 toggle; 908 909 musb_ep_select(mbase, ep->epnum); 910 if (is_in) { 911 dma = is_dma_capable() ? ep->rx_channel : NULL; 912 913 /* 914 * Need to stop the transaction by clearing REQPKT first 915 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED 916 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2 917 */ 918 rx_csr = musb_readw(epio, MUSB_RXCSR); 919 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 920 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 921 musb_writew(epio, MUSB_RXCSR, rx_csr); 922 rx_csr &= ~MUSB_RXCSR_DATAERROR; 923 musb_writew(epio, MUSB_RXCSR, rx_csr); 924 925 cur_qh = first_qh(&musb->in_bulk); 926 } else { 927 dma = is_dma_capable() ? ep->tx_channel : NULL; 928 929 /* clear nak timeout bit */ 930 tx_csr = musb_readw(epio, MUSB_TXCSR); 931 tx_csr |= MUSB_TXCSR_H_WZC_BITS; 932 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; 933 musb_writew(epio, MUSB_TXCSR, tx_csr); 934 935 cur_qh = first_qh(&musb->out_bulk); 936 } 937 if (cur_qh) { 938 urb = next_urb(cur_qh); 939 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 940 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 941 musb->dma_controller->channel_abort(dma); 942 urb->actual_length += dma->actual_len; 943 dma->actual_len = 0L; 944 } 945 toggle = musb->io.get_toggle(cur_qh, !is_in); 946 usb_settoggle(urb->dev, cur_qh->epnum, !is_in, toggle ? 1 : 0); 947 948 if (is_in) { 949 /* move cur_qh to end of queue */ 950 list_move_tail(&cur_qh->ring, &musb->in_bulk); 951 952 /* get the next qh from musb->in_bulk */ 953 next_qh = first_qh(&musb->in_bulk); 954 955 /* set rx_reinit and schedule the next qh */ 956 ep->rx_reinit = 1; 957 } else { 958 /* move cur_qh to end of queue */ 959 list_move_tail(&cur_qh->ring, &musb->out_bulk); 960 961 /* get the next qh from musb->out_bulk */ 962 next_qh = first_qh(&musb->out_bulk); 963 964 /* set tx_reinit and schedule the next qh */ 965 ep->tx_reinit = 1; 966 } 967 968 if (next_qh) 969 musb_start_urb(musb, is_in, next_qh); 970 } 971 } 972 973 /* 974 * Service the default endpoint (ep0) as host. 975 * Return true until it's time to start the status stage. 976 */ 977 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 978 { 979 bool more = false; 980 u8 *fifo_dest = NULL; 981 u16 fifo_count = 0; 982 struct musb_hw_ep *hw_ep = musb->control_ep; 983 struct musb_qh *qh = hw_ep->in_qh; 984 struct usb_ctrlrequest *request; 985 986 switch (musb->ep0_stage) { 987 case MUSB_EP0_IN: 988 fifo_dest = urb->transfer_buffer + urb->actual_length; 989 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 990 urb->actual_length); 991 if (fifo_count < len) 992 urb->status = -EOVERFLOW; 993 994 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 995 996 urb->actual_length += fifo_count; 997 if (len < qh->maxpacket) { 998 /* always terminate on short read; it's 999 * rarely reported as an error. 1000 */ 1001 } else if (urb->actual_length < 1002 urb->transfer_buffer_length) 1003 more = true; 1004 break; 1005 case MUSB_EP0_START: 1006 request = (struct usb_ctrlrequest *) urb->setup_packet; 1007 1008 if (!request->wLength) { 1009 musb_dbg(musb, "start no-DATA"); 1010 break; 1011 } else if (request->bRequestType & USB_DIR_IN) { 1012 musb_dbg(musb, "start IN-DATA"); 1013 musb->ep0_stage = MUSB_EP0_IN; 1014 more = true; 1015 break; 1016 } else { 1017 musb_dbg(musb, "start OUT-DATA"); 1018 musb->ep0_stage = MUSB_EP0_OUT; 1019 more = true; 1020 } 1021 fallthrough; 1022 case MUSB_EP0_OUT: 1023 fifo_count = min_t(size_t, qh->maxpacket, 1024 urb->transfer_buffer_length - 1025 urb->actual_length); 1026 if (fifo_count) { 1027 fifo_dest = (u8 *) (urb->transfer_buffer 1028 + urb->actual_length); 1029 musb_dbg(musb, "Sending %d byte%s to ep0 fifo %p", 1030 fifo_count, 1031 (fifo_count == 1) ? "" : "s", 1032 fifo_dest); 1033 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 1034 1035 urb->actual_length += fifo_count; 1036 more = true; 1037 } 1038 break; 1039 default: 1040 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 1041 break; 1042 } 1043 1044 return more; 1045 } 1046 1047 /* 1048 * Handle default endpoint interrupt as host. Only called in IRQ time 1049 * from musb_interrupt(). 1050 * 1051 * called with controller irqlocked 1052 */ 1053 irqreturn_t musb_h_ep0_irq(struct musb *musb) 1054 { 1055 struct urb *urb; 1056 u16 csr, len; 1057 int status = 0; 1058 void __iomem *mbase = musb->mregs; 1059 struct musb_hw_ep *hw_ep = musb->control_ep; 1060 void __iomem *epio = hw_ep->regs; 1061 struct musb_qh *qh = hw_ep->in_qh; 1062 bool complete = false; 1063 irqreturn_t retval = IRQ_NONE; 1064 1065 /* ep0 only has one queue, "in" */ 1066 urb = next_urb(qh); 1067 1068 musb_ep_select(mbase, 0); 1069 csr = musb_readw(epio, MUSB_CSR0); 1070 len = (csr & MUSB_CSR0_RXPKTRDY) 1071 ? musb_readb(epio, MUSB_COUNT0) 1072 : 0; 1073 1074 musb_dbg(musb, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d", 1075 csr, qh, len, urb, musb->ep0_stage); 1076 1077 /* if we just did status stage, we are done */ 1078 if (MUSB_EP0_STATUS == musb->ep0_stage) { 1079 retval = IRQ_HANDLED; 1080 complete = true; 1081 } 1082 1083 /* prepare status */ 1084 if (csr & MUSB_CSR0_H_RXSTALL) { 1085 musb_dbg(musb, "STALLING ENDPOINT"); 1086 status = -EPIPE; 1087 1088 } else if (csr & MUSB_CSR0_H_ERROR) { 1089 musb_dbg(musb, "no response, csr0 %04x", csr); 1090 status = -EPROTO; 1091 1092 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1093 musb_dbg(musb, "control NAK timeout"); 1094 1095 /* NOTE: this code path would be a good place to PAUSE a 1096 * control transfer, if another one is queued, so that 1097 * ep0 is more likely to stay busy. That's already done 1098 * for bulk RX transfers. 1099 * 1100 * if (qh->ring.next != &musb->control), then 1101 * we have a candidate... NAKing is *NOT* an error 1102 */ 1103 musb_writew(epio, MUSB_CSR0, 0); 1104 retval = IRQ_HANDLED; 1105 } 1106 1107 if (status) { 1108 musb_dbg(musb, "aborting"); 1109 retval = IRQ_HANDLED; 1110 if (urb) 1111 urb->status = status; 1112 complete = true; 1113 1114 /* use the proper sequence to abort the transfer */ 1115 if (csr & MUSB_CSR0_H_REQPKT) { 1116 csr &= ~MUSB_CSR0_H_REQPKT; 1117 musb_writew(epio, MUSB_CSR0, csr); 1118 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1119 musb_writew(epio, MUSB_CSR0, csr); 1120 } else { 1121 musb_h_ep0_flush_fifo(hw_ep); 1122 } 1123 1124 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1125 1126 /* clear it */ 1127 musb_writew(epio, MUSB_CSR0, 0); 1128 } 1129 1130 if (unlikely(!urb)) { 1131 /* stop endpoint since we have no place for its data, this 1132 * SHOULD NEVER HAPPEN! */ 1133 ERR("no URB for end 0\n"); 1134 1135 musb_h_ep0_flush_fifo(hw_ep); 1136 goto done; 1137 } 1138 1139 if (!complete) { 1140 /* call common logic and prepare response */ 1141 if (musb_h_ep0_continue(musb, len, urb)) { 1142 /* more packets required */ 1143 csr = (MUSB_EP0_IN == musb->ep0_stage) 1144 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1145 } else { 1146 /* data transfer complete; perform status phase */ 1147 if (usb_pipeout(urb->pipe) 1148 || !urb->transfer_buffer_length) 1149 csr = MUSB_CSR0_H_STATUSPKT 1150 | MUSB_CSR0_H_REQPKT; 1151 else 1152 csr = MUSB_CSR0_H_STATUSPKT 1153 | MUSB_CSR0_TXPKTRDY; 1154 1155 /* disable ping token in status phase */ 1156 csr |= MUSB_CSR0_H_DIS_PING; 1157 1158 /* flag status stage */ 1159 musb->ep0_stage = MUSB_EP0_STATUS; 1160 1161 musb_dbg(musb, "ep0 STATUS, csr %04x", csr); 1162 1163 } 1164 musb_writew(epio, MUSB_CSR0, csr); 1165 retval = IRQ_HANDLED; 1166 } else 1167 musb->ep0_stage = MUSB_EP0_IDLE; 1168 1169 /* call completion handler if done */ 1170 if (complete) 1171 musb_advance_schedule(musb, urb, hw_ep, 1); 1172 done: 1173 return retval; 1174 } 1175 1176 1177 #ifdef CONFIG_USB_INVENTRA_DMA 1178 1179 /* Host side TX (OUT) using Mentor DMA works as follows: 1180 submit_urb -> 1181 - if queue was empty, Program Endpoint 1182 - ... which starts DMA to fifo in mode 1 or 0 1183 1184 DMA Isr (transfer complete) -> TxAvail() 1185 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1186 only in musb_cleanup_urb) 1187 - TxPktRdy has to be set in mode 0 or for 1188 short packets in mode 1. 1189 */ 1190 1191 #endif 1192 1193 /* Service a Tx-Available or dma completion irq for the endpoint */ 1194 void musb_host_tx(struct musb *musb, u8 epnum) 1195 { 1196 int pipe; 1197 bool done = false; 1198 u16 tx_csr; 1199 size_t length = 0; 1200 size_t offset = 0; 1201 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1202 void __iomem *epio = hw_ep->regs; 1203 struct musb_qh *qh = hw_ep->out_qh; 1204 struct urb *urb = next_urb(qh); 1205 u32 status = 0; 1206 void __iomem *mbase = musb->mregs; 1207 struct dma_channel *dma; 1208 bool transfer_pending = false; 1209 1210 musb_ep_select(mbase, epnum); 1211 tx_csr = musb_readw(epio, MUSB_TXCSR); 1212 1213 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1214 if (!urb) { 1215 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); 1216 return; 1217 } 1218 1219 pipe = urb->pipe; 1220 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1221 trace_musb_urb_tx(musb, urb); 1222 musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr, 1223 dma ? ", dma" : ""); 1224 1225 /* check for errors */ 1226 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1227 /* dma was disabled, fifo flushed */ 1228 musb_dbg(musb, "TX end %d stall", epnum); 1229 1230 /* stall; record URB status */ 1231 status = -EPIPE; 1232 1233 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1234 /* (NON-ISO) dma was disabled, fifo flushed */ 1235 musb_dbg(musb, "TX 3strikes on ep=%d", epnum); 1236 1237 status = -ETIMEDOUT; 1238 1239 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1240 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 1241 && !list_is_singular(&musb->out_bulk)) { 1242 musb_dbg(musb, "NAK timeout on TX%d ep", epnum); 1243 musb_bulk_nak_timeout(musb, hw_ep, 0); 1244 } else { 1245 musb_dbg(musb, "TX ep%d device not responding", epnum); 1246 /* NOTE: this code path would be a good place to PAUSE a 1247 * transfer, if there's some other (nonperiodic) tx urb 1248 * that could use this fifo. (dma complicates it...) 1249 * That's already done for bulk RX transfers. 1250 * 1251 * if (bulk && qh->ring.next != &musb->out_bulk), then 1252 * we have a candidate... NAKing is *NOT* an error 1253 */ 1254 musb_ep_select(mbase, epnum); 1255 musb_writew(epio, MUSB_TXCSR, 1256 MUSB_TXCSR_H_WZC_BITS 1257 | MUSB_TXCSR_TXPKTRDY); 1258 } 1259 return; 1260 } 1261 1262 done: 1263 if (status) { 1264 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1265 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1266 musb->dma_controller->channel_abort(dma); 1267 } 1268 1269 /* do the proper sequence to abort the transfer in the 1270 * usb core; the dma engine should already be stopped. 1271 */ 1272 musb_h_tx_flush_fifo(hw_ep); 1273 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1274 | MUSB_TXCSR_DMAENAB 1275 | MUSB_TXCSR_H_ERROR 1276 | MUSB_TXCSR_H_RXSTALL 1277 | MUSB_TXCSR_H_NAKTIMEOUT 1278 ); 1279 1280 musb_ep_select(mbase, epnum); 1281 musb_writew(epio, MUSB_TXCSR, tx_csr); 1282 /* REVISIT may need to clear FLUSHFIFO ... */ 1283 musb_writew(epio, MUSB_TXCSR, tx_csr); 1284 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1285 1286 done = true; 1287 } 1288 1289 /* second cppi case */ 1290 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1291 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); 1292 return; 1293 } 1294 1295 if (is_dma_capable() && dma && !status) { 1296 /* 1297 * DMA has completed. But if we're using DMA mode 1 (multi 1298 * packet DMA), we need a terminal TXPKTRDY interrupt before 1299 * we can consider this transfer completed, lest we trash 1300 * its last packet when writing the next URB's data. So we 1301 * switch back to mode 0 to get that interrupt; we'll come 1302 * back here once it happens. 1303 */ 1304 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1305 /* 1306 * We shouldn't clear DMAMODE with DMAENAB set; so 1307 * clear them in a safe order. That should be OK 1308 * once TXPKTRDY has been set (and I've never seen 1309 * it being 0 at this moment -- DMA interrupt latency 1310 * is significant) but if it hasn't been then we have 1311 * no choice but to stop being polite and ignore the 1312 * programmer's guide... :-) 1313 * 1314 * Note that we must write TXCSR with TXPKTRDY cleared 1315 * in order not to re-trigger the packet send (this bit 1316 * can't be cleared by CPU), and there's another caveat: 1317 * TXPKTRDY may be set shortly and then cleared in the 1318 * double-buffered FIFO mode, so we do an extra TXCSR 1319 * read for debouncing... 1320 */ 1321 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1322 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1323 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1324 MUSB_TXCSR_TXPKTRDY); 1325 musb_writew(epio, MUSB_TXCSR, 1326 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1327 } 1328 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1329 MUSB_TXCSR_TXPKTRDY); 1330 musb_writew(epio, MUSB_TXCSR, 1331 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1332 1333 /* 1334 * There is no guarantee that we'll get an interrupt 1335 * after clearing DMAMODE as we might have done this 1336 * too late (after TXPKTRDY was cleared by controller). 1337 * Re-read TXCSR as we have spoiled its previous value. 1338 */ 1339 tx_csr = musb_readw(epio, MUSB_TXCSR); 1340 } 1341 1342 /* 1343 * We may get here from a DMA completion or TXPKTRDY interrupt. 1344 * In any case, we must check the FIFO status here and bail out 1345 * only if the FIFO still has data -- that should prevent the 1346 * "missed" TXPKTRDY interrupts and deal with double-buffered 1347 * FIFO mode too... 1348 */ 1349 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1350 musb_dbg(musb, 1351 "DMA complete but FIFO not empty, CSR %04x", 1352 tx_csr); 1353 return; 1354 } 1355 } 1356 1357 if (!status || dma || usb_pipeisoc(pipe)) { 1358 if (dma) 1359 length = dma->actual_len; 1360 else 1361 length = qh->segsize; 1362 qh->offset += length; 1363 1364 if (usb_pipeisoc(pipe)) { 1365 struct usb_iso_packet_descriptor *d; 1366 1367 d = urb->iso_frame_desc + qh->iso_idx; 1368 d->actual_length = length; 1369 d->status = status; 1370 if (++qh->iso_idx >= urb->number_of_packets) { 1371 done = true; 1372 } else { 1373 d++; 1374 offset = d->offset; 1375 length = d->length; 1376 } 1377 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1378 done = true; 1379 } else { 1380 /* see if we need to send more data, or ZLP */ 1381 if (qh->segsize < qh->maxpacket) 1382 done = true; 1383 else if (qh->offset == urb->transfer_buffer_length 1384 && !(urb->transfer_flags 1385 & URB_ZERO_PACKET)) 1386 done = true; 1387 if (!done) { 1388 offset = qh->offset; 1389 length = urb->transfer_buffer_length - offset; 1390 transfer_pending = true; 1391 } 1392 } 1393 } 1394 1395 /* urb->status != -EINPROGRESS means request has been faulted, 1396 * so we must abort this transfer after cleanup 1397 */ 1398 if (urb->status != -EINPROGRESS) { 1399 done = true; 1400 if (status == 0) 1401 status = urb->status; 1402 } 1403 1404 if (done) { 1405 /* set status */ 1406 urb->status = status; 1407 urb->actual_length = qh->offset; 1408 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1409 return; 1410 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1411 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1412 offset, length)) { 1413 if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) 1414 musb_h_tx_dma_start(hw_ep); 1415 return; 1416 } 1417 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1418 musb_dbg(musb, "not complete, but DMA enabled?"); 1419 return; 1420 } 1421 1422 /* 1423 * PIO: start next packet in this URB. 1424 * 1425 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1426 * (and presumably, FIFO is not half-full) we should write *two* 1427 * packets before updating TXCSR; other docs disagree... 1428 */ 1429 if (length > qh->maxpacket) 1430 length = qh->maxpacket; 1431 /* Unmap the buffer so that CPU can use it */ 1432 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 1433 1434 /* 1435 * We need to map sg if the transfer_buffer is 1436 * NULL. 1437 */ 1438 if (!urb->transfer_buffer) { 1439 /* sg_miter_start is already done in musb_ep_program */ 1440 if (!sg_miter_next(&qh->sg_miter)) { 1441 dev_err(musb->controller, "error: sg list empty\n"); 1442 sg_miter_stop(&qh->sg_miter); 1443 status = -EINVAL; 1444 goto done; 1445 } 1446 length = min_t(u32, length, qh->sg_miter.length); 1447 musb_write_fifo(hw_ep, length, qh->sg_miter.addr); 1448 qh->sg_miter.consumed = length; 1449 sg_miter_stop(&qh->sg_miter); 1450 } else { 1451 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1452 } 1453 1454 qh->segsize = length; 1455 1456 musb_ep_select(mbase, epnum); 1457 musb_writew(epio, MUSB_TXCSR, 1458 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1459 } 1460 1461 #ifdef CONFIG_USB_TI_CPPI41_DMA 1462 /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */ 1463 static int musb_rx_dma_iso_cppi41(struct dma_controller *dma, 1464 struct musb_hw_ep *hw_ep, 1465 struct musb_qh *qh, 1466 struct urb *urb, 1467 size_t len) 1468 { 1469 struct dma_channel *channel = hw_ep->rx_channel; 1470 void __iomem *epio = hw_ep->regs; 1471 dma_addr_t *buf; 1472 u32 length; 1473 u16 val; 1474 1475 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset + 1476 (u32)urb->transfer_dma; 1477 1478 length = urb->iso_frame_desc[qh->iso_idx].length; 1479 1480 val = musb_readw(epio, MUSB_RXCSR); 1481 val |= MUSB_RXCSR_DMAENAB; 1482 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1483 1484 return dma->channel_program(channel, qh->maxpacket, 0, 1485 (u32)buf, length); 1486 } 1487 #else 1488 static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma, 1489 struct musb_hw_ep *hw_ep, 1490 struct musb_qh *qh, 1491 struct urb *urb, 1492 size_t len) 1493 { 1494 return false; 1495 } 1496 #endif 1497 1498 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \ 1499 defined(CONFIG_USB_TI_CPPI41_DMA) 1500 /* Host side RX (IN) using Mentor DMA works as follows: 1501 submit_urb -> 1502 - if queue was empty, ProgramEndpoint 1503 - first IN token is sent out (by setting ReqPkt) 1504 LinuxIsr -> RxReady() 1505 /\ => first packet is received 1506 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1507 | -> DMA Isr (transfer complete) -> RxReady() 1508 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1509 | - if urb not complete, send next IN token (ReqPkt) 1510 | | else complete urb. 1511 | | 1512 --------------------------- 1513 * 1514 * Nuances of mode 1: 1515 * For short packets, no ack (+RxPktRdy) is sent automatically 1516 * (even if AutoClear is ON) 1517 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1518 * automatically => major problem, as collecting the next packet becomes 1519 * difficult. Hence mode 1 is not used. 1520 * 1521 * REVISIT 1522 * All we care about at this driver level is that 1523 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1524 * (b) termination conditions are: short RX, or buffer full; 1525 * (c) fault modes include 1526 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1527 * (and that endpoint's dma queue stops immediately) 1528 * - overflow (full, PLUS more bytes in the terminal packet) 1529 * 1530 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1531 * thus be a great candidate for using mode 1 ... for all but the 1532 * last packet of one URB's transfer. 1533 */ 1534 static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, 1535 struct musb_hw_ep *hw_ep, 1536 struct musb_qh *qh, 1537 struct urb *urb, 1538 size_t len) 1539 { 1540 struct dma_channel *channel = hw_ep->rx_channel; 1541 void __iomem *epio = hw_ep->regs; 1542 u16 val; 1543 int pipe; 1544 bool done; 1545 1546 pipe = urb->pipe; 1547 1548 if (usb_pipeisoc(pipe)) { 1549 struct usb_iso_packet_descriptor *d; 1550 1551 d = urb->iso_frame_desc + qh->iso_idx; 1552 d->actual_length = len; 1553 1554 /* even if there was an error, we did the dma 1555 * for iso_frame_desc->length 1556 */ 1557 if (d->status != -EILSEQ && d->status != -EOVERFLOW) 1558 d->status = 0; 1559 1560 if (++qh->iso_idx >= urb->number_of_packets) { 1561 done = true; 1562 } else { 1563 /* REVISIT: Why ignore return value here? */ 1564 if (musb_dma_cppi41(hw_ep->musb)) 1565 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh, 1566 urb, len); 1567 done = false; 1568 } 1569 1570 } else { 1571 /* done if urb buffer is full or short packet is recd */ 1572 done = (urb->actual_length + len >= 1573 urb->transfer_buffer_length 1574 || channel->actual_len < qh->maxpacket 1575 || channel->rx_packet_done); 1576 } 1577 1578 /* send IN token for next packet, without AUTOREQ */ 1579 if (!done) { 1580 val = musb_readw(epio, MUSB_RXCSR); 1581 val |= MUSB_RXCSR_H_REQPKT; 1582 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); 1583 } 1584 1585 return done; 1586 } 1587 1588 /* Disadvantage of using mode 1: 1589 * It's basically usable only for mass storage class; essentially all 1590 * other protocols also terminate transfers on short packets. 1591 * 1592 * Details: 1593 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1594 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1595 * to use the extra IN token to grab the last packet using mode 0, then 1596 * the problem is that you cannot be sure when the device will send the 1597 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1598 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1599 * transfer, while sometimes it is recd just a little late so that if you 1600 * try to configure for mode 0 soon after the mode 1 transfer is 1601 * completed, you will find rxcount 0. Okay, so you might think why not 1602 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1603 */ 1604 static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, 1605 struct musb_hw_ep *hw_ep, 1606 struct musb_qh *qh, 1607 struct urb *urb, 1608 size_t len, 1609 u8 iso_err) 1610 { 1611 struct musb *musb = hw_ep->musb; 1612 void __iomem *epio = hw_ep->regs; 1613 struct dma_channel *channel = hw_ep->rx_channel; 1614 u16 rx_count, val; 1615 int length, pipe, done; 1616 dma_addr_t buf; 1617 1618 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1619 pipe = urb->pipe; 1620 1621 if (usb_pipeisoc(pipe)) { 1622 int d_status = 0; 1623 struct usb_iso_packet_descriptor *d; 1624 1625 d = urb->iso_frame_desc + qh->iso_idx; 1626 1627 if (iso_err) { 1628 d_status = -EILSEQ; 1629 urb->error_count++; 1630 } 1631 if (rx_count > d->length) { 1632 if (d_status == 0) { 1633 d_status = -EOVERFLOW; 1634 urb->error_count++; 1635 } 1636 musb_dbg(musb, "** OVERFLOW %d into %d", 1637 rx_count, d->length); 1638 1639 length = d->length; 1640 } else 1641 length = rx_count; 1642 d->status = d_status; 1643 buf = urb->transfer_dma + d->offset; 1644 } else { 1645 length = rx_count; 1646 buf = urb->transfer_dma + urb->actual_length; 1647 } 1648 1649 channel->desired_mode = 0; 1650 #ifdef USE_MODE1 1651 /* because of the issue below, mode 1 will 1652 * only rarely behave with correct semantics. 1653 */ 1654 if ((urb->transfer_flags & URB_SHORT_NOT_OK) 1655 && (urb->transfer_buffer_length - urb->actual_length) 1656 > qh->maxpacket) 1657 channel->desired_mode = 1; 1658 if (rx_count < hw_ep->max_packet_sz_rx) { 1659 length = rx_count; 1660 channel->desired_mode = 0; 1661 } else { 1662 length = urb->transfer_buffer_length; 1663 } 1664 #endif 1665 1666 /* See comments above on disadvantages of using mode 1 */ 1667 val = musb_readw(epio, MUSB_RXCSR); 1668 val &= ~MUSB_RXCSR_H_REQPKT; 1669 1670 if (channel->desired_mode == 0) 1671 val &= ~MUSB_RXCSR_H_AUTOREQ; 1672 else 1673 val |= MUSB_RXCSR_H_AUTOREQ; 1674 val |= MUSB_RXCSR_DMAENAB; 1675 1676 /* autoclear shouldn't be set in high bandwidth */ 1677 if (qh->hb_mult == 1) 1678 val |= MUSB_RXCSR_AUTOCLEAR; 1679 1680 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); 1681 1682 /* REVISIT if when actual_length != 0, 1683 * transfer_buffer_length needs to be 1684 * adjusted first... 1685 */ 1686 done = dma->channel_program(channel, qh->maxpacket, 1687 channel->desired_mode, 1688 buf, length); 1689 1690 if (!done) { 1691 dma->channel_release(channel); 1692 hw_ep->rx_channel = NULL; 1693 channel = NULL; 1694 val = musb_readw(epio, MUSB_RXCSR); 1695 val &= ~(MUSB_RXCSR_DMAENAB 1696 | MUSB_RXCSR_H_AUTOREQ 1697 | MUSB_RXCSR_AUTOCLEAR); 1698 musb_writew(epio, MUSB_RXCSR, val); 1699 } 1700 1701 return done; 1702 } 1703 #else 1704 static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, 1705 struct musb_hw_ep *hw_ep, 1706 struct musb_qh *qh, 1707 struct urb *urb, 1708 size_t len) 1709 { 1710 return false; 1711 } 1712 1713 static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, 1714 struct musb_hw_ep *hw_ep, 1715 struct musb_qh *qh, 1716 struct urb *urb, 1717 size_t len, 1718 u8 iso_err) 1719 { 1720 return false; 1721 } 1722 #endif 1723 1724 /* 1725 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1726 * and high-bandwidth IN transfer cases. 1727 */ 1728 void musb_host_rx(struct musb *musb, u8 epnum) 1729 { 1730 struct urb *urb; 1731 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1732 struct dma_controller *c = musb->dma_controller; 1733 void __iomem *epio = hw_ep->regs; 1734 struct musb_qh *qh = hw_ep->in_qh; 1735 size_t xfer_len; 1736 void __iomem *mbase = musb->mregs; 1737 u16 rx_csr, val; 1738 bool iso_err = false; 1739 bool done = false; 1740 u32 status; 1741 struct dma_channel *dma; 1742 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; 1743 1744 musb_ep_select(mbase, epnum); 1745 1746 urb = next_urb(qh); 1747 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1748 status = 0; 1749 xfer_len = 0; 1750 1751 rx_csr = musb_readw(epio, MUSB_RXCSR); 1752 val = rx_csr; 1753 1754 if (unlikely(!urb)) { 1755 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1756 * usbtest #11 (unlinks) triggers it regularly, sometimes 1757 * with fifo full. (Only with DMA??) 1758 */ 1759 musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d", 1760 epnum, val, musb_readw(epio, MUSB_RXCOUNT)); 1761 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1762 return; 1763 } 1764 1765 trace_musb_urb_rx(musb, urb); 1766 1767 /* check for errors, concurrent stall & unlink is not really 1768 * handled yet! */ 1769 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1770 musb_dbg(musb, "RX end %d STALL", epnum); 1771 1772 /* stall; record URB status */ 1773 status = -EPIPE; 1774 1775 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1776 dev_err(musb->controller, "ep%d RX three-strikes error", epnum); 1777 1778 /* 1779 * The three-strikes error could only happen when the USB 1780 * device is not accessible, for example detached or powered 1781 * off. So return the fatal error -ESHUTDOWN so hopefully the 1782 * USB device drivers won't immediately resubmit the same URB. 1783 */ 1784 status = -ESHUTDOWN; 1785 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1786 1787 rx_csr &= ~MUSB_RXCSR_H_ERROR; 1788 musb_writew(epio, MUSB_RXCSR, rx_csr); 1789 1790 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1791 1792 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1793 musb_dbg(musb, "RX end %d NAK timeout", epnum); 1794 1795 /* NOTE: NAKing is *NOT* an error, so we want to 1796 * continue. Except ... if there's a request for 1797 * another QH, use that instead of starving it. 1798 * 1799 * Devices like Ethernet and serial adapters keep 1800 * reads posted at all times, which will starve 1801 * other devices without this logic. 1802 */ 1803 if (usb_pipebulk(urb->pipe) 1804 && qh->mux == 1 1805 && !list_is_singular(&musb->in_bulk)) { 1806 musb_bulk_nak_timeout(musb, hw_ep, 1); 1807 return; 1808 } 1809 musb_ep_select(mbase, epnum); 1810 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1811 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1812 musb_writew(epio, MUSB_RXCSR, rx_csr); 1813 1814 goto finish; 1815 } else { 1816 musb_dbg(musb, "RX end %d ISO data error", epnum); 1817 /* packet error reported later */ 1818 iso_err = true; 1819 } 1820 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1821 musb_dbg(musb, "end %d high bandwidth incomplete ISO packet RX", 1822 epnum); 1823 status = -EPROTO; 1824 } 1825 1826 /* faults abort the transfer */ 1827 if (status) { 1828 /* clean up dma and collect transfer count */ 1829 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1830 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1831 musb->dma_controller->channel_abort(dma); 1832 xfer_len = dma->actual_len; 1833 } 1834 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1835 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1836 done = true; 1837 goto finish; 1838 } 1839 1840 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1841 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1842 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1843 goto finish; 1844 } 1845 1846 /* thorough shutdown for now ... given more precise fault handling 1847 * and better queueing support, we might keep a DMA pipeline going 1848 * while processing this irq for earlier completions. 1849 */ 1850 1851 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1852 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) && 1853 (rx_csr & MUSB_RXCSR_H_REQPKT)) { 1854 /* REVISIT this happened for a while on some short reads... 1855 * the cleanup still needs investigation... looks bad... 1856 * and also duplicates dma cleanup code above ... plus, 1857 * shouldn't this be the "half full" double buffer case? 1858 */ 1859 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1860 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1861 musb->dma_controller->channel_abort(dma); 1862 xfer_len = dma->actual_len; 1863 done = true; 1864 } 1865 1866 musb_dbg(musb, "RXCSR%d %04x, reqpkt, len %zu%s", epnum, rx_csr, 1867 xfer_len, dma ? ", dma" : ""); 1868 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1869 1870 musb_ep_select(mbase, epnum); 1871 musb_writew(epio, MUSB_RXCSR, 1872 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1873 } 1874 1875 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1876 xfer_len = dma->actual_len; 1877 1878 val &= ~(MUSB_RXCSR_DMAENAB 1879 | MUSB_RXCSR_H_AUTOREQ 1880 | MUSB_RXCSR_AUTOCLEAR 1881 | MUSB_RXCSR_RXPKTRDY); 1882 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1883 1884 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) || 1885 musb_dma_cppi41(musb)) { 1886 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len); 1887 musb_dbg(hw_ep->musb, 1888 "ep %d dma %s, rxcsr %04x, rxcount %d", 1889 epnum, done ? "off" : "reset", 1890 musb_readw(epio, MUSB_RXCSR), 1891 musb_readw(epio, MUSB_RXCOUNT)); 1892 } else { 1893 done = true; 1894 } 1895 1896 } else if (urb->status == -EINPROGRESS) { 1897 /* if no errors, be sure a packet is ready for unloading */ 1898 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1899 status = -EPROTO; 1900 ERR("Rx interrupt with no errors or packet!\n"); 1901 1902 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1903 1904 /* SCRUB (RX) */ 1905 /* do the proper sequence to abort the transfer */ 1906 musb_ep_select(mbase, epnum); 1907 val &= ~MUSB_RXCSR_H_REQPKT; 1908 musb_writew(epio, MUSB_RXCSR, val); 1909 goto finish; 1910 } 1911 1912 /* we are expecting IN packets */ 1913 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) || 1914 musb_dma_cppi41(musb)) && dma) { 1915 musb_dbg(hw_ep->musb, 1916 "RX%d count %d, buffer 0x%llx len %d/%d", 1917 epnum, musb_readw(epio, MUSB_RXCOUNT), 1918 (unsigned long long) urb->transfer_dma 1919 + urb->actual_length, 1920 qh->offset, 1921 urb->transfer_buffer_length); 1922 1923 if (musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, urb, 1924 xfer_len, iso_err)) 1925 goto finish; 1926 else 1927 dev_err(musb->controller, "error: rx_dma failed\n"); 1928 } 1929 1930 if (!dma) { 1931 unsigned int received_len; 1932 1933 /* Unmap the buffer so that CPU can use it */ 1934 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 1935 1936 /* 1937 * We need to map sg if the transfer_buffer is 1938 * NULL. 1939 */ 1940 if (!urb->transfer_buffer) { 1941 qh->use_sg = true; 1942 sg_miter_start(&qh->sg_miter, urb->sg, 1, 1943 sg_flags); 1944 } 1945 1946 if (qh->use_sg) { 1947 if (!sg_miter_next(&qh->sg_miter)) { 1948 dev_err(musb->controller, "error: sg list empty\n"); 1949 sg_miter_stop(&qh->sg_miter); 1950 status = -EINVAL; 1951 done = true; 1952 goto finish; 1953 } 1954 urb->transfer_buffer = qh->sg_miter.addr; 1955 received_len = urb->actual_length; 1956 qh->offset = 0x0; 1957 done = musb_host_packet_rx(musb, urb, epnum, 1958 iso_err); 1959 /* Calculate the number of bytes received */ 1960 received_len = urb->actual_length - 1961 received_len; 1962 qh->sg_miter.consumed = received_len; 1963 sg_miter_stop(&qh->sg_miter); 1964 } else { 1965 done = musb_host_packet_rx(musb, urb, 1966 epnum, iso_err); 1967 } 1968 musb_dbg(musb, "read %spacket", done ? "last " : ""); 1969 } 1970 } 1971 1972 finish: 1973 urb->actual_length += xfer_len; 1974 qh->offset += xfer_len; 1975 if (done) { 1976 if (qh->use_sg) { 1977 qh->use_sg = false; 1978 urb->transfer_buffer = NULL; 1979 } 1980 1981 if (urb->status == -EINPROGRESS) 1982 urb->status = status; 1983 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1984 } 1985 } 1986 1987 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1988 * the software schedule associates multiple such nodes with a given 1989 * host side hardware endpoint + direction; scheduling may activate 1990 * that hardware endpoint. 1991 */ 1992 static int musb_schedule( 1993 struct musb *musb, 1994 struct musb_qh *qh, 1995 int is_in) 1996 { 1997 int idle = 0; 1998 int best_diff; 1999 int best_end, epnum; 2000 struct musb_hw_ep *hw_ep = NULL; 2001 struct list_head *head = NULL; 2002 u8 toggle; 2003 u8 txtype; 2004 struct urb *urb = next_urb(qh); 2005 2006 /* use fixed hardware for control and bulk */ 2007 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 2008 head = &musb->control; 2009 hw_ep = musb->control_ep; 2010 goto success; 2011 } 2012 2013 /* else, periodic transfers get muxed to other endpoints */ 2014 2015 /* 2016 * We know this qh hasn't been scheduled, so all we need to do 2017 * is choose which hardware endpoint to put it on ... 2018 * 2019 * REVISIT what we really want here is a regular schedule tree 2020 * like e.g. OHCI uses. 2021 */ 2022 best_diff = 4096; 2023 best_end = -1; 2024 2025 for (epnum = 1, hw_ep = musb->endpoints + 1; 2026 epnum < musb->nr_endpoints; 2027 epnum++, hw_ep++) { 2028 int diff; 2029 2030 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 2031 continue; 2032 2033 if (hw_ep == musb->bulk_ep) 2034 continue; 2035 2036 if (is_in) 2037 diff = hw_ep->max_packet_sz_rx; 2038 else 2039 diff = hw_ep->max_packet_sz_tx; 2040 diff -= (qh->maxpacket * qh->hb_mult); 2041 2042 if (diff >= 0 && best_diff > diff) { 2043 2044 /* 2045 * Mentor controller has a bug in that if we schedule 2046 * a BULK Tx transfer on an endpoint that had earlier 2047 * handled ISOC then the BULK transfer has to start on 2048 * a zero toggle. If the BULK transfer starts on a 1 2049 * toggle then this transfer will fail as the mentor 2050 * controller starts the Bulk transfer on a 0 toggle 2051 * irrespective of the programming of the toggle bits 2052 * in the TXCSR register. Check for this condition 2053 * while allocating the EP for a Tx Bulk transfer. If 2054 * so skip this EP. 2055 */ 2056 hw_ep = musb->endpoints + epnum; 2057 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 2058 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 2059 >> 4) & 0x3; 2060 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 2061 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 2062 continue; 2063 2064 best_diff = diff; 2065 best_end = epnum; 2066 } 2067 } 2068 /* use bulk reserved ep1 if no other ep is free */ 2069 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 2070 hw_ep = musb->bulk_ep; 2071 if (is_in) 2072 head = &musb->in_bulk; 2073 else 2074 head = &musb->out_bulk; 2075 2076 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are 2077 * multiplexed. This scheme does not work in high speed to full 2078 * speed scenario as NAK interrupts are not coming from a 2079 * full speed device connected to a high speed device. 2080 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 2081 * 4 (8 frame or 8ms) for FS device. 2082 */ 2083 if (qh->dev) 2084 qh->intv_reg = 2085 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 2086 goto success; 2087 } else if (best_end < 0) { 2088 dev_err(musb->controller, 2089 "%s hwep alloc failed for %dx%d\n", 2090 musb_ep_xfertype_string(qh->type), 2091 qh->hb_mult, qh->maxpacket); 2092 return -ENOSPC; 2093 } 2094 2095 idle = 1; 2096 qh->mux = 0; 2097 hw_ep = musb->endpoints + best_end; 2098 musb_dbg(musb, "qh %p periodic slot %d", qh, best_end); 2099 success: 2100 if (head) { 2101 idle = list_empty(head); 2102 list_add_tail(&qh->ring, head); 2103 qh->mux = 1; 2104 } 2105 qh->hw_ep = hw_ep; 2106 qh->hep->hcpriv = qh; 2107 if (idle) 2108 musb_start_urb(musb, is_in, qh); 2109 return 0; 2110 } 2111 2112 static int musb_urb_enqueue( 2113 struct usb_hcd *hcd, 2114 struct urb *urb, 2115 gfp_t mem_flags) 2116 { 2117 unsigned long flags; 2118 struct musb *musb = hcd_to_musb(hcd); 2119 struct usb_host_endpoint *hep = urb->ep; 2120 struct musb_qh *qh; 2121 struct usb_endpoint_descriptor *epd = &hep->desc; 2122 int ret; 2123 unsigned type_reg; 2124 unsigned interval; 2125 2126 /* host role must be active */ 2127 if (!is_host_active(musb) || !musb->is_active) 2128 return -ENODEV; 2129 2130 trace_musb_urb_enq(musb, urb); 2131 2132 spin_lock_irqsave(&musb->lock, flags); 2133 ret = usb_hcd_link_urb_to_ep(hcd, urb); 2134 qh = ret ? NULL : hep->hcpriv; 2135 if (qh) 2136 urb->hcpriv = qh; 2137 spin_unlock_irqrestore(&musb->lock, flags); 2138 2139 /* DMA mapping was already done, if needed, and this urb is on 2140 * hep->urb_list now ... so we're done, unless hep wasn't yet 2141 * scheduled onto a live qh. 2142 * 2143 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 2144 * disabled, testing for empty qh->ring and avoiding qh setup costs 2145 * except for the first urb queued after a config change. 2146 */ 2147 if (qh || ret) 2148 return ret; 2149 2150 /* Allocate and initialize qh, minimizing the work done each time 2151 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 2152 * 2153 * REVISIT consider a dedicated qh kmem_cache, so it's harder 2154 * for bugs in other kernel code to break this driver... 2155 */ 2156 qh = kzalloc(sizeof *qh, mem_flags); 2157 if (!qh) { 2158 spin_lock_irqsave(&musb->lock, flags); 2159 usb_hcd_unlink_urb_from_ep(hcd, urb); 2160 spin_unlock_irqrestore(&musb->lock, flags); 2161 return -ENOMEM; 2162 } 2163 2164 qh->hep = hep; 2165 qh->dev = urb->dev; 2166 INIT_LIST_HEAD(&qh->ring); 2167 qh->is_ready = 1; 2168 2169 qh->maxpacket = usb_endpoint_maxp(epd); 2170 qh->type = usb_endpoint_type(epd); 2171 2172 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 2173 * Some musb cores don't support high bandwidth ISO transfers; and 2174 * we don't (yet!) support high bandwidth interrupt transfers. 2175 */ 2176 qh->hb_mult = usb_endpoint_maxp_mult(epd); 2177 if (qh->hb_mult > 1) { 2178 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 2179 2180 if (ok) 2181 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 2182 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 2183 if (!ok) { 2184 dev_err(musb->controller, 2185 "high bandwidth %s (%dx%d) not supported\n", 2186 musb_ep_xfertype_string(qh->type), 2187 qh->hb_mult, qh->maxpacket & 0x7ff); 2188 ret = -EMSGSIZE; 2189 goto done; 2190 } 2191 qh->maxpacket &= 0x7ff; 2192 } 2193 2194 qh->epnum = usb_endpoint_num(epd); 2195 2196 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 2197 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 2198 2199 /* precompute rxtype/txtype/type0 register */ 2200 type_reg = (qh->type << 4) | qh->epnum; 2201 switch (urb->dev->speed) { 2202 case USB_SPEED_LOW: 2203 type_reg |= 0xc0; 2204 break; 2205 case USB_SPEED_FULL: 2206 type_reg |= 0x80; 2207 break; 2208 default: 2209 type_reg |= 0x40; 2210 } 2211 qh->type_reg = type_reg; 2212 2213 /* Precompute RXINTERVAL/TXINTERVAL register */ 2214 switch (qh->type) { 2215 case USB_ENDPOINT_XFER_INT: 2216 /* 2217 * Full/low speeds use the linear encoding, 2218 * high speed uses the logarithmic encoding. 2219 */ 2220 if (urb->dev->speed <= USB_SPEED_FULL) { 2221 interval = max_t(u8, epd->bInterval, 1); 2222 break; 2223 } 2224 fallthrough; 2225 case USB_ENDPOINT_XFER_ISOC: 2226 /* ISO always uses logarithmic encoding */ 2227 interval = min_t(u8, epd->bInterval, 16); 2228 break; 2229 default: 2230 /* REVISIT we actually want to use NAK limits, hinting to the 2231 * transfer scheduling logic to try some other qh, e.g. try 2232 * for 2 msec first: 2233 * 2234 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2235 * 2236 * The downside of disabling this is that transfer scheduling 2237 * gets VERY unfair for nonperiodic transfers; a misbehaving 2238 * peripheral could make that hurt. That's perfectly normal 2239 * for reads from network or serial adapters ... so we have 2240 * partial NAKlimit support for bulk RX. 2241 * 2242 * The upside of disabling it is simpler transfer scheduling. 2243 */ 2244 interval = 0; 2245 } 2246 qh->intv_reg = interval; 2247 2248 /* precompute addressing for external hub/tt ports */ 2249 if (musb->is_multipoint) { 2250 struct usb_device *parent = urb->dev->parent; 2251 2252 if (parent != hcd->self.root_hub) { 2253 qh->h_addr_reg = (u8) parent->devnum; 2254 2255 /* set up tt info if needed */ 2256 if (urb->dev->tt) { 2257 qh->h_port_reg = (u8) urb->dev->ttport; 2258 if (urb->dev->tt->hub) 2259 qh->h_addr_reg = 2260 (u8) urb->dev->tt->hub->devnum; 2261 if (urb->dev->tt->multi) 2262 qh->h_addr_reg |= 0x80; 2263 } 2264 } 2265 } 2266 2267 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2268 * until we get real dma queues (with an entry for each urb/buffer), 2269 * we only have work to do in the former case. 2270 */ 2271 spin_lock_irqsave(&musb->lock, flags); 2272 if (hep->hcpriv || !next_urb(qh)) { 2273 /* some concurrent activity submitted another urb to hep... 2274 * odd, rare, error prone, but legal. 2275 */ 2276 kfree(qh); 2277 qh = NULL; 2278 ret = 0; 2279 } else 2280 ret = musb_schedule(musb, qh, 2281 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2282 2283 if (ret == 0) { 2284 urb->hcpriv = qh; 2285 /* FIXME set urb->start_frame for iso/intr, it's tested in 2286 * musb_start_urb(), but otherwise only konicawc cares ... 2287 */ 2288 } 2289 spin_unlock_irqrestore(&musb->lock, flags); 2290 2291 done: 2292 if (ret != 0) { 2293 spin_lock_irqsave(&musb->lock, flags); 2294 usb_hcd_unlink_urb_from_ep(hcd, urb); 2295 spin_unlock_irqrestore(&musb->lock, flags); 2296 kfree(qh); 2297 } 2298 return ret; 2299 } 2300 2301 2302 /* 2303 * abort a transfer that's at the head of a hardware queue. 2304 * called with controller locked, irqs blocked 2305 * that hardware queue advances to the next transfer, unless prevented 2306 */ 2307 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2308 { 2309 struct musb_hw_ep *ep = qh->hw_ep; 2310 struct musb *musb = ep->musb; 2311 void __iomem *epio = ep->regs; 2312 unsigned hw_end = ep->epnum; 2313 void __iomem *regs = ep->musb->mregs; 2314 int is_in = usb_pipein(urb->pipe); 2315 int status = 0; 2316 u16 csr; 2317 struct dma_channel *dma = NULL; 2318 2319 musb_ep_select(regs, hw_end); 2320 2321 if (is_dma_capable()) { 2322 dma = is_in ? ep->rx_channel : ep->tx_channel; 2323 if (dma) { 2324 status = ep->musb->dma_controller->channel_abort(dma); 2325 musb_dbg(musb, "abort %cX%d DMA for urb %p --> %d", 2326 is_in ? 'R' : 'T', ep->epnum, 2327 urb, status); 2328 urb->actual_length += dma->actual_len; 2329 } 2330 } 2331 2332 /* turn off DMA requests, discard state, stop polling ... */ 2333 if (ep->epnum && is_in) { 2334 /* giveback saves bulk toggle */ 2335 csr = musb_h_flush_rxfifo(ep, 0); 2336 2337 /* clear the endpoint's irq status here to avoid bogus irqs */ 2338 if (is_dma_capable() && dma) 2339 musb_platform_clear_ep_rxintr(musb, ep->epnum); 2340 } else if (ep->epnum) { 2341 musb_h_tx_flush_fifo(ep); 2342 csr = musb_readw(epio, MUSB_TXCSR); 2343 csr &= ~(MUSB_TXCSR_AUTOSET 2344 | MUSB_TXCSR_DMAENAB 2345 | MUSB_TXCSR_H_RXSTALL 2346 | MUSB_TXCSR_H_NAKTIMEOUT 2347 | MUSB_TXCSR_H_ERROR 2348 | MUSB_TXCSR_TXPKTRDY); 2349 musb_writew(epio, MUSB_TXCSR, csr); 2350 /* REVISIT may need to clear FLUSHFIFO ... */ 2351 musb_writew(epio, MUSB_TXCSR, csr); 2352 /* flush cpu writebuffer */ 2353 csr = musb_readw(epio, MUSB_TXCSR); 2354 } else { 2355 musb_h_ep0_flush_fifo(ep); 2356 } 2357 if (status == 0) 2358 musb_advance_schedule(ep->musb, urb, ep, is_in); 2359 return status; 2360 } 2361 2362 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2363 { 2364 struct musb *musb = hcd_to_musb(hcd); 2365 struct musb_qh *qh; 2366 unsigned long flags; 2367 int is_in = usb_pipein(urb->pipe); 2368 int ret; 2369 2370 trace_musb_urb_deq(musb, urb); 2371 2372 spin_lock_irqsave(&musb->lock, flags); 2373 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2374 if (ret) 2375 goto done; 2376 2377 qh = urb->hcpriv; 2378 if (!qh) 2379 goto done; 2380 2381 /* 2382 * Any URB not actively programmed into endpoint hardware can be 2383 * immediately given back; that's any URB not at the head of an 2384 * endpoint queue, unless someday we get real DMA queues. And even 2385 * if it's at the head, it might not be known to the hardware... 2386 * 2387 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2388 * has already been updated. This is a synchronous abort; it'd be 2389 * OK to hold off until after some IRQ, though. 2390 * 2391 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2392 */ 2393 if (!qh->is_ready 2394 || urb->urb_list.prev != &qh->hep->urb_list 2395 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2396 int ready = qh->is_ready; 2397 2398 qh->is_ready = 0; 2399 musb_giveback(musb, urb, 0); 2400 qh->is_ready = ready; 2401 2402 /* If nothing else (usually musb_giveback) is using it 2403 * and its URB list has emptied, recycle this qh. 2404 */ 2405 if (ready && list_empty(&qh->hep->urb_list)) { 2406 musb_ep_set_qh(qh->hw_ep, is_in, NULL); 2407 qh->hep->hcpriv = NULL; 2408 list_del(&qh->ring); 2409 kfree(qh); 2410 } 2411 } else 2412 ret = musb_cleanup_urb(urb, qh); 2413 done: 2414 spin_unlock_irqrestore(&musb->lock, flags); 2415 return ret; 2416 } 2417 2418 /* disable an endpoint */ 2419 static void 2420 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2421 { 2422 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2423 unsigned long flags; 2424 struct musb *musb = hcd_to_musb(hcd); 2425 struct musb_qh *qh; 2426 struct urb *urb; 2427 2428 spin_lock_irqsave(&musb->lock, flags); 2429 2430 qh = hep->hcpriv; 2431 if (qh == NULL) 2432 goto exit; 2433 2434 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2435 2436 /* Kick the first URB off the hardware, if needed */ 2437 qh->is_ready = 0; 2438 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2439 urb = next_urb(qh); 2440 2441 /* make software (then hardware) stop ASAP */ 2442 if (!urb->unlinked) 2443 urb->status = -ESHUTDOWN; 2444 2445 /* cleanup */ 2446 musb_cleanup_urb(urb, qh); 2447 2448 /* Then nuke all the others ... and advance the 2449 * queue on hw_ep (e.g. bulk ring) when we're done. 2450 */ 2451 while (!list_empty(&hep->urb_list)) { 2452 urb = next_urb(qh); 2453 urb->status = -ESHUTDOWN; 2454 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2455 } 2456 } else { 2457 /* Just empty the queue; the hardware is busy with 2458 * other transfers, and since !qh->is_ready nothing 2459 * will activate any of these as it advances. 2460 */ 2461 while (!list_empty(&hep->urb_list)) 2462 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2463 2464 hep->hcpriv = NULL; 2465 list_del(&qh->ring); 2466 kfree(qh); 2467 } 2468 exit: 2469 spin_unlock_irqrestore(&musb->lock, flags); 2470 } 2471 2472 static int musb_h_get_frame_number(struct usb_hcd *hcd) 2473 { 2474 struct musb *musb = hcd_to_musb(hcd); 2475 2476 return musb_readw(musb->mregs, MUSB_FRAME); 2477 } 2478 2479 static int musb_h_start(struct usb_hcd *hcd) 2480 { 2481 struct musb *musb = hcd_to_musb(hcd); 2482 2483 /* NOTE: musb_start() is called when the hub driver turns 2484 * on port power, or when (OTG) peripheral starts. 2485 */ 2486 hcd->state = HC_STATE_RUNNING; 2487 musb->port1_status = 0; 2488 return 0; 2489 } 2490 2491 static void musb_h_stop(struct usb_hcd *hcd) 2492 { 2493 musb_stop(hcd_to_musb(hcd)); 2494 hcd->state = HC_STATE_HALT; 2495 } 2496 2497 static int musb_bus_suspend(struct usb_hcd *hcd) 2498 { 2499 struct musb *musb = hcd_to_musb(hcd); 2500 u8 devctl; 2501 int ret; 2502 2503 ret = musb_port_suspend(musb, true); 2504 if (ret) 2505 return ret; 2506 2507 if (!is_host_active(musb)) 2508 return 0; 2509 2510 switch (musb_get_state(musb)) { 2511 case OTG_STATE_A_SUSPEND: 2512 return 0; 2513 case OTG_STATE_A_WAIT_VRISE: 2514 /* ID could be grounded even if there's no device 2515 * on the other end of the cable. NOTE that the 2516 * A_WAIT_VRISE timers are messy with MUSB... 2517 */ 2518 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2519 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2520 musb_set_state(musb, OTG_STATE_A_WAIT_BCON); 2521 break; 2522 default: 2523 break; 2524 } 2525 2526 if (musb->is_active) { 2527 WARNING("trying to suspend as %s while active\n", 2528 musb_otg_state_string(musb)); 2529 return -EBUSY; 2530 } else 2531 return 0; 2532 } 2533 2534 static int musb_bus_resume(struct usb_hcd *hcd) 2535 { 2536 struct musb *musb = hcd_to_musb(hcd); 2537 2538 if (musb->config && 2539 musb->config->host_port_deassert_reset_at_resume) 2540 musb_port_reset(musb, false); 2541 2542 return 0; 2543 } 2544 2545 #ifndef CONFIG_MUSB_PIO_ONLY 2546 2547 #define MUSB_USB_DMA_ALIGN 4 2548 2549 struct musb_temp_buffer { 2550 void *kmalloc_ptr; 2551 void *old_xfer_buffer; 2552 u8 data[]; 2553 }; 2554 2555 static void musb_free_temp_buffer(struct urb *urb) 2556 { 2557 enum dma_data_direction dir; 2558 struct musb_temp_buffer *temp; 2559 size_t length; 2560 2561 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2562 return; 2563 2564 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2565 2566 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, 2567 data); 2568 2569 if (dir == DMA_FROM_DEVICE) { 2570 if (usb_pipeisoc(urb->pipe)) 2571 length = urb->transfer_buffer_length; 2572 else 2573 length = urb->actual_length; 2574 2575 memcpy(temp->old_xfer_buffer, temp->data, length); 2576 } 2577 urb->transfer_buffer = temp->old_xfer_buffer; 2578 kfree(temp->kmalloc_ptr); 2579 2580 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2581 } 2582 2583 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 2584 { 2585 enum dma_data_direction dir; 2586 struct musb_temp_buffer *temp; 2587 void *kmalloc_ptr; 2588 size_t kmalloc_size; 2589 2590 if (urb->num_sgs || urb->sg || 2591 urb->transfer_buffer_length == 0 || 2592 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) 2593 return 0; 2594 2595 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2596 2597 /* Allocate a buffer with enough padding for alignment */ 2598 kmalloc_size = urb->transfer_buffer_length + 2599 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; 2600 2601 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2602 if (!kmalloc_ptr) 2603 return -ENOMEM; 2604 2605 /* Position our struct temp_buffer such that data is aligned */ 2606 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); 2607 2608 2609 temp->kmalloc_ptr = kmalloc_ptr; 2610 temp->old_xfer_buffer = urb->transfer_buffer; 2611 if (dir == DMA_TO_DEVICE) 2612 memcpy(temp->data, urb->transfer_buffer, 2613 urb->transfer_buffer_length); 2614 urb->transfer_buffer = temp->data; 2615 2616 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2617 2618 return 0; 2619 } 2620 2621 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2622 gfp_t mem_flags) 2623 { 2624 struct musb *musb = hcd_to_musb(hcd); 2625 int ret; 2626 2627 /* 2628 * The DMA engine in RTL1.8 and above cannot handle 2629 * DMA addresses that are not aligned to a 4 byte boundary. 2630 * For such engine implemented (un)map_urb_for_dma hooks. 2631 * Do not use these hooks for RTL<1.8 2632 */ 2633 if (musb->hwvers < MUSB_HWVERS_1800) 2634 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2635 2636 ret = musb_alloc_temp_buffer(urb, mem_flags); 2637 if (ret) 2638 return ret; 2639 2640 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2641 if (ret) 2642 musb_free_temp_buffer(urb); 2643 2644 return ret; 2645 } 2646 2647 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2648 { 2649 struct musb *musb = hcd_to_musb(hcd); 2650 2651 usb_hcd_unmap_urb_for_dma(hcd, urb); 2652 2653 /* Do not use this hook for RTL<1.8 (see description above) */ 2654 if (musb->hwvers < MUSB_HWVERS_1800) 2655 return; 2656 2657 musb_free_temp_buffer(urb); 2658 } 2659 #endif /* !CONFIG_MUSB_PIO_ONLY */ 2660 2661 static const struct hc_driver musb_hc_driver = { 2662 .description = "musb-hcd", 2663 .product_desc = "MUSB HDRC host driver", 2664 .hcd_priv_size = sizeof(struct musb *), 2665 .flags = HCD_USB2 | HCD_DMA | HCD_MEMORY, 2666 2667 /* not using irq handler or reset hooks from usbcore, since 2668 * those must be shared with peripheral code for OTG configs 2669 */ 2670 2671 .start = musb_h_start, 2672 .stop = musb_h_stop, 2673 2674 .get_frame_number = musb_h_get_frame_number, 2675 2676 .urb_enqueue = musb_urb_enqueue, 2677 .urb_dequeue = musb_urb_dequeue, 2678 .endpoint_disable = musb_h_disable, 2679 2680 #ifndef CONFIG_MUSB_PIO_ONLY 2681 .map_urb_for_dma = musb_map_urb_for_dma, 2682 .unmap_urb_for_dma = musb_unmap_urb_for_dma, 2683 #endif 2684 2685 .hub_status_data = musb_hub_status_data, 2686 .hub_control = musb_hub_control, 2687 .bus_suspend = musb_bus_suspend, 2688 .bus_resume = musb_bus_resume, 2689 /* .start_port_reset = NULL, */ 2690 /* .hub_irq_enable = NULL, */ 2691 }; 2692 2693 int musb_host_alloc(struct musb *musb) 2694 { 2695 struct device *dev = musb->controller; 2696 2697 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 2698 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 2699 if (!musb->hcd) 2700 return -EINVAL; 2701 2702 *musb->hcd->hcd_priv = (unsigned long) musb; 2703 musb->hcd->self.uses_pio_for_control = 1; 2704 musb->hcd->uses_new_polling = 1; 2705 musb->hcd->has_tt = 1; 2706 2707 return 0; 2708 } 2709 2710 void musb_host_cleanup(struct musb *musb) 2711 { 2712 if (musb->port_mode == MUSB_PERIPHERAL) 2713 return; 2714 usb_remove_hcd(musb->hcd); 2715 } 2716 2717 void musb_host_free(struct musb *musb) 2718 { 2719 usb_put_hcd(musb->hcd); 2720 } 2721 2722 int musb_host_setup(struct musb *musb, int power_budget) 2723 { 2724 int ret; 2725 struct usb_hcd *hcd = musb->hcd; 2726 2727 if (musb->port_mode == MUSB_HOST) { 2728 MUSB_HST_MODE(musb); 2729 musb_set_state(musb, OTG_STATE_A_IDLE); 2730 } 2731 2732 if (musb->xceiv) { 2733 otg_set_host(musb->xceiv->otg, &hcd->self); 2734 musb->xceiv->otg->host = &hcd->self; 2735 } else { 2736 phy_set_mode(musb->phy, PHY_MODE_USB_HOST); 2737 } 2738 2739 /* don't support otg protocols */ 2740 hcd->self.otg_port = 0; 2741 hcd->power_budget = 2 * (power_budget ? : 250); 2742 hcd->skip_phy_initialization = 1; 2743 2744 ret = usb_add_hcd(hcd, 0, 0); 2745 if (ret < 0) 2746 return ret; 2747 2748 device_wakeup_enable(hcd->self.controller); 2749 return 0; 2750 } 2751 2752 void musb_host_resume_root_hub(struct musb *musb) 2753 { 2754 usb_hcd_resume_root_hub(musb->hcd); 2755 } 2756 2757 void musb_host_poke_root_hub(struct musb *musb) 2758 { 2759 MUSB_HST_MODE(musb); 2760 if (musb->hcd->status_urb) 2761 usb_hcd_poll_rh_status(musb->hcd); 2762 else 2763 usb_hcd_resume_root_hub(musb->hcd); 2764 } 2765