1 /* 2 * MUSB OTG driver peripheral support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/list.h> 38 #include <linux/timer.h> 39 #include <linux/module.h> 40 #include <linux/smp.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/moduleparam.h> 44 #include <linux/stat.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/slab.h> 47 48 #include "musb_core.h" 49 50 51 /* MUSB PERIPHERAL status 3-mar-2006: 52 * 53 * - EP0 seems solid. It passes both USBCV and usbtest control cases. 54 * Minor glitches: 55 * 56 * + remote wakeup to Linux hosts work, but saw USBCV failures; 57 * in one test run (operator error?) 58 * + endpoint halt tests -- in both usbtest and usbcv -- seem 59 * to break when dma is enabled ... is something wrongly 60 * clearing SENDSTALL? 61 * 62 * - Mass storage behaved ok when last tested. Network traffic patterns 63 * (with lots of short transfers etc) need retesting; they turn up the 64 * worst cases of the DMA, since short packets are typical but are not 65 * required. 66 * 67 * - TX/IN 68 * + both pio and dma behave in with network and g_zero tests 69 * + no cppi throughput issues other than no-hw-queueing 70 * + failed with FLAT_REG (DaVinci) 71 * + seems to behave with double buffering, PIO -and- CPPI 72 * + with gadgetfs + AIO, requests got lost? 73 * 74 * - RX/OUT 75 * + both pio and dma behave in with network and g_zero tests 76 * + dma is slow in typical case (short_not_ok is clear) 77 * + double buffering ok with PIO 78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes 79 * + request lossage observed with gadgetfs 80 * 81 * - ISO not tested ... might work, but only weakly isochronous 82 * 83 * - Gadget driver disabling of softconnect during bind() is ignored; so 84 * drivers can't hold off host requests until userspace is ready. 85 * (Workaround: they can turn it off later.) 86 * 87 * - PORTABILITY (assumes PIO works): 88 * + DaVinci, basically works with cppi dma 89 * + OMAP 2430, ditto with mentor dma 90 * + TUSB 6010, platform-specific dma in the works 91 */ 92 93 /* ----------------------------------------------------------------------- */ 94 95 #define is_buffer_mapped(req) (is_dma_capable() && \ 96 (req->map_state != UN_MAPPED)) 97 98 /* Maps the buffer to dma */ 99 100 static inline void map_dma_buffer(struct musb_request *request, 101 struct musb *musb, struct musb_ep *musb_ep) 102 { 103 int compatible = true; 104 struct dma_controller *dma = musb->dma_controller; 105 106 request->map_state = UN_MAPPED; 107 108 if (!is_dma_capable() || !musb_ep->dma) 109 return; 110 111 /* Check if DMA engine can handle this request. 112 * DMA code must reject the USB request explicitly. 113 * Default behaviour is to map the request. 114 */ 115 if (dma->is_compatible) 116 compatible = dma->is_compatible(musb_ep->dma, 117 musb_ep->packet_sz, request->request.buf, 118 request->request.length); 119 if (!compatible) 120 return; 121 122 if (request->request.dma == DMA_ADDR_INVALID) { 123 request->request.dma = dma_map_single( 124 musb->controller, 125 request->request.buf, 126 request->request.length, 127 request->tx 128 ? DMA_TO_DEVICE 129 : DMA_FROM_DEVICE); 130 request->map_state = MUSB_MAPPED; 131 } else { 132 dma_sync_single_for_device(musb->controller, 133 request->request.dma, 134 request->request.length, 135 request->tx 136 ? DMA_TO_DEVICE 137 : DMA_FROM_DEVICE); 138 request->map_state = PRE_MAPPED; 139 } 140 } 141 142 /* Unmap the buffer from dma and maps it back to cpu */ 143 static inline void unmap_dma_buffer(struct musb_request *request, 144 struct musb *musb) 145 { 146 if (!is_buffer_mapped(request)) 147 return; 148 149 if (request->request.dma == DMA_ADDR_INVALID) { 150 dev_vdbg(musb->controller, 151 "not unmapping a never mapped buffer\n"); 152 return; 153 } 154 if (request->map_state == MUSB_MAPPED) { 155 dma_unmap_single(musb->controller, 156 request->request.dma, 157 request->request.length, 158 request->tx 159 ? DMA_TO_DEVICE 160 : DMA_FROM_DEVICE); 161 request->request.dma = DMA_ADDR_INVALID; 162 } else { /* PRE_MAPPED */ 163 dma_sync_single_for_cpu(musb->controller, 164 request->request.dma, 165 request->request.length, 166 request->tx 167 ? DMA_TO_DEVICE 168 : DMA_FROM_DEVICE); 169 } 170 request->map_state = UN_MAPPED; 171 } 172 173 /* 174 * Immediately complete a request. 175 * 176 * @param request the request to complete 177 * @param status the status to complete the request with 178 * Context: controller locked, IRQs blocked. 179 */ 180 void musb_g_giveback( 181 struct musb_ep *ep, 182 struct usb_request *request, 183 int status) 184 __releases(ep->musb->lock) 185 __acquires(ep->musb->lock) 186 { 187 struct musb_request *req; 188 struct musb *musb; 189 int busy = ep->busy; 190 191 req = to_musb_request(request); 192 193 list_del(&req->list); 194 if (req->request.status == -EINPROGRESS) 195 req->request.status = status; 196 musb = req->musb; 197 198 ep->busy = 1; 199 spin_unlock(&musb->lock); 200 unmap_dma_buffer(req, musb); 201 if (request->status == 0) 202 dev_dbg(musb->controller, "%s done request %p, %d/%d\n", 203 ep->end_point.name, request, 204 req->request.actual, req->request.length); 205 else 206 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", 207 ep->end_point.name, request, 208 req->request.actual, req->request.length, 209 request->status); 210 req->request.complete(&req->ep->end_point, &req->request); 211 spin_lock(&musb->lock); 212 ep->busy = busy; 213 } 214 215 /* ----------------------------------------------------------------------- */ 216 217 /* 218 * Abort requests queued to an endpoint using the status. Synchronous. 219 * caller locked controller and blocked irqs, and selected this ep. 220 */ 221 static void nuke(struct musb_ep *ep, const int status) 222 { 223 struct musb *musb = ep->musb; 224 struct musb_request *req = NULL; 225 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 226 227 ep->busy = 1; 228 229 if (is_dma_capable() && ep->dma) { 230 struct dma_controller *c = ep->musb->dma_controller; 231 int value; 232 233 if (ep->is_in) { 234 /* 235 * The programming guide says that we must not clear 236 * the DMAMODE bit before DMAENAB, so we only 237 * clear it in the second write... 238 */ 239 musb_writew(epio, MUSB_TXCSR, 240 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); 241 musb_writew(epio, MUSB_TXCSR, 242 0 | MUSB_TXCSR_FLUSHFIFO); 243 } else { 244 musb_writew(epio, MUSB_RXCSR, 245 0 | MUSB_RXCSR_FLUSHFIFO); 246 musb_writew(epio, MUSB_RXCSR, 247 0 | MUSB_RXCSR_FLUSHFIFO); 248 } 249 250 value = c->channel_abort(ep->dma); 251 dev_dbg(musb->controller, "%s: abort DMA --> %d\n", 252 ep->name, value); 253 c->channel_release(ep->dma); 254 ep->dma = NULL; 255 } 256 257 while (!list_empty(&ep->req_list)) { 258 req = list_first_entry(&ep->req_list, struct musb_request, list); 259 musb_g_giveback(ep, &req->request, status); 260 } 261 } 262 263 /* ----------------------------------------------------------------------- */ 264 265 /* Data transfers - pure PIO, pure DMA, or mixed mode */ 266 267 /* 268 * This assumes the separate CPPI engine is responding to DMA requests 269 * from the usb core ... sequenced a bit differently from mentor dma. 270 */ 271 272 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) 273 { 274 if (can_bulk_split(musb, ep->type)) 275 return ep->hw_ep->max_packet_sz_tx; 276 else 277 return ep->packet_sz; 278 } 279 280 281 #ifdef CONFIG_USB_INVENTRA_DMA 282 283 /* Peripheral tx (IN) using Mentor DMA works as follows: 284 Only mode 0 is used for transfers <= wPktSize, 285 mode 1 is used for larger transfers, 286 287 One of the following happens: 288 - Host sends IN token which causes an endpoint interrupt 289 -> TxAvail 290 -> if DMA is currently busy, exit. 291 -> if queue is non-empty, txstate(). 292 293 - Request is queued by the gadget driver. 294 -> if queue was previously empty, txstate() 295 296 txstate() 297 -> start 298 /\ -> setup DMA 299 | (data is transferred to the FIFO, then sent out when 300 | IN token(s) are recd from Host. 301 | -> DMA interrupt on completion 302 | calls TxAvail. 303 | -> stop DMA, ~DMAENAB, 304 | -> set TxPktRdy for last short pkt or zlp 305 | -> Complete Request 306 | -> Continue next request (call txstate) 307 |___________________________________| 308 309 * Non-Mentor DMA engines can of course work differently, such as by 310 * upleveling from irq-per-packet to irq-per-buffer. 311 */ 312 313 #endif 314 315 /* 316 * An endpoint is transmitting data. This can be called either from 317 * the IRQ routine or from ep.queue() to kickstart a request on an 318 * endpoint. 319 * 320 * Context: controller locked, IRQs blocked, endpoint selected 321 */ 322 static void txstate(struct musb *musb, struct musb_request *req) 323 { 324 u8 epnum = req->epnum; 325 struct musb_ep *musb_ep; 326 void __iomem *epio = musb->endpoints[epnum].regs; 327 struct usb_request *request; 328 u16 fifo_count = 0, csr; 329 int use_dma = 0; 330 331 musb_ep = req->ep; 332 333 /* we shouldn't get here while DMA is active ... but we do ... */ 334 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 335 dev_dbg(musb->controller, "dma pending...\n"); 336 return; 337 } 338 339 /* read TXCSR before */ 340 csr = musb_readw(epio, MUSB_TXCSR); 341 342 request = &req->request; 343 fifo_count = min(max_ep_writesize(musb, musb_ep), 344 (int)(request->length - request->actual)); 345 346 if (csr & MUSB_TXCSR_TXPKTRDY) { 347 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", 348 musb_ep->end_point.name, csr); 349 return; 350 } 351 352 if (csr & MUSB_TXCSR_P_SENDSTALL) { 353 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", 354 musb_ep->end_point.name, csr); 355 return; 356 } 357 358 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 359 epnum, musb_ep->packet_sz, fifo_count, 360 csr); 361 362 #ifndef CONFIG_MUSB_PIO_ONLY 363 if (is_buffer_mapped(req)) { 364 struct dma_controller *c = musb->dma_controller; 365 size_t request_size; 366 367 /* setup DMA, then program endpoint CSR */ 368 request_size = min_t(size_t, request->length - request->actual, 369 musb_ep->dma->max_len); 370 371 use_dma = (request->dma != DMA_ADDR_INVALID); 372 373 /* MUSB_TXCSR_P_ISO is still set correctly */ 374 375 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 376 { 377 if (request_size < musb_ep->packet_sz) 378 musb_ep->dma->desired_mode = 0; 379 else 380 musb_ep->dma->desired_mode = 1; 381 382 use_dma = use_dma && c->channel_program( 383 musb_ep->dma, musb_ep->packet_sz, 384 musb_ep->dma->desired_mode, 385 request->dma + request->actual, request_size); 386 if (use_dma) { 387 if (musb_ep->dma->desired_mode == 0) { 388 /* 389 * We must not clear the DMAMODE bit 390 * before the DMAENAB bit -- and the 391 * latter doesn't always get cleared 392 * before we get here... 393 */ 394 csr &= ~(MUSB_TXCSR_AUTOSET 395 | MUSB_TXCSR_DMAENAB); 396 musb_writew(epio, MUSB_TXCSR, csr 397 | MUSB_TXCSR_P_WZC_BITS); 398 csr &= ~MUSB_TXCSR_DMAMODE; 399 csr |= (MUSB_TXCSR_DMAENAB | 400 MUSB_TXCSR_MODE); 401 /* against programming guide */ 402 } else { 403 csr |= (MUSB_TXCSR_DMAENAB 404 | MUSB_TXCSR_DMAMODE 405 | MUSB_TXCSR_MODE); 406 if (!musb_ep->hb_mult) 407 csr |= MUSB_TXCSR_AUTOSET; 408 } 409 csr &= ~MUSB_TXCSR_P_UNDERRUN; 410 411 musb_writew(epio, MUSB_TXCSR, csr); 412 } 413 } 414 415 #elif defined(CONFIG_USB_TI_CPPI_DMA) 416 /* program endpoint CSR first, then setup DMA */ 417 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 418 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | 419 MUSB_TXCSR_MODE; 420 musb_writew(epio, MUSB_TXCSR, 421 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) 422 | csr); 423 424 /* ensure writebuffer is empty */ 425 csr = musb_readw(epio, MUSB_TXCSR); 426 427 /* NOTE host side sets DMAENAB later than this; both are 428 * OK since the transfer dma glue (between CPPI and Mentor 429 * fifos) just tells CPPI it could start. Data only moves 430 * to the USB TX fifo when both fifos are ready. 431 */ 432 433 /* "mode" is irrelevant here; handle terminating ZLPs like 434 * PIO does, since the hardware RNDIS mode seems unreliable 435 * except for the last-packet-is-already-short case. 436 */ 437 use_dma = use_dma && c->channel_program( 438 musb_ep->dma, musb_ep->packet_sz, 439 0, 440 request->dma + request->actual, 441 request_size); 442 if (!use_dma) { 443 c->channel_release(musb_ep->dma); 444 musb_ep->dma = NULL; 445 csr &= ~MUSB_TXCSR_DMAENAB; 446 musb_writew(epio, MUSB_TXCSR, csr); 447 /* invariant: prequest->buf is non-null */ 448 } 449 #elif defined(CONFIG_USB_TUSB_OMAP_DMA) 450 use_dma = use_dma && c->channel_program( 451 musb_ep->dma, musb_ep->packet_sz, 452 request->zero, 453 request->dma + request->actual, 454 request_size); 455 #endif 456 } 457 #endif 458 459 if (!use_dma) { 460 /* 461 * Unmap the dma buffer back to cpu if dma channel 462 * programming fails 463 */ 464 unmap_dma_buffer(req, musb); 465 466 musb_write_fifo(musb_ep->hw_ep, fifo_count, 467 (u8 *) (request->buf + request->actual)); 468 request->actual += fifo_count; 469 csr |= MUSB_TXCSR_TXPKTRDY; 470 csr &= ~MUSB_TXCSR_P_UNDERRUN; 471 musb_writew(epio, MUSB_TXCSR, csr); 472 } 473 474 /* host may already have the data when this message shows... */ 475 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 476 musb_ep->end_point.name, use_dma ? "dma" : "pio", 477 request->actual, request->length, 478 musb_readw(epio, MUSB_TXCSR), 479 fifo_count, 480 musb_readw(epio, MUSB_TXMAXP)); 481 } 482 483 /* 484 * FIFO state update (e.g. data ready). 485 * Called from IRQ, with controller locked. 486 */ 487 void musb_g_tx(struct musb *musb, u8 epnum) 488 { 489 u16 csr; 490 struct musb_request *req; 491 struct usb_request *request; 492 u8 __iomem *mbase = musb->mregs; 493 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; 494 void __iomem *epio = musb->endpoints[epnum].regs; 495 struct dma_channel *dma; 496 497 musb_ep_select(mbase, epnum); 498 req = next_request(musb_ep); 499 request = &req->request; 500 501 csr = musb_readw(epio, MUSB_TXCSR); 502 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 503 504 dma = is_dma_capable() ? musb_ep->dma : NULL; 505 506 /* 507 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX 508 * probably rates reporting as a host error. 509 */ 510 if (csr & MUSB_TXCSR_P_SENTSTALL) { 511 csr |= MUSB_TXCSR_P_WZC_BITS; 512 csr &= ~MUSB_TXCSR_P_SENTSTALL; 513 musb_writew(epio, MUSB_TXCSR, csr); 514 return; 515 } 516 517 if (csr & MUSB_TXCSR_P_UNDERRUN) { 518 /* We NAKed, no big deal... little reason to care. */ 519 csr |= MUSB_TXCSR_P_WZC_BITS; 520 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 521 musb_writew(epio, MUSB_TXCSR, csr); 522 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", 523 epnum, request); 524 } 525 526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 527 /* 528 * SHOULD NOT HAPPEN... has with CPPI though, after 529 * changing SENDSTALL (and other cases); harmless? 530 */ 531 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); 532 return; 533 } 534 535 if (request) { 536 u8 is_dma = 0; 537 538 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 539 is_dma = 1; 540 csr |= MUSB_TXCSR_P_WZC_BITS; 541 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | 542 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); 543 musb_writew(epio, MUSB_TXCSR, csr); 544 /* Ensure writebuffer is empty. */ 545 csr = musb_readw(epio, MUSB_TXCSR); 546 request->actual += musb_ep->dma->actual_len; 547 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 548 epnum, csr, musb_ep->dma->actual_len, request); 549 } 550 551 /* 552 * First, maybe a terminating short packet. Some DMA 553 * engines might handle this by themselves. 554 */ 555 if ((request->zero && request->length 556 && (request->length % musb_ep->packet_sz == 0) 557 && (request->actual == request->length)) 558 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 559 || (is_dma && (!dma->desired_mode || 560 (request->actual & 561 (musb_ep->packet_sz - 1)))) 562 #endif 563 ) { 564 /* 565 * On DMA completion, FIFO may not be 566 * available yet... 567 */ 568 if (csr & MUSB_TXCSR_TXPKTRDY) 569 return; 570 571 dev_dbg(musb->controller, "sending zero pkt\n"); 572 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 573 | MUSB_TXCSR_TXPKTRDY); 574 request->zero = 0; 575 } 576 577 if (request->actual == request->length) { 578 musb_g_giveback(musb_ep, request, 0); 579 req = musb_ep->desc ? next_request(musb_ep) : NULL; 580 if (!req) { 581 dev_dbg(musb->controller, "%s idle now\n", 582 musb_ep->end_point.name); 583 return; 584 } 585 } 586 587 txstate(musb, req); 588 } 589 } 590 591 /* ------------------------------------------------------------ */ 592 593 #ifdef CONFIG_USB_INVENTRA_DMA 594 595 /* Peripheral rx (OUT) using Mentor DMA works as follows: 596 - Only mode 0 is used. 597 598 - Request is queued by the gadget class driver. 599 -> if queue was previously empty, rxstate() 600 601 - Host sends OUT token which causes an endpoint interrupt 602 /\ -> RxReady 603 | -> if request queued, call rxstate 604 | /\ -> setup DMA 605 | | -> DMA interrupt on completion 606 | | -> RxReady 607 | | -> stop DMA 608 | | -> ack the read 609 | | -> if data recd = max expected 610 | | by the request, or host 611 | | sent a short packet, 612 | | complete the request, 613 | | and start the next one. 614 | |_____________________________________| 615 | else just wait for the host 616 | to send the next OUT token. 617 |__________________________________________________| 618 619 * Non-Mentor DMA engines can of course work differently. 620 */ 621 622 #endif 623 624 /* 625 * Context: controller locked, IRQs blocked, endpoint selected 626 */ 627 static void rxstate(struct musb *musb, struct musb_request *req) 628 { 629 const u8 epnum = req->epnum; 630 struct usb_request *request = &req->request; 631 struct musb_ep *musb_ep; 632 void __iomem *epio = musb->endpoints[epnum].regs; 633 unsigned fifo_count = 0; 634 u16 len; 635 u16 csr = musb_readw(epio, MUSB_RXCSR); 636 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 637 u8 use_mode_1; 638 639 if (hw_ep->is_shared_fifo) 640 musb_ep = &hw_ep->ep_in; 641 else 642 musb_ep = &hw_ep->ep_out; 643 644 len = musb_ep->packet_sz; 645 646 /* We shouldn't get here while DMA is active, but we do... */ 647 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 648 dev_dbg(musb->controller, "DMA pending...\n"); 649 return; 650 } 651 652 if (csr & MUSB_RXCSR_P_SENDSTALL) { 653 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", 654 musb_ep->end_point.name, csr); 655 return; 656 } 657 658 if (is_cppi_enabled() && is_buffer_mapped(req)) { 659 struct dma_controller *c = musb->dma_controller; 660 struct dma_channel *channel = musb_ep->dma; 661 662 /* NOTE: CPPI won't actually stop advancing the DMA 663 * queue after short packet transfers, so this is almost 664 * always going to run as IRQ-per-packet DMA so that 665 * faults will be handled correctly. 666 */ 667 if (c->channel_program(channel, 668 musb_ep->packet_sz, 669 !request->short_not_ok, 670 request->dma + request->actual, 671 request->length - request->actual)) { 672 673 /* make sure that if an rxpkt arrived after the irq, 674 * the cppi engine will be ready to take it as soon 675 * as DMA is enabled 676 */ 677 csr &= ~(MUSB_RXCSR_AUTOCLEAR 678 | MUSB_RXCSR_DMAMODE); 679 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; 680 musb_writew(epio, MUSB_RXCSR, csr); 681 return; 682 } 683 } 684 685 if (csr & MUSB_RXCSR_RXPKTRDY) { 686 len = musb_readw(epio, MUSB_RXCOUNT); 687 688 /* 689 * Enable Mode 1 on RX transfers only when short_not_ok flag 690 * is set. Currently short_not_ok flag is set only from 691 * file_storage and f_mass_storage drivers 692 */ 693 694 if (request->short_not_ok && len == musb_ep->packet_sz) 695 use_mode_1 = 1; 696 else 697 use_mode_1 = 0; 698 699 if (request->actual < request->length) { 700 #ifdef CONFIG_USB_INVENTRA_DMA 701 if (is_buffer_mapped(req)) { 702 struct dma_controller *c; 703 struct dma_channel *channel; 704 int use_dma = 0; 705 706 c = musb->dma_controller; 707 channel = musb_ep->dma; 708 709 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in 710 * mode 0 only. So we do not get endpoint interrupts due to DMA 711 * completion. We only get interrupts from DMA controller. 712 * 713 * We could operate in DMA mode 1 if we knew the size of the tranfer 714 * in advance. For mass storage class, request->length = what the host 715 * sends, so that'd work. But for pretty much everything else, 716 * request->length is routinely more than what the host sends. For 717 * most these gadgets, end of is signified either by a short packet, 718 * or filling the last byte of the buffer. (Sending extra data in 719 * that last pckate should trigger an overflow fault.) But in mode 1, 720 * we don't get DMA completion interrupt for short packets. 721 * 722 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), 723 * to get endpoint interrupt on every DMA req, but that didn't seem 724 * to work reliably. 725 * 726 * REVISIT an updated g_file_storage can set req->short_not_ok, which 727 * then becomes usable as a runtime "use mode 1" hint... 728 */ 729 730 /* Experimental: Mode1 works with mass storage use cases */ 731 if (use_mode_1) { 732 csr |= MUSB_RXCSR_AUTOCLEAR; 733 musb_writew(epio, MUSB_RXCSR, csr); 734 csr |= MUSB_RXCSR_DMAENAB; 735 musb_writew(epio, MUSB_RXCSR, csr); 736 737 /* 738 * this special sequence (enabling and then 739 * disabling MUSB_RXCSR_DMAMODE) is required 740 * to get DMAReq to activate 741 */ 742 musb_writew(epio, MUSB_RXCSR, 743 csr | MUSB_RXCSR_DMAMODE); 744 musb_writew(epio, MUSB_RXCSR, csr); 745 746 } else { 747 if (!musb_ep->hb_mult && 748 musb_ep->hw_ep->rx_double_buffered) 749 csr |= MUSB_RXCSR_AUTOCLEAR; 750 csr |= MUSB_RXCSR_DMAENAB; 751 musb_writew(epio, MUSB_RXCSR, csr); 752 } 753 754 if (request->actual < request->length) { 755 int transfer_size = 0; 756 if (use_mode_1) { 757 transfer_size = min(request->length - request->actual, 758 channel->max_len); 759 musb_ep->dma->desired_mode = 1; 760 } else { 761 transfer_size = min(request->length - request->actual, 762 (unsigned)len); 763 musb_ep->dma->desired_mode = 0; 764 } 765 766 use_dma = c->channel_program( 767 channel, 768 musb_ep->packet_sz, 769 channel->desired_mode, 770 request->dma 771 + request->actual, 772 transfer_size); 773 } 774 775 if (use_dma) 776 return; 777 } 778 #elif defined(CONFIG_USB_UX500_DMA) 779 if ((is_buffer_mapped(req)) && 780 (request->actual < request->length)) { 781 782 struct dma_controller *c; 783 struct dma_channel *channel; 784 int transfer_size = 0; 785 786 c = musb->dma_controller; 787 channel = musb_ep->dma; 788 789 /* In case first packet is short */ 790 if (len < musb_ep->packet_sz) 791 transfer_size = len; 792 else if (request->short_not_ok) 793 transfer_size = min(request->length - 794 request->actual, 795 channel->max_len); 796 else 797 transfer_size = min(request->length - 798 request->actual, 799 (unsigned)len); 800 801 csr &= ~MUSB_RXCSR_DMAMODE; 802 csr |= (MUSB_RXCSR_DMAENAB | 803 MUSB_RXCSR_AUTOCLEAR); 804 805 musb_writew(epio, MUSB_RXCSR, csr); 806 807 if (transfer_size <= musb_ep->packet_sz) { 808 musb_ep->dma->desired_mode = 0; 809 } else { 810 musb_ep->dma->desired_mode = 1; 811 /* Mode must be set after DMAENAB */ 812 csr |= MUSB_RXCSR_DMAMODE; 813 musb_writew(epio, MUSB_RXCSR, csr); 814 } 815 816 if (c->channel_program(channel, 817 musb_ep->packet_sz, 818 channel->desired_mode, 819 request->dma 820 + request->actual, 821 transfer_size)) 822 823 return; 824 } 825 #endif /* Mentor's DMA */ 826 827 fifo_count = request->length - request->actual; 828 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 829 musb_ep->end_point.name, 830 len, fifo_count, 831 musb_ep->packet_sz); 832 833 fifo_count = min_t(unsigned, len, fifo_count); 834 835 #ifdef CONFIG_USB_TUSB_OMAP_DMA 836 if (tusb_dma_omap() && is_buffer_mapped(req)) { 837 struct dma_controller *c = musb->dma_controller; 838 struct dma_channel *channel = musb_ep->dma; 839 u32 dma_addr = request->dma + request->actual; 840 int ret; 841 842 ret = c->channel_program(channel, 843 musb_ep->packet_sz, 844 channel->desired_mode, 845 dma_addr, 846 fifo_count); 847 if (ret) 848 return; 849 } 850 #endif 851 /* 852 * Unmap the dma buffer back to cpu if dma channel 853 * programming fails. This buffer is mapped if the 854 * channel allocation is successful 855 */ 856 if (is_buffer_mapped(req)) { 857 unmap_dma_buffer(req, musb); 858 859 /* 860 * Clear DMAENAB and AUTOCLEAR for the 861 * PIO mode transfer 862 */ 863 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); 864 musb_writew(epio, MUSB_RXCSR, csr); 865 } 866 867 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) 868 (request->buf + request->actual)); 869 request->actual += fifo_count; 870 871 /* REVISIT if we left anything in the fifo, flush 872 * it and report -EOVERFLOW 873 */ 874 875 /* ack the read! */ 876 csr |= MUSB_RXCSR_P_WZC_BITS; 877 csr &= ~MUSB_RXCSR_RXPKTRDY; 878 musb_writew(epio, MUSB_RXCSR, csr); 879 } 880 } 881 882 /* reach the end or short packet detected */ 883 if (request->actual == request->length || len < musb_ep->packet_sz) 884 musb_g_giveback(musb_ep, request, 0); 885 } 886 887 /* 888 * Data ready for a request; called from IRQ 889 */ 890 void musb_g_rx(struct musb *musb, u8 epnum) 891 { 892 u16 csr; 893 struct musb_request *req; 894 struct usb_request *request; 895 void __iomem *mbase = musb->mregs; 896 struct musb_ep *musb_ep; 897 void __iomem *epio = musb->endpoints[epnum].regs; 898 struct dma_channel *dma; 899 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 900 901 if (hw_ep->is_shared_fifo) 902 musb_ep = &hw_ep->ep_in; 903 else 904 musb_ep = &hw_ep->ep_out; 905 906 musb_ep_select(mbase, epnum); 907 908 req = next_request(musb_ep); 909 if (!req) 910 return; 911 912 request = &req->request; 913 914 csr = musb_readw(epio, MUSB_RXCSR); 915 dma = is_dma_capable() ? musb_ep->dma : NULL; 916 917 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 918 csr, dma ? " (dma)" : "", request); 919 920 if (csr & MUSB_RXCSR_P_SENTSTALL) { 921 csr |= MUSB_RXCSR_P_WZC_BITS; 922 csr &= ~MUSB_RXCSR_P_SENTSTALL; 923 musb_writew(epio, MUSB_RXCSR, csr); 924 return; 925 } 926 927 if (csr & MUSB_RXCSR_P_OVERRUN) { 928 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ 929 csr &= ~MUSB_RXCSR_P_OVERRUN; 930 musb_writew(epio, MUSB_RXCSR, csr); 931 932 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); 933 if (request->status == -EINPROGRESS) 934 request->status = -EOVERFLOW; 935 } 936 if (csr & MUSB_RXCSR_INCOMPRX) { 937 /* REVISIT not necessarily an error */ 938 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); 939 } 940 941 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 942 /* "should not happen"; likely RXPKTRDY pending for DMA */ 943 dev_dbg(musb->controller, "%s busy, csr %04x\n", 944 musb_ep->end_point.name, csr); 945 return; 946 } 947 948 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { 949 csr &= ~(MUSB_RXCSR_AUTOCLEAR 950 | MUSB_RXCSR_DMAENAB 951 | MUSB_RXCSR_DMAMODE); 952 musb_writew(epio, MUSB_RXCSR, 953 MUSB_RXCSR_P_WZC_BITS | csr); 954 955 request->actual += musb_ep->dma->actual_len; 956 957 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 958 epnum, csr, 959 musb_readw(epio, MUSB_RXCSR), 960 musb_ep->dma->actual_len, request); 961 962 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 963 defined(CONFIG_USB_UX500_DMA) 964 /* Autoclear doesn't clear RxPktRdy for short packets */ 965 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) 966 || (dma->actual_len 967 & (musb_ep->packet_sz - 1))) { 968 /* ack the read! */ 969 csr &= ~MUSB_RXCSR_RXPKTRDY; 970 musb_writew(epio, MUSB_RXCSR, csr); 971 } 972 973 /* incomplete, and not short? wait for next IN packet */ 974 if ((request->actual < request->length) 975 && (musb_ep->dma->actual_len 976 == musb_ep->packet_sz)) { 977 /* In double buffer case, continue to unload fifo if 978 * there is Rx packet in FIFO. 979 **/ 980 csr = musb_readw(epio, MUSB_RXCSR); 981 if ((csr & MUSB_RXCSR_RXPKTRDY) && 982 hw_ep->rx_double_buffered) 983 goto exit; 984 return; 985 } 986 #endif 987 musb_g_giveback(musb_ep, request, 0); 988 989 req = next_request(musb_ep); 990 if (!req) 991 return; 992 } 993 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 994 defined(CONFIG_USB_UX500_DMA) 995 exit: 996 #endif 997 /* Analyze request */ 998 rxstate(musb, req); 999 } 1000 1001 /* ------------------------------------------------------------ */ 1002 1003 static int musb_gadget_enable(struct usb_ep *ep, 1004 const struct usb_endpoint_descriptor *desc) 1005 { 1006 unsigned long flags; 1007 struct musb_ep *musb_ep; 1008 struct musb_hw_ep *hw_ep; 1009 void __iomem *regs; 1010 struct musb *musb; 1011 void __iomem *mbase; 1012 u8 epnum; 1013 u16 csr; 1014 unsigned tmp; 1015 int status = -EINVAL; 1016 1017 if (!ep || !desc) 1018 return -EINVAL; 1019 1020 musb_ep = to_musb_ep(ep); 1021 hw_ep = musb_ep->hw_ep; 1022 regs = hw_ep->regs; 1023 musb = musb_ep->musb; 1024 mbase = musb->mregs; 1025 epnum = musb_ep->current_epnum; 1026 1027 spin_lock_irqsave(&musb->lock, flags); 1028 1029 if (musb_ep->desc) { 1030 status = -EBUSY; 1031 goto fail; 1032 } 1033 musb_ep->type = usb_endpoint_type(desc); 1034 1035 /* check direction and (later) maxpacket size against endpoint */ 1036 if (usb_endpoint_num(desc) != epnum) 1037 goto fail; 1038 1039 /* REVISIT this rules out high bandwidth periodic transfers */ 1040 tmp = usb_endpoint_maxp(desc); 1041 if (tmp & ~0x07ff) { 1042 int ok; 1043 1044 if (usb_endpoint_dir_in(desc)) 1045 ok = musb->hb_iso_tx; 1046 else 1047 ok = musb->hb_iso_rx; 1048 1049 if (!ok) { 1050 dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); 1051 goto fail; 1052 } 1053 musb_ep->hb_mult = (tmp >> 11) & 3; 1054 } else { 1055 musb_ep->hb_mult = 0; 1056 } 1057 1058 musb_ep->packet_sz = tmp & 0x7ff; 1059 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); 1060 1061 /* enable the interrupts for the endpoint, set the endpoint 1062 * packet size (or fail), set the mode, clear the fifo 1063 */ 1064 musb_ep_select(mbase, epnum); 1065 if (usb_endpoint_dir_in(desc)) { 1066 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1067 1068 if (hw_ep->is_shared_fifo) 1069 musb_ep->is_in = 1; 1070 if (!musb_ep->is_in) 1071 goto fail; 1072 1073 if (tmp > hw_ep->max_packet_sz_tx) { 1074 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1075 goto fail; 1076 } 1077 1078 int_txe |= (1 << epnum); 1079 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1080 1081 /* REVISIT if can_bulk_split(), use by updating "tmp"; 1082 * likewise high bandwidth periodic tx 1083 */ 1084 /* Set TXMAXP with the FIFO size of the endpoint 1085 * to disable double buffering mode. 1086 */ 1087 if (musb->double_buffer_not_ok) 1088 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); 1089 else 1090 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz 1091 | (musb_ep->hb_mult << 11)); 1092 1093 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 1094 if (musb_readw(regs, MUSB_TXCSR) 1095 & MUSB_TXCSR_FIFONOTEMPTY) 1096 csr |= MUSB_TXCSR_FLUSHFIFO; 1097 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1098 csr |= MUSB_TXCSR_P_ISO; 1099 1100 /* set twice in case of double buffering */ 1101 musb_writew(regs, MUSB_TXCSR, csr); 1102 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1103 musb_writew(regs, MUSB_TXCSR, csr); 1104 1105 } else { 1106 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); 1107 1108 if (hw_ep->is_shared_fifo) 1109 musb_ep->is_in = 0; 1110 if (musb_ep->is_in) 1111 goto fail; 1112 1113 if (tmp > hw_ep->max_packet_sz_rx) { 1114 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1115 goto fail; 1116 } 1117 1118 int_rxe |= (1 << epnum); 1119 musb_writew(mbase, MUSB_INTRRXE, int_rxe); 1120 1121 /* REVISIT if can_bulk_combine() use by updating "tmp" 1122 * likewise high bandwidth periodic rx 1123 */ 1124 /* Set RXMAXP with the FIFO size of the endpoint 1125 * to disable double buffering mode. 1126 */ 1127 if (musb->double_buffer_not_ok) 1128 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); 1129 else 1130 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz 1131 | (musb_ep->hb_mult << 11)); 1132 1133 /* force shared fifo to OUT-only mode */ 1134 if (hw_ep->is_shared_fifo) { 1135 csr = musb_readw(regs, MUSB_TXCSR); 1136 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); 1137 musb_writew(regs, MUSB_TXCSR, csr); 1138 } 1139 1140 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; 1141 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1142 csr |= MUSB_RXCSR_P_ISO; 1143 else if (musb_ep->type == USB_ENDPOINT_XFER_INT) 1144 csr |= MUSB_RXCSR_DISNYET; 1145 1146 /* set twice in case of double buffering */ 1147 musb_writew(regs, MUSB_RXCSR, csr); 1148 musb_writew(regs, MUSB_RXCSR, csr); 1149 } 1150 1151 /* NOTE: all the I/O code _should_ work fine without DMA, in case 1152 * for some reason you run out of channels here. 1153 */ 1154 if (is_dma_capable() && musb->dma_controller) { 1155 struct dma_controller *c = musb->dma_controller; 1156 1157 musb_ep->dma = c->channel_alloc(c, hw_ep, 1158 (desc->bEndpointAddress & USB_DIR_IN)); 1159 } else 1160 musb_ep->dma = NULL; 1161 1162 musb_ep->desc = desc; 1163 musb_ep->busy = 0; 1164 musb_ep->wedged = 0; 1165 status = 0; 1166 1167 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 1168 musb_driver_name, musb_ep->end_point.name, 1169 ({ char *s; switch (musb_ep->type) { 1170 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; 1171 case USB_ENDPOINT_XFER_INT: s = "int"; break; 1172 default: s = "iso"; break; 1173 }; s; }), 1174 musb_ep->is_in ? "IN" : "OUT", 1175 musb_ep->dma ? "dma, " : "", 1176 musb_ep->packet_sz); 1177 1178 schedule_work(&musb->irq_work); 1179 1180 fail: 1181 spin_unlock_irqrestore(&musb->lock, flags); 1182 return status; 1183 } 1184 1185 /* 1186 * Disable an endpoint flushing all requests queued. 1187 */ 1188 static int musb_gadget_disable(struct usb_ep *ep) 1189 { 1190 unsigned long flags; 1191 struct musb *musb; 1192 u8 epnum; 1193 struct musb_ep *musb_ep; 1194 void __iomem *epio; 1195 int status = 0; 1196 1197 musb_ep = to_musb_ep(ep); 1198 musb = musb_ep->musb; 1199 epnum = musb_ep->current_epnum; 1200 epio = musb->endpoints[epnum].regs; 1201 1202 spin_lock_irqsave(&musb->lock, flags); 1203 musb_ep_select(musb->mregs, epnum); 1204 1205 /* zero the endpoint sizes */ 1206 if (musb_ep->is_in) { 1207 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); 1208 int_txe &= ~(1 << epnum); 1209 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); 1210 musb_writew(epio, MUSB_TXMAXP, 0); 1211 } else { 1212 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); 1213 int_rxe &= ~(1 << epnum); 1214 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); 1215 musb_writew(epio, MUSB_RXMAXP, 0); 1216 } 1217 1218 musb_ep->desc = NULL; 1219 1220 /* abort all pending DMA and requests */ 1221 nuke(musb_ep, -ESHUTDOWN); 1222 1223 schedule_work(&musb->irq_work); 1224 1225 spin_unlock_irqrestore(&(musb->lock), flags); 1226 1227 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); 1228 1229 return status; 1230 } 1231 1232 /* 1233 * Allocate a request for an endpoint. 1234 * Reused by ep0 code. 1235 */ 1236 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1237 { 1238 struct musb_ep *musb_ep = to_musb_ep(ep); 1239 struct musb *musb = musb_ep->musb; 1240 struct musb_request *request = NULL; 1241 1242 request = kzalloc(sizeof *request, gfp_flags); 1243 if (!request) { 1244 dev_dbg(musb->controller, "not enough memory\n"); 1245 return NULL; 1246 } 1247 1248 request->request.dma = DMA_ADDR_INVALID; 1249 request->epnum = musb_ep->current_epnum; 1250 request->ep = musb_ep; 1251 1252 return &request->request; 1253 } 1254 1255 /* 1256 * Free a request 1257 * Reused by ep0 code. 1258 */ 1259 void musb_free_request(struct usb_ep *ep, struct usb_request *req) 1260 { 1261 kfree(to_musb_request(req)); 1262 } 1263 1264 static LIST_HEAD(buffers); 1265 1266 struct free_record { 1267 struct list_head list; 1268 struct device *dev; 1269 unsigned bytes; 1270 dma_addr_t dma; 1271 }; 1272 1273 /* 1274 * Context: controller locked, IRQs blocked. 1275 */ 1276 void musb_ep_restart(struct musb *musb, struct musb_request *req) 1277 { 1278 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", 1279 req->tx ? "TX/IN" : "RX/OUT", 1280 &req->request, req->request.length, req->epnum); 1281 1282 musb_ep_select(musb->mregs, req->epnum); 1283 if (req->tx) 1284 txstate(musb, req); 1285 else 1286 rxstate(musb, req); 1287 } 1288 1289 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, 1290 gfp_t gfp_flags) 1291 { 1292 struct musb_ep *musb_ep; 1293 struct musb_request *request; 1294 struct musb *musb; 1295 int status = 0; 1296 unsigned long lockflags; 1297 1298 if (!ep || !req) 1299 return -EINVAL; 1300 if (!req->buf) 1301 return -ENODATA; 1302 1303 musb_ep = to_musb_ep(ep); 1304 musb = musb_ep->musb; 1305 1306 request = to_musb_request(req); 1307 request->musb = musb; 1308 1309 if (request->ep != musb_ep) 1310 return -EINVAL; 1311 1312 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); 1313 1314 /* request is mine now... */ 1315 request->request.actual = 0; 1316 request->request.status = -EINPROGRESS; 1317 request->epnum = musb_ep->current_epnum; 1318 request->tx = musb_ep->is_in; 1319 1320 map_dma_buffer(request, musb, musb_ep); 1321 1322 spin_lock_irqsave(&musb->lock, lockflags); 1323 1324 /* don't queue if the ep is down */ 1325 if (!musb_ep->desc) { 1326 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", 1327 req, ep->name, "disabled"); 1328 status = -ESHUTDOWN; 1329 goto cleanup; 1330 } 1331 1332 /* add request to the list */ 1333 list_add_tail(&request->list, &musb_ep->req_list); 1334 1335 /* it this is the head of the queue, start i/o ... */ 1336 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) 1337 musb_ep_restart(musb, request); 1338 1339 cleanup: 1340 spin_unlock_irqrestore(&musb->lock, lockflags); 1341 return status; 1342 } 1343 1344 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) 1345 { 1346 struct musb_ep *musb_ep = to_musb_ep(ep); 1347 struct musb_request *req = to_musb_request(request); 1348 struct musb_request *r; 1349 unsigned long flags; 1350 int status = 0; 1351 struct musb *musb = musb_ep->musb; 1352 1353 if (!ep || !request || to_musb_request(request)->ep != musb_ep) 1354 return -EINVAL; 1355 1356 spin_lock_irqsave(&musb->lock, flags); 1357 1358 list_for_each_entry(r, &musb_ep->req_list, list) { 1359 if (r == req) 1360 break; 1361 } 1362 if (r != req) { 1363 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); 1364 status = -EINVAL; 1365 goto done; 1366 } 1367 1368 /* if the hardware doesn't have the request, easy ... */ 1369 if (musb_ep->req_list.next != &req->list || musb_ep->busy) 1370 musb_g_giveback(musb_ep, request, -ECONNRESET); 1371 1372 /* ... else abort the dma transfer ... */ 1373 else if (is_dma_capable() && musb_ep->dma) { 1374 struct dma_controller *c = musb->dma_controller; 1375 1376 musb_ep_select(musb->mregs, musb_ep->current_epnum); 1377 if (c->channel_abort) 1378 status = c->channel_abort(musb_ep->dma); 1379 else 1380 status = -EBUSY; 1381 if (status == 0) 1382 musb_g_giveback(musb_ep, request, -ECONNRESET); 1383 } else { 1384 /* NOTE: by sticking to easily tested hardware/driver states, 1385 * we leave counting of in-flight packets imprecise. 1386 */ 1387 musb_g_giveback(musb_ep, request, -ECONNRESET); 1388 } 1389 1390 done: 1391 spin_unlock_irqrestore(&musb->lock, flags); 1392 return status; 1393 } 1394 1395 /* 1396 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any 1397 * data but will queue requests. 1398 * 1399 * exported to ep0 code 1400 */ 1401 static int musb_gadget_set_halt(struct usb_ep *ep, int value) 1402 { 1403 struct musb_ep *musb_ep = to_musb_ep(ep); 1404 u8 epnum = musb_ep->current_epnum; 1405 struct musb *musb = musb_ep->musb; 1406 void __iomem *epio = musb->endpoints[epnum].regs; 1407 void __iomem *mbase; 1408 unsigned long flags; 1409 u16 csr; 1410 struct musb_request *request; 1411 int status = 0; 1412 1413 if (!ep) 1414 return -EINVAL; 1415 mbase = musb->mregs; 1416 1417 spin_lock_irqsave(&musb->lock, flags); 1418 1419 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { 1420 status = -EINVAL; 1421 goto done; 1422 } 1423 1424 musb_ep_select(mbase, epnum); 1425 1426 request = next_request(musb_ep); 1427 if (value) { 1428 if (request) { 1429 dev_dbg(musb->controller, "request in progress, cannot halt %s\n", 1430 ep->name); 1431 status = -EAGAIN; 1432 goto done; 1433 } 1434 /* Cannot portably stall with non-empty FIFO */ 1435 if (musb_ep->is_in) { 1436 csr = musb_readw(epio, MUSB_TXCSR); 1437 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1438 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); 1439 status = -EAGAIN; 1440 goto done; 1441 } 1442 } 1443 } else 1444 musb_ep->wedged = 0; 1445 1446 /* set/clear the stall and toggle bits */ 1447 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1448 if (musb_ep->is_in) { 1449 csr = musb_readw(epio, MUSB_TXCSR); 1450 csr |= MUSB_TXCSR_P_WZC_BITS 1451 | MUSB_TXCSR_CLRDATATOG; 1452 if (value) 1453 csr |= MUSB_TXCSR_P_SENDSTALL; 1454 else 1455 csr &= ~(MUSB_TXCSR_P_SENDSTALL 1456 | MUSB_TXCSR_P_SENTSTALL); 1457 csr &= ~MUSB_TXCSR_TXPKTRDY; 1458 musb_writew(epio, MUSB_TXCSR, csr); 1459 } else { 1460 csr = musb_readw(epio, MUSB_RXCSR); 1461 csr |= MUSB_RXCSR_P_WZC_BITS 1462 | MUSB_RXCSR_FLUSHFIFO 1463 | MUSB_RXCSR_CLRDATATOG; 1464 if (value) 1465 csr |= MUSB_RXCSR_P_SENDSTALL; 1466 else 1467 csr &= ~(MUSB_RXCSR_P_SENDSTALL 1468 | MUSB_RXCSR_P_SENTSTALL); 1469 musb_writew(epio, MUSB_RXCSR, csr); 1470 } 1471 1472 /* maybe start the first request in the queue */ 1473 if (!musb_ep->busy && !value && request) { 1474 dev_dbg(musb->controller, "restarting the request\n"); 1475 musb_ep_restart(musb, request); 1476 } 1477 1478 done: 1479 spin_unlock_irqrestore(&musb->lock, flags); 1480 return status; 1481 } 1482 1483 /* 1484 * Sets the halt feature with the clear requests ignored 1485 */ 1486 static int musb_gadget_set_wedge(struct usb_ep *ep) 1487 { 1488 struct musb_ep *musb_ep = to_musb_ep(ep); 1489 1490 if (!ep) 1491 return -EINVAL; 1492 1493 musb_ep->wedged = 1; 1494 1495 return usb_ep_set_halt(ep); 1496 } 1497 1498 static int musb_gadget_fifo_status(struct usb_ep *ep) 1499 { 1500 struct musb_ep *musb_ep = to_musb_ep(ep); 1501 void __iomem *epio = musb_ep->hw_ep->regs; 1502 int retval = -EINVAL; 1503 1504 if (musb_ep->desc && !musb_ep->is_in) { 1505 struct musb *musb = musb_ep->musb; 1506 int epnum = musb_ep->current_epnum; 1507 void __iomem *mbase = musb->mregs; 1508 unsigned long flags; 1509 1510 spin_lock_irqsave(&musb->lock, flags); 1511 1512 musb_ep_select(mbase, epnum); 1513 /* FIXME return zero unless RXPKTRDY is set */ 1514 retval = musb_readw(epio, MUSB_RXCOUNT); 1515 1516 spin_unlock_irqrestore(&musb->lock, flags); 1517 } 1518 return retval; 1519 } 1520 1521 static void musb_gadget_fifo_flush(struct usb_ep *ep) 1522 { 1523 struct musb_ep *musb_ep = to_musb_ep(ep); 1524 struct musb *musb = musb_ep->musb; 1525 u8 epnum = musb_ep->current_epnum; 1526 void __iomem *epio = musb->endpoints[epnum].regs; 1527 void __iomem *mbase; 1528 unsigned long flags; 1529 u16 csr, int_txe; 1530 1531 mbase = musb->mregs; 1532 1533 spin_lock_irqsave(&musb->lock, flags); 1534 musb_ep_select(mbase, (u8) epnum); 1535 1536 /* disable interrupts */ 1537 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1538 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 1539 1540 if (musb_ep->is_in) { 1541 csr = musb_readw(epio, MUSB_TXCSR); 1542 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1543 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1544 /* 1545 * Setting both TXPKTRDY and FLUSHFIFO makes controller 1546 * to interrupt current FIFO loading, but not flushing 1547 * the already loaded ones. 1548 */ 1549 csr &= ~MUSB_TXCSR_TXPKTRDY; 1550 musb_writew(epio, MUSB_TXCSR, csr); 1551 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1552 musb_writew(epio, MUSB_TXCSR, csr); 1553 } 1554 } else { 1555 csr = musb_readw(epio, MUSB_RXCSR); 1556 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; 1557 musb_writew(epio, MUSB_RXCSR, csr); 1558 musb_writew(epio, MUSB_RXCSR, csr); 1559 } 1560 1561 /* re-enable interrupt */ 1562 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1563 spin_unlock_irqrestore(&musb->lock, flags); 1564 } 1565 1566 static const struct usb_ep_ops musb_ep_ops = { 1567 .enable = musb_gadget_enable, 1568 .disable = musb_gadget_disable, 1569 .alloc_request = musb_alloc_request, 1570 .free_request = musb_free_request, 1571 .queue = musb_gadget_queue, 1572 .dequeue = musb_gadget_dequeue, 1573 .set_halt = musb_gadget_set_halt, 1574 .set_wedge = musb_gadget_set_wedge, 1575 .fifo_status = musb_gadget_fifo_status, 1576 .fifo_flush = musb_gadget_fifo_flush 1577 }; 1578 1579 /* ----------------------------------------------------------------------- */ 1580 1581 static int musb_gadget_get_frame(struct usb_gadget *gadget) 1582 { 1583 struct musb *musb = gadget_to_musb(gadget); 1584 1585 return (int)musb_readw(musb->mregs, MUSB_FRAME); 1586 } 1587 1588 static int musb_gadget_wakeup(struct usb_gadget *gadget) 1589 { 1590 struct musb *musb = gadget_to_musb(gadget); 1591 void __iomem *mregs = musb->mregs; 1592 unsigned long flags; 1593 int status = -EINVAL; 1594 u8 power, devctl; 1595 int retries; 1596 1597 spin_lock_irqsave(&musb->lock, flags); 1598 1599 switch (musb->xceiv->state) { 1600 case OTG_STATE_B_PERIPHERAL: 1601 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1602 * that's part of the standard usb 1.1 state machine, and 1603 * doesn't affect OTG transitions. 1604 */ 1605 if (musb->may_wakeup && musb->is_suspended) 1606 break; 1607 goto done; 1608 case OTG_STATE_B_IDLE: 1609 /* Start SRP ... OTG not required. */ 1610 devctl = musb_readb(mregs, MUSB_DEVCTL); 1611 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); 1612 devctl |= MUSB_DEVCTL_SESSION; 1613 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1614 devctl = musb_readb(mregs, MUSB_DEVCTL); 1615 retries = 100; 1616 while (!(devctl & MUSB_DEVCTL_SESSION)) { 1617 devctl = musb_readb(mregs, MUSB_DEVCTL); 1618 if (retries-- < 1) 1619 break; 1620 } 1621 retries = 10000; 1622 while (devctl & MUSB_DEVCTL_SESSION) { 1623 devctl = musb_readb(mregs, MUSB_DEVCTL); 1624 if (retries-- < 1) 1625 break; 1626 } 1627 1628 spin_unlock_irqrestore(&musb->lock, flags); 1629 otg_start_srp(musb->xceiv); 1630 spin_lock_irqsave(&musb->lock, flags); 1631 1632 /* Block idling for at least 1s */ 1633 musb_platform_try_idle(musb, 1634 jiffies + msecs_to_jiffies(1 * HZ)); 1635 1636 status = 0; 1637 goto done; 1638 default: 1639 dev_dbg(musb->controller, "Unhandled wake: %s\n", 1640 otg_state_string(musb->xceiv->state)); 1641 goto done; 1642 } 1643 1644 status = 0; 1645 1646 power = musb_readb(mregs, MUSB_POWER); 1647 power |= MUSB_POWER_RESUME; 1648 musb_writeb(mregs, MUSB_POWER, power); 1649 dev_dbg(musb->controller, "issue wakeup\n"); 1650 1651 /* FIXME do this next chunk in a timer callback, no udelay */ 1652 mdelay(2); 1653 1654 power = musb_readb(mregs, MUSB_POWER); 1655 power &= ~MUSB_POWER_RESUME; 1656 musb_writeb(mregs, MUSB_POWER, power); 1657 done: 1658 spin_unlock_irqrestore(&musb->lock, flags); 1659 return status; 1660 } 1661 1662 static int 1663 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) 1664 { 1665 struct musb *musb = gadget_to_musb(gadget); 1666 1667 musb->is_self_powered = !!is_selfpowered; 1668 return 0; 1669 } 1670 1671 static void musb_pullup(struct musb *musb, int is_on) 1672 { 1673 u8 power; 1674 1675 power = musb_readb(musb->mregs, MUSB_POWER); 1676 if (is_on) 1677 power |= MUSB_POWER_SOFTCONN; 1678 else 1679 power &= ~MUSB_POWER_SOFTCONN; 1680 1681 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1682 1683 dev_dbg(musb->controller, "gadget D+ pullup %s\n", 1684 is_on ? "on" : "off"); 1685 musb_writeb(musb->mregs, MUSB_POWER, power); 1686 } 1687 1688 #if 0 1689 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1690 { 1691 dev_dbg(musb->controller, "<= %s =>\n", __func__); 1692 1693 /* 1694 * FIXME iff driver's softconnect flag is set (as it is during probe, 1695 * though that can clear it), just musb_pullup(). 1696 */ 1697 1698 return -EINVAL; 1699 } 1700 #endif 1701 1702 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1703 { 1704 struct musb *musb = gadget_to_musb(gadget); 1705 1706 if (!musb->xceiv->set_power) 1707 return -EOPNOTSUPP; 1708 return otg_set_power(musb->xceiv, mA); 1709 } 1710 1711 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1712 { 1713 struct musb *musb = gadget_to_musb(gadget); 1714 unsigned long flags; 1715 1716 is_on = !!is_on; 1717 1718 pm_runtime_get_sync(musb->controller); 1719 1720 /* NOTE: this assumes we are sensing vbus; we'd rather 1721 * not pullup unless the B-session is active. 1722 */ 1723 spin_lock_irqsave(&musb->lock, flags); 1724 if (is_on != musb->softconnect) { 1725 musb->softconnect = is_on; 1726 musb_pullup(musb, is_on); 1727 } 1728 spin_unlock_irqrestore(&musb->lock, flags); 1729 1730 pm_runtime_put(musb->controller); 1731 1732 return 0; 1733 } 1734 1735 static int musb_gadget_start(struct usb_gadget *g, 1736 struct usb_gadget_driver *driver); 1737 static int musb_gadget_stop(struct usb_gadget *g, 1738 struct usb_gadget_driver *driver); 1739 1740 static const struct usb_gadget_ops musb_gadget_operations = { 1741 .get_frame = musb_gadget_get_frame, 1742 .wakeup = musb_gadget_wakeup, 1743 .set_selfpowered = musb_gadget_set_self_powered, 1744 /* .vbus_session = musb_gadget_vbus_session, */ 1745 .vbus_draw = musb_gadget_vbus_draw, 1746 .pullup = musb_gadget_pullup, 1747 .udc_start = musb_gadget_start, 1748 .udc_stop = musb_gadget_stop, 1749 }; 1750 1751 /* ----------------------------------------------------------------------- */ 1752 1753 /* Registration */ 1754 1755 /* Only this registration code "knows" the rule (from USB standards) 1756 * about there being only one external upstream port. It assumes 1757 * all peripheral ports are external... 1758 */ 1759 1760 static void musb_gadget_release(struct device *dev) 1761 { 1762 /* kref_put(WHAT) */ 1763 dev_dbg(dev, "%s\n", __func__); 1764 } 1765 1766 1767 static void __init 1768 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) 1769 { 1770 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1771 1772 memset(ep, 0, sizeof *ep); 1773 1774 ep->current_epnum = epnum; 1775 ep->musb = musb; 1776 ep->hw_ep = hw_ep; 1777 ep->is_in = is_in; 1778 1779 INIT_LIST_HEAD(&ep->req_list); 1780 1781 sprintf(ep->name, "ep%d%s", epnum, 1782 (!epnum || hw_ep->is_shared_fifo) ? "" : ( 1783 is_in ? "in" : "out")); 1784 ep->end_point.name = ep->name; 1785 INIT_LIST_HEAD(&ep->end_point.ep_list); 1786 if (!epnum) { 1787 ep->end_point.maxpacket = 64; 1788 ep->end_point.ops = &musb_g_ep0_ops; 1789 musb->g.ep0 = &ep->end_point; 1790 } else { 1791 if (is_in) 1792 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; 1793 else 1794 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; 1795 ep->end_point.ops = &musb_ep_ops; 1796 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); 1797 } 1798 } 1799 1800 /* 1801 * Initialize the endpoints exposed to peripheral drivers, with backlinks 1802 * to the rest of the driver state. 1803 */ 1804 static inline void __init musb_g_init_endpoints(struct musb *musb) 1805 { 1806 u8 epnum; 1807 struct musb_hw_ep *hw_ep; 1808 unsigned count = 0; 1809 1810 /* initialize endpoint list just once */ 1811 INIT_LIST_HEAD(&(musb->g.ep_list)); 1812 1813 for (epnum = 0, hw_ep = musb->endpoints; 1814 epnum < musb->nr_endpoints; 1815 epnum++, hw_ep++) { 1816 if (hw_ep->is_shared_fifo /* || !epnum */) { 1817 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); 1818 count++; 1819 } else { 1820 if (hw_ep->max_packet_sz_tx) { 1821 init_peripheral_ep(musb, &hw_ep->ep_in, 1822 epnum, 1); 1823 count++; 1824 } 1825 if (hw_ep->max_packet_sz_rx) { 1826 init_peripheral_ep(musb, &hw_ep->ep_out, 1827 epnum, 0); 1828 count++; 1829 } 1830 } 1831 } 1832 } 1833 1834 /* called once during driver setup to initialize and link into 1835 * the driver model; memory is zeroed. 1836 */ 1837 int __init musb_gadget_setup(struct musb *musb) 1838 { 1839 int status; 1840 1841 /* REVISIT minor race: if (erroneously) setting up two 1842 * musb peripherals at the same time, only the bus lock 1843 * is probably held. 1844 */ 1845 1846 musb->g.ops = &musb_gadget_operations; 1847 musb->g.is_dualspeed = 1; 1848 musb->g.speed = USB_SPEED_UNKNOWN; 1849 1850 /* this "gadget" abstracts/virtualizes the controller */ 1851 dev_set_name(&musb->g.dev, "gadget"); 1852 musb->g.dev.parent = musb->controller; 1853 musb->g.dev.dma_mask = musb->controller->dma_mask; 1854 musb->g.dev.release = musb_gadget_release; 1855 musb->g.name = musb_driver_name; 1856 1857 if (is_otg_enabled(musb)) 1858 musb->g.is_otg = 1; 1859 1860 musb_g_init_endpoints(musb); 1861 1862 musb->is_active = 0; 1863 musb_platform_try_idle(musb, 0); 1864 1865 status = device_register(&musb->g.dev); 1866 if (status != 0) { 1867 put_device(&musb->g.dev); 1868 return status; 1869 } 1870 status = usb_add_gadget_udc(musb->controller, &musb->g); 1871 if (status) 1872 goto err; 1873 1874 return 0; 1875 err: 1876 musb->g.dev.parent = NULL; 1877 device_unregister(&musb->g.dev); 1878 return status; 1879 } 1880 1881 void musb_gadget_cleanup(struct musb *musb) 1882 { 1883 usb_del_gadget_udc(&musb->g); 1884 if (musb->g.dev.parent) 1885 device_unregister(&musb->g.dev); 1886 } 1887 1888 /* 1889 * Register the gadget driver. Used by gadget drivers when 1890 * registering themselves with the controller. 1891 * 1892 * -EINVAL something went wrong (not driver) 1893 * -EBUSY another gadget is already using the controller 1894 * -ENOMEM no memory to perform the operation 1895 * 1896 * @param driver the gadget driver 1897 * @return <0 if error, 0 if everything is fine 1898 */ 1899 static int musb_gadget_start(struct usb_gadget *g, 1900 struct usb_gadget_driver *driver) 1901 { 1902 struct musb *musb = gadget_to_musb(g); 1903 unsigned long flags; 1904 int retval = -EINVAL; 1905 1906 if (driver->speed != USB_SPEED_HIGH) 1907 goto err0; 1908 1909 pm_runtime_get_sync(musb->controller); 1910 1911 dev_dbg(musb->controller, "registering driver %s\n", driver->function); 1912 1913 musb->softconnect = 0; 1914 musb->gadget_driver = driver; 1915 1916 spin_lock_irqsave(&musb->lock, flags); 1917 musb->is_active = 1; 1918 1919 otg_set_peripheral(musb->xceiv, &musb->g); 1920 musb->xceiv->state = OTG_STATE_B_IDLE; 1921 1922 /* 1923 * FIXME this ignores the softconnect flag. Drivers are 1924 * allowed hold the peripheral inactive until for example 1925 * userspace hooks up printer hardware or DSP codecs, so 1926 * hosts only see fully functional devices. 1927 */ 1928 1929 if (!is_otg_enabled(musb)) 1930 musb_start(musb); 1931 1932 spin_unlock_irqrestore(&musb->lock, flags); 1933 1934 if (is_otg_enabled(musb)) { 1935 struct usb_hcd *hcd = musb_to_hcd(musb); 1936 1937 dev_dbg(musb->controller, "OTG startup...\n"); 1938 1939 /* REVISIT: funcall to other code, which also 1940 * handles power budgeting ... this way also 1941 * ensures HdrcStart is indirectly called. 1942 */ 1943 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1944 if (retval < 0) { 1945 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval); 1946 goto err2; 1947 } 1948 1949 if ((musb->xceiv->last_event == USB_EVENT_ID) 1950 && musb->xceiv->set_vbus) 1951 otg_set_vbus(musb->xceiv, 1); 1952 1953 hcd->self.uses_pio_for_control = 1; 1954 } 1955 if (musb->xceiv->last_event == USB_EVENT_NONE) 1956 pm_runtime_put(musb->controller); 1957 1958 return 0; 1959 1960 err2: 1961 if (!is_otg_enabled(musb)) 1962 musb_stop(musb); 1963 err0: 1964 return retval; 1965 } 1966 1967 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) 1968 { 1969 int i; 1970 struct musb_hw_ep *hw_ep; 1971 1972 /* don't disconnect if it's not connected */ 1973 if (musb->g.speed == USB_SPEED_UNKNOWN) 1974 driver = NULL; 1975 else 1976 musb->g.speed = USB_SPEED_UNKNOWN; 1977 1978 /* deactivate the hardware */ 1979 if (musb->softconnect) { 1980 musb->softconnect = 0; 1981 musb_pullup(musb, 0); 1982 } 1983 musb_stop(musb); 1984 1985 /* killing any outstanding requests will quiesce the driver; 1986 * then report disconnect 1987 */ 1988 if (driver) { 1989 for (i = 0, hw_ep = musb->endpoints; 1990 i < musb->nr_endpoints; 1991 i++, hw_ep++) { 1992 musb_ep_select(musb->mregs, i); 1993 if (hw_ep->is_shared_fifo /* || !epnum */) { 1994 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1995 } else { 1996 if (hw_ep->max_packet_sz_tx) 1997 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1998 if (hw_ep->max_packet_sz_rx) 1999 nuke(&hw_ep->ep_out, -ESHUTDOWN); 2000 } 2001 } 2002 2003 spin_unlock(&musb->lock); 2004 driver->disconnect(&musb->g); 2005 spin_lock(&musb->lock); 2006 } 2007 } 2008 2009 /* 2010 * Unregister the gadget driver. Used by gadget drivers when 2011 * unregistering themselves from the controller. 2012 * 2013 * @param driver the gadget driver to unregister 2014 */ 2015 static int musb_gadget_stop(struct usb_gadget *g, 2016 struct usb_gadget_driver *driver) 2017 { 2018 struct musb *musb = gadget_to_musb(g); 2019 unsigned long flags; 2020 2021 if (musb->xceiv->last_event == USB_EVENT_NONE) 2022 pm_runtime_get_sync(musb->controller); 2023 2024 /* 2025 * REVISIT always use otg_set_peripheral() here too; 2026 * this needs to shut down the OTG engine. 2027 */ 2028 2029 spin_lock_irqsave(&musb->lock, flags); 2030 2031 musb_hnp_stop(musb); 2032 2033 (void) musb_gadget_vbus_draw(&musb->g, 0); 2034 2035 musb->xceiv->state = OTG_STATE_UNDEFINED; 2036 stop_activity(musb, driver); 2037 otg_set_peripheral(musb->xceiv, NULL); 2038 2039 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function); 2040 2041 musb->is_active = 0; 2042 musb_platform_try_idle(musb, 0); 2043 spin_unlock_irqrestore(&musb->lock, flags); 2044 2045 if (is_otg_enabled(musb)) { 2046 usb_remove_hcd(musb_to_hcd(musb)); 2047 /* FIXME we need to be able to register another 2048 * gadget driver here and have everything work; 2049 * that currently misbehaves. 2050 */ 2051 } 2052 2053 if (!is_otg_enabled(musb)) 2054 musb_stop(musb); 2055 2056 pm_runtime_put(musb->controller); 2057 2058 return 0; 2059 } 2060 2061 /* ----------------------------------------------------------------------- */ 2062 2063 /* lifecycle operations called through plat_uds.c */ 2064 2065 void musb_g_resume(struct musb *musb) 2066 { 2067 musb->is_suspended = 0; 2068 switch (musb->xceiv->state) { 2069 case OTG_STATE_B_IDLE: 2070 break; 2071 case OTG_STATE_B_WAIT_ACON: 2072 case OTG_STATE_B_PERIPHERAL: 2073 musb->is_active = 1; 2074 if (musb->gadget_driver && musb->gadget_driver->resume) { 2075 spin_unlock(&musb->lock); 2076 musb->gadget_driver->resume(&musb->g); 2077 spin_lock(&musb->lock); 2078 } 2079 break; 2080 default: 2081 WARNING("unhandled RESUME transition (%s)\n", 2082 otg_state_string(musb->xceiv->state)); 2083 } 2084 } 2085 2086 /* called when SOF packets stop for 3+ msec */ 2087 void musb_g_suspend(struct musb *musb) 2088 { 2089 u8 devctl; 2090 2091 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2092 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2093 2094 switch (musb->xceiv->state) { 2095 case OTG_STATE_B_IDLE: 2096 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2097 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2098 break; 2099 case OTG_STATE_B_PERIPHERAL: 2100 musb->is_suspended = 1; 2101 if (musb->gadget_driver && musb->gadget_driver->suspend) { 2102 spin_unlock(&musb->lock); 2103 musb->gadget_driver->suspend(&musb->g); 2104 spin_lock(&musb->lock); 2105 } 2106 break; 2107 default: 2108 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; 2109 * A_PERIPHERAL may need care too 2110 */ 2111 WARNING("unhandled SUSPEND transition (%s)\n", 2112 otg_state_string(musb->xceiv->state)); 2113 } 2114 } 2115 2116 /* Called during SRP */ 2117 void musb_g_wakeup(struct musb *musb) 2118 { 2119 musb_gadget_wakeup(&musb->g); 2120 } 2121 2122 /* called when VBUS drops below session threshold, and in other cases */ 2123 void musb_g_disconnect(struct musb *musb) 2124 { 2125 void __iomem *mregs = musb->mregs; 2126 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2127 2128 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2129 2130 /* clear HR */ 2131 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2132 2133 /* don't draw vbus until new b-default session */ 2134 (void) musb_gadget_vbus_draw(&musb->g, 0); 2135 2136 musb->g.speed = USB_SPEED_UNKNOWN; 2137 if (musb->gadget_driver && musb->gadget_driver->disconnect) { 2138 spin_unlock(&musb->lock); 2139 musb->gadget_driver->disconnect(&musb->g); 2140 spin_lock(&musb->lock); 2141 } 2142 2143 switch (musb->xceiv->state) { 2144 default: 2145 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", 2146 otg_state_string(musb->xceiv->state)); 2147 musb->xceiv->state = OTG_STATE_A_IDLE; 2148 MUSB_HST_MODE(musb); 2149 break; 2150 case OTG_STATE_A_PERIPHERAL: 2151 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2152 MUSB_HST_MODE(musb); 2153 break; 2154 case OTG_STATE_B_WAIT_ACON: 2155 case OTG_STATE_B_HOST: 2156 case OTG_STATE_B_PERIPHERAL: 2157 case OTG_STATE_B_IDLE: 2158 musb->xceiv->state = OTG_STATE_B_IDLE; 2159 break; 2160 case OTG_STATE_B_SRP_INIT: 2161 break; 2162 } 2163 2164 musb->is_active = 0; 2165 } 2166 2167 void musb_g_reset(struct musb *musb) 2168 __releases(musb->lock) 2169 __acquires(musb->lock) 2170 { 2171 void __iomem *mbase = musb->mregs; 2172 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2173 u8 power; 2174 2175 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n", 2176 (devctl & MUSB_DEVCTL_BDEVICE) 2177 ? "B-Device" : "A-Device", 2178 musb_readb(mbase, MUSB_FADDR), 2179 musb->gadget_driver 2180 ? musb->gadget_driver->driver.name 2181 : NULL 2182 ); 2183 2184 /* report disconnect, if we didn't already (flushing EP state) */ 2185 if (musb->g.speed != USB_SPEED_UNKNOWN) 2186 musb_g_disconnect(musb); 2187 2188 /* clear HR */ 2189 else if (devctl & MUSB_DEVCTL_HR) 2190 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 2191 2192 2193 /* what speed did we negotiate? */ 2194 power = musb_readb(mbase, MUSB_POWER); 2195 musb->g.speed = (power & MUSB_POWER_HSMODE) 2196 ? USB_SPEED_HIGH : USB_SPEED_FULL; 2197 2198 /* start in USB_STATE_DEFAULT */ 2199 musb->is_active = 1; 2200 musb->is_suspended = 0; 2201 MUSB_DEV_MODE(musb); 2202 musb->address = 0; 2203 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 2204 2205 musb->may_wakeup = 0; 2206 musb->g.b_hnp_enable = 0; 2207 musb->g.a_alt_hnp_support = 0; 2208 musb->g.a_hnp_support = 0; 2209 2210 /* Normal reset, as B-Device; 2211 * or else after HNP, as A-Device 2212 */ 2213 if (devctl & MUSB_DEVCTL_BDEVICE) { 2214 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2215 musb->g.is_a_peripheral = 0; 2216 } else if (is_otg_enabled(musb)) { 2217 musb->xceiv->state = OTG_STATE_A_PERIPHERAL; 2218 musb->g.is_a_peripheral = 1; 2219 } else 2220 WARN_ON(1); 2221 2222 /* start with default limits on VBUS power draw */ 2223 (void) musb_gadget_vbus_draw(&musb->g, 2224 is_otg_enabled(musb) ? 8 : 100); 2225 } 2226