1 /* 2 * MUSB OTG driver peripheral support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/list.h> 38 #include <linux/timer.h> 39 #include <linux/module.h> 40 #include <linux/smp.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 46 #include "musb_core.h" 47 48 49 /* MUSB PERIPHERAL status 3-mar-2006: 50 * 51 * - EP0 seems solid. It passes both USBCV and usbtest control cases. 52 * Minor glitches: 53 * 54 * + remote wakeup to Linux hosts work, but saw USBCV failures; 55 * in one test run (operator error?) 56 * + endpoint halt tests -- in both usbtest and usbcv -- seem 57 * to break when dma is enabled ... is something wrongly 58 * clearing SENDSTALL? 59 * 60 * - Mass storage behaved ok when last tested. Network traffic patterns 61 * (with lots of short transfers etc) need retesting; they turn up the 62 * worst cases of the DMA, since short packets are typical but are not 63 * required. 64 * 65 * - TX/IN 66 * + both pio and dma behave in with network and g_zero tests 67 * + no cppi throughput issues other than no-hw-queueing 68 * + failed with FLAT_REG (DaVinci) 69 * + seems to behave with double buffering, PIO -and- CPPI 70 * + with gadgetfs + AIO, requests got lost? 71 * 72 * - RX/OUT 73 * + both pio and dma behave in with network and g_zero tests 74 * + dma is slow in typical case (short_not_ok is clear) 75 * + double buffering ok with PIO 76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes 77 * + request lossage observed with gadgetfs 78 * 79 * - ISO not tested ... might work, but only weakly isochronous 80 * 81 * - Gadget driver disabling of softconnect during bind() is ignored; so 82 * drivers can't hold off host requests until userspace is ready. 83 * (Workaround: they can turn it off later.) 84 * 85 * - PORTABILITY (assumes PIO works): 86 * + DaVinci, basically works with cppi dma 87 * + OMAP 2430, ditto with mentor dma 88 * + TUSB 6010, platform-specific dma in the works 89 */ 90 91 /* ----------------------------------------------------------------------- */ 92 93 #define is_buffer_mapped(req) (is_dma_capable() && \ 94 (req->map_state != UN_MAPPED)) 95 96 /* Maps the buffer to dma */ 97 98 static inline void map_dma_buffer(struct musb_request *request, 99 struct musb *musb, struct musb_ep *musb_ep) 100 { 101 int compatible = true; 102 struct dma_controller *dma = musb->dma_controller; 103 104 request->map_state = UN_MAPPED; 105 106 if (!is_dma_capable() || !musb_ep->dma) 107 return; 108 109 /* Check if DMA engine can handle this request. 110 * DMA code must reject the USB request explicitly. 111 * Default behaviour is to map the request. 112 */ 113 if (dma->is_compatible) 114 compatible = dma->is_compatible(musb_ep->dma, 115 musb_ep->packet_sz, request->request.buf, 116 request->request.length); 117 if (!compatible) 118 return; 119 120 if (request->request.dma == DMA_ADDR_INVALID) { 121 request->request.dma = dma_map_single( 122 musb->controller, 123 request->request.buf, 124 request->request.length, 125 request->tx 126 ? DMA_TO_DEVICE 127 : DMA_FROM_DEVICE); 128 request->map_state = MUSB_MAPPED; 129 } else { 130 dma_sync_single_for_device(musb->controller, 131 request->request.dma, 132 request->request.length, 133 request->tx 134 ? DMA_TO_DEVICE 135 : DMA_FROM_DEVICE); 136 request->map_state = PRE_MAPPED; 137 } 138 } 139 140 /* Unmap the buffer from dma and maps it back to cpu */ 141 static inline void unmap_dma_buffer(struct musb_request *request, 142 struct musb *musb) 143 { 144 if (!is_buffer_mapped(request)) 145 return; 146 147 if (request->request.dma == DMA_ADDR_INVALID) { 148 dev_vdbg(musb->controller, 149 "not unmapping a never mapped buffer\n"); 150 return; 151 } 152 if (request->map_state == MUSB_MAPPED) { 153 dma_unmap_single(musb->controller, 154 request->request.dma, 155 request->request.length, 156 request->tx 157 ? DMA_TO_DEVICE 158 : DMA_FROM_DEVICE); 159 request->request.dma = DMA_ADDR_INVALID; 160 } else { /* PRE_MAPPED */ 161 dma_sync_single_for_cpu(musb->controller, 162 request->request.dma, 163 request->request.length, 164 request->tx 165 ? DMA_TO_DEVICE 166 : DMA_FROM_DEVICE); 167 } 168 request->map_state = UN_MAPPED; 169 } 170 171 /* 172 * Immediately complete a request. 173 * 174 * @param request the request to complete 175 * @param status the status to complete the request with 176 * Context: controller locked, IRQs blocked. 177 */ 178 void musb_g_giveback( 179 struct musb_ep *ep, 180 struct usb_request *request, 181 int status) 182 __releases(ep->musb->lock) 183 __acquires(ep->musb->lock) 184 { 185 struct musb_request *req; 186 struct musb *musb; 187 int busy = ep->busy; 188 189 req = to_musb_request(request); 190 191 list_del(&req->list); 192 if (req->request.status == -EINPROGRESS) 193 req->request.status = status; 194 musb = req->musb; 195 196 ep->busy = 1; 197 spin_unlock(&musb->lock); 198 unmap_dma_buffer(req, musb); 199 if (request->status == 0) 200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n", 201 ep->end_point.name, request, 202 req->request.actual, req->request.length); 203 else 204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", 205 ep->end_point.name, request, 206 req->request.actual, req->request.length, 207 request->status); 208 req->request.complete(&req->ep->end_point, &req->request); 209 spin_lock(&musb->lock); 210 ep->busy = busy; 211 } 212 213 /* ----------------------------------------------------------------------- */ 214 215 /* 216 * Abort requests queued to an endpoint using the status. Synchronous. 217 * caller locked controller and blocked irqs, and selected this ep. 218 */ 219 static void nuke(struct musb_ep *ep, const int status) 220 { 221 struct musb *musb = ep->musb; 222 struct musb_request *req = NULL; 223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 224 225 ep->busy = 1; 226 227 if (is_dma_capable() && ep->dma) { 228 struct dma_controller *c = ep->musb->dma_controller; 229 int value; 230 231 if (ep->is_in) { 232 /* 233 * The programming guide says that we must not clear 234 * the DMAMODE bit before DMAENAB, so we only 235 * clear it in the second write... 236 */ 237 musb_writew(epio, MUSB_TXCSR, 238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); 239 musb_writew(epio, MUSB_TXCSR, 240 0 | MUSB_TXCSR_FLUSHFIFO); 241 } else { 242 musb_writew(epio, MUSB_RXCSR, 243 0 | MUSB_RXCSR_FLUSHFIFO); 244 musb_writew(epio, MUSB_RXCSR, 245 0 | MUSB_RXCSR_FLUSHFIFO); 246 } 247 248 value = c->channel_abort(ep->dma); 249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n", 250 ep->name, value); 251 c->channel_release(ep->dma); 252 ep->dma = NULL; 253 } 254 255 while (!list_empty(&ep->req_list)) { 256 req = list_first_entry(&ep->req_list, struct musb_request, list); 257 musb_g_giveback(ep, &req->request, status); 258 } 259 } 260 261 /* ----------------------------------------------------------------------- */ 262 263 /* Data transfers - pure PIO, pure DMA, or mixed mode */ 264 265 /* 266 * This assumes the separate CPPI engine is responding to DMA requests 267 * from the usb core ... sequenced a bit differently from mentor dma. 268 */ 269 270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) 271 { 272 if (can_bulk_split(musb, ep->type)) 273 return ep->hw_ep->max_packet_sz_tx; 274 else 275 return ep->packet_sz; 276 } 277 278 279 #ifdef CONFIG_USB_INVENTRA_DMA 280 281 /* Peripheral tx (IN) using Mentor DMA works as follows: 282 Only mode 0 is used for transfers <= wPktSize, 283 mode 1 is used for larger transfers, 284 285 One of the following happens: 286 - Host sends IN token which causes an endpoint interrupt 287 -> TxAvail 288 -> if DMA is currently busy, exit. 289 -> if queue is non-empty, txstate(). 290 291 - Request is queued by the gadget driver. 292 -> if queue was previously empty, txstate() 293 294 txstate() 295 -> start 296 /\ -> setup DMA 297 | (data is transferred to the FIFO, then sent out when 298 | IN token(s) are recd from Host. 299 | -> DMA interrupt on completion 300 | calls TxAvail. 301 | -> stop DMA, ~DMAENAB, 302 | -> set TxPktRdy for last short pkt or zlp 303 | -> Complete Request 304 | -> Continue next request (call txstate) 305 |___________________________________| 306 307 * Non-Mentor DMA engines can of course work differently, such as by 308 * upleveling from irq-per-packet to irq-per-buffer. 309 */ 310 311 #endif 312 313 /* 314 * An endpoint is transmitting data. This can be called either from 315 * the IRQ routine or from ep.queue() to kickstart a request on an 316 * endpoint. 317 * 318 * Context: controller locked, IRQs blocked, endpoint selected 319 */ 320 static void txstate(struct musb *musb, struct musb_request *req) 321 { 322 u8 epnum = req->epnum; 323 struct musb_ep *musb_ep; 324 void __iomem *epio = musb->endpoints[epnum].regs; 325 struct usb_request *request; 326 u16 fifo_count = 0, csr; 327 int use_dma = 0; 328 329 musb_ep = req->ep; 330 331 /* we shouldn't get here while DMA is active ... but we do ... */ 332 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 333 dev_dbg(musb->controller, "dma pending...\n"); 334 return; 335 } 336 337 /* read TXCSR before */ 338 csr = musb_readw(epio, MUSB_TXCSR); 339 340 request = &req->request; 341 fifo_count = min(max_ep_writesize(musb, musb_ep), 342 (int)(request->length - request->actual)); 343 344 if (csr & MUSB_TXCSR_TXPKTRDY) { 345 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", 346 musb_ep->end_point.name, csr); 347 return; 348 } 349 350 if (csr & MUSB_TXCSR_P_SENDSTALL) { 351 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", 352 musb_ep->end_point.name, csr); 353 return; 354 } 355 356 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 357 epnum, musb_ep->packet_sz, fifo_count, 358 csr); 359 360 #ifndef CONFIG_MUSB_PIO_ONLY 361 if (is_buffer_mapped(req)) { 362 struct dma_controller *c = musb->dma_controller; 363 size_t request_size; 364 365 /* setup DMA, then program endpoint CSR */ 366 request_size = min_t(size_t, request->length - request->actual, 367 musb_ep->dma->max_len); 368 369 use_dma = (request->dma != DMA_ADDR_INVALID); 370 371 /* MUSB_TXCSR_P_ISO is still set correctly */ 372 373 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 374 { 375 if (request_size < musb_ep->packet_sz) 376 musb_ep->dma->desired_mode = 0; 377 else 378 musb_ep->dma->desired_mode = 1; 379 380 use_dma = use_dma && c->channel_program( 381 musb_ep->dma, musb_ep->packet_sz, 382 musb_ep->dma->desired_mode, 383 request->dma + request->actual, request_size); 384 if (use_dma) { 385 if (musb_ep->dma->desired_mode == 0) { 386 /* 387 * We must not clear the DMAMODE bit 388 * before the DMAENAB bit -- and the 389 * latter doesn't always get cleared 390 * before we get here... 391 */ 392 csr &= ~(MUSB_TXCSR_AUTOSET 393 | MUSB_TXCSR_DMAENAB); 394 musb_writew(epio, MUSB_TXCSR, csr 395 | MUSB_TXCSR_P_WZC_BITS); 396 csr &= ~MUSB_TXCSR_DMAMODE; 397 csr |= (MUSB_TXCSR_DMAENAB | 398 MUSB_TXCSR_MODE); 399 /* against programming guide */ 400 } else { 401 csr |= (MUSB_TXCSR_DMAENAB 402 | MUSB_TXCSR_DMAMODE 403 | MUSB_TXCSR_MODE); 404 if (!musb_ep->hb_mult) 405 csr |= MUSB_TXCSR_AUTOSET; 406 } 407 csr &= ~MUSB_TXCSR_P_UNDERRUN; 408 409 musb_writew(epio, MUSB_TXCSR, csr); 410 } 411 } 412 413 #elif defined(CONFIG_USB_TI_CPPI_DMA) 414 /* program endpoint CSR first, then setup DMA */ 415 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 416 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | 417 MUSB_TXCSR_MODE; 418 musb_writew(epio, MUSB_TXCSR, 419 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) 420 | csr); 421 422 /* ensure writebuffer is empty */ 423 csr = musb_readw(epio, MUSB_TXCSR); 424 425 /* NOTE host side sets DMAENAB later than this; both are 426 * OK since the transfer dma glue (between CPPI and Mentor 427 * fifos) just tells CPPI it could start. Data only moves 428 * to the USB TX fifo when both fifos are ready. 429 */ 430 431 /* "mode" is irrelevant here; handle terminating ZLPs like 432 * PIO does, since the hardware RNDIS mode seems unreliable 433 * except for the last-packet-is-already-short case. 434 */ 435 use_dma = use_dma && c->channel_program( 436 musb_ep->dma, musb_ep->packet_sz, 437 0, 438 request->dma + request->actual, 439 request_size); 440 if (!use_dma) { 441 c->channel_release(musb_ep->dma); 442 musb_ep->dma = NULL; 443 csr &= ~MUSB_TXCSR_DMAENAB; 444 musb_writew(epio, MUSB_TXCSR, csr); 445 /* invariant: prequest->buf is non-null */ 446 } 447 #elif defined(CONFIG_USB_TUSB_OMAP_DMA) 448 use_dma = use_dma && c->channel_program( 449 musb_ep->dma, musb_ep->packet_sz, 450 request->zero, 451 request->dma + request->actual, 452 request_size); 453 #endif 454 } 455 #endif 456 457 if (!use_dma) { 458 /* 459 * Unmap the dma buffer back to cpu if dma channel 460 * programming fails 461 */ 462 unmap_dma_buffer(req, musb); 463 464 musb_write_fifo(musb_ep->hw_ep, fifo_count, 465 (u8 *) (request->buf + request->actual)); 466 request->actual += fifo_count; 467 csr |= MUSB_TXCSR_TXPKTRDY; 468 csr &= ~MUSB_TXCSR_P_UNDERRUN; 469 musb_writew(epio, MUSB_TXCSR, csr); 470 } 471 472 /* host may already have the data when this message shows... */ 473 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 474 musb_ep->end_point.name, use_dma ? "dma" : "pio", 475 request->actual, request->length, 476 musb_readw(epio, MUSB_TXCSR), 477 fifo_count, 478 musb_readw(epio, MUSB_TXMAXP)); 479 } 480 481 /* 482 * FIFO state update (e.g. data ready). 483 * Called from IRQ, with controller locked. 484 */ 485 void musb_g_tx(struct musb *musb, u8 epnum) 486 { 487 u16 csr; 488 struct musb_request *req; 489 struct usb_request *request; 490 u8 __iomem *mbase = musb->mregs; 491 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; 492 void __iomem *epio = musb->endpoints[epnum].regs; 493 struct dma_channel *dma; 494 495 musb_ep_select(mbase, epnum); 496 req = next_request(musb_ep); 497 request = &req->request; 498 499 csr = musb_readw(epio, MUSB_TXCSR); 500 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 501 502 dma = is_dma_capable() ? musb_ep->dma : NULL; 503 504 /* 505 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX 506 * probably rates reporting as a host error. 507 */ 508 if (csr & MUSB_TXCSR_P_SENTSTALL) { 509 csr |= MUSB_TXCSR_P_WZC_BITS; 510 csr &= ~MUSB_TXCSR_P_SENTSTALL; 511 musb_writew(epio, MUSB_TXCSR, csr); 512 return; 513 } 514 515 if (csr & MUSB_TXCSR_P_UNDERRUN) { 516 /* We NAKed, no big deal... little reason to care. */ 517 csr |= MUSB_TXCSR_P_WZC_BITS; 518 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 519 musb_writew(epio, MUSB_TXCSR, csr); 520 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", 521 epnum, request); 522 } 523 524 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 525 /* 526 * SHOULD NOT HAPPEN... has with CPPI though, after 527 * changing SENDSTALL (and other cases); harmless? 528 */ 529 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); 530 return; 531 } 532 533 if (request) { 534 u8 is_dma = 0; 535 536 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 537 is_dma = 1; 538 csr |= MUSB_TXCSR_P_WZC_BITS; 539 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | 540 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); 541 musb_writew(epio, MUSB_TXCSR, csr); 542 /* Ensure writebuffer is empty. */ 543 csr = musb_readw(epio, MUSB_TXCSR); 544 request->actual += musb_ep->dma->actual_len; 545 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 546 epnum, csr, musb_ep->dma->actual_len, request); 547 } 548 549 /* 550 * First, maybe a terminating short packet. Some DMA 551 * engines might handle this by themselves. 552 */ 553 if ((request->zero && request->length 554 && (request->length % musb_ep->packet_sz == 0) 555 && (request->actual == request->length)) 556 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 557 || (is_dma && (!dma->desired_mode || 558 (request->actual & 559 (musb_ep->packet_sz - 1)))) 560 #endif 561 ) { 562 /* 563 * On DMA completion, FIFO may not be 564 * available yet... 565 */ 566 if (csr & MUSB_TXCSR_TXPKTRDY) 567 return; 568 569 dev_dbg(musb->controller, "sending zero pkt\n"); 570 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 571 | MUSB_TXCSR_TXPKTRDY); 572 request->zero = 0; 573 } 574 575 if (request->actual == request->length) { 576 musb_g_giveback(musb_ep, request, 0); 577 req = musb_ep->desc ? next_request(musb_ep) : NULL; 578 if (!req) { 579 dev_dbg(musb->controller, "%s idle now\n", 580 musb_ep->end_point.name); 581 return; 582 } 583 } 584 585 txstate(musb, req); 586 } 587 } 588 589 /* ------------------------------------------------------------ */ 590 591 #ifdef CONFIG_USB_INVENTRA_DMA 592 593 /* Peripheral rx (OUT) using Mentor DMA works as follows: 594 - Only mode 0 is used. 595 596 - Request is queued by the gadget class driver. 597 -> if queue was previously empty, rxstate() 598 599 - Host sends OUT token which causes an endpoint interrupt 600 /\ -> RxReady 601 | -> if request queued, call rxstate 602 | /\ -> setup DMA 603 | | -> DMA interrupt on completion 604 | | -> RxReady 605 | | -> stop DMA 606 | | -> ack the read 607 | | -> if data recd = max expected 608 | | by the request, or host 609 | | sent a short packet, 610 | | complete the request, 611 | | and start the next one. 612 | |_____________________________________| 613 | else just wait for the host 614 | to send the next OUT token. 615 |__________________________________________________| 616 617 * Non-Mentor DMA engines can of course work differently. 618 */ 619 620 #endif 621 622 /* 623 * Context: controller locked, IRQs blocked, endpoint selected 624 */ 625 static void rxstate(struct musb *musb, struct musb_request *req) 626 { 627 const u8 epnum = req->epnum; 628 struct usb_request *request = &req->request; 629 struct musb_ep *musb_ep; 630 void __iomem *epio = musb->endpoints[epnum].regs; 631 unsigned fifo_count = 0; 632 u16 len; 633 u16 csr = musb_readw(epio, MUSB_RXCSR); 634 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 635 u8 use_mode_1; 636 637 if (hw_ep->is_shared_fifo) 638 musb_ep = &hw_ep->ep_in; 639 else 640 musb_ep = &hw_ep->ep_out; 641 642 len = musb_ep->packet_sz; 643 644 /* We shouldn't get here while DMA is active, but we do... */ 645 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 646 dev_dbg(musb->controller, "DMA pending...\n"); 647 return; 648 } 649 650 if (csr & MUSB_RXCSR_P_SENDSTALL) { 651 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", 652 musb_ep->end_point.name, csr); 653 return; 654 } 655 656 if (is_cppi_enabled() && is_buffer_mapped(req)) { 657 struct dma_controller *c = musb->dma_controller; 658 struct dma_channel *channel = musb_ep->dma; 659 660 /* NOTE: CPPI won't actually stop advancing the DMA 661 * queue after short packet transfers, so this is almost 662 * always going to run as IRQ-per-packet DMA so that 663 * faults will be handled correctly. 664 */ 665 if (c->channel_program(channel, 666 musb_ep->packet_sz, 667 !request->short_not_ok, 668 request->dma + request->actual, 669 request->length - request->actual)) { 670 671 /* make sure that if an rxpkt arrived after the irq, 672 * the cppi engine will be ready to take it as soon 673 * as DMA is enabled 674 */ 675 csr &= ~(MUSB_RXCSR_AUTOCLEAR 676 | MUSB_RXCSR_DMAMODE); 677 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; 678 musb_writew(epio, MUSB_RXCSR, csr); 679 return; 680 } 681 } 682 683 if (csr & MUSB_RXCSR_RXPKTRDY) { 684 len = musb_readw(epio, MUSB_RXCOUNT); 685 686 /* 687 * Enable Mode 1 on RX transfers only when short_not_ok flag 688 * is set. Currently short_not_ok flag is set only from 689 * file_storage and f_mass_storage drivers 690 */ 691 692 if (request->short_not_ok && len == musb_ep->packet_sz) 693 use_mode_1 = 1; 694 else 695 use_mode_1 = 0; 696 697 if (request->actual < request->length) { 698 #ifdef CONFIG_USB_INVENTRA_DMA 699 if (is_buffer_mapped(req)) { 700 struct dma_controller *c; 701 struct dma_channel *channel; 702 int use_dma = 0; 703 704 c = musb->dma_controller; 705 channel = musb_ep->dma; 706 707 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in 708 * mode 0 only. So we do not get endpoint interrupts due to DMA 709 * completion. We only get interrupts from DMA controller. 710 * 711 * We could operate in DMA mode 1 if we knew the size of the tranfer 712 * in advance. For mass storage class, request->length = what the host 713 * sends, so that'd work. But for pretty much everything else, 714 * request->length is routinely more than what the host sends. For 715 * most these gadgets, end of is signified either by a short packet, 716 * or filling the last byte of the buffer. (Sending extra data in 717 * that last pckate should trigger an overflow fault.) But in mode 1, 718 * we don't get DMA completion interrupt for short packets. 719 * 720 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), 721 * to get endpoint interrupt on every DMA req, but that didn't seem 722 * to work reliably. 723 * 724 * REVISIT an updated g_file_storage can set req->short_not_ok, which 725 * then becomes usable as a runtime "use mode 1" hint... 726 */ 727 728 /* Experimental: Mode1 works with mass storage use cases */ 729 if (use_mode_1) { 730 csr |= MUSB_RXCSR_AUTOCLEAR; 731 musb_writew(epio, MUSB_RXCSR, csr); 732 csr |= MUSB_RXCSR_DMAENAB; 733 musb_writew(epio, MUSB_RXCSR, csr); 734 735 /* 736 * this special sequence (enabling and then 737 * disabling MUSB_RXCSR_DMAMODE) is required 738 * to get DMAReq to activate 739 */ 740 musb_writew(epio, MUSB_RXCSR, 741 csr | MUSB_RXCSR_DMAMODE); 742 musb_writew(epio, MUSB_RXCSR, csr); 743 744 } else { 745 if (!musb_ep->hb_mult && 746 musb_ep->hw_ep->rx_double_buffered) 747 csr |= MUSB_RXCSR_AUTOCLEAR; 748 csr |= MUSB_RXCSR_DMAENAB; 749 musb_writew(epio, MUSB_RXCSR, csr); 750 } 751 752 if (request->actual < request->length) { 753 int transfer_size = 0; 754 if (use_mode_1) { 755 transfer_size = min(request->length - request->actual, 756 channel->max_len); 757 musb_ep->dma->desired_mode = 1; 758 } else { 759 transfer_size = min(request->length - request->actual, 760 (unsigned)len); 761 musb_ep->dma->desired_mode = 0; 762 } 763 764 use_dma = c->channel_program( 765 channel, 766 musb_ep->packet_sz, 767 channel->desired_mode, 768 request->dma 769 + request->actual, 770 transfer_size); 771 } 772 773 if (use_dma) 774 return; 775 } 776 #elif defined(CONFIG_USB_UX500_DMA) 777 if ((is_buffer_mapped(req)) && 778 (request->actual < request->length)) { 779 780 struct dma_controller *c; 781 struct dma_channel *channel; 782 int transfer_size = 0; 783 784 c = musb->dma_controller; 785 channel = musb_ep->dma; 786 787 /* In case first packet is short */ 788 if (len < musb_ep->packet_sz) 789 transfer_size = len; 790 else if (request->short_not_ok) 791 transfer_size = min(request->length - 792 request->actual, 793 channel->max_len); 794 else 795 transfer_size = min(request->length - 796 request->actual, 797 (unsigned)len); 798 799 csr &= ~MUSB_RXCSR_DMAMODE; 800 csr |= (MUSB_RXCSR_DMAENAB | 801 MUSB_RXCSR_AUTOCLEAR); 802 803 musb_writew(epio, MUSB_RXCSR, csr); 804 805 if (transfer_size <= musb_ep->packet_sz) { 806 musb_ep->dma->desired_mode = 0; 807 } else { 808 musb_ep->dma->desired_mode = 1; 809 /* Mode must be set after DMAENAB */ 810 csr |= MUSB_RXCSR_DMAMODE; 811 musb_writew(epio, MUSB_RXCSR, csr); 812 } 813 814 if (c->channel_program(channel, 815 musb_ep->packet_sz, 816 channel->desired_mode, 817 request->dma 818 + request->actual, 819 transfer_size)) 820 821 return; 822 } 823 #endif /* Mentor's DMA */ 824 825 fifo_count = request->length - request->actual; 826 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 827 musb_ep->end_point.name, 828 len, fifo_count, 829 musb_ep->packet_sz); 830 831 fifo_count = min_t(unsigned, len, fifo_count); 832 833 #ifdef CONFIG_USB_TUSB_OMAP_DMA 834 if (tusb_dma_omap() && is_buffer_mapped(req)) { 835 struct dma_controller *c = musb->dma_controller; 836 struct dma_channel *channel = musb_ep->dma; 837 u32 dma_addr = request->dma + request->actual; 838 int ret; 839 840 ret = c->channel_program(channel, 841 musb_ep->packet_sz, 842 channel->desired_mode, 843 dma_addr, 844 fifo_count); 845 if (ret) 846 return; 847 } 848 #endif 849 /* 850 * Unmap the dma buffer back to cpu if dma channel 851 * programming fails. This buffer is mapped if the 852 * channel allocation is successful 853 */ 854 if (is_buffer_mapped(req)) { 855 unmap_dma_buffer(req, musb); 856 857 /* 858 * Clear DMAENAB and AUTOCLEAR for the 859 * PIO mode transfer 860 */ 861 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); 862 musb_writew(epio, MUSB_RXCSR, csr); 863 } 864 865 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) 866 (request->buf + request->actual)); 867 request->actual += fifo_count; 868 869 /* REVISIT if we left anything in the fifo, flush 870 * it and report -EOVERFLOW 871 */ 872 873 /* ack the read! */ 874 csr |= MUSB_RXCSR_P_WZC_BITS; 875 csr &= ~MUSB_RXCSR_RXPKTRDY; 876 musb_writew(epio, MUSB_RXCSR, csr); 877 } 878 } 879 880 /* reach the end or short packet detected */ 881 if (request->actual == request->length || len < musb_ep->packet_sz) 882 musb_g_giveback(musb_ep, request, 0); 883 } 884 885 /* 886 * Data ready for a request; called from IRQ 887 */ 888 void musb_g_rx(struct musb *musb, u8 epnum) 889 { 890 u16 csr; 891 struct musb_request *req; 892 struct usb_request *request; 893 void __iomem *mbase = musb->mregs; 894 struct musb_ep *musb_ep; 895 void __iomem *epio = musb->endpoints[epnum].regs; 896 struct dma_channel *dma; 897 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 898 899 if (hw_ep->is_shared_fifo) 900 musb_ep = &hw_ep->ep_in; 901 else 902 musb_ep = &hw_ep->ep_out; 903 904 musb_ep_select(mbase, epnum); 905 906 req = next_request(musb_ep); 907 if (!req) 908 return; 909 910 request = &req->request; 911 912 csr = musb_readw(epio, MUSB_RXCSR); 913 dma = is_dma_capable() ? musb_ep->dma : NULL; 914 915 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 916 csr, dma ? " (dma)" : "", request); 917 918 if (csr & MUSB_RXCSR_P_SENTSTALL) { 919 csr |= MUSB_RXCSR_P_WZC_BITS; 920 csr &= ~MUSB_RXCSR_P_SENTSTALL; 921 musb_writew(epio, MUSB_RXCSR, csr); 922 return; 923 } 924 925 if (csr & MUSB_RXCSR_P_OVERRUN) { 926 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ 927 csr &= ~MUSB_RXCSR_P_OVERRUN; 928 musb_writew(epio, MUSB_RXCSR, csr); 929 930 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); 931 if (request->status == -EINPROGRESS) 932 request->status = -EOVERFLOW; 933 } 934 if (csr & MUSB_RXCSR_INCOMPRX) { 935 /* REVISIT not necessarily an error */ 936 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); 937 } 938 939 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 940 /* "should not happen"; likely RXPKTRDY pending for DMA */ 941 dev_dbg(musb->controller, "%s busy, csr %04x\n", 942 musb_ep->end_point.name, csr); 943 return; 944 } 945 946 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { 947 csr &= ~(MUSB_RXCSR_AUTOCLEAR 948 | MUSB_RXCSR_DMAENAB 949 | MUSB_RXCSR_DMAMODE); 950 musb_writew(epio, MUSB_RXCSR, 951 MUSB_RXCSR_P_WZC_BITS | csr); 952 953 request->actual += musb_ep->dma->actual_len; 954 955 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 956 epnum, csr, 957 musb_readw(epio, MUSB_RXCSR), 958 musb_ep->dma->actual_len, request); 959 960 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 961 defined(CONFIG_USB_UX500_DMA) 962 /* Autoclear doesn't clear RxPktRdy for short packets */ 963 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) 964 || (dma->actual_len 965 & (musb_ep->packet_sz - 1))) { 966 /* ack the read! */ 967 csr &= ~MUSB_RXCSR_RXPKTRDY; 968 musb_writew(epio, MUSB_RXCSR, csr); 969 } 970 971 /* incomplete, and not short? wait for next IN packet */ 972 if ((request->actual < request->length) 973 && (musb_ep->dma->actual_len 974 == musb_ep->packet_sz)) { 975 /* In double buffer case, continue to unload fifo if 976 * there is Rx packet in FIFO. 977 **/ 978 csr = musb_readw(epio, MUSB_RXCSR); 979 if ((csr & MUSB_RXCSR_RXPKTRDY) && 980 hw_ep->rx_double_buffered) 981 goto exit; 982 return; 983 } 984 #endif 985 musb_g_giveback(musb_ep, request, 0); 986 987 req = next_request(musb_ep); 988 if (!req) 989 return; 990 } 991 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 992 defined(CONFIG_USB_UX500_DMA) 993 exit: 994 #endif 995 /* Analyze request */ 996 rxstate(musb, req); 997 } 998 999 /* ------------------------------------------------------------ */ 1000 1001 static int musb_gadget_enable(struct usb_ep *ep, 1002 const struct usb_endpoint_descriptor *desc) 1003 { 1004 unsigned long flags; 1005 struct musb_ep *musb_ep; 1006 struct musb_hw_ep *hw_ep; 1007 void __iomem *regs; 1008 struct musb *musb; 1009 void __iomem *mbase; 1010 u8 epnum; 1011 u16 csr; 1012 unsigned tmp; 1013 int status = -EINVAL; 1014 1015 if (!ep || !desc) 1016 return -EINVAL; 1017 1018 musb_ep = to_musb_ep(ep); 1019 hw_ep = musb_ep->hw_ep; 1020 regs = hw_ep->regs; 1021 musb = musb_ep->musb; 1022 mbase = musb->mregs; 1023 epnum = musb_ep->current_epnum; 1024 1025 spin_lock_irqsave(&musb->lock, flags); 1026 1027 if (musb_ep->desc) { 1028 status = -EBUSY; 1029 goto fail; 1030 } 1031 musb_ep->type = usb_endpoint_type(desc); 1032 1033 /* check direction and (later) maxpacket size against endpoint */ 1034 if (usb_endpoint_num(desc) != epnum) 1035 goto fail; 1036 1037 /* REVISIT this rules out high bandwidth periodic transfers */ 1038 tmp = usb_endpoint_maxp(desc); 1039 if (tmp & ~0x07ff) { 1040 int ok; 1041 1042 if (usb_endpoint_dir_in(desc)) 1043 ok = musb->hb_iso_tx; 1044 else 1045 ok = musb->hb_iso_rx; 1046 1047 if (!ok) { 1048 dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); 1049 goto fail; 1050 } 1051 musb_ep->hb_mult = (tmp >> 11) & 3; 1052 } else { 1053 musb_ep->hb_mult = 0; 1054 } 1055 1056 musb_ep->packet_sz = tmp & 0x7ff; 1057 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); 1058 1059 /* enable the interrupts for the endpoint, set the endpoint 1060 * packet size (or fail), set the mode, clear the fifo 1061 */ 1062 musb_ep_select(mbase, epnum); 1063 if (usb_endpoint_dir_in(desc)) { 1064 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1065 1066 if (hw_ep->is_shared_fifo) 1067 musb_ep->is_in = 1; 1068 if (!musb_ep->is_in) 1069 goto fail; 1070 1071 if (tmp > hw_ep->max_packet_sz_tx) { 1072 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1073 goto fail; 1074 } 1075 1076 int_txe |= (1 << epnum); 1077 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1078 1079 /* REVISIT if can_bulk_split(), use by updating "tmp"; 1080 * likewise high bandwidth periodic tx 1081 */ 1082 /* Set TXMAXP with the FIFO size of the endpoint 1083 * to disable double buffering mode. 1084 */ 1085 if (musb->double_buffer_not_ok) 1086 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); 1087 else 1088 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz 1089 | (musb_ep->hb_mult << 11)); 1090 1091 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 1092 if (musb_readw(regs, MUSB_TXCSR) 1093 & MUSB_TXCSR_FIFONOTEMPTY) 1094 csr |= MUSB_TXCSR_FLUSHFIFO; 1095 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1096 csr |= MUSB_TXCSR_P_ISO; 1097 1098 /* set twice in case of double buffering */ 1099 musb_writew(regs, MUSB_TXCSR, csr); 1100 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1101 musb_writew(regs, MUSB_TXCSR, csr); 1102 1103 } else { 1104 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); 1105 1106 if (hw_ep->is_shared_fifo) 1107 musb_ep->is_in = 0; 1108 if (musb_ep->is_in) 1109 goto fail; 1110 1111 if (tmp > hw_ep->max_packet_sz_rx) { 1112 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1113 goto fail; 1114 } 1115 1116 int_rxe |= (1 << epnum); 1117 musb_writew(mbase, MUSB_INTRRXE, int_rxe); 1118 1119 /* REVISIT if can_bulk_combine() use by updating "tmp" 1120 * likewise high bandwidth periodic rx 1121 */ 1122 /* Set RXMAXP with the FIFO size of the endpoint 1123 * to disable double buffering mode. 1124 */ 1125 if (musb->double_buffer_not_ok) 1126 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); 1127 else 1128 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz 1129 | (musb_ep->hb_mult << 11)); 1130 1131 /* force shared fifo to OUT-only mode */ 1132 if (hw_ep->is_shared_fifo) { 1133 csr = musb_readw(regs, MUSB_TXCSR); 1134 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); 1135 musb_writew(regs, MUSB_TXCSR, csr); 1136 } 1137 1138 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; 1139 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1140 csr |= MUSB_RXCSR_P_ISO; 1141 else if (musb_ep->type == USB_ENDPOINT_XFER_INT) 1142 csr |= MUSB_RXCSR_DISNYET; 1143 1144 /* set twice in case of double buffering */ 1145 musb_writew(regs, MUSB_RXCSR, csr); 1146 musb_writew(regs, MUSB_RXCSR, csr); 1147 } 1148 1149 /* NOTE: all the I/O code _should_ work fine without DMA, in case 1150 * for some reason you run out of channels here. 1151 */ 1152 if (is_dma_capable() && musb->dma_controller) { 1153 struct dma_controller *c = musb->dma_controller; 1154 1155 musb_ep->dma = c->channel_alloc(c, hw_ep, 1156 (desc->bEndpointAddress & USB_DIR_IN)); 1157 } else 1158 musb_ep->dma = NULL; 1159 1160 musb_ep->desc = desc; 1161 musb_ep->busy = 0; 1162 musb_ep->wedged = 0; 1163 status = 0; 1164 1165 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 1166 musb_driver_name, musb_ep->end_point.name, 1167 ({ char *s; switch (musb_ep->type) { 1168 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; 1169 case USB_ENDPOINT_XFER_INT: s = "int"; break; 1170 default: s = "iso"; break; 1171 }; s; }), 1172 musb_ep->is_in ? "IN" : "OUT", 1173 musb_ep->dma ? "dma, " : "", 1174 musb_ep->packet_sz); 1175 1176 schedule_work(&musb->irq_work); 1177 1178 fail: 1179 spin_unlock_irqrestore(&musb->lock, flags); 1180 return status; 1181 } 1182 1183 /* 1184 * Disable an endpoint flushing all requests queued. 1185 */ 1186 static int musb_gadget_disable(struct usb_ep *ep) 1187 { 1188 unsigned long flags; 1189 struct musb *musb; 1190 u8 epnum; 1191 struct musb_ep *musb_ep; 1192 void __iomem *epio; 1193 int status = 0; 1194 1195 musb_ep = to_musb_ep(ep); 1196 musb = musb_ep->musb; 1197 epnum = musb_ep->current_epnum; 1198 epio = musb->endpoints[epnum].regs; 1199 1200 spin_lock_irqsave(&musb->lock, flags); 1201 musb_ep_select(musb->mregs, epnum); 1202 1203 /* zero the endpoint sizes */ 1204 if (musb_ep->is_in) { 1205 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); 1206 int_txe &= ~(1 << epnum); 1207 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); 1208 musb_writew(epio, MUSB_TXMAXP, 0); 1209 } else { 1210 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); 1211 int_rxe &= ~(1 << epnum); 1212 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); 1213 musb_writew(epio, MUSB_RXMAXP, 0); 1214 } 1215 1216 musb_ep->desc = NULL; 1217 1218 /* abort all pending DMA and requests */ 1219 nuke(musb_ep, -ESHUTDOWN); 1220 1221 schedule_work(&musb->irq_work); 1222 1223 spin_unlock_irqrestore(&(musb->lock), flags); 1224 1225 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); 1226 1227 return status; 1228 } 1229 1230 /* 1231 * Allocate a request for an endpoint. 1232 * Reused by ep0 code. 1233 */ 1234 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1235 { 1236 struct musb_ep *musb_ep = to_musb_ep(ep); 1237 struct musb *musb = musb_ep->musb; 1238 struct musb_request *request = NULL; 1239 1240 request = kzalloc(sizeof *request, gfp_flags); 1241 if (!request) { 1242 dev_dbg(musb->controller, "not enough memory\n"); 1243 return NULL; 1244 } 1245 1246 request->request.dma = DMA_ADDR_INVALID; 1247 request->epnum = musb_ep->current_epnum; 1248 request->ep = musb_ep; 1249 1250 return &request->request; 1251 } 1252 1253 /* 1254 * Free a request 1255 * Reused by ep0 code. 1256 */ 1257 void musb_free_request(struct usb_ep *ep, struct usb_request *req) 1258 { 1259 kfree(to_musb_request(req)); 1260 } 1261 1262 static LIST_HEAD(buffers); 1263 1264 struct free_record { 1265 struct list_head list; 1266 struct device *dev; 1267 unsigned bytes; 1268 dma_addr_t dma; 1269 }; 1270 1271 /* 1272 * Context: controller locked, IRQs blocked. 1273 */ 1274 void musb_ep_restart(struct musb *musb, struct musb_request *req) 1275 { 1276 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", 1277 req->tx ? "TX/IN" : "RX/OUT", 1278 &req->request, req->request.length, req->epnum); 1279 1280 musb_ep_select(musb->mregs, req->epnum); 1281 if (req->tx) 1282 txstate(musb, req); 1283 else 1284 rxstate(musb, req); 1285 } 1286 1287 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, 1288 gfp_t gfp_flags) 1289 { 1290 struct musb_ep *musb_ep; 1291 struct musb_request *request; 1292 struct musb *musb; 1293 int status = 0; 1294 unsigned long lockflags; 1295 1296 if (!ep || !req) 1297 return -EINVAL; 1298 if (!req->buf) 1299 return -ENODATA; 1300 1301 musb_ep = to_musb_ep(ep); 1302 musb = musb_ep->musb; 1303 1304 request = to_musb_request(req); 1305 request->musb = musb; 1306 1307 if (request->ep != musb_ep) 1308 return -EINVAL; 1309 1310 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); 1311 1312 /* request is mine now... */ 1313 request->request.actual = 0; 1314 request->request.status = -EINPROGRESS; 1315 request->epnum = musb_ep->current_epnum; 1316 request->tx = musb_ep->is_in; 1317 1318 map_dma_buffer(request, musb, musb_ep); 1319 1320 spin_lock_irqsave(&musb->lock, lockflags); 1321 1322 /* don't queue if the ep is down */ 1323 if (!musb_ep->desc) { 1324 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", 1325 req, ep->name, "disabled"); 1326 status = -ESHUTDOWN; 1327 goto cleanup; 1328 } 1329 1330 /* add request to the list */ 1331 list_add_tail(&request->list, &musb_ep->req_list); 1332 1333 /* it this is the head of the queue, start i/o ... */ 1334 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) 1335 musb_ep_restart(musb, request); 1336 1337 cleanup: 1338 spin_unlock_irqrestore(&musb->lock, lockflags); 1339 return status; 1340 } 1341 1342 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) 1343 { 1344 struct musb_ep *musb_ep = to_musb_ep(ep); 1345 struct musb_request *req = to_musb_request(request); 1346 struct musb_request *r; 1347 unsigned long flags; 1348 int status = 0; 1349 struct musb *musb = musb_ep->musb; 1350 1351 if (!ep || !request || to_musb_request(request)->ep != musb_ep) 1352 return -EINVAL; 1353 1354 spin_lock_irqsave(&musb->lock, flags); 1355 1356 list_for_each_entry(r, &musb_ep->req_list, list) { 1357 if (r == req) 1358 break; 1359 } 1360 if (r != req) { 1361 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); 1362 status = -EINVAL; 1363 goto done; 1364 } 1365 1366 /* if the hardware doesn't have the request, easy ... */ 1367 if (musb_ep->req_list.next != &req->list || musb_ep->busy) 1368 musb_g_giveback(musb_ep, request, -ECONNRESET); 1369 1370 /* ... else abort the dma transfer ... */ 1371 else if (is_dma_capable() && musb_ep->dma) { 1372 struct dma_controller *c = musb->dma_controller; 1373 1374 musb_ep_select(musb->mregs, musb_ep->current_epnum); 1375 if (c->channel_abort) 1376 status = c->channel_abort(musb_ep->dma); 1377 else 1378 status = -EBUSY; 1379 if (status == 0) 1380 musb_g_giveback(musb_ep, request, -ECONNRESET); 1381 } else { 1382 /* NOTE: by sticking to easily tested hardware/driver states, 1383 * we leave counting of in-flight packets imprecise. 1384 */ 1385 musb_g_giveback(musb_ep, request, -ECONNRESET); 1386 } 1387 1388 done: 1389 spin_unlock_irqrestore(&musb->lock, flags); 1390 return status; 1391 } 1392 1393 /* 1394 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any 1395 * data but will queue requests. 1396 * 1397 * exported to ep0 code 1398 */ 1399 static int musb_gadget_set_halt(struct usb_ep *ep, int value) 1400 { 1401 struct musb_ep *musb_ep = to_musb_ep(ep); 1402 u8 epnum = musb_ep->current_epnum; 1403 struct musb *musb = musb_ep->musb; 1404 void __iomem *epio = musb->endpoints[epnum].regs; 1405 void __iomem *mbase; 1406 unsigned long flags; 1407 u16 csr; 1408 struct musb_request *request; 1409 int status = 0; 1410 1411 if (!ep) 1412 return -EINVAL; 1413 mbase = musb->mregs; 1414 1415 spin_lock_irqsave(&musb->lock, flags); 1416 1417 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { 1418 status = -EINVAL; 1419 goto done; 1420 } 1421 1422 musb_ep_select(mbase, epnum); 1423 1424 request = next_request(musb_ep); 1425 if (value) { 1426 if (request) { 1427 dev_dbg(musb->controller, "request in progress, cannot halt %s\n", 1428 ep->name); 1429 status = -EAGAIN; 1430 goto done; 1431 } 1432 /* Cannot portably stall with non-empty FIFO */ 1433 if (musb_ep->is_in) { 1434 csr = musb_readw(epio, MUSB_TXCSR); 1435 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1436 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); 1437 status = -EAGAIN; 1438 goto done; 1439 } 1440 } 1441 } else 1442 musb_ep->wedged = 0; 1443 1444 /* set/clear the stall and toggle bits */ 1445 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1446 if (musb_ep->is_in) { 1447 csr = musb_readw(epio, MUSB_TXCSR); 1448 csr |= MUSB_TXCSR_P_WZC_BITS 1449 | MUSB_TXCSR_CLRDATATOG; 1450 if (value) 1451 csr |= MUSB_TXCSR_P_SENDSTALL; 1452 else 1453 csr &= ~(MUSB_TXCSR_P_SENDSTALL 1454 | MUSB_TXCSR_P_SENTSTALL); 1455 csr &= ~MUSB_TXCSR_TXPKTRDY; 1456 musb_writew(epio, MUSB_TXCSR, csr); 1457 } else { 1458 csr = musb_readw(epio, MUSB_RXCSR); 1459 csr |= MUSB_RXCSR_P_WZC_BITS 1460 | MUSB_RXCSR_FLUSHFIFO 1461 | MUSB_RXCSR_CLRDATATOG; 1462 if (value) 1463 csr |= MUSB_RXCSR_P_SENDSTALL; 1464 else 1465 csr &= ~(MUSB_RXCSR_P_SENDSTALL 1466 | MUSB_RXCSR_P_SENTSTALL); 1467 musb_writew(epio, MUSB_RXCSR, csr); 1468 } 1469 1470 /* maybe start the first request in the queue */ 1471 if (!musb_ep->busy && !value && request) { 1472 dev_dbg(musb->controller, "restarting the request\n"); 1473 musb_ep_restart(musb, request); 1474 } 1475 1476 done: 1477 spin_unlock_irqrestore(&musb->lock, flags); 1478 return status; 1479 } 1480 1481 /* 1482 * Sets the halt feature with the clear requests ignored 1483 */ 1484 static int musb_gadget_set_wedge(struct usb_ep *ep) 1485 { 1486 struct musb_ep *musb_ep = to_musb_ep(ep); 1487 1488 if (!ep) 1489 return -EINVAL; 1490 1491 musb_ep->wedged = 1; 1492 1493 return usb_ep_set_halt(ep); 1494 } 1495 1496 static int musb_gadget_fifo_status(struct usb_ep *ep) 1497 { 1498 struct musb_ep *musb_ep = to_musb_ep(ep); 1499 void __iomem *epio = musb_ep->hw_ep->regs; 1500 int retval = -EINVAL; 1501 1502 if (musb_ep->desc && !musb_ep->is_in) { 1503 struct musb *musb = musb_ep->musb; 1504 int epnum = musb_ep->current_epnum; 1505 void __iomem *mbase = musb->mregs; 1506 unsigned long flags; 1507 1508 spin_lock_irqsave(&musb->lock, flags); 1509 1510 musb_ep_select(mbase, epnum); 1511 /* FIXME return zero unless RXPKTRDY is set */ 1512 retval = musb_readw(epio, MUSB_RXCOUNT); 1513 1514 spin_unlock_irqrestore(&musb->lock, flags); 1515 } 1516 return retval; 1517 } 1518 1519 static void musb_gadget_fifo_flush(struct usb_ep *ep) 1520 { 1521 struct musb_ep *musb_ep = to_musb_ep(ep); 1522 struct musb *musb = musb_ep->musb; 1523 u8 epnum = musb_ep->current_epnum; 1524 void __iomem *epio = musb->endpoints[epnum].regs; 1525 void __iomem *mbase; 1526 unsigned long flags; 1527 u16 csr, int_txe; 1528 1529 mbase = musb->mregs; 1530 1531 spin_lock_irqsave(&musb->lock, flags); 1532 musb_ep_select(mbase, (u8) epnum); 1533 1534 /* disable interrupts */ 1535 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1536 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 1537 1538 if (musb_ep->is_in) { 1539 csr = musb_readw(epio, MUSB_TXCSR); 1540 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1541 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1542 /* 1543 * Setting both TXPKTRDY and FLUSHFIFO makes controller 1544 * to interrupt current FIFO loading, but not flushing 1545 * the already loaded ones. 1546 */ 1547 csr &= ~MUSB_TXCSR_TXPKTRDY; 1548 musb_writew(epio, MUSB_TXCSR, csr); 1549 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1550 musb_writew(epio, MUSB_TXCSR, csr); 1551 } 1552 } else { 1553 csr = musb_readw(epio, MUSB_RXCSR); 1554 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; 1555 musb_writew(epio, MUSB_RXCSR, csr); 1556 musb_writew(epio, MUSB_RXCSR, csr); 1557 } 1558 1559 /* re-enable interrupt */ 1560 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1561 spin_unlock_irqrestore(&musb->lock, flags); 1562 } 1563 1564 static const struct usb_ep_ops musb_ep_ops = { 1565 .enable = musb_gadget_enable, 1566 .disable = musb_gadget_disable, 1567 .alloc_request = musb_alloc_request, 1568 .free_request = musb_free_request, 1569 .queue = musb_gadget_queue, 1570 .dequeue = musb_gadget_dequeue, 1571 .set_halt = musb_gadget_set_halt, 1572 .set_wedge = musb_gadget_set_wedge, 1573 .fifo_status = musb_gadget_fifo_status, 1574 .fifo_flush = musb_gadget_fifo_flush 1575 }; 1576 1577 /* ----------------------------------------------------------------------- */ 1578 1579 static int musb_gadget_get_frame(struct usb_gadget *gadget) 1580 { 1581 struct musb *musb = gadget_to_musb(gadget); 1582 1583 return (int)musb_readw(musb->mregs, MUSB_FRAME); 1584 } 1585 1586 static int musb_gadget_wakeup(struct usb_gadget *gadget) 1587 { 1588 struct musb *musb = gadget_to_musb(gadget); 1589 void __iomem *mregs = musb->mregs; 1590 unsigned long flags; 1591 int status = -EINVAL; 1592 u8 power, devctl; 1593 int retries; 1594 1595 spin_lock_irqsave(&musb->lock, flags); 1596 1597 switch (musb->xceiv->state) { 1598 case OTG_STATE_B_PERIPHERAL: 1599 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1600 * that's part of the standard usb 1.1 state machine, and 1601 * doesn't affect OTG transitions. 1602 */ 1603 if (musb->may_wakeup && musb->is_suspended) 1604 break; 1605 goto done; 1606 case OTG_STATE_B_IDLE: 1607 /* Start SRP ... OTG not required. */ 1608 devctl = musb_readb(mregs, MUSB_DEVCTL); 1609 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); 1610 devctl |= MUSB_DEVCTL_SESSION; 1611 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1612 devctl = musb_readb(mregs, MUSB_DEVCTL); 1613 retries = 100; 1614 while (!(devctl & MUSB_DEVCTL_SESSION)) { 1615 devctl = musb_readb(mregs, MUSB_DEVCTL); 1616 if (retries-- < 1) 1617 break; 1618 } 1619 retries = 10000; 1620 while (devctl & MUSB_DEVCTL_SESSION) { 1621 devctl = musb_readb(mregs, MUSB_DEVCTL); 1622 if (retries-- < 1) 1623 break; 1624 } 1625 1626 spin_unlock_irqrestore(&musb->lock, flags); 1627 otg_start_srp(musb->xceiv); 1628 spin_lock_irqsave(&musb->lock, flags); 1629 1630 /* Block idling for at least 1s */ 1631 musb_platform_try_idle(musb, 1632 jiffies + msecs_to_jiffies(1 * HZ)); 1633 1634 status = 0; 1635 goto done; 1636 default: 1637 dev_dbg(musb->controller, "Unhandled wake: %s\n", 1638 otg_state_string(musb->xceiv->state)); 1639 goto done; 1640 } 1641 1642 status = 0; 1643 1644 power = musb_readb(mregs, MUSB_POWER); 1645 power |= MUSB_POWER_RESUME; 1646 musb_writeb(mregs, MUSB_POWER, power); 1647 dev_dbg(musb->controller, "issue wakeup\n"); 1648 1649 /* FIXME do this next chunk in a timer callback, no udelay */ 1650 mdelay(2); 1651 1652 power = musb_readb(mregs, MUSB_POWER); 1653 power &= ~MUSB_POWER_RESUME; 1654 musb_writeb(mregs, MUSB_POWER, power); 1655 done: 1656 spin_unlock_irqrestore(&musb->lock, flags); 1657 return status; 1658 } 1659 1660 static int 1661 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) 1662 { 1663 struct musb *musb = gadget_to_musb(gadget); 1664 1665 musb->is_self_powered = !!is_selfpowered; 1666 return 0; 1667 } 1668 1669 static void musb_pullup(struct musb *musb, int is_on) 1670 { 1671 u8 power; 1672 1673 power = musb_readb(musb->mregs, MUSB_POWER); 1674 if (is_on) 1675 power |= MUSB_POWER_SOFTCONN; 1676 else 1677 power &= ~MUSB_POWER_SOFTCONN; 1678 1679 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1680 1681 dev_dbg(musb->controller, "gadget D+ pullup %s\n", 1682 is_on ? "on" : "off"); 1683 musb_writeb(musb->mregs, MUSB_POWER, power); 1684 } 1685 1686 #if 0 1687 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1688 { 1689 dev_dbg(musb->controller, "<= %s =>\n", __func__); 1690 1691 /* 1692 * FIXME iff driver's softconnect flag is set (as it is during probe, 1693 * though that can clear it), just musb_pullup(). 1694 */ 1695 1696 return -EINVAL; 1697 } 1698 #endif 1699 1700 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1701 { 1702 struct musb *musb = gadget_to_musb(gadget); 1703 1704 if (!musb->xceiv->set_power) 1705 return -EOPNOTSUPP; 1706 return otg_set_power(musb->xceiv, mA); 1707 } 1708 1709 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1710 { 1711 struct musb *musb = gadget_to_musb(gadget); 1712 unsigned long flags; 1713 1714 is_on = !!is_on; 1715 1716 pm_runtime_get_sync(musb->controller); 1717 1718 /* NOTE: this assumes we are sensing vbus; we'd rather 1719 * not pullup unless the B-session is active. 1720 */ 1721 spin_lock_irqsave(&musb->lock, flags); 1722 if (is_on != musb->softconnect) { 1723 musb->softconnect = is_on; 1724 musb_pullup(musb, is_on); 1725 } 1726 spin_unlock_irqrestore(&musb->lock, flags); 1727 1728 pm_runtime_put(musb->controller); 1729 1730 return 0; 1731 } 1732 1733 static int musb_gadget_start(struct usb_gadget *g, 1734 struct usb_gadget_driver *driver); 1735 static int musb_gadget_stop(struct usb_gadget *g, 1736 struct usb_gadget_driver *driver); 1737 1738 static const struct usb_gadget_ops musb_gadget_operations = { 1739 .get_frame = musb_gadget_get_frame, 1740 .wakeup = musb_gadget_wakeup, 1741 .set_selfpowered = musb_gadget_set_self_powered, 1742 /* .vbus_session = musb_gadget_vbus_session, */ 1743 .vbus_draw = musb_gadget_vbus_draw, 1744 .pullup = musb_gadget_pullup, 1745 .udc_start = musb_gadget_start, 1746 .udc_stop = musb_gadget_stop, 1747 }; 1748 1749 /* ----------------------------------------------------------------------- */ 1750 1751 /* Registration */ 1752 1753 /* Only this registration code "knows" the rule (from USB standards) 1754 * about there being only one external upstream port. It assumes 1755 * all peripheral ports are external... 1756 */ 1757 1758 static void musb_gadget_release(struct device *dev) 1759 { 1760 /* kref_put(WHAT) */ 1761 dev_dbg(dev, "%s\n", __func__); 1762 } 1763 1764 1765 static void __init 1766 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) 1767 { 1768 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1769 1770 memset(ep, 0, sizeof *ep); 1771 1772 ep->current_epnum = epnum; 1773 ep->musb = musb; 1774 ep->hw_ep = hw_ep; 1775 ep->is_in = is_in; 1776 1777 INIT_LIST_HEAD(&ep->req_list); 1778 1779 sprintf(ep->name, "ep%d%s", epnum, 1780 (!epnum || hw_ep->is_shared_fifo) ? "" : ( 1781 is_in ? "in" : "out")); 1782 ep->end_point.name = ep->name; 1783 INIT_LIST_HEAD(&ep->end_point.ep_list); 1784 if (!epnum) { 1785 ep->end_point.maxpacket = 64; 1786 ep->end_point.ops = &musb_g_ep0_ops; 1787 musb->g.ep0 = &ep->end_point; 1788 } else { 1789 if (is_in) 1790 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; 1791 else 1792 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; 1793 ep->end_point.ops = &musb_ep_ops; 1794 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); 1795 } 1796 } 1797 1798 /* 1799 * Initialize the endpoints exposed to peripheral drivers, with backlinks 1800 * to the rest of the driver state. 1801 */ 1802 static inline void __init musb_g_init_endpoints(struct musb *musb) 1803 { 1804 u8 epnum; 1805 struct musb_hw_ep *hw_ep; 1806 unsigned count = 0; 1807 1808 /* initialize endpoint list just once */ 1809 INIT_LIST_HEAD(&(musb->g.ep_list)); 1810 1811 for (epnum = 0, hw_ep = musb->endpoints; 1812 epnum < musb->nr_endpoints; 1813 epnum++, hw_ep++) { 1814 if (hw_ep->is_shared_fifo /* || !epnum */) { 1815 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); 1816 count++; 1817 } else { 1818 if (hw_ep->max_packet_sz_tx) { 1819 init_peripheral_ep(musb, &hw_ep->ep_in, 1820 epnum, 1); 1821 count++; 1822 } 1823 if (hw_ep->max_packet_sz_rx) { 1824 init_peripheral_ep(musb, &hw_ep->ep_out, 1825 epnum, 0); 1826 count++; 1827 } 1828 } 1829 } 1830 } 1831 1832 /* called once during driver setup to initialize and link into 1833 * the driver model; memory is zeroed. 1834 */ 1835 int __init musb_gadget_setup(struct musb *musb) 1836 { 1837 int status; 1838 1839 /* REVISIT minor race: if (erroneously) setting up two 1840 * musb peripherals at the same time, only the bus lock 1841 * is probably held. 1842 */ 1843 1844 musb->g.ops = &musb_gadget_operations; 1845 musb->g.max_speed = USB_SPEED_HIGH; 1846 musb->g.speed = USB_SPEED_UNKNOWN; 1847 1848 /* this "gadget" abstracts/virtualizes the controller */ 1849 dev_set_name(&musb->g.dev, "gadget"); 1850 musb->g.dev.parent = musb->controller; 1851 musb->g.dev.dma_mask = musb->controller->dma_mask; 1852 musb->g.dev.release = musb_gadget_release; 1853 musb->g.name = musb_driver_name; 1854 1855 if (is_otg_enabled(musb)) 1856 musb->g.is_otg = 1; 1857 1858 musb_g_init_endpoints(musb); 1859 1860 musb->is_active = 0; 1861 musb_platform_try_idle(musb, 0); 1862 1863 status = device_register(&musb->g.dev); 1864 if (status != 0) { 1865 put_device(&musb->g.dev); 1866 return status; 1867 } 1868 status = usb_add_gadget_udc(musb->controller, &musb->g); 1869 if (status) 1870 goto err; 1871 1872 return 0; 1873 err: 1874 musb->g.dev.parent = NULL; 1875 device_unregister(&musb->g.dev); 1876 return status; 1877 } 1878 1879 void musb_gadget_cleanup(struct musb *musb) 1880 { 1881 usb_del_gadget_udc(&musb->g); 1882 if (musb->g.dev.parent) 1883 device_unregister(&musb->g.dev); 1884 } 1885 1886 /* 1887 * Register the gadget driver. Used by gadget drivers when 1888 * registering themselves with the controller. 1889 * 1890 * -EINVAL something went wrong (not driver) 1891 * -EBUSY another gadget is already using the controller 1892 * -ENOMEM no memory to perform the operation 1893 * 1894 * @param driver the gadget driver 1895 * @return <0 if error, 0 if everything is fine 1896 */ 1897 static int musb_gadget_start(struct usb_gadget *g, 1898 struct usb_gadget_driver *driver) 1899 { 1900 struct musb *musb = gadget_to_musb(g); 1901 unsigned long flags; 1902 int retval = -EINVAL; 1903 1904 if (driver->max_speed < USB_SPEED_HIGH) 1905 goto err0; 1906 1907 pm_runtime_get_sync(musb->controller); 1908 1909 dev_dbg(musb->controller, "registering driver %s\n", driver->function); 1910 1911 musb->softconnect = 0; 1912 musb->gadget_driver = driver; 1913 1914 spin_lock_irqsave(&musb->lock, flags); 1915 musb->is_active = 1; 1916 1917 otg_set_peripheral(musb->xceiv, &musb->g); 1918 musb->xceiv->state = OTG_STATE_B_IDLE; 1919 1920 /* 1921 * FIXME this ignores the softconnect flag. Drivers are 1922 * allowed hold the peripheral inactive until for example 1923 * userspace hooks up printer hardware or DSP codecs, so 1924 * hosts only see fully functional devices. 1925 */ 1926 1927 if (!is_otg_enabled(musb)) 1928 musb_start(musb); 1929 1930 spin_unlock_irqrestore(&musb->lock, flags); 1931 1932 if (is_otg_enabled(musb)) { 1933 struct usb_hcd *hcd = musb_to_hcd(musb); 1934 1935 dev_dbg(musb->controller, "OTG startup...\n"); 1936 1937 /* REVISIT: funcall to other code, which also 1938 * handles power budgeting ... this way also 1939 * ensures HdrcStart is indirectly called. 1940 */ 1941 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1942 if (retval < 0) { 1943 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval); 1944 goto err2; 1945 } 1946 1947 if ((musb->xceiv->last_event == USB_EVENT_ID) 1948 && musb->xceiv->set_vbus) 1949 otg_set_vbus(musb->xceiv, 1); 1950 1951 hcd->self.uses_pio_for_control = 1; 1952 } 1953 if (musb->xceiv->last_event == USB_EVENT_NONE) 1954 pm_runtime_put(musb->controller); 1955 1956 return 0; 1957 1958 err2: 1959 if (!is_otg_enabled(musb)) 1960 musb_stop(musb); 1961 err0: 1962 return retval; 1963 } 1964 1965 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) 1966 { 1967 int i; 1968 struct musb_hw_ep *hw_ep; 1969 1970 /* don't disconnect if it's not connected */ 1971 if (musb->g.speed == USB_SPEED_UNKNOWN) 1972 driver = NULL; 1973 else 1974 musb->g.speed = USB_SPEED_UNKNOWN; 1975 1976 /* deactivate the hardware */ 1977 if (musb->softconnect) { 1978 musb->softconnect = 0; 1979 musb_pullup(musb, 0); 1980 } 1981 musb_stop(musb); 1982 1983 /* killing any outstanding requests will quiesce the driver; 1984 * then report disconnect 1985 */ 1986 if (driver) { 1987 for (i = 0, hw_ep = musb->endpoints; 1988 i < musb->nr_endpoints; 1989 i++, hw_ep++) { 1990 musb_ep_select(musb->mregs, i); 1991 if (hw_ep->is_shared_fifo /* || !epnum */) { 1992 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1993 } else { 1994 if (hw_ep->max_packet_sz_tx) 1995 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1996 if (hw_ep->max_packet_sz_rx) 1997 nuke(&hw_ep->ep_out, -ESHUTDOWN); 1998 } 1999 } 2000 } 2001 } 2002 2003 /* 2004 * Unregister the gadget driver. Used by gadget drivers when 2005 * unregistering themselves from the controller. 2006 * 2007 * @param driver the gadget driver to unregister 2008 */ 2009 static int musb_gadget_stop(struct usb_gadget *g, 2010 struct usb_gadget_driver *driver) 2011 { 2012 struct musb *musb = gadget_to_musb(g); 2013 unsigned long flags; 2014 2015 if (musb->xceiv->last_event == USB_EVENT_NONE) 2016 pm_runtime_get_sync(musb->controller); 2017 2018 /* 2019 * REVISIT always use otg_set_peripheral() here too; 2020 * this needs to shut down the OTG engine. 2021 */ 2022 2023 spin_lock_irqsave(&musb->lock, flags); 2024 2025 musb_hnp_stop(musb); 2026 2027 (void) musb_gadget_vbus_draw(&musb->g, 0); 2028 2029 musb->xceiv->state = OTG_STATE_UNDEFINED; 2030 stop_activity(musb, driver); 2031 otg_set_peripheral(musb->xceiv, NULL); 2032 2033 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function); 2034 2035 musb->is_active = 0; 2036 musb_platform_try_idle(musb, 0); 2037 spin_unlock_irqrestore(&musb->lock, flags); 2038 2039 if (is_otg_enabled(musb)) { 2040 usb_remove_hcd(musb_to_hcd(musb)); 2041 /* FIXME we need to be able to register another 2042 * gadget driver here and have everything work; 2043 * that currently misbehaves. 2044 */ 2045 } 2046 2047 if (!is_otg_enabled(musb)) 2048 musb_stop(musb); 2049 2050 pm_runtime_put(musb->controller); 2051 2052 return 0; 2053 } 2054 2055 /* ----------------------------------------------------------------------- */ 2056 2057 /* lifecycle operations called through plat_uds.c */ 2058 2059 void musb_g_resume(struct musb *musb) 2060 { 2061 musb->is_suspended = 0; 2062 switch (musb->xceiv->state) { 2063 case OTG_STATE_B_IDLE: 2064 break; 2065 case OTG_STATE_B_WAIT_ACON: 2066 case OTG_STATE_B_PERIPHERAL: 2067 musb->is_active = 1; 2068 if (musb->gadget_driver && musb->gadget_driver->resume) { 2069 spin_unlock(&musb->lock); 2070 musb->gadget_driver->resume(&musb->g); 2071 spin_lock(&musb->lock); 2072 } 2073 break; 2074 default: 2075 WARNING("unhandled RESUME transition (%s)\n", 2076 otg_state_string(musb->xceiv->state)); 2077 } 2078 } 2079 2080 /* called when SOF packets stop for 3+ msec */ 2081 void musb_g_suspend(struct musb *musb) 2082 { 2083 u8 devctl; 2084 2085 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2086 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2087 2088 switch (musb->xceiv->state) { 2089 case OTG_STATE_B_IDLE: 2090 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2091 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2092 break; 2093 case OTG_STATE_B_PERIPHERAL: 2094 musb->is_suspended = 1; 2095 if (musb->gadget_driver && musb->gadget_driver->suspend) { 2096 spin_unlock(&musb->lock); 2097 musb->gadget_driver->suspend(&musb->g); 2098 spin_lock(&musb->lock); 2099 } 2100 break; 2101 default: 2102 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; 2103 * A_PERIPHERAL may need care too 2104 */ 2105 WARNING("unhandled SUSPEND transition (%s)\n", 2106 otg_state_string(musb->xceiv->state)); 2107 } 2108 } 2109 2110 /* Called during SRP */ 2111 void musb_g_wakeup(struct musb *musb) 2112 { 2113 musb_gadget_wakeup(&musb->g); 2114 } 2115 2116 /* called when VBUS drops below session threshold, and in other cases */ 2117 void musb_g_disconnect(struct musb *musb) 2118 { 2119 void __iomem *mregs = musb->mregs; 2120 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2121 2122 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2123 2124 /* clear HR */ 2125 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2126 2127 /* don't draw vbus until new b-default session */ 2128 (void) musb_gadget_vbus_draw(&musb->g, 0); 2129 2130 musb->g.speed = USB_SPEED_UNKNOWN; 2131 if (musb->gadget_driver && musb->gadget_driver->disconnect) { 2132 spin_unlock(&musb->lock); 2133 musb->gadget_driver->disconnect(&musb->g); 2134 spin_lock(&musb->lock); 2135 } 2136 2137 switch (musb->xceiv->state) { 2138 default: 2139 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", 2140 otg_state_string(musb->xceiv->state)); 2141 musb->xceiv->state = OTG_STATE_A_IDLE; 2142 MUSB_HST_MODE(musb); 2143 break; 2144 case OTG_STATE_A_PERIPHERAL: 2145 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2146 MUSB_HST_MODE(musb); 2147 break; 2148 case OTG_STATE_B_WAIT_ACON: 2149 case OTG_STATE_B_HOST: 2150 case OTG_STATE_B_PERIPHERAL: 2151 case OTG_STATE_B_IDLE: 2152 musb->xceiv->state = OTG_STATE_B_IDLE; 2153 break; 2154 case OTG_STATE_B_SRP_INIT: 2155 break; 2156 } 2157 2158 musb->is_active = 0; 2159 } 2160 2161 void musb_g_reset(struct musb *musb) 2162 __releases(musb->lock) 2163 __acquires(musb->lock) 2164 { 2165 void __iomem *mbase = musb->mregs; 2166 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2167 u8 power; 2168 2169 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n", 2170 (devctl & MUSB_DEVCTL_BDEVICE) 2171 ? "B-Device" : "A-Device", 2172 musb_readb(mbase, MUSB_FADDR), 2173 musb->gadget_driver 2174 ? musb->gadget_driver->driver.name 2175 : NULL 2176 ); 2177 2178 /* report disconnect, if we didn't already (flushing EP state) */ 2179 if (musb->g.speed != USB_SPEED_UNKNOWN) 2180 musb_g_disconnect(musb); 2181 2182 /* clear HR */ 2183 else if (devctl & MUSB_DEVCTL_HR) 2184 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 2185 2186 2187 /* what speed did we negotiate? */ 2188 power = musb_readb(mbase, MUSB_POWER); 2189 musb->g.speed = (power & MUSB_POWER_HSMODE) 2190 ? USB_SPEED_HIGH : USB_SPEED_FULL; 2191 2192 /* start in USB_STATE_DEFAULT */ 2193 musb->is_active = 1; 2194 musb->is_suspended = 0; 2195 MUSB_DEV_MODE(musb); 2196 musb->address = 0; 2197 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 2198 2199 musb->may_wakeup = 0; 2200 musb->g.b_hnp_enable = 0; 2201 musb->g.a_alt_hnp_support = 0; 2202 musb->g.a_hnp_support = 0; 2203 2204 /* Normal reset, as B-Device; 2205 * or else after HNP, as A-Device 2206 */ 2207 if (devctl & MUSB_DEVCTL_BDEVICE) { 2208 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2209 musb->g.is_a_peripheral = 0; 2210 } else if (is_otg_enabled(musb)) { 2211 musb->xceiv->state = OTG_STATE_A_PERIPHERAL; 2212 musb->g.is_a_peripheral = 1; 2213 } else 2214 WARN_ON(1); 2215 2216 /* start with default limits on VBUS power draw */ 2217 (void) musb_gadget_vbus_draw(&musb->g, 2218 is_otg_enabled(musb) ? 8 : 100); 2219 } 2220