1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific information 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/list.h> 97 #include <linux/kobject.h> 98 #include <linux/prefetch.h> 99 #include <linux/platform_device.h> 100 #include <linux/io.h> 101 #include <linux/dma-mapping.h> 102 #include <linux/usb.h> 103 #include <linux/usb/of.h> 104 105 #include "musb_core.h" 106 #include "musb_trace.h" 107 108 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 109 110 111 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 112 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 113 114 #define MUSB_VERSION "6.0" 115 116 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 117 118 #define MUSB_DRIVER_NAME "musb-hdrc" 119 const char musb_driver_name[] = MUSB_DRIVER_NAME; 120 121 MODULE_DESCRIPTION(DRIVER_INFO); 122 MODULE_AUTHOR(DRIVER_AUTHOR); 123 MODULE_LICENSE("GPL"); 124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 125 126 127 /*-------------------------------------------------------------------------*/ 128 129 static inline struct musb *dev_to_musb(struct device *dev) 130 { 131 return dev_get_drvdata(dev); 132 } 133 134 enum musb_mode musb_get_mode(struct device *dev) 135 { 136 enum usb_dr_mode mode; 137 138 mode = usb_get_dr_mode(dev); 139 switch (mode) { 140 case USB_DR_MODE_HOST: 141 return MUSB_HOST; 142 case USB_DR_MODE_PERIPHERAL: 143 return MUSB_PERIPHERAL; 144 case USB_DR_MODE_OTG: 145 case USB_DR_MODE_UNKNOWN: 146 default: 147 return MUSB_OTG; 148 } 149 } 150 EXPORT_SYMBOL_GPL(musb_get_mode); 151 152 /*-------------------------------------------------------------------------*/ 153 154 #ifndef CONFIG_BLACKFIN 155 static int musb_ulpi_read(struct usb_phy *phy, u32 reg) 156 { 157 void __iomem *addr = phy->io_priv; 158 int i = 0; 159 u8 r; 160 u8 power; 161 int ret; 162 163 pm_runtime_get_sync(phy->io_dev); 164 165 /* Make sure the transceiver is not in low power mode */ 166 power = musb_readb(addr, MUSB_POWER); 167 power &= ~MUSB_POWER_SUSPENDM; 168 musb_writeb(addr, MUSB_POWER, power); 169 170 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 171 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 172 */ 173 174 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 175 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 176 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 177 178 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 179 & MUSB_ULPI_REG_CMPLT)) { 180 i++; 181 if (i == 10000) { 182 ret = -ETIMEDOUT; 183 goto out; 184 } 185 186 } 187 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 188 r &= ~MUSB_ULPI_REG_CMPLT; 189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 190 191 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 192 193 out: 194 pm_runtime_put(phy->io_dev); 195 196 return ret; 197 } 198 199 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) 200 { 201 void __iomem *addr = phy->io_priv; 202 int i = 0; 203 u8 r = 0; 204 u8 power; 205 int ret = 0; 206 207 pm_runtime_get_sync(phy->io_dev); 208 209 /* Make sure the transceiver is not in low power mode */ 210 power = musb_readb(addr, MUSB_POWER); 211 power &= ~MUSB_POWER_SUSPENDM; 212 musb_writeb(addr, MUSB_POWER, power); 213 214 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 215 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); 216 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 217 218 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 219 & MUSB_ULPI_REG_CMPLT)) { 220 i++; 221 if (i == 10000) { 222 ret = -ETIMEDOUT; 223 goto out; 224 } 225 } 226 227 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 228 r &= ~MUSB_ULPI_REG_CMPLT; 229 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 230 231 out: 232 pm_runtime_put(phy->io_dev); 233 234 return ret; 235 } 236 #else 237 #define musb_ulpi_read NULL 238 #define musb_ulpi_write NULL 239 #endif 240 241 static struct usb_phy_io_ops musb_ulpi_access = { 242 .read = musb_ulpi_read, 243 .write = musb_ulpi_write, 244 }; 245 246 /*-------------------------------------------------------------------------*/ 247 248 static u32 musb_default_fifo_offset(u8 epnum) 249 { 250 return 0x20 + (epnum * 4); 251 } 252 253 /* "flat" mapping: each endpoint has its own i/o address */ 254 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) 255 { 256 } 257 258 static u32 musb_flat_ep_offset(u8 epnum, u16 offset) 259 { 260 return 0x100 + (0x10 * epnum) + offset; 261 } 262 263 /* "indexed" mapping: INDEX register controls register bank select */ 264 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) 265 { 266 musb_writeb(mbase, MUSB_INDEX, epnum); 267 } 268 269 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) 270 { 271 return 0x10 + offset; 272 } 273 274 static u32 musb_default_busctl_offset(u8 epnum, u16 offset) 275 { 276 return 0x80 + (0x08 * epnum) + offset; 277 } 278 279 static u8 musb_default_readb(const void __iomem *addr, unsigned offset) 280 { 281 u8 data = __raw_readb(addr + offset); 282 283 trace_musb_readb(__builtin_return_address(0), addr, offset, data); 284 return data; 285 } 286 287 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data) 288 { 289 trace_musb_writeb(__builtin_return_address(0), addr, offset, data); 290 __raw_writeb(data, addr + offset); 291 } 292 293 static u16 musb_default_readw(const void __iomem *addr, unsigned offset) 294 { 295 u16 data = __raw_readw(addr + offset); 296 297 trace_musb_readw(__builtin_return_address(0), addr, offset, data); 298 return data; 299 } 300 301 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data) 302 { 303 trace_musb_writew(__builtin_return_address(0), addr, offset, data); 304 __raw_writew(data, addr + offset); 305 } 306 307 static u32 musb_default_readl(const void __iomem *addr, unsigned offset) 308 { 309 u32 data = __raw_readl(addr + offset); 310 311 trace_musb_readl(__builtin_return_address(0), addr, offset, data); 312 return data; 313 } 314 315 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data) 316 { 317 trace_musb_writel(__builtin_return_address(0), addr, offset, data); 318 __raw_writel(data, addr + offset); 319 } 320 321 /* 322 * Load an endpoint's FIFO 323 */ 324 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 325 const u8 *src) 326 { 327 struct musb *musb = hw_ep->musb; 328 void __iomem *fifo = hw_ep->fifo; 329 330 if (unlikely(len == 0)) 331 return; 332 333 prefetch((u8 *)src); 334 335 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 336 'T', hw_ep->epnum, fifo, len, src); 337 338 /* we can't assume unaligned reads work */ 339 if (likely((0x01 & (unsigned long) src) == 0)) { 340 u16 index = 0; 341 342 /* best case is 32bit-aligned source address */ 343 if ((0x02 & (unsigned long) src) == 0) { 344 if (len >= 4) { 345 iowrite32_rep(fifo, src + index, len >> 2); 346 index += len & ~0x03; 347 } 348 if (len & 0x02) { 349 __raw_writew(*(u16 *)&src[index], fifo); 350 index += 2; 351 } 352 } else { 353 if (len >= 2) { 354 iowrite16_rep(fifo, src + index, len >> 1); 355 index += len & ~0x01; 356 } 357 } 358 if (len & 0x01) 359 __raw_writeb(src[index], fifo); 360 } else { 361 /* byte aligned */ 362 iowrite8_rep(fifo, src, len); 363 } 364 } 365 366 /* 367 * Unload an endpoint's FIFO 368 */ 369 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 370 { 371 struct musb *musb = hw_ep->musb; 372 void __iomem *fifo = hw_ep->fifo; 373 374 if (unlikely(len == 0)) 375 return; 376 377 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 378 'R', hw_ep->epnum, fifo, len, dst); 379 380 /* we can't assume unaligned writes work */ 381 if (likely((0x01 & (unsigned long) dst) == 0)) { 382 u16 index = 0; 383 384 /* best case is 32bit-aligned destination address */ 385 if ((0x02 & (unsigned long) dst) == 0) { 386 if (len >= 4) { 387 ioread32_rep(fifo, dst, len >> 2); 388 index = len & ~0x03; 389 } 390 if (len & 0x02) { 391 *(u16 *)&dst[index] = __raw_readw(fifo); 392 index += 2; 393 } 394 } else { 395 if (len >= 2) { 396 ioread16_rep(fifo, dst, len >> 1); 397 index = len & ~0x01; 398 } 399 } 400 if (len & 0x01) 401 dst[index] = __raw_readb(fifo); 402 } else { 403 /* byte aligned */ 404 ioread8_rep(fifo, dst, len); 405 } 406 } 407 408 /* 409 * Old style IO functions 410 */ 411 u8 (*musb_readb)(const void __iomem *addr, unsigned offset); 412 EXPORT_SYMBOL_GPL(musb_readb); 413 414 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data); 415 EXPORT_SYMBOL_GPL(musb_writeb); 416 417 u16 (*musb_readw)(const void __iomem *addr, unsigned offset); 418 EXPORT_SYMBOL_GPL(musb_readw); 419 420 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data); 421 EXPORT_SYMBOL_GPL(musb_writew); 422 423 u32 (*musb_readl)(const void __iomem *addr, unsigned offset); 424 EXPORT_SYMBOL_GPL(musb_readl); 425 426 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data); 427 EXPORT_SYMBOL_GPL(musb_writel); 428 429 #ifndef CONFIG_MUSB_PIO_ONLY 430 struct dma_controller * 431 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); 432 EXPORT_SYMBOL(musb_dma_controller_create); 433 434 void (*musb_dma_controller_destroy)(struct dma_controller *c); 435 EXPORT_SYMBOL(musb_dma_controller_destroy); 436 #endif 437 438 /* 439 * New style IO functions 440 */ 441 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 442 { 443 return hw_ep->musb->io.read_fifo(hw_ep, len, dst); 444 } 445 446 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 447 { 448 return hw_ep->musb->io.write_fifo(hw_ep, len, src); 449 } 450 451 /*-------------------------------------------------------------------------*/ 452 453 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 454 static const u8 musb_test_packet[53] = { 455 /* implicit SYNC then DATA0 to start */ 456 457 /* JKJKJKJK x9 */ 458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 459 /* JJKKJJKK x8 */ 460 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 461 /* JJJJKKKK x8 */ 462 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 463 /* JJJJJJJKKKKKKK x8 */ 464 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 465 /* JJJJJJJK x8 */ 466 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 467 /* JKKKKKKK x10, JK */ 468 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 469 470 /* implicit CRC16 then EOP to end */ 471 }; 472 473 void musb_load_testpacket(struct musb *musb) 474 { 475 void __iomem *regs = musb->endpoints[0].regs; 476 477 musb_ep_select(musb->mregs, 0); 478 musb_write_fifo(musb->control_ep, 479 sizeof(musb_test_packet), musb_test_packet); 480 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 481 } 482 483 /*-------------------------------------------------------------------------*/ 484 485 /* 486 * Handles OTG hnp timeouts, such as b_ase0_brst 487 */ 488 static void musb_otg_timer_func(unsigned long data) 489 { 490 struct musb *musb = (struct musb *)data; 491 unsigned long flags; 492 493 spin_lock_irqsave(&musb->lock, flags); 494 switch (musb->xceiv->otg->state) { 495 case OTG_STATE_B_WAIT_ACON: 496 musb_dbg(musb, 497 "HNP: b_wait_acon timeout; back to b_peripheral"); 498 musb_g_disconnect(musb); 499 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 500 musb->is_active = 0; 501 break; 502 case OTG_STATE_A_SUSPEND: 503 case OTG_STATE_A_WAIT_BCON: 504 musb_dbg(musb, "HNP: %s timeout", 505 usb_otg_state_string(musb->xceiv->otg->state)); 506 musb_platform_set_vbus(musb, 0); 507 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 508 break; 509 default: 510 musb_dbg(musb, "HNP: Unhandled mode %s", 511 usb_otg_state_string(musb->xceiv->otg->state)); 512 } 513 spin_unlock_irqrestore(&musb->lock, flags); 514 } 515 516 /* 517 * Stops the HNP transition. Caller must take care of locking. 518 */ 519 void musb_hnp_stop(struct musb *musb) 520 { 521 struct usb_hcd *hcd = musb->hcd; 522 void __iomem *mbase = musb->mregs; 523 u8 reg; 524 525 musb_dbg(musb, "HNP: stop from %s", 526 usb_otg_state_string(musb->xceiv->otg->state)); 527 528 switch (musb->xceiv->otg->state) { 529 case OTG_STATE_A_PERIPHERAL: 530 musb_g_disconnect(musb); 531 musb_dbg(musb, "HNP: back to %s", 532 usb_otg_state_string(musb->xceiv->otg->state)); 533 break; 534 case OTG_STATE_B_HOST: 535 musb_dbg(musb, "HNP: Disabling HR"); 536 if (hcd) 537 hcd->self.is_b_host = 0; 538 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 539 MUSB_DEV_MODE(musb); 540 reg = musb_readb(mbase, MUSB_POWER); 541 reg |= MUSB_POWER_SUSPENDM; 542 musb_writeb(mbase, MUSB_POWER, reg); 543 /* REVISIT: Start SESSION_REQUEST here? */ 544 break; 545 default: 546 musb_dbg(musb, "HNP: Stopping in unknown state %s", 547 usb_otg_state_string(musb->xceiv->otg->state)); 548 } 549 550 /* 551 * When returning to A state after HNP, avoid hub_port_rebounce(), 552 * which cause occasional OPT A "Did not receive reset after connect" 553 * errors. 554 */ 555 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 556 } 557 558 static void musb_recover_from_babble(struct musb *musb); 559 560 /* 561 * Interrupt Service Routine to record USB "global" interrupts. 562 * Since these do not happen often and signify things of 563 * paramount importance, it seems OK to check them individually; 564 * the order of the tests is specified in the manual 565 * 566 * @param musb instance pointer 567 * @param int_usb register contents 568 * @param devctl 569 * @param power 570 */ 571 572 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 573 u8 devctl) 574 { 575 irqreturn_t handled = IRQ_NONE; 576 577 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb); 578 579 /* in host mode, the peripheral may issue remote wakeup. 580 * in peripheral mode, the host may resume the link. 581 * spurious RESUME irqs happen too, paired with SUSPEND. 582 */ 583 if (int_usb & MUSB_INTR_RESUME) { 584 handled = IRQ_HANDLED; 585 musb_dbg(musb, "RESUME (%s)", 586 usb_otg_state_string(musb->xceiv->otg->state)); 587 588 if (devctl & MUSB_DEVCTL_HM) { 589 switch (musb->xceiv->otg->state) { 590 case OTG_STATE_A_SUSPEND: 591 /* remote wakeup? */ 592 musb->port1_status |= 593 (USB_PORT_STAT_C_SUSPEND << 16) 594 | MUSB_PORT_STAT_RESUME; 595 musb->rh_timer = jiffies 596 + msecs_to_jiffies(USB_RESUME_TIMEOUT); 597 musb->xceiv->otg->state = OTG_STATE_A_HOST; 598 musb->is_active = 1; 599 musb_host_resume_root_hub(musb); 600 schedule_delayed_work(&musb->finish_resume_work, 601 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 602 break; 603 case OTG_STATE_B_WAIT_ACON: 604 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 605 musb->is_active = 1; 606 MUSB_DEV_MODE(musb); 607 break; 608 default: 609 WARNING("bogus %s RESUME (%s)\n", 610 "host", 611 usb_otg_state_string(musb->xceiv->otg->state)); 612 } 613 } else { 614 switch (musb->xceiv->otg->state) { 615 case OTG_STATE_A_SUSPEND: 616 /* possibly DISCONNECT is upcoming */ 617 musb->xceiv->otg->state = OTG_STATE_A_HOST; 618 musb_host_resume_root_hub(musb); 619 break; 620 case OTG_STATE_B_WAIT_ACON: 621 case OTG_STATE_B_PERIPHERAL: 622 /* disconnect while suspended? we may 623 * not get a disconnect irq... 624 */ 625 if ((devctl & MUSB_DEVCTL_VBUS) 626 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 627 ) { 628 musb->int_usb |= MUSB_INTR_DISCONNECT; 629 musb->int_usb &= ~MUSB_INTR_SUSPEND; 630 break; 631 } 632 musb_g_resume(musb); 633 break; 634 case OTG_STATE_B_IDLE: 635 musb->int_usb &= ~MUSB_INTR_SUSPEND; 636 break; 637 default: 638 WARNING("bogus %s RESUME (%s)\n", 639 "peripheral", 640 usb_otg_state_string(musb->xceiv->otg->state)); 641 } 642 } 643 } 644 645 /* see manual for the order of the tests */ 646 if (int_usb & MUSB_INTR_SESSREQ) { 647 void __iomem *mbase = musb->mregs; 648 649 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 650 && (devctl & MUSB_DEVCTL_BDEVICE)) { 651 musb_dbg(musb, "SessReq while on B state"); 652 return IRQ_HANDLED; 653 } 654 655 musb_dbg(musb, "SESSION_REQUEST (%s)", 656 usb_otg_state_string(musb->xceiv->otg->state)); 657 658 /* IRQ arrives from ID pin sense or (later, if VBUS power 659 * is removed) SRP. responses are time critical: 660 * - turn on VBUS (with silicon-specific mechanism) 661 * - go through A_WAIT_VRISE 662 * - ... to A_WAIT_BCON. 663 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 664 */ 665 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 666 musb->ep0_stage = MUSB_EP0_START; 667 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 668 MUSB_HST_MODE(musb); 669 musb_platform_set_vbus(musb, 1); 670 671 handled = IRQ_HANDLED; 672 } 673 674 if (int_usb & MUSB_INTR_VBUSERROR) { 675 int ignore = 0; 676 677 /* During connection as an A-Device, we may see a short 678 * current spikes causing voltage drop, because of cable 679 * and peripheral capacitance combined with vbus draw. 680 * (So: less common with truly self-powered devices, where 681 * vbus doesn't act like a power supply.) 682 * 683 * Such spikes are short; usually less than ~500 usec, max 684 * of ~2 msec. That is, they're not sustained overcurrent 685 * errors, though they're reported using VBUSERROR irqs. 686 * 687 * Workarounds: (a) hardware: use self powered devices. 688 * (b) software: ignore non-repeated VBUS errors. 689 * 690 * REVISIT: do delays from lots of DEBUG_KERNEL checks 691 * make trouble here, keeping VBUS < 4.4V ? 692 */ 693 switch (musb->xceiv->otg->state) { 694 case OTG_STATE_A_HOST: 695 /* recovery is dicey once we've gotten past the 696 * initial stages of enumeration, but if VBUS 697 * stayed ok at the other end of the link, and 698 * another reset is due (at least for high speed, 699 * to redo the chirp etc), it might work OK... 700 */ 701 case OTG_STATE_A_WAIT_BCON: 702 case OTG_STATE_A_WAIT_VRISE: 703 if (musb->vbuserr_retry) { 704 void __iomem *mbase = musb->mregs; 705 706 musb->vbuserr_retry--; 707 ignore = 1; 708 devctl |= MUSB_DEVCTL_SESSION; 709 musb_writeb(mbase, MUSB_DEVCTL, devctl); 710 } else { 711 musb->port1_status |= 712 USB_PORT_STAT_OVERCURRENT 713 | (USB_PORT_STAT_C_OVERCURRENT << 16); 714 } 715 break; 716 default: 717 break; 718 } 719 720 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 721 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 722 usb_otg_state_string(musb->xceiv->otg->state), 723 devctl, 724 ({ char *s; 725 switch (devctl & MUSB_DEVCTL_VBUS) { 726 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 727 s = "<SessEnd"; break; 728 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 729 s = "<AValid"; break; 730 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 731 s = "<VBusValid"; break; 732 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 733 default: 734 s = "VALID"; break; 735 } s; }), 736 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 737 musb->port1_status); 738 739 /* go through A_WAIT_VFALL then start a new session */ 740 if (!ignore) 741 musb_platform_set_vbus(musb, 0); 742 handled = IRQ_HANDLED; 743 } 744 745 if (int_usb & MUSB_INTR_SUSPEND) { 746 musb_dbg(musb, "SUSPEND (%s) devctl %02x", 747 usb_otg_state_string(musb->xceiv->otg->state), devctl); 748 handled = IRQ_HANDLED; 749 750 switch (musb->xceiv->otg->state) { 751 case OTG_STATE_A_PERIPHERAL: 752 /* We also come here if the cable is removed, since 753 * this silicon doesn't report ID-no-longer-grounded. 754 * 755 * We depend on T(a_wait_bcon) to shut us down, and 756 * hope users don't do anything dicey during this 757 * undesired detour through A_WAIT_BCON. 758 */ 759 musb_hnp_stop(musb); 760 musb_host_resume_root_hub(musb); 761 musb_root_disconnect(musb); 762 musb_platform_try_idle(musb, jiffies 763 + msecs_to_jiffies(musb->a_wait_bcon 764 ? : OTG_TIME_A_WAIT_BCON)); 765 766 break; 767 case OTG_STATE_B_IDLE: 768 if (!musb->is_active) 769 break; 770 case OTG_STATE_B_PERIPHERAL: 771 musb_g_suspend(musb); 772 musb->is_active = musb->g.b_hnp_enable; 773 if (musb->is_active) { 774 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; 775 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst"); 776 mod_timer(&musb->otg_timer, jiffies 777 + msecs_to_jiffies( 778 OTG_TIME_B_ASE0_BRST)); 779 } 780 break; 781 case OTG_STATE_A_WAIT_BCON: 782 if (musb->a_wait_bcon != 0) 783 musb_platform_try_idle(musb, jiffies 784 + msecs_to_jiffies(musb->a_wait_bcon)); 785 break; 786 case OTG_STATE_A_HOST: 787 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; 788 musb->is_active = musb->hcd->self.b_hnp_enable; 789 break; 790 case OTG_STATE_B_HOST: 791 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 792 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST"); 793 break; 794 default: 795 /* "should not happen" */ 796 musb->is_active = 0; 797 break; 798 } 799 } 800 801 if (int_usb & MUSB_INTR_CONNECT) { 802 struct usb_hcd *hcd = musb->hcd; 803 804 handled = IRQ_HANDLED; 805 musb->is_active = 1; 806 807 musb->ep0_stage = MUSB_EP0_START; 808 809 musb->intrtxe = musb->epmask; 810 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 811 musb->intrrxe = musb->epmask & 0xfffe; 812 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 813 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 814 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 815 |USB_PORT_STAT_HIGH_SPEED 816 |USB_PORT_STAT_ENABLE 817 ); 818 musb->port1_status |= USB_PORT_STAT_CONNECTION 819 |(USB_PORT_STAT_C_CONNECTION << 16); 820 821 /* high vs full speed is just a guess until after reset */ 822 if (devctl & MUSB_DEVCTL_LSDEV) 823 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 824 825 /* indicate new connection to OTG machine */ 826 switch (musb->xceiv->otg->state) { 827 case OTG_STATE_B_PERIPHERAL: 828 if (int_usb & MUSB_INTR_SUSPEND) { 829 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host"); 830 int_usb &= ~MUSB_INTR_SUSPEND; 831 goto b_host; 832 } else 833 musb_dbg(musb, "CONNECT as b_peripheral???"); 834 break; 835 case OTG_STATE_B_WAIT_ACON: 836 musb_dbg(musb, "HNP: CONNECT, now b_host"); 837 b_host: 838 musb->xceiv->otg->state = OTG_STATE_B_HOST; 839 if (musb->hcd) 840 musb->hcd->self.is_b_host = 1; 841 del_timer(&musb->otg_timer); 842 break; 843 default: 844 if ((devctl & MUSB_DEVCTL_VBUS) 845 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 846 musb->xceiv->otg->state = OTG_STATE_A_HOST; 847 if (hcd) 848 hcd->self.is_b_host = 0; 849 } 850 break; 851 } 852 853 musb_host_poke_root_hub(musb); 854 855 musb_dbg(musb, "CONNECT (%s) devctl %02x", 856 usb_otg_state_string(musb->xceiv->otg->state), devctl); 857 } 858 859 if (int_usb & MUSB_INTR_DISCONNECT) { 860 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x", 861 usb_otg_state_string(musb->xceiv->otg->state), 862 MUSB_MODE(musb), devctl); 863 handled = IRQ_HANDLED; 864 865 switch (musb->xceiv->otg->state) { 866 case OTG_STATE_A_HOST: 867 case OTG_STATE_A_SUSPEND: 868 musb_host_resume_root_hub(musb); 869 musb_root_disconnect(musb); 870 if (musb->a_wait_bcon != 0) 871 musb_platform_try_idle(musb, jiffies 872 + msecs_to_jiffies(musb->a_wait_bcon)); 873 break; 874 case OTG_STATE_B_HOST: 875 /* REVISIT this behaves for "real disconnect" 876 * cases; make sure the other transitions from 877 * from B_HOST act right too. The B_HOST code 878 * in hnp_stop() is currently not used... 879 */ 880 musb_root_disconnect(musb); 881 if (musb->hcd) 882 musb->hcd->self.is_b_host = 0; 883 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 884 MUSB_DEV_MODE(musb); 885 musb_g_disconnect(musb); 886 break; 887 case OTG_STATE_A_PERIPHERAL: 888 musb_hnp_stop(musb); 889 musb_root_disconnect(musb); 890 /* FALLTHROUGH */ 891 case OTG_STATE_B_WAIT_ACON: 892 /* FALLTHROUGH */ 893 case OTG_STATE_B_PERIPHERAL: 894 case OTG_STATE_B_IDLE: 895 musb_g_disconnect(musb); 896 break; 897 default: 898 WARNING("unhandled DISCONNECT transition (%s)\n", 899 usb_otg_state_string(musb->xceiv->otg->state)); 900 break; 901 } 902 } 903 904 /* mentor saves a bit: bus reset and babble share the same irq. 905 * only host sees babble; only peripheral sees bus reset. 906 */ 907 if (int_usb & MUSB_INTR_RESET) { 908 handled = IRQ_HANDLED; 909 if (is_host_active(musb)) { 910 /* 911 * When BABBLE happens what we can depends on which 912 * platform MUSB is running, because some platforms 913 * implemented proprietary means for 'recovering' from 914 * Babble conditions. One such platform is AM335x. In 915 * most cases, however, the only thing we can do is 916 * drop the session. 917 */ 918 dev_err(musb->controller, "Babble\n"); 919 musb_recover_from_babble(musb); 920 } else { 921 musb_dbg(musb, "BUS RESET as %s", 922 usb_otg_state_string(musb->xceiv->otg->state)); 923 switch (musb->xceiv->otg->state) { 924 case OTG_STATE_A_SUSPEND: 925 musb_g_reset(musb); 926 /* FALLTHROUGH */ 927 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 928 /* never use invalid T(a_wait_bcon) */ 929 musb_dbg(musb, "HNP: in %s, %d msec timeout", 930 usb_otg_state_string(musb->xceiv->otg->state), 931 TA_WAIT_BCON(musb)); 932 mod_timer(&musb->otg_timer, jiffies 933 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 934 break; 935 case OTG_STATE_A_PERIPHERAL: 936 del_timer(&musb->otg_timer); 937 musb_g_reset(musb); 938 break; 939 case OTG_STATE_B_WAIT_ACON: 940 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral", 941 usb_otg_state_string(musb->xceiv->otg->state)); 942 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 943 musb_g_reset(musb); 944 break; 945 case OTG_STATE_B_IDLE: 946 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 947 /* FALLTHROUGH */ 948 case OTG_STATE_B_PERIPHERAL: 949 musb_g_reset(musb); 950 break; 951 default: 952 musb_dbg(musb, "Unhandled BUS RESET as %s", 953 usb_otg_state_string(musb->xceiv->otg->state)); 954 } 955 } 956 } 957 958 #if 0 959 /* REVISIT ... this would be for multiplexing periodic endpoints, or 960 * supporting transfer phasing to prevent exceeding ISO bandwidth 961 * limits of a given frame or microframe. 962 * 963 * It's not needed for peripheral side, which dedicates endpoints; 964 * though it _might_ use SOF irqs for other purposes. 965 * 966 * And it's not currently needed for host side, which also dedicates 967 * endpoints, relies on TX/RX interval registers, and isn't claimed 968 * to support ISO transfers yet. 969 */ 970 if (int_usb & MUSB_INTR_SOF) { 971 void __iomem *mbase = musb->mregs; 972 struct musb_hw_ep *ep; 973 u8 epnum; 974 u16 frame; 975 976 dev_dbg(musb->controller, "START_OF_FRAME\n"); 977 handled = IRQ_HANDLED; 978 979 /* start any periodic Tx transfers waiting for current frame */ 980 frame = musb_readw(mbase, MUSB_FRAME); 981 ep = musb->endpoints; 982 for (epnum = 1; (epnum < musb->nr_endpoints) 983 && (musb->epmask >= (1 << epnum)); 984 epnum++, ep++) { 985 /* 986 * FIXME handle framecounter wraps (12 bits) 987 * eliminate duplicated StartUrb logic 988 */ 989 if (ep->dwWaitFrame >= frame) { 990 ep->dwWaitFrame = 0; 991 pr_debug("SOF --> periodic TX%s on %d\n", 992 ep->tx_channel ? " DMA" : "", 993 epnum); 994 if (!ep->tx_channel) 995 musb_h_tx_start(musb, epnum); 996 else 997 cppi_hostdma_start(musb, epnum); 998 } 999 } /* end of for loop */ 1000 } 1001 #endif 1002 1003 schedule_delayed_work(&musb->irq_work, 0); 1004 1005 return handled; 1006 } 1007 1008 /*-------------------------------------------------------------------------*/ 1009 1010 static void musb_disable_interrupts(struct musb *musb) 1011 { 1012 void __iomem *mbase = musb->mregs; 1013 u16 temp; 1014 1015 /* disable interrupts */ 1016 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1017 musb->intrtxe = 0; 1018 musb_writew(mbase, MUSB_INTRTXE, 0); 1019 musb->intrrxe = 0; 1020 musb_writew(mbase, MUSB_INTRRXE, 0); 1021 1022 /* flush pending interrupts */ 1023 temp = musb_readb(mbase, MUSB_INTRUSB); 1024 temp = musb_readw(mbase, MUSB_INTRTX); 1025 temp = musb_readw(mbase, MUSB_INTRRX); 1026 } 1027 1028 static void musb_enable_interrupts(struct musb *musb) 1029 { 1030 void __iomem *regs = musb->mregs; 1031 1032 /* Set INT enable registers, enable interrupts */ 1033 musb->intrtxe = musb->epmask; 1034 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); 1035 musb->intrrxe = musb->epmask & 0xfffe; 1036 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); 1037 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 1038 1039 } 1040 1041 /* 1042 * Program the HDRC to start (enable interrupts, dma, etc.). 1043 */ 1044 void musb_start(struct musb *musb) 1045 { 1046 void __iomem *regs = musb->mregs; 1047 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 1048 u8 power; 1049 1050 musb_dbg(musb, "<== devctl %02x", devctl); 1051 1052 musb_enable_interrupts(musb); 1053 musb_writeb(regs, MUSB_TESTMODE, 0); 1054 1055 power = MUSB_POWER_ISOUPDATE; 1056 /* 1057 * treating UNKNOWN as unspecified maximum speed, in which case 1058 * we will default to high-speed. 1059 */ 1060 if (musb->config->maximum_speed == USB_SPEED_HIGH || 1061 musb->config->maximum_speed == USB_SPEED_UNKNOWN) 1062 power |= MUSB_POWER_HSENAB; 1063 musb_writeb(regs, MUSB_POWER, power); 1064 1065 musb->is_active = 0; 1066 devctl = musb_readb(regs, MUSB_DEVCTL); 1067 devctl &= ~MUSB_DEVCTL_SESSION; 1068 1069 /* session started after: 1070 * (a) ID-grounded irq, host mode; 1071 * (b) vbus present/connect IRQ, peripheral mode; 1072 * (c) peripheral initiates, using SRP 1073 */ 1074 if (musb->port_mode != MUSB_PORT_MODE_HOST && 1075 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON && 1076 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { 1077 musb->is_active = 1; 1078 } else { 1079 devctl |= MUSB_DEVCTL_SESSION; 1080 } 1081 1082 musb_platform_enable(musb); 1083 musb_writeb(regs, MUSB_DEVCTL, devctl); 1084 } 1085 1086 /* 1087 * Make the HDRC stop (disable interrupts, etc.); 1088 * reversible by musb_start 1089 * called on gadget driver unregister 1090 * with controller locked, irqs blocked 1091 * acts as a NOP unless some role activated the hardware 1092 */ 1093 void musb_stop(struct musb *musb) 1094 { 1095 /* stop IRQs, timers, ... */ 1096 musb_platform_disable(musb); 1097 musb_disable_interrupts(musb); 1098 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1099 1100 /* FIXME 1101 * - mark host and/or peripheral drivers unusable/inactive 1102 * - disable DMA (and enable it in HdrcStart) 1103 * - make sure we can musb_start() after musb_stop(); with 1104 * OTG mode, gadget driver module rmmod/modprobe cycles that 1105 * - ... 1106 */ 1107 musb_platform_try_idle(musb, 0); 1108 } 1109 1110 /*-------------------------------------------------------------------------*/ 1111 1112 /* 1113 * The silicon either has hard-wired endpoint configurations, or else 1114 * "dynamic fifo" sizing. The driver has support for both, though at this 1115 * writing only the dynamic sizing is very well tested. Since we switched 1116 * away from compile-time hardware parameters, we can no longer rely on 1117 * dead code elimination to leave only the relevant one in the object file. 1118 * 1119 * We don't currently use dynamic fifo setup capability to do anything 1120 * more than selecting one of a bunch of predefined configurations. 1121 */ 1122 static ushort fifo_mode; 1123 1124 /* "modprobe ... fifo_mode=1" etc */ 1125 module_param(fifo_mode, ushort, 0); 1126 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1127 1128 /* 1129 * tables defining fifo_mode values. define more if you like. 1130 * for host side, make sure both halves of ep1 are set up. 1131 */ 1132 1133 /* mode 0 - fits in 2KB */ 1134 static struct musb_fifo_cfg mode_0_cfg[] = { 1135 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1136 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1137 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1138 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1139 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1140 }; 1141 1142 /* mode 1 - fits in 4KB */ 1143 static struct musb_fifo_cfg mode_1_cfg[] = { 1144 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1145 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1146 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1147 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1148 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1149 }; 1150 1151 /* mode 2 - fits in 4KB */ 1152 static struct musb_fifo_cfg mode_2_cfg[] = { 1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1157 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, }, 1158 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, }, 1159 }; 1160 1161 /* mode 3 - fits in 4KB */ 1162 static struct musb_fifo_cfg mode_3_cfg[] = { 1163 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1164 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1165 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1166 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1167 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1168 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1169 }; 1170 1171 /* mode 4 - fits in 16KB */ 1172 static struct musb_fifo_cfg mode_4_cfg[] = { 1173 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1174 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1175 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1176 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1177 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1178 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1179 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1180 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1181 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1182 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1183 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1184 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1185 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1186 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1187 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1188 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1189 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1190 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1191 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1192 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1193 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1194 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1195 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1196 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1197 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1198 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1199 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1200 }; 1201 1202 /* mode 5 - fits in 8KB */ 1203 static struct musb_fifo_cfg mode_5_cfg[] = { 1204 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1205 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1206 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1207 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1208 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1209 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1210 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1211 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1212 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1213 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1214 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1215 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1216 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1217 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1218 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1219 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1220 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1221 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1222 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1223 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1224 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1225 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1226 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1227 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1228 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1229 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1230 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1231 }; 1232 1233 /* 1234 * configure a fifo; for non-shared endpoints, this may be called 1235 * once for a tx fifo and once for an rx fifo. 1236 * 1237 * returns negative errno or offset for next fifo. 1238 */ 1239 static int 1240 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1241 const struct musb_fifo_cfg *cfg, u16 offset) 1242 { 1243 void __iomem *mbase = musb->mregs; 1244 int size = 0; 1245 u16 maxpacket = cfg->maxpacket; 1246 u16 c_off = offset >> 3; 1247 u8 c_size; 1248 1249 /* expect hw_ep has already been zero-initialized */ 1250 1251 size = ffs(max(maxpacket, (u16) 8)) - 1; 1252 maxpacket = 1 << size; 1253 1254 c_size = size - 3; 1255 if (cfg->mode == BUF_DOUBLE) { 1256 if ((offset + (maxpacket << 1)) > 1257 (1 << (musb->config->ram_bits + 2))) 1258 return -EMSGSIZE; 1259 c_size |= MUSB_FIFOSZ_DPB; 1260 } else { 1261 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1262 return -EMSGSIZE; 1263 } 1264 1265 /* configure the FIFO */ 1266 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1267 1268 /* EP0 reserved endpoint for control, bidirectional; 1269 * EP1 reserved for bulk, two unidirectional halves. 1270 */ 1271 if (hw_ep->epnum == 1) 1272 musb->bulk_ep = hw_ep; 1273 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1274 switch (cfg->style) { 1275 case FIFO_TX: 1276 musb_write_txfifosz(mbase, c_size); 1277 musb_write_txfifoadd(mbase, c_off); 1278 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1279 hw_ep->max_packet_sz_tx = maxpacket; 1280 break; 1281 case FIFO_RX: 1282 musb_write_rxfifosz(mbase, c_size); 1283 musb_write_rxfifoadd(mbase, c_off); 1284 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1285 hw_ep->max_packet_sz_rx = maxpacket; 1286 break; 1287 case FIFO_RXTX: 1288 musb_write_txfifosz(mbase, c_size); 1289 musb_write_txfifoadd(mbase, c_off); 1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1291 hw_ep->max_packet_sz_rx = maxpacket; 1292 1293 musb_write_rxfifosz(mbase, c_size); 1294 musb_write_rxfifoadd(mbase, c_off); 1295 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1296 hw_ep->max_packet_sz_tx = maxpacket; 1297 1298 hw_ep->is_shared_fifo = true; 1299 break; 1300 } 1301 1302 /* NOTE rx and tx endpoint irqs aren't managed separately, 1303 * which happens to be ok 1304 */ 1305 musb->epmask |= (1 << hw_ep->epnum); 1306 1307 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1308 } 1309 1310 static struct musb_fifo_cfg ep0_cfg = { 1311 .style = FIFO_RXTX, .maxpacket = 64, 1312 }; 1313 1314 static int ep_config_from_table(struct musb *musb) 1315 { 1316 const struct musb_fifo_cfg *cfg; 1317 unsigned i, n; 1318 int offset; 1319 struct musb_hw_ep *hw_ep = musb->endpoints; 1320 1321 if (musb->config->fifo_cfg) { 1322 cfg = musb->config->fifo_cfg; 1323 n = musb->config->fifo_cfg_size; 1324 goto done; 1325 } 1326 1327 switch (fifo_mode) { 1328 default: 1329 fifo_mode = 0; 1330 /* FALLTHROUGH */ 1331 case 0: 1332 cfg = mode_0_cfg; 1333 n = ARRAY_SIZE(mode_0_cfg); 1334 break; 1335 case 1: 1336 cfg = mode_1_cfg; 1337 n = ARRAY_SIZE(mode_1_cfg); 1338 break; 1339 case 2: 1340 cfg = mode_2_cfg; 1341 n = ARRAY_SIZE(mode_2_cfg); 1342 break; 1343 case 3: 1344 cfg = mode_3_cfg; 1345 n = ARRAY_SIZE(mode_3_cfg); 1346 break; 1347 case 4: 1348 cfg = mode_4_cfg; 1349 n = ARRAY_SIZE(mode_4_cfg); 1350 break; 1351 case 5: 1352 cfg = mode_5_cfg; 1353 n = ARRAY_SIZE(mode_5_cfg); 1354 break; 1355 } 1356 1357 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1358 1359 1360 done: 1361 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1362 /* assert(offset > 0) */ 1363 1364 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1365 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1366 */ 1367 1368 for (i = 0; i < n; i++) { 1369 u8 epn = cfg->hw_ep_num; 1370 1371 if (epn >= musb->config->num_eps) { 1372 pr_debug("%s: invalid ep %d\n", 1373 musb_driver_name, epn); 1374 return -EINVAL; 1375 } 1376 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1377 if (offset < 0) { 1378 pr_debug("%s: mem overrun, ep %d\n", 1379 musb_driver_name, epn); 1380 return offset; 1381 } 1382 epn++; 1383 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1384 } 1385 1386 pr_debug("%s: %d/%d max ep, %d/%d memory\n", 1387 musb_driver_name, 1388 n + 1, musb->config->num_eps * 2 - 1, 1389 offset, (1 << (musb->config->ram_bits + 2))); 1390 1391 if (!musb->bulk_ep) { 1392 pr_debug("%s: missing bulk\n", musb_driver_name); 1393 return -EINVAL; 1394 } 1395 1396 return 0; 1397 } 1398 1399 1400 /* 1401 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1402 * @param musb the controller 1403 */ 1404 static int ep_config_from_hw(struct musb *musb) 1405 { 1406 u8 epnum = 0; 1407 struct musb_hw_ep *hw_ep; 1408 void __iomem *mbase = musb->mregs; 1409 int ret = 0; 1410 1411 musb_dbg(musb, "<== static silicon ep config"); 1412 1413 /* FIXME pick up ep0 maxpacket size */ 1414 1415 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1416 musb_ep_select(mbase, epnum); 1417 hw_ep = musb->endpoints + epnum; 1418 1419 ret = musb_read_fifosize(musb, hw_ep, epnum); 1420 if (ret < 0) 1421 break; 1422 1423 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1424 1425 /* pick an RX/TX endpoint for bulk */ 1426 if (hw_ep->max_packet_sz_tx < 512 1427 || hw_ep->max_packet_sz_rx < 512) 1428 continue; 1429 1430 /* REVISIT: this algorithm is lazy, we should at least 1431 * try to pick a double buffered endpoint. 1432 */ 1433 if (musb->bulk_ep) 1434 continue; 1435 musb->bulk_ep = hw_ep; 1436 } 1437 1438 if (!musb->bulk_ep) { 1439 pr_debug("%s: missing bulk\n", musb_driver_name); 1440 return -EINVAL; 1441 } 1442 1443 return 0; 1444 } 1445 1446 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1447 1448 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1449 * configure endpoints, or take their config from silicon 1450 */ 1451 static int musb_core_init(u16 musb_type, struct musb *musb) 1452 { 1453 u8 reg; 1454 char *type; 1455 char aInfo[90]; 1456 void __iomem *mbase = musb->mregs; 1457 int status = 0; 1458 int i; 1459 1460 /* log core options (read using indexed model) */ 1461 reg = musb_read_configdata(mbase); 1462 1463 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1464 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1465 strcat(aInfo, ", dyn FIFOs"); 1466 musb->dyn_fifo = true; 1467 } 1468 if (reg & MUSB_CONFIGDATA_MPRXE) { 1469 strcat(aInfo, ", bulk combine"); 1470 musb->bulk_combine = true; 1471 } 1472 if (reg & MUSB_CONFIGDATA_MPTXE) { 1473 strcat(aInfo, ", bulk split"); 1474 musb->bulk_split = true; 1475 } 1476 if (reg & MUSB_CONFIGDATA_HBRXE) { 1477 strcat(aInfo, ", HB-ISO Rx"); 1478 musb->hb_iso_rx = true; 1479 } 1480 if (reg & MUSB_CONFIGDATA_HBTXE) { 1481 strcat(aInfo, ", HB-ISO Tx"); 1482 musb->hb_iso_tx = true; 1483 } 1484 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1485 strcat(aInfo, ", SoftConn"); 1486 1487 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1488 1489 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1490 musb->is_multipoint = 1; 1491 type = "M"; 1492 } else { 1493 musb->is_multipoint = 0; 1494 type = ""; 1495 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1496 pr_err("%s: kernel must blacklist external hubs\n", 1497 musb_driver_name); 1498 #endif 1499 } 1500 1501 /* log release info */ 1502 musb->hwvers = musb_read_hwvers(mbase); 1503 pr_debug("%s: %sHDRC RTL version %d.%d%s\n", 1504 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers), 1505 MUSB_HWVERS_MINOR(musb->hwvers), 1506 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1507 1508 /* configure ep0 */ 1509 musb_configure_ep0(musb); 1510 1511 /* discover endpoint configuration */ 1512 musb->nr_endpoints = 1; 1513 musb->epmask = 1; 1514 1515 if (musb->dyn_fifo) 1516 status = ep_config_from_table(musb); 1517 else 1518 status = ep_config_from_hw(musb); 1519 1520 if (status < 0) 1521 return status; 1522 1523 /* finish init, and print endpoint config */ 1524 for (i = 0; i < musb->nr_endpoints; i++) { 1525 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1526 1527 hw_ep->fifo = musb->io.fifo_offset(i) + mbase; 1528 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) 1529 if (musb->io.quirks & MUSB_IN_TUSB) { 1530 hw_ep->fifo_async = musb->async + 0x400 + 1531 musb->io.fifo_offset(i); 1532 hw_ep->fifo_sync = musb->sync + 0x400 + 1533 musb->io.fifo_offset(i); 1534 hw_ep->fifo_sync_va = 1535 musb->sync_va + 0x400 + musb->io.fifo_offset(i); 1536 1537 if (i == 0) 1538 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1539 else 1540 hw_ep->conf = mbase + 0x400 + 1541 (((i - 1) & 0xf) << 2); 1542 } 1543 #endif 1544 1545 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; 1546 hw_ep->rx_reinit = 1; 1547 hw_ep->tx_reinit = 1; 1548 1549 if (hw_ep->max_packet_sz_tx) { 1550 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1551 musb_driver_name, i, 1552 hw_ep->is_shared_fifo ? "shared" : "tx", 1553 hw_ep->tx_double_buffered 1554 ? "doublebuffer, " : "", 1555 hw_ep->max_packet_sz_tx); 1556 } 1557 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1558 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1559 musb_driver_name, i, 1560 "rx", 1561 hw_ep->rx_double_buffered 1562 ? "doublebuffer, " : "", 1563 hw_ep->max_packet_sz_rx); 1564 } 1565 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1566 musb_dbg(musb, "hw_ep %d not configured", i); 1567 } 1568 1569 return 0; 1570 } 1571 1572 /*-------------------------------------------------------------------------*/ 1573 1574 /* 1575 * handle all the irqs defined by the HDRC core. for now we expect: other 1576 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1577 * will be assigned, and the irq will already have been acked. 1578 * 1579 * called in irq context with spinlock held, irqs blocked 1580 */ 1581 irqreturn_t musb_interrupt(struct musb *musb) 1582 { 1583 irqreturn_t retval = IRQ_NONE; 1584 unsigned long status; 1585 unsigned long epnum; 1586 u8 devctl; 1587 1588 if (!musb->int_usb && !musb->int_tx && !musb->int_rx) 1589 return IRQ_NONE; 1590 1591 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1592 1593 trace_musb_isr(musb); 1594 1595 /** 1596 * According to Mentor Graphics' documentation, flowchart on page 98, 1597 * IRQ should be handled as follows: 1598 * 1599 * . Resume IRQ 1600 * . Session Request IRQ 1601 * . VBUS Error IRQ 1602 * . Suspend IRQ 1603 * . Connect IRQ 1604 * . Disconnect IRQ 1605 * . Reset/Babble IRQ 1606 * . SOF IRQ (we're not using this one) 1607 * . Endpoint 0 IRQ 1608 * . TX Endpoints 1609 * . RX Endpoints 1610 * 1611 * We will be following that flowchart in order to avoid any problems 1612 * that might arise with internal Finite State Machine. 1613 */ 1614 1615 if (musb->int_usb) 1616 retval |= musb_stage0_irq(musb, musb->int_usb, devctl); 1617 1618 if (musb->int_tx & 1) { 1619 if (is_host_active(musb)) 1620 retval |= musb_h_ep0_irq(musb); 1621 else 1622 retval |= musb_g_ep0_irq(musb); 1623 1624 /* we have just handled endpoint 0 IRQ, clear it */ 1625 musb->int_tx &= ~BIT(0); 1626 } 1627 1628 status = musb->int_tx; 1629 1630 for_each_set_bit(epnum, &status, 16) { 1631 retval = IRQ_HANDLED; 1632 if (is_host_active(musb)) 1633 musb_host_tx(musb, epnum); 1634 else 1635 musb_g_tx(musb, epnum); 1636 } 1637 1638 status = musb->int_rx; 1639 1640 for_each_set_bit(epnum, &status, 16) { 1641 retval = IRQ_HANDLED; 1642 if (is_host_active(musb)) 1643 musb_host_rx(musb, epnum); 1644 else 1645 musb_g_rx(musb, epnum); 1646 } 1647 1648 return retval; 1649 } 1650 EXPORT_SYMBOL_GPL(musb_interrupt); 1651 1652 #ifndef CONFIG_MUSB_PIO_ONLY 1653 static bool use_dma = 1; 1654 1655 /* "modprobe ... use_dma=0" etc */ 1656 module_param(use_dma, bool, 0644); 1657 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1658 1659 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1660 { 1661 /* called with controller lock already held */ 1662 1663 if (!epnum) { 1664 if (!is_cppi_enabled(musb)) { 1665 /* endpoint 0 */ 1666 if (is_host_active(musb)) 1667 musb_h_ep0_irq(musb); 1668 else 1669 musb_g_ep0_irq(musb); 1670 } 1671 } else { 1672 /* endpoints 1..15 */ 1673 if (transmit) { 1674 if (is_host_active(musb)) 1675 musb_host_tx(musb, epnum); 1676 else 1677 musb_g_tx(musb, epnum); 1678 } else { 1679 /* receive */ 1680 if (is_host_active(musb)) 1681 musb_host_rx(musb, epnum); 1682 else 1683 musb_g_rx(musb, epnum); 1684 } 1685 } 1686 } 1687 EXPORT_SYMBOL_GPL(musb_dma_completion); 1688 1689 #else 1690 #define use_dma 0 1691 #endif 1692 1693 static int (*musb_phy_callback)(enum musb_vbus_id_status status); 1694 1695 /* 1696 * musb_mailbox - optional phy notifier function 1697 * @status phy state change 1698 * 1699 * Optionally gets called from the USB PHY. Note that the USB PHY must be 1700 * disabled at the point the phy_callback is registered or unregistered. 1701 */ 1702 int musb_mailbox(enum musb_vbus_id_status status) 1703 { 1704 if (musb_phy_callback) 1705 return musb_phy_callback(status); 1706 1707 return -ENODEV; 1708 }; 1709 EXPORT_SYMBOL_GPL(musb_mailbox); 1710 1711 /*-------------------------------------------------------------------------*/ 1712 1713 static ssize_t 1714 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1715 { 1716 struct musb *musb = dev_to_musb(dev); 1717 unsigned long flags; 1718 int ret = -EINVAL; 1719 1720 spin_lock_irqsave(&musb->lock, flags); 1721 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); 1722 spin_unlock_irqrestore(&musb->lock, flags); 1723 1724 return ret; 1725 } 1726 1727 static ssize_t 1728 musb_mode_store(struct device *dev, struct device_attribute *attr, 1729 const char *buf, size_t n) 1730 { 1731 struct musb *musb = dev_to_musb(dev); 1732 unsigned long flags; 1733 int status; 1734 1735 spin_lock_irqsave(&musb->lock, flags); 1736 if (sysfs_streq(buf, "host")) 1737 status = musb_platform_set_mode(musb, MUSB_HOST); 1738 else if (sysfs_streq(buf, "peripheral")) 1739 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1740 else if (sysfs_streq(buf, "otg")) 1741 status = musb_platform_set_mode(musb, MUSB_OTG); 1742 else 1743 status = -EINVAL; 1744 spin_unlock_irqrestore(&musb->lock, flags); 1745 1746 return (status == 0) ? n : status; 1747 } 1748 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1749 1750 static ssize_t 1751 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1752 const char *buf, size_t n) 1753 { 1754 struct musb *musb = dev_to_musb(dev); 1755 unsigned long flags; 1756 unsigned long val; 1757 1758 if (sscanf(buf, "%lu", &val) < 1) { 1759 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1760 return -EINVAL; 1761 } 1762 1763 spin_lock_irqsave(&musb->lock, flags); 1764 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1765 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1766 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) 1767 musb->is_active = 0; 1768 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1769 spin_unlock_irqrestore(&musb->lock, flags); 1770 1771 return n; 1772 } 1773 1774 static ssize_t 1775 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1776 { 1777 struct musb *musb = dev_to_musb(dev); 1778 unsigned long flags; 1779 unsigned long val; 1780 int vbus; 1781 u8 devctl; 1782 1783 spin_lock_irqsave(&musb->lock, flags); 1784 val = musb->a_wait_bcon; 1785 vbus = musb_platform_get_vbus_status(musb); 1786 if (vbus < 0) { 1787 /* Use default MUSB method by means of DEVCTL register */ 1788 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1789 if ((devctl & MUSB_DEVCTL_VBUS) 1790 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) 1791 vbus = 1; 1792 else 1793 vbus = 0; 1794 } 1795 spin_unlock_irqrestore(&musb->lock, flags); 1796 1797 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1798 vbus ? "on" : "off", val); 1799 } 1800 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1801 1802 /* Gadget drivers can't know that a host is connected so they might want 1803 * to start SRP, but users can. This allows userspace to trigger SRP. 1804 */ 1805 static ssize_t 1806 musb_srp_store(struct device *dev, struct device_attribute *attr, 1807 const char *buf, size_t n) 1808 { 1809 struct musb *musb = dev_to_musb(dev); 1810 unsigned short srp; 1811 1812 if (sscanf(buf, "%hu", &srp) != 1 1813 || (srp != 1)) { 1814 dev_err(dev, "SRP: Value must be 1\n"); 1815 return -EINVAL; 1816 } 1817 1818 if (srp == 1) 1819 musb_g_wakeup(musb); 1820 1821 return n; 1822 } 1823 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1824 1825 static struct attribute *musb_attributes[] = { 1826 &dev_attr_mode.attr, 1827 &dev_attr_vbus.attr, 1828 &dev_attr_srp.attr, 1829 NULL 1830 }; 1831 1832 static const struct attribute_group musb_attr_group = { 1833 .attrs = musb_attributes, 1834 }; 1835 1836 #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \ 1837 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1838 MUSB_DEVCTL_SESSION) 1839 #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1840 MUSB_DEVCTL_SESSION) 1841 1842 /* 1843 * Check the musb devctl session bit to determine if we want to 1844 * allow PM runtime for the device. In general, we want to keep things 1845 * active when the session bit is set except after host disconnect. 1846 * 1847 * Only called from musb_irq_work. If this ever needs to get called 1848 * elsewhere, proper locking must be implemented for musb->session. 1849 */ 1850 static void musb_pm_runtime_check_session(struct musb *musb) 1851 { 1852 u8 devctl, s; 1853 int error; 1854 1855 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1856 1857 /* Handle session status quirks first */ 1858 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV | 1859 MUSB_DEVCTL_HR; 1860 switch (devctl & ~s) { 1861 case MUSB_QUIRK_B_INVALID_VBUS_91: 1862 if (musb->quirk_retries && !musb->flush_irq_work) { 1863 musb_dbg(musb, 1864 "Poll devctl on invalid vbus, assume no session"); 1865 schedule_delayed_work(&musb->irq_work, 1866 msecs_to_jiffies(1000)); 1867 musb->quirk_retries--; 1868 return; 1869 } 1870 /* fall through */ 1871 case MUSB_QUIRK_A_DISCONNECT_19: 1872 if (musb->quirk_retries && !musb->flush_irq_work) { 1873 musb_dbg(musb, 1874 "Poll devctl on possible host mode disconnect"); 1875 schedule_delayed_work(&musb->irq_work, 1876 msecs_to_jiffies(1000)); 1877 musb->quirk_retries--; 1878 return; 1879 } 1880 if (!musb->session) 1881 break; 1882 musb_dbg(musb, "Allow PM on possible host mode disconnect"); 1883 pm_runtime_mark_last_busy(musb->controller); 1884 pm_runtime_put_autosuspend(musb->controller); 1885 musb->session = false; 1886 return; 1887 default: 1888 break; 1889 } 1890 1891 /* No need to do anything if session has not changed */ 1892 s = devctl & MUSB_DEVCTL_SESSION; 1893 if (s == musb->session) 1894 return; 1895 1896 /* Block PM or allow PM? */ 1897 if (s) { 1898 musb_dbg(musb, "Block PM on active session: %02x", devctl); 1899 error = pm_runtime_get_sync(musb->controller); 1900 if (error < 0) 1901 dev_err(musb->controller, "Could not enable: %i\n", 1902 error); 1903 musb->quirk_retries = 3; 1904 } else { 1905 musb_dbg(musb, "Allow PM with no session: %02x", devctl); 1906 pm_runtime_mark_last_busy(musb->controller); 1907 pm_runtime_put_autosuspend(musb->controller); 1908 } 1909 1910 musb->session = s; 1911 } 1912 1913 /* Only used to provide driver mode change events */ 1914 static void musb_irq_work(struct work_struct *data) 1915 { 1916 struct musb *musb = container_of(data, struct musb, irq_work.work); 1917 int error; 1918 1919 error = pm_runtime_get_sync(musb->controller); 1920 if (error < 0) { 1921 dev_err(musb->controller, "Could not enable: %i\n", error); 1922 1923 return; 1924 } 1925 1926 musb_pm_runtime_check_session(musb); 1927 1928 if (musb->xceiv->otg->state != musb->xceiv_old_state) { 1929 musb->xceiv_old_state = musb->xceiv->otg->state; 1930 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1931 } 1932 1933 pm_runtime_mark_last_busy(musb->controller); 1934 pm_runtime_put_autosuspend(musb->controller); 1935 } 1936 1937 static void musb_recover_from_babble(struct musb *musb) 1938 { 1939 int ret; 1940 u8 devctl; 1941 1942 musb_disable_interrupts(musb); 1943 1944 /* 1945 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give 1946 * it some slack and wait for 10us. 1947 */ 1948 udelay(10); 1949 1950 ret = musb_platform_recover(musb); 1951 if (ret) { 1952 musb_enable_interrupts(musb); 1953 return; 1954 } 1955 1956 /* drop session bit */ 1957 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1958 devctl &= ~MUSB_DEVCTL_SESSION; 1959 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 1960 1961 /* tell usbcore about it */ 1962 musb_root_disconnect(musb); 1963 1964 /* 1965 * When a babble condition occurs, the musb controller 1966 * removes the session bit and the endpoint config is lost. 1967 */ 1968 if (musb->dyn_fifo) 1969 ret = ep_config_from_table(musb); 1970 else 1971 ret = ep_config_from_hw(musb); 1972 1973 /* restart session */ 1974 if (ret == 0) 1975 musb_start(musb); 1976 } 1977 1978 /* -------------------------------------------------------------------------- 1979 * Init support 1980 */ 1981 1982 static struct musb *allocate_instance(struct device *dev, 1983 const struct musb_hdrc_config *config, void __iomem *mbase) 1984 { 1985 struct musb *musb; 1986 struct musb_hw_ep *ep; 1987 int epnum; 1988 int ret; 1989 1990 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 1991 if (!musb) 1992 return NULL; 1993 1994 INIT_LIST_HEAD(&musb->control); 1995 INIT_LIST_HEAD(&musb->in_bulk); 1996 INIT_LIST_HEAD(&musb->out_bulk); 1997 INIT_LIST_HEAD(&musb->pending_list); 1998 1999 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 2000 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 2001 musb->mregs = mbase; 2002 musb->ctrl_base = mbase; 2003 musb->nIrq = -ENODEV; 2004 musb->config = config; 2005 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 2006 for (epnum = 0, ep = musb->endpoints; 2007 epnum < musb->config->num_eps; 2008 epnum++, ep++) { 2009 ep->musb = musb; 2010 ep->epnum = epnum; 2011 } 2012 2013 musb->controller = dev; 2014 2015 ret = musb_host_alloc(musb); 2016 if (ret < 0) 2017 goto err_free; 2018 2019 dev_set_drvdata(dev, musb); 2020 2021 return musb; 2022 2023 err_free: 2024 return NULL; 2025 } 2026 2027 static void musb_free(struct musb *musb) 2028 { 2029 /* this has multiple entry modes. it handles fault cleanup after 2030 * probe(), where things may be partially set up, as well as rmmod 2031 * cleanup after everything's been de-activated. 2032 */ 2033 2034 #ifdef CONFIG_SYSFS 2035 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 2036 #endif 2037 2038 if (musb->nIrq >= 0) { 2039 if (musb->irq_wake) 2040 disable_irq_wake(musb->nIrq); 2041 free_irq(musb->nIrq, musb); 2042 } 2043 2044 musb_host_free(musb); 2045 } 2046 2047 struct musb_pending_work { 2048 int (*callback)(struct musb *musb, void *data); 2049 void *data; 2050 struct list_head node; 2051 }; 2052 2053 #ifdef CONFIG_PM 2054 /* 2055 * Called from musb_runtime_resume(), musb_resume(), and 2056 * musb_queue_resume_work(). Callers must take musb->lock. 2057 */ 2058 static int musb_run_resume_work(struct musb *musb) 2059 { 2060 struct musb_pending_work *w, *_w; 2061 unsigned long flags; 2062 int error = 0; 2063 2064 spin_lock_irqsave(&musb->list_lock, flags); 2065 list_for_each_entry_safe(w, _w, &musb->pending_list, node) { 2066 if (w->callback) { 2067 error = w->callback(musb, w->data); 2068 if (error < 0) { 2069 dev_err(musb->controller, 2070 "resume callback %p failed: %i\n", 2071 w->callback, error); 2072 } 2073 } 2074 list_del(&w->node); 2075 devm_kfree(musb->controller, w); 2076 } 2077 spin_unlock_irqrestore(&musb->list_lock, flags); 2078 2079 return error; 2080 } 2081 #endif 2082 2083 /* 2084 * Called to run work if device is active or else queue the work to happen 2085 * on resume. Caller must take musb->lock and must hold an RPM reference. 2086 * 2087 * Note that we cowardly refuse queuing work after musb PM runtime 2088 * resume is done calling musb_run_resume_work() and return -EINPROGRESS 2089 * instead. 2090 */ 2091 int musb_queue_resume_work(struct musb *musb, 2092 int (*callback)(struct musb *musb, void *data), 2093 void *data) 2094 { 2095 struct musb_pending_work *w; 2096 unsigned long flags; 2097 int error; 2098 2099 if (WARN_ON(!callback)) 2100 return -EINVAL; 2101 2102 if (pm_runtime_active(musb->controller)) 2103 return callback(musb, data); 2104 2105 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); 2106 if (!w) 2107 return -ENOMEM; 2108 2109 w->callback = callback; 2110 w->data = data; 2111 spin_lock_irqsave(&musb->list_lock, flags); 2112 if (musb->is_runtime_suspended) { 2113 list_add_tail(&w->node, &musb->pending_list); 2114 error = 0; 2115 } else { 2116 dev_err(musb->controller, "could not add resume work %p\n", 2117 callback); 2118 devm_kfree(musb->controller, w); 2119 error = -EINPROGRESS; 2120 } 2121 spin_unlock_irqrestore(&musb->list_lock, flags); 2122 2123 return error; 2124 } 2125 EXPORT_SYMBOL_GPL(musb_queue_resume_work); 2126 2127 static void musb_deassert_reset(struct work_struct *work) 2128 { 2129 struct musb *musb; 2130 unsigned long flags; 2131 2132 musb = container_of(work, struct musb, deassert_reset_work.work); 2133 2134 spin_lock_irqsave(&musb->lock, flags); 2135 2136 if (musb->port1_status & USB_PORT_STAT_RESET) 2137 musb_port_reset(musb, false); 2138 2139 spin_unlock_irqrestore(&musb->lock, flags); 2140 } 2141 2142 /* 2143 * Perform generic per-controller initialization. 2144 * 2145 * @dev: the controller (already clocked, etc) 2146 * @nIrq: IRQ number 2147 * @ctrl: virtual address of controller registers, 2148 * not yet corrected for platform-specific offsets 2149 */ 2150 static int 2151 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 2152 { 2153 int status; 2154 struct musb *musb; 2155 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 2156 2157 /* The driver might handle more features than the board; OK. 2158 * Fail when the board needs a feature that's not enabled. 2159 */ 2160 if (!plat) { 2161 dev_err(dev, "no platform_data?\n"); 2162 status = -ENODEV; 2163 goto fail0; 2164 } 2165 2166 /* allocate */ 2167 musb = allocate_instance(dev, plat->config, ctrl); 2168 if (!musb) { 2169 status = -ENOMEM; 2170 goto fail0; 2171 } 2172 2173 spin_lock_init(&musb->lock); 2174 spin_lock_init(&musb->list_lock); 2175 musb->board_set_power = plat->set_power; 2176 musb->min_power = plat->min_power; 2177 musb->ops = plat->platform_ops; 2178 musb->port_mode = plat->mode; 2179 2180 /* 2181 * Initialize the default IO functions. At least omap2430 needs 2182 * these early. We initialize the platform specific IO functions 2183 * later on. 2184 */ 2185 musb_readb = musb_default_readb; 2186 musb_writeb = musb_default_writeb; 2187 musb_readw = musb_default_readw; 2188 musb_writew = musb_default_writew; 2189 musb_readl = musb_default_readl; 2190 musb_writel = musb_default_writel; 2191 2192 /* The musb_platform_init() call: 2193 * - adjusts musb->mregs 2194 * - sets the musb->isr 2195 * - may initialize an integrated transceiver 2196 * - initializes musb->xceiv, usually by otg_get_phy() 2197 * - stops powering VBUS 2198 * 2199 * There are various transceiver configurations. Blackfin, 2200 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2201 * external/discrete ones in various flavors (twl4030 family, 2202 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2203 */ 2204 status = musb_platform_init(musb); 2205 if (status < 0) 2206 goto fail1; 2207 2208 if (!musb->isr) { 2209 status = -ENODEV; 2210 goto fail2; 2211 } 2212 2213 if (musb->ops->quirks) 2214 musb->io.quirks = musb->ops->quirks; 2215 2216 /* Most devices use indexed offset or flat offset */ 2217 if (musb->io.quirks & MUSB_INDEXED_EP) { 2218 musb->io.ep_offset = musb_indexed_ep_offset; 2219 musb->io.ep_select = musb_indexed_ep_select; 2220 } else { 2221 musb->io.ep_offset = musb_flat_ep_offset; 2222 musb->io.ep_select = musb_flat_ep_select; 2223 } 2224 2225 if (musb->io.quirks & MUSB_G_NO_SKB_RESERVE) 2226 musb->g.quirk_avoids_skb_reserve = 1; 2227 2228 /* At least tusb6010 has its own offsets */ 2229 if (musb->ops->ep_offset) 2230 musb->io.ep_offset = musb->ops->ep_offset; 2231 if (musb->ops->ep_select) 2232 musb->io.ep_select = musb->ops->ep_select; 2233 2234 if (musb->ops->fifo_mode) 2235 fifo_mode = musb->ops->fifo_mode; 2236 else 2237 fifo_mode = 4; 2238 2239 if (musb->ops->fifo_offset) 2240 musb->io.fifo_offset = musb->ops->fifo_offset; 2241 else 2242 musb->io.fifo_offset = musb_default_fifo_offset; 2243 2244 if (musb->ops->busctl_offset) 2245 musb->io.busctl_offset = musb->ops->busctl_offset; 2246 else 2247 musb->io.busctl_offset = musb_default_busctl_offset; 2248 2249 if (musb->ops->readb) 2250 musb_readb = musb->ops->readb; 2251 if (musb->ops->writeb) 2252 musb_writeb = musb->ops->writeb; 2253 if (musb->ops->readw) 2254 musb_readw = musb->ops->readw; 2255 if (musb->ops->writew) 2256 musb_writew = musb->ops->writew; 2257 if (musb->ops->readl) 2258 musb_readl = musb->ops->readl; 2259 if (musb->ops->writel) 2260 musb_writel = musb->ops->writel; 2261 2262 #ifndef CONFIG_MUSB_PIO_ONLY 2263 if (!musb->ops->dma_init || !musb->ops->dma_exit) { 2264 dev_err(dev, "DMA controller not set\n"); 2265 status = -ENODEV; 2266 goto fail2; 2267 } 2268 musb_dma_controller_create = musb->ops->dma_init; 2269 musb_dma_controller_destroy = musb->ops->dma_exit; 2270 #endif 2271 2272 if (musb->ops->read_fifo) 2273 musb->io.read_fifo = musb->ops->read_fifo; 2274 else 2275 musb->io.read_fifo = musb_default_read_fifo; 2276 2277 if (musb->ops->write_fifo) 2278 musb->io.write_fifo = musb->ops->write_fifo; 2279 else 2280 musb->io.write_fifo = musb_default_write_fifo; 2281 2282 if (!musb->xceiv->io_ops) { 2283 musb->xceiv->io_dev = musb->controller; 2284 musb->xceiv->io_priv = musb->mregs; 2285 musb->xceiv->io_ops = &musb_ulpi_access; 2286 } 2287 2288 if (musb->ops->phy_callback) 2289 musb_phy_callback = musb->ops->phy_callback; 2290 2291 /* 2292 * We need musb_read/write functions initialized for PM. 2293 * Note that at least 2430 glue needs autosuspend delay 2294 * somewhere above 300 ms for the hardware to idle properly 2295 * after disconnecting the cable in host mode. Let's use 2296 * 500 ms for some margin. 2297 */ 2298 pm_runtime_use_autosuspend(musb->controller); 2299 pm_runtime_set_autosuspend_delay(musb->controller, 500); 2300 pm_runtime_enable(musb->controller); 2301 pm_runtime_get_sync(musb->controller); 2302 2303 status = usb_phy_init(musb->xceiv); 2304 if (status < 0) 2305 goto err_usb_phy_init; 2306 2307 if (use_dma && dev->dma_mask) { 2308 musb->dma_controller = 2309 musb_dma_controller_create(musb, musb->mregs); 2310 if (IS_ERR(musb->dma_controller)) { 2311 status = PTR_ERR(musb->dma_controller); 2312 goto fail2_5; 2313 } 2314 } 2315 2316 /* be sure interrupts are disabled before connecting ISR */ 2317 musb_platform_disable(musb); 2318 musb_disable_interrupts(musb); 2319 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2320 2321 /* Init IRQ workqueue before request_irq */ 2322 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); 2323 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); 2324 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); 2325 2326 /* setup musb parts of the core (especially endpoints) */ 2327 status = musb_core_init(plat->config->multipoint 2328 ? MUSB_CONTROLLER_MHDRC 2329 : MUSB_CONTROLLER_HDRC, musb); 2330 if (status < 0) 2331 goto fail3; 2332 2333 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2334 2335 /* attach to the IRQ */ 2336 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) { 2337 dev_err(dev, "request_irq %d failed!\n", nIrq); 2338 status = -ENODEV; 2339 goto fail3; 2340 } 2341 musb->nIrq = nIrq; 2342 /* FIXME this handles wakeup irqs wrong */ 2343 if (enable_irq_wake(nIrq) == 0) { 2344 musb->irq_wake = 1; 2345 device_init_wakeup(dev, 1); 2346 } else { 2347 musb->irq_wake = 0; 2348 } 2349 2350 /* program PHY to use external vBus if required */ 2351 if (plat->extvbus) { 2352 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2353 busctl |= MUSB_ULPI_USE_EXTVBUS; 2354 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2355 } 2356 2357 if (musb->xceiv->otg->default_a) { 2358 MUSB_HST_MODE(musb); 2359 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 2360 } else { 2361 MUSB_DEV_MODE(musb); 2362 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 2363 } 2364 2365 switch (musb->port_mode) { 2366 case MUSB_PORT_MODE_HOST: 2367 status = musb_host_setup(musb, plat->power); 2368 if (status < 0) 2369 goto fail3; 2370 status = musb_platform_set_mode(musb, MUSB_HOST); 2371 break; 2372 case MUSB_PORT_MODE_GADGET: 2373 status = musb_gadget_setup(musb); 2374 if (status < 0) 2375 goto fail3; 2376 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 2377 break; 2378 case MUSB_PORT_MODE_DUAL_ROLE: 2379 status = musb_host_setup(musb, plat->power); 2380 if (status < 0) 2381 goto fail3; 2382 status = musb_gadget_setup(musb); 2383 if (status) { 2384 musb_host_cleanup(musb); 2385 goto fail3; 2386 } 2387 status = musb_platform_set_mode(musb, MUSB_OTG); 2388 break; 2389 default: 2390 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 2391 break; 2392 } 2393 2394 if (status < 0) 2395 goto fail3; 2396 2397 status = musb_init_debugfs(musb); 2398 if (status < 0) 2399 goto fail4; 2400 2401 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2402 if (status) 2403 goto fail5; 2404 2405 musb->is_initialized = 1; 2406 pm_runtime_mark_last_busy(musb->controller); 2407 pm_runtime_put_autosuspend(musb->controller); 2408 2409 return 0; 2410 2411 fail5: 2412 musb_exit_debugfs(musb); 2413 2414 fail4: 2415 musb_gadget_cleanup(musb); 2416 musb_host_cleanup(musb); 2417 2418 fail3: 2419 cancel_delayed_work_sync(&musb->irq_work); 2420 cancel_delayed_work_sync(&musb->finish_resume_work); 2421 cancel_delayed_work_sync(&musb->deassert_reset_work); 2422 if (musb->dma_controller) 2423 musb_dma_controller_destroy(musb->dma_controller); 2424 2425 fail2_5: 2426 usb_phy_shutdown(musb->xceiv); 2427 2428 err_usb_phy_init: 2429 pm_runtime_dont_use_autosuspend(musb->controller); 2430 pm_runtime_put_sync(musb->controller); 2431 pm_runtime_disable(musb->controller); 2432 2433 fail2: 2434 if (musb->irq_wake) 2435 device_init_wakeup(dev, 0); 2436 musb_platform_exit(musb); 2437 2438 fail1: 2439 if (status != -EPROBE_DEFER) 2440 dev_err(musb->controller, 2441 "%s failed with status %d\n", __func__, status); 2442 2443 musb_free(musb); 2444 2445 fail0: 2446 2447 return status; 2448 2449 } 2450 2451 /*-------------------------------------------------------------------------*/ 2452 2453 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2454 * bridge to a platform device; this driver then suffices. 2455 */ 2456 static int musb_probe(struct platform_device *pdev) 2457 { 2458 struct device *dev = &pdev->dev; 2459 int irq = platform_get_irq_byname(pdev, "mc"); 2460 struct resource *iomem; 2461 void __iomem *base; 2462 2463 if (irq <= 0) 2464 return -ENODEV; 2465 2466 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2467 base = devm_ioremap_resource(dev, iomem); 2468 if (IS_ERR(base)) 2469 return PTR_ERR(base); 2470 2471 return musb_init_controller(dev, irq, base); 2472 } 2473 2474 static int musb_remove(struct platform_device *pdev) 2475 { 2476 struct device *dev = &pdev->dev; 2477 struct musb *musb = dev_to_musb(dev); 2478 unsigned long flags; 2479 2480 /* this gets called on rmmod. 2481 * - Host mode: host may still be active 2482 * - Peripheral mode: peripheral is deactivated (or never-activated) 2483 * - OTG mode: both roles are deactivated (or never-activated) 2484 */ 2485 musb_exit_debugfs(musb); 2486 2487 cancel_delayed_work_sync(&musb->irq_work); 2488 cancel_delayed_work_sync(&musb->finish_resume_work); 2489 cancel_delayed_work_sync(&musb->deassert_reset_work); 2490 pm_runtime_get_sync(musb->controller); 2491 musb_host_cleanup(musb); 2492 musb_gadget_cleanup(musb); 2493 2494 musb_platform_disable(musb); 2495 spin_lock_irqsave(&musb->lock, flags); 2496 musb_disable_interrupts(musb); 2497 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2498 spin_unlock_irqrestore(&musb->lock, flags); 2499 2500 pm_runtime_dont_use_autosuspend(musb->controller); 2501 pm_runtime_put_sync(musb->controller); 2502 pm_runtime_disable(musb->controller); 2503 musb_platform_exit(musb); 2504 musb_phy_callback = NULL; 2505 if (musb->dma_controller) 2506 musb_dma_controller_destroy(musb->dma_controller); 2507 usb_phy_shutdown(musb->xceiv); 2508 musb_free(musb); 2509 device_init_wakeup(dev, 0); 2510 return 0; 2511 } 2512 2513 #ifdef CONFIG_PM 2514 2515 static void musb_save_context(struct musb *musb) 2516 { 2517 int i; 2518 void __iomem *musb_base = musb->mregs; 2519 void __iomem *epio; 2520 2521 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2522 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2523 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2524 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2525 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2526 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2527 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2528 2529 for (i = 0; i < musb->config->num_eps; ++i) { 2530 struct musb_hw_ep *hw_ep; 2531 2532 hw_ep = &musb->endpoints[i]; 2533 if (!hw_ep) 2534 continue; 2535 2536 epio = hw_ep->regs; 2537 if (!epio) 2538 continue; 2539 2540 musb_writeb(musb_base, MUSB_INDEX, i); 2541 musb->context.index_regs[i].txmaxp = 2542 musb_readw(epio, MUSB_TXMAXP); 2543 musb->context.index_regs[i].txcsr = 2544 musb_readw(epio, MUSB_TXCSR); 2545 musb->context.index_regs[i].rxmaxp = 2546 musb_readw(epio, MUSB_RXMAXP); 2547 musb->context.index_regs[i].rxcsr = 2548 musb_readw(epio, MUSB_RXCSR); 2549 2550 if (musb->dyn_fifo) { 2551 musb->context.index_regs[i].txfifoadd = 2552 musb_read_txfifoadd(musb_base); 2553 musb->context.index_regs[i].rxfifoadd = 2554 musb_read_rxfifoadd(musb_base); 2555 musb->context.index_regs[i].txfifosz = 2556 musb_read_txfifosz(musb_base); 2557 musb->context.index_regs[i].rxfifosz = 2558 musb_read_rxfifosz(musb_base); 2559 } 2560 2561 musb->context.index_regs[i].txtype = 2562 musb_readb(epio, MUSB_TXTYPE); 2563 musb->context.index_regs[i].txinterval = 2564 musb_readb(epio, MUSB_TXINTERVAL); 2565 musb->context.index_regs[i].rxtype = 2566 musb_readb(epio, MUSB_RXTYPE); 2567 musb->context.index_regs[i].rxinterval = 2568 musb_readb(epio, MUSB_RXINTERVAL); 2569 2570 musb->context.index_regs[i].txfunaddr = 2571 musb_read_txfunaddr(musb, i); 2572 musb->context.index_regs[i].txhubaddr = 2573 musb_read_txhubaddr(musb, i); 2574 musb->context.index_regs[i].txhubport = 2575 musb_read_txhubport(musb, i); 2576 2577 musb->context.index_regs[i].rxfunaddr = 2578 musb_read_rxfunaddr(musb, i); 2579 musb->context.index_regs[i].rxhubaddr = 2580 musb_read_rxhubaddr(musb, i); 2581 musb->context.index_regs[i].rxhubport = 2582 musb_read_rxhubport(musb, i); 2583 } 2584 } 2585 2586 static void musb_restore_context(struct musb *musb) 2587 { 2588 int i; 2589 void __iomem *musb_base = musb->mregs; 2590 void __iomem *epio; 2591 u8 power; 2592 2593 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2594 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2595 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2596 2597 /* Don't affect SUSPENDM/RESUME bits in POWER reg */ 2598 power = musb_readb(musb_base, MUSB_POWER); 2599 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; 2600 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); 2601 power |= musb->context.power; 2602 musb_writeb(musb_base, MUSB_POWER, power); 2603 2604 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2605 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2606 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2607 if (musb->context.devctl & MUSB_DEVCTL_SESSION) 2608 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2609 2610 for (i = 0; i < musb->config->num_eps; ++i) { 2611 struct musb_hw_ep *hw_ep; 2612 2613 hw_ep = &musb->endpoints[i]; 2614 if (!hw_ep) 2615 continue; 2616 2617 epio = hw_ep->regs; 2618 if (!epio) 2619 continue; 2620 2621 musb_writeb(musb_base, MUSB_INDEX, i); 2622 musb_writew(epio, MUSB_TXMAXP, 2623 musb->context.index_regs[i].txmaxp); 2624 musb_writew(epio, MUSB_TXCSR, 2625 musb->context.index_regs[i].txcsr); 2626 musb_writew(epio, MUSB_RXMAXP, 2627 musb->context.index_regs[i].rxmaxp); 2628 musb_writew(epio, MUSB_RXCSR, 2629 musb->context.index_regs[i].rxcsr); 2630 2631 if (musb->dyn_fifo) { 2632 musb_write_txfifosz(musb_base, 2633 musb->context.index_regs[i].txfifosz); 2634 musb_write_rxfifosz(musb_base, 2635 musb->context.index_regs[i].rxfifosz); 2636 musb_write_txfifoadd(musb_base, 2637 musb->context.index_regs[i].txfifoadd); 2638 musb_write_rxfifoadd(musb_base, 2639 musb->context.index_regs[i].rxfifoadd); 2640 } 2641 2642 musb_writeb(epio, MUSB_TXTYPE, 2643 musb->context.index_regs[i].txtype); 2644 musb_writeb(epio, MUSB_TXINTERVAL, 2645 musb->context.index_regs[i].txinterval); 2646 musb_writeb(epio, MUSB_RXTYPE, 2647 musb->context.index_regs[i].rxtype); 2648 musb_writeb(epio, MUSB_RXINTERVAL, 2649 2650 musb->context.index_regs[i].rxinterval); 2651 musb_write_txfunaddr(musb, i, 2652 musb->context.index_regs[i].txfunaddr); 2653 musb_write_txhubaddr(musb, i, 2654 musb->context.index_regs[i].txhubaddr); 2655 musb_write_txhubport(musb, i, 2656 musb->context.index_regs[i].txhubport); 2657 2658 musb_write_rxfunaddr(musb, i, 2659 musb->context.index_regs[i].rxfunaddr); 2660 musb_write_rxhubaddr(musb, i, 2661 musb->context.index_regs[i].rxhubaddr); 2662 musb_write_rxhubport(musb, i, 2663 musb->context.index_regs[i].rxhubport); 2664 } 2665 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2666 } 2667 2668 static int musb_suspend(struct device *dev) 2669 { 2670 struct musb *musb = dev_to_musb(dev); 2671 unsigned long flags; 2672 int ret; 2673 2674 ret = pm_runtime_get_sync(dev); 2675 if (ret < 0) { 2676 pm_runtime_put_noidle(dev); 2677 return ret; 2678 } 2679 2680 musb_platform_disable(musb); 2681 musb_disable_interrupts(musb); 2682 2683 musb->flush_irq_work = true; 2684 while (flush_delayed_work(&musb->irq_work)) 2685 ; 2686 musb->flush_irq_work = false; 2687 2688 if (!(musb->io.quirks & MUSB_PRESERVE_SESSION)) 2689 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2690 2691 WARN_ON(!list_empty(&musb->pending_list)); 2692 2693 spin_lock_irqsave(&musb->lock, flags); 2694 2695 if (is_peripheral_active(musb)) { 2696 /* FIXME force disconnect unless we know USB will wake 2697 * the system up quickly enough to respond ... 2698 */ 2699 } else if (is_host_active(musb)) { 2700 /* we know all the children are suspended; sometimes 2701 * they will even be wakeup-enabled. 2702 */ 2703 } 2704 2705 musb_save_context(musb); 2706 2707 spin_unlock_irqrestore(&musb->lock, flags); 2708 return 0; 2709 } 2710 2711 static int musb_resume(struct device *dev) 2712 { 2713 struct musb *musb = dev_to_musb(dev); 2714 unsigned long flags; 2715 int error; 2716 u8 devctl; 2717 u8 mask; 2718 2719 /* 2720 * For static cmos like DaVinci, register values were preserved 2721 * unless for some reason the whole soc powered down or the USB 2722 * module got reset through the PSC (vs just being disabled). 2723 * 2724 * For the DSPS glue layer though, a full register restore has to 2725 * be done. As it shouldn't harm other platforms, we do it 2726 * unconditionally. 2727 */ 2728 2729 musb_restore_context(musb); 2730 2731 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2732 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; 2733 if ((devctl & mask) != (musb->context.devctl & mask)) 2734 musb->port1_status = 0; 2735 2736 musb_start(musb); 2737 2738 spin_lock_irqsave(&musb->lock, flags); 2739 error = musb_run_resume_work(musb); 2740 if (error) 2741 dev_err(musb->controller, "resume work failed with %i\n", 2742 error); 2743 spin_unlock_irqrestore(&musb->lock, flags); 2744 2745 pm_runtime_mark_last_busy(dev); 2746 pm_runtime_put_autosuspend(dev); 2747 2748 return 0; 2749 } 2750 2751 static int musb_runtime_suspend(struct device *dev) 2752 { 2753 struct musb *musb = dev_to_musb(dev); 2754 2755 musb_save_context(musb); 2756 musb->is_runtime_suspended = 1; 2757 2758 return 0; 2759 } 2760 2761 static int musb_runtime_resume(struct device *dev) 2762 { 2763 struct musb *musb = dev_to_musb(dev); 2764 unsigned long flags; 2765 int error; 2766 2767 /* 2768 * When pm_runtime_get_sync called for the first time in driver 2769 * init, some of the structure is still not initialized which is 2770 * used in restore function. But clock needs to be 2771 * enabled before any register access, so 2772 * pm_runtime_get_sync has to be called. 2773 * Also context restore without save does not make 2774 * any sense 2775 */ 2776 if (!musb->is_initialized) 2777 return 0; 2778 2779 musb_restore_context(musb); 2780 2781 spin_lock_irqsave(&musb->lock, flags); 2782 error = musb_run_resume_work(musb); 2783 if (error) 2784 dev_err(musb->controller, "resume work failed with %i\n", 2785 error); 2786 musb->is_runtime_suspended = 0; 2787 spin_unlock_irqrestore(&musb->lock, flags); 2788 2789 return 0; 2790 } 2791 2792 static const struct dev_pm_ops musb_dev_pm_ops = { 2793 .suspend = musb_suspend, 2794 .resume = musb_resume, 2795 .runtime_suspend = musb_runtime_suspend, 2796 .runtime_resume = musb_runtime_resume, 2797 }; 2798 2799 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2800 #else 2801 #define MUSB_DEV_PM_OPS NULL 2802 #endif 2803 2804 static struct platform_driver musb_driver = { 2805 .driver = { 2806 .name = (char *)musb_driver_name, 2807 .bus = &platform_bus_type, 2808 .pm = MUSB_DEV_PM_OPS, 2809 }, 2810 .probe = musb_probe, 2811 .remove = musb_remove, 2812 }; 2813 2814 module_platform_driver(musb_driver); 2815