1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/init.h> 97 #include <linux/list.h> 98 #include <linux/kobject.h> 99 #include <linux/prefetch.h> 100 #include <linux/platform_device.h> 101 #include <linux/io.h> 102 #include <linux/idr.h> 103 #include <linux/dma-mapping.h> 104 105 #include "musb_core.h" 106 107 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 108 109 110 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 111 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 112 113 #define MUSB_VERSION "6.0" 114 115 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 116 117 #define MUSB_DRIVER_NAME "musb-hdrc" 118 const char musb_driver_name[] = MUSB_DRIVER_NAME; 119 static DEFINE_IDA(musb_ida); 120 121 MODULE_DESCRIPTION(DRIVER_INFO); 122 MODULE_AUTHOR(DRIVER_AUTHOR); 123 MODULE_LICENSE("GPL"); 124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 125 126 127 /*-------------------------------------------------------------------------*/ 128 129 static inline struct musb *dev_to_musb(struct device *dev) 130 { 131 return dev_get_drvdata(dev); 132 } 133 134 /*-------------------------------------------------------------------------*/ 135 136 int musb_get_id(struct device *dev, gfp_t gfp_mask) 137 { 138 int ret; 139 int id; 140 141 ret = ida_pre_get(&musb_ida, gfp_mask); 142 if (!ret) { 143 dev_err(dev, "failed to reserve resource for id\n"); 144 return -ENOMEM; 145 } 146 147 ret = ida_get_new(&musb_ida, &id); 148 if (ret < 0) { 149 dev_err(dev, "failed to allocate a new id\n"); 150 return ret; 151 } 152 153 return id; 154 } 155 EXPORT_SYMBOL_GPL(musb_get_id); 156 157 void musb_put_id(struct device *dev, int id) 158 { 159 160 dev_dbg(dev, "removing id %d\n", id); 161 ida_remove(&musb_ida, id); 162 } 163 EXPORT_SYMBOL_GPL(musb_put_id); 164 165 #ifndef CONFIG_BLACKFIN 166 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 167 { 168 void __iomem *addr = phy->io_priv; 169 int i = 0; 170 u8 r; 171 u8 power; 172 int ret; 173 174 pm_runtime_get_sync(phy->io_dev); 175 176 /* Make sure the transceiver is not in low power mode */ 177 power = musb_readb(addr, MUSB_POWER); 178 power &= ~MUSB_POWER_SUSPENDM; 179 musb_writeb(addr, MUSB_POWER, power); 180 181 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 182 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 183 */ 184 185 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 186 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 187 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 188 189 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 190 & MUSB_ULPI_REG_CMPLT)) { 191 i++; 192 if (i == 10000) { 193 ret = -ETIMEDOUT; 194 goto out; 195 } 196 197 } 198 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 199 r &= ~MUSB_ULPI_REG_CMPLT; 200 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 201 202 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 203 204 out: 205 pm_runtime_put(phy->io_dev); 206 207 return ret; 208 } 209 210 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 211 { 212 void __iomem *addr = phy->io_priv; 213 int i = 0; 214 u8 r = 0; 215 u8 power; 216 int ret = 0; 217 218 pm_runtime_get_sync(phy->io_dev); 219 220 /* Make sure the transceiver is not in low power mode */ 221 power = musb_readb(addr, MUSB_POWER); 222 power &= ~MUSB_POWER_SUSPENDM; 223 musb_writeb(addr, MUSB_POWER, power); 224 225 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 226 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 227 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 228 229 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 230 & MUSB_ULPI_REG_CMPLT)) { 231 i++; 232 if (i == 10000) { 233 ret = -ETIMEDOUT; 234 goto out; 235 } 236 } 237 238 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 239 r &= ~MUSB_ULPI_REG_CMPLT; 240 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 241 242 out: 243 pm_runtime_put(phy->io_dev); 244 245 return ret; 246 } 247 #else 248 #define musb_ulpi_read NULL 249 #define musb_ulpi_write NULL 250 #endif 251 252 static struct usb_phy_io_ops musb_ulpi_access = { 253 .read = musb_ulpi_read, 254 .write = musb_ulpi_write, 255 }; 256 257 /*-------------------------------------------------------------------------*/ 258 259 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 260 261 /* 262 * Load an endpoint's FIFO 263 */ 264 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 265 { 266 struct musb *musb = hw_ep->musb; 267 void __iomem *fifo = hw_ep->fifo; 268 269 if (unlikely(len == 0)) 270 return; 271 272 prefetch((u8 *)src); 273 274 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 275 'T', hw_ep->epnum, fifo, len, src); 276 277 /* we can't assume unaligned reads work */ 278 if (likely((0x01 & (unsigned long) src) == 0)) { 279 u16 index = 0; 280 281 /* best case is 32bit-aligned source address */ 282 if ((0x02 & (unsigned long) src) == 0) { 283 if (len >= 4) { 284 writesl(fifo, src + index, len >> 2); 285 index += len & ~0x03; 286 } 287 if (len & 0x02) { 288 musb_writew(fifo, 0, *(u16 *)&src[index]); 289 index += 2; 290 } 291 } else { 292 if (len >= 2) { 293 writesw(fifo, src + index, len >> 1); 294 index += len & ~0x01; 295 } 296 } 297 if (len & 0x01) 298 musb_writeb(fifo, 0, src[index]); 299 } else { 300 /* byte aligned */ 301 writesb(fifo, src, len); 302 } 303 } 304 305 #if !defined(CONFIG_USB_MUSB_AM35X) 306 /* 307 * Unload an endpoint's FIFO 308 */ 309 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 310 { 311 struct musb *musb = hw_ep->musb; 312 void __iomem *fifo = hw_ep->fifo; 313 314 if (unlikely(len == 0)) 315 return; 316 317 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 318 'R', hw_ep->epnum, fifo, len, dst); 319 320 /* we can't assume unaligned writes work */ 321 if (likely((0x01 & (unsigned long) dst) == 0)) { 322 u16 index = 0; 323 324 /* best case is 32bit-aligned destination address */ 325 if ((0x02 & (unsigned long) dst) == 0) { 326 if (len >= 4) { 327 readsl(fifo, dst, len >> 2); 328 index = len & ~0x03; 329 } 330 if (len & 0x02) { 331 *(u16 *)&dst[index] = musb_readw(fifo, 0); 332 index += 2; 333 } 334 } else { 335 if (len >= 2) { 336 readsw(fifo, dst, len >> 1); 337 index = len & ~0x01; 338 } 339 } 340 if (len & 0x01) 341 dst[index] = musb_readb(fifo, 0); 342 } else { 343 /* byte aligned */ 344 readsb(fifo, dst, len); 345 } 346 } 347 #endif 348 349 #endif /* normal PIO */ 350 351 352 /*-------------------------------------------------------------------------*/ 353 354 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 355 static const u8 musb_test_packet[53] = { 356 /* implicit SYNC then DATA0 to start */ 357 358 /* JKJKJKJK x9 */ 359 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 360 /* JJKKJJKK x8 */ 361 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 362 /* JJJJKKKK x8 */ 363 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 364 /* JJJJJJJKKKKKKK x8 */ 365 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 366 /* JJJJJJJK x8 */ 367 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 368 /* JKKKKKKK x10, JK */ 369 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 370 371 /* implicit CRC16 then EOP to end */ 372 }; 373 374 void musb_load_testpacket(struct musb *musb) 375 { 376 void __iomem *regs = musb->endpoints[0].regs; 377 378 musb_ep_select(musb->mregs, 0); 379 musb_write_fifo(musb->control_ep, 380 sizeof(musb_test_packet), musb_test_packet); 381 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 382 } 383 384 /*-------------------------------------------------------------------------*/ 385 386 /* 387 * Handles OTG hnp timeouts, such as b_ase0_brst 388 */ 389 static void musb_otg_timer_func(unsigned long data) 390 { 391 struct musb *musb = (struct musb *)data; 392 unsigned long flags; 393 394 spin_lock_irqsave(&musb->lock, flags); 395 switch (musb->xceiv->state) { 396 case OTG_STATE_B_WAIT_ACON: 397 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 398 musb_g_disconnect(musb); 399 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 400 musb->is_active = 0; 401 break; 402 case OTG_STATE_A_SUSPEND: 403 case OTG_STATE_A_WAIT_BCON: 404 dev_dbg(musb->controller, "HNP: %s timeout\n", 405 otg_state_string(musb->xceiv->state)); 406 musb_platform_set_vbus(musb, 0); 407 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 408 break; 409 default: 410 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 411 otg_state_string(musb->xceiv->state)); 412 } 413 musb->ignore_disconnect = 0; 414 spin_unlock_irqrestore(&musb->lock, flags); 415 } 416 417 /* 418 * Stops the HNP transition. Caller must take care of locking. 419 */ 420 void musb_hnp_stop(struct musb *musb) 421 { 422 struct usb_hcd *hcd = musb_to_hcd(musb); 423 void __iomem *mbase = musb->mregs; 424 u8 reg; 425 426 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 427 428 switch (musb->xceiv->state) { 429 case OTG_STATE_A_PERIPHERAL: 430 musb_g_disconnect(musb); 431 dev_dbg(musb->controller, "HNP: back to %s\n", 432 otg_state_string(musb->xceiv->state)); 433 break; 434 case OTG_STATE_B_HOST: 435 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 436 hcd->self.is_b_host = 0; 437 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 438 MUSB_DEV_MODE(musb); 439 reg = musb_readb(mbase, MUSB_POWER); 440 reg |= MUSB_POWER_SUSPENDM; 441 musb_writeb(mbase, MUSB_POWER, reg); 442 /* REVISIT: Start SESSION_REQUEST here? */ 443 break; 444 default: 445 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 446 otg_state_string(musb->xceiv->state)); 447 } 448 449 /* 450 * When returning to A state after HNP, avoid hub_port_rebounce(), 451 * which cause occasional OPT A "Did not receive reset after connect" 452 * errors. 453 */ 454 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 455 } 456 457 /* 458 * Interrupt Service Routine to record USB "global" interrupts. 459 * Since these do not happen often and signify things of 460 * paramount importance, it seems OK to check them individually; 461 * the order of the tests is specified in the manual 462 * 463 * @param musb instance pointer 464 * @param int_usb register contents 465 * @param devctl 466 * @param power 467 */ 468 469 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 470 u8 devctl, u8 power) 471 { 472 struct usb_otg *otg = musb->xceiv->otg; 473 irqreturn_t handled = IRQ_NONE; 474 475 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 476 int_usb); 477 478 /* in host mode, the peripheral may issue remote wakeup. 479 * in peripheral mode, the host may resume the link. 480 * spurious RESUME irqs happen too, paired with SUSPEND. 481 */ 482 if (int_usb & MUSB_INTR_RESUME) { 483 handled = IRQ_HANDLED; 484 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 485 486 if (devctl & MUSB_DEVCTL_HM) { 487 void __iomem *mbase = musb->mregs; 488 489 switch (musb->xceiv->state) { 490 case OTG_STATE_A_SUSPEND: 491 /* remote wakeup? later, GetPortStatus 492 * will stop RESUME signaling 493 */ 494 495 if (power & MUSB_POWER_SUSPENDM) { 496 /* spurious */ 497 musb->int_usb &= ~MUSB_INTR_SUSPEND; 498 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 499 break; 500 } 501 502 power &= ~MUSB_POWER_SUSPENDM; 503 musb_writeb(mbase, MUSB_POWER, 504 power | MUSB_POWER_RESUME); 505 506 musb->port1_status |= 507 (USB_PORT_STAT_C_SUSPEND << 16) 508 | MUSB_PORT_STAT_RESUME; 509 musb->rh_timer = jiffies 510 + msecs_to_jiffies(20); 511 512 musb->xceiv->state = OTG_STATE_A_HOST; 513 musb->is_active = 1; 514 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 515 break; 516 case OTG_STATE_B_WAIT_ACON: 517 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 518 musb->is_active = 1; 519 MUSB_DEV_MODE(musb); 520 break; 521 default: 522 WARNING("bogus %s RESUME (%s)\n", 523 "host", 524 otg_state_string(musb->xceiv->state)); 525 } 526 } else { 527 switch (musb->xceiv->state) { 528 case OTG_STATE_A_SUSPEND: 529 /* possibly DISCONNECT is upcoming */ 530 musb->xceiv->state = OTG_STATE_A_HOST; 531 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 532 break; 533 case OTG_STATE_B_WAIT_ACON: 534 case OTG_STATE_B_PERIPHERAL: 535 /* disconnect while suspended? we may 536 * not get a disconnect irq... 537 */ 538 if ((devctl & MUSB_DEVCTL_VBUS) 539 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 540 ) { 541 musb->int_usb |= MUSB_INTR_DISCONNECT; 542 musb->int_usb &= ~MUSB_INTR_SUSPEND; 543 break; 544 } 545 musb_g_resume(musb); 546 break; 547 case OTG_STATE_B_IDLE: 548 musb->int_usb &= ~MUSB_INTR_SUSPEND; 549 break; 550 default: 551 WARNING("bogus %s RESUME (%s)\n", 552 "peripheral", 553 otg_state_string(musb->xceiv->state)); 554 } 555 } 556 } 557 558 /* see manual for the order of the tests */ 559 if (int_usb & MUSB_INTR_SESSREQ) { 560 void __iomem *mbase = musb->mregs; 561 562 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 563 && (devctl & MUSB_DEVCTL_BDEVICE)) { 564 dev_dbg(musb->controller, "SessReq while on B state\n"); 565 return IRQ_HANDLED; 566 } 567 568 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 569 otg_state_string(musb->xceiv->state)); 570 571 /* IRQ arrives from ID pin sense or (later, if VBUS power 572 * is removed) SRP. responses are time critical: 573 * - turn on VBUS (with silicon-specific mechanism) 574 * - go through A_WAIT_VRISE 575 * - ... to A_WAIT_BCON. 576 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 577 */ 578 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 579 musb->ep0_stage = MUSB_EP0_START; 580 musb->xceiv->state = OTG_STATE_A_IDLE; 581 MUSB_HST_MODE(musb); 582 musb_platform_set_vbus(musb, 1); 583 584 handled = IRQ_HANDLED; 585 } 586 587 if (int_usb & MUSB_INTR_VBUSERROR) { 588 int ignore = 0; 589 590 /* During connection as an A-Device, we may see a short 591 * current spikes causing voltage drop, because of cable 592 * and peripheral capacitance combined with vbus draw. 593 * (So: less common with truly self-powered devices, where 594 * vbus doesn't act like a power supply.) 595 * 596 * Such spikes are short; usually less than ~500 usec, max 597 * of ~2 msec. That is, they're not sustained overcurrent 598 * errors, though they're reported using VBUSERROR irqs. 599 * 600 * Workarounds: (a) hardware: use self powered devices. 601 * (b) software: ignore non-repeated VBUS errors. 602 * 603 * REVISIT: do delays from lots of DEBUG_KERNEL checks 604 * make trouble here, keeping VBUS < 4.4V ? 605 */ 606 switch (musb->xceiv->state) { 607 case OTG_STATE_A_HOST: 608 /* recovery is dicey once we've gotten past the 609 * initial stages of enumeration, but if VBUS 610 * stayed ok at the other end of the link, and 611 * another reset is due (at least for high speed, 612 * to redo the chirp etc), it might work OK... 613 */ 614 case OTG_STATE_A_WAIT_BCON: 615 case OTG_STATE_A_WAIT_VRISE: 616 if (musb->vbuserr_retry) { 617 void __iomem *mbase = musb->mregs; 618 619 musb->vbuserr_retry--; 620 ignore = 1; 621 devctl |= MUSB_DEVCTL_SESSION; 622 musb_writeb(mbase, MUSB_DEVCTL, devctl); 623 } else { 624 musb->port1_status |= 625 USB_PORT_STAT_OVERCURRENT 626 | (USB_PORT_STAT_C_OVERCURRENT << 16); 627 } 628 break; 629 default: 630 break; 631 } 632 633 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 634 otg_state_string(musb->xceiv->state), 635 devctl, 636 ({ char *s; 637 switch (devctl & MUSB_DEVCTL_VBUS) { 638 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 639 s = "<SessEnd"; break; 640 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 641 s = "<AValid"; break; 642 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 643 s = "<VBusValid"; break; 644 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 645 default: 646 s = "VALID"; break; 647 }; s; }), 648 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 649 musb->port1_status); 650 651 /* go through A_WAIT_VFALL then start a new session */ 652 if (!ignore) 653 musb_platform_set_vbus(musb, 0); 654 handled = IRQ_HANDLED; 655 } 656 657 if (int_usb & MUSB_INTR_SUSPEND) { 658 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 659 otg_state_string(musb->xceiv->state), devctl, power); 660 handled = IRQ_HANDLED; 661 662 switch (musb->xceiv->state) { 663 case OTG_STATE_A_PERIPHERAL: 664 /* We also come here if the cable is removed, since 665 * this silicon doesn't report ID-no-longer-grounded. 666 * 667 * We depend on T(a_wait_bcon) to shut us down, and 668 * hope users don't do anything dicey during this 669 * undesired detour through A_WAIT_BCON. 670 */ 671 musb_hnp_stop(musb); 672 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 673 musb_root_disconnect(musb); 674 musb_platform_try_idle(musb, jiffies 675 + msecs_to_jiffies(musb->a_wait_bcon 676 ? : OTG_TIME_A_WAIT_BCON)); 677 678 break; 679 case OTG_STATE_B_IDLE: 680 if (!musb->is_active) 681 break; 682 case OTG_STATE_B_PERIPHERAL: 683 musb_g_suspend(musb); 684 musb->is_active = otg->gadget->b_hnp_enable; 685 if (musb->is_active) { 686 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 687 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 688 mod_timer(&musb->otg_timer, jiffies 689 + msecs_to_jiffies( 690 OTG_TIME_B_ASE0_BRST)); 691 } 692 break; 693 case OTG_STATE_A_WAIT_BCON: 694 if (musb->a_wait_bcon != 0) 695 musb_platform_try_idle(musb, jiffies 696 + msecs_to_jiffies(musb->a_wait_bcon)); 697 break; 698 case OTG_STATE_A_HOST: 699 musb->xceiv->state = OTG_STATE_A_SUSPEND; 700 musb->is_active = otg->host->b_hnp_enable; 701 break; 702 case OTG_STATE_B_HOST: 703 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 704 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 705 break; 706 default: 707 /* "should not happen" */ 708 musb->is_active = 0; 709 break; 710 } 711 } 712 713 if (int_usb & MUSB_INTR_CONNECT) { 714 struct usb_hcd *hcd = musb_to_hcd(musb); 715 716 handled = IRQ_HANDLED; 717 musb->is_active = 1; 718 719 musb->ep0_stage = MUSB_EP0_START; 720 721 /* flush endpoints when transitioning from Device Mode */ 722 if (is_peripheral_active(musb)) { 723 /* REVISIT HNP; just force disconnect */ 724 } 725 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 726 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 727 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 728 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 729 |USB_PORT_STAT_HIGH_SPEED 730 |USB_PORT_STAT_ENABLE 731 ); 732 musb->port1_status |= USB_PORT_STAT_CONNECTION 733 |(USB_PORT_STAT_C_CONNECTION << 16); 734 735 /* high vs full speed is just a guess until after reset */ 736 if (devctl & MUSB_DEVCTL_LSDEV) 737 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 738 739 /* indicate new connection to OTG machine */ 740 switch (musb->xceiv->state) { 741 case OTG_STATE_B_PERIPHERAL: 742 if (int_usb & MUSB_INTR_SUSPEND) { 743 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 744 int_usb &= ~MUSB_INTR_SUSPEND; 745 goto b_host; 746 } else 747 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 748 break; 749 case OTG_STATE_B_WAIT_ACON: 750 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 751 b_host: 752 musb->xceiv->state = OTG_STATE_B_HOST; 753 hcd->self.is_b_host = 1; 754 musb->ignore_disconnect = 0; 755 del_timer(&musb->otg_timer); 756 break; 757 default: 758 if ((devctl & MUSB_DEVCTL_VBUS) 759 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 760 musb->xceiv->state = OTG_STATE_A_HOST; 761 hcd->self.is_b_host = 0; 762 } 763 break; 764 } 765 766 /* poke the root hub */ 767 MUSB_HST_MODE(musb); 768 if (hcd->status_urb) 769 usb_hcd_poll_rh_status(hcd); 770 else 771 usb_hcd_resume_root_hub(hcd); 772 773 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 774 otg_state_string(musb->xceiv->state), devctl); 775 } 776 777 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 778 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 779 otg_state_string(musb->xceiv->state), 780 MUSB_MODE(musb), devctl); 781 handled = IRQ_HANDLED; 782 783 switch (musb->xceiv->state) { 784 case OTG_STATE_A_HOST: 785 case OTG_STATE_A_SUSPEND: 786 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 787 musb_root_disconnect(musb); 788 if (musb->a_wait_bcon != 0) 789 musb_platform_try_idle(musb, jiffies 790 + msecs_to_jiffies(musb->a_wait_bcon)); 791 break; 792 case OTG_STATE_B_HOST: 793 /* REVISIT this behaves for "real disconnect" 794 * cases; make sure the other transitions from 795 * from B_HOST act right too. The B_HOST code 796 * in hnp_stop() is currently not used... 797 */ 798 musb_root_disconnect(musb); 799 musb_to_hcd(musb)->self.is_b_host = 0; 800 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 801 MUSB_DEV_MODE(musb); 802 musb_g_disconnect(musb); 803 break; 804 case OTG_STATE_A_PERIPHERAL: 805 musb_hnp_stop(musb); 806 musb_root_disconnect(musb); 807 /* FALLTHROUGH */ 808 case OTG_STATE_B_WAIT_ACON: 809 /* FALLTHROUGH */ 810 case OTG_STATE_B_PERIPHERAL: 811 case OTG_STATE_B_IDLE: 812 musb_g_disconnect(musb); 813 break; 814 default: 815 WARNING("unhandled DISCONNECT transition (%s)\n", 816 otg_state_string(musb->xceiv->state)); 817 break; 818 } 819 } 820 821 /* mentor saves a bit: bus reset and babble share the same irq. 822 * only host sees babble; only peripheral sees bus reset. 823 */ 824 if (int_usb & MUSB_INTR_RESET) { 825 handled = IRQ_HANDLED; 826 if ((devctl & MUSB_DEVCTL_HM) != 0) { 827 /* 828 * Looks like non-HS BABBLE can be ignored, but 829 * HS BABBLE is an error condition. For HS the solution 830 * is to avoid babble in the first place and fix what 831 * caused BABBLE. When HS BABBLE happens we can only 832 * stop the session. 833 */ 834 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 835 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 836 else { 837 ERR("Stopping host session -- babble\n"); 838 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 839 } 840 } else { 841 dev_dbg(musb->controller, "BUS RESET as %s\n", 842 otg_state_string(musb->xceiv->state)); 843 switch (musb->xceiv->state) { 844 case OTG_STATE_A_SUSPEND: 845 /* We need to ignore disconnect on suspend 846 * otherwise tusb 2.0 won't reconnect after a 847 * power cycle, which breaks otg compliance. 848 */ 849 musb->ignore_disconnect = 1; 850 musb_g_reset(musb); 851 /* FALLTHROUGH */ 852 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 853 /* never use invalid T(a_wait_bcon) */ 854 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 855 otg_state_string(musb->xceiv->state), 856 TA_WAIT_BCON(musb)); 857 mod_timer(&musb->otg_timer, jiffies 858 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 859 break; 860 case OTG_STATE_A_PERIPHERAL: 861 musb->ignore_disconnect = 0; 862 del_timer(&musb->otg_timer); 863 musb_g_reset(musb); 864 break; 865 case OTG_STATE_B_WAIT_ACON: 866 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 867 otg_state_string(musb->xceiv->state)); 868 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 869 musb_g_reset(musb); 870 break; 871 case OTG_STATE_B_IDLE: 872 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 873 /* FALLTHROUGH */ 874 case OTG_STATE_B_PERIPHERAL: 875 musb_g_reset(musb); 876 break; 877 default: 878 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 879 otg_state_string(musb->xceiv->state)); 880 } 881 } 882 } 883 884 #if 0 885 /* REVISIT ... this would be for multiplexing periodic endpoints, or 886 * supporting transfer phasing to prevent exceeding ISO bandwidth 887 * limits of a given frame or microframe. 888 * 889 * It's not needed for peripheral side, which dedicates endpoints; 890 * though it _might_ use SOF irqs for other purposes. 891 * 892 * And it's not currently needed for host side, which also dedicates 893 * endpoints, relies on TX/RX interval registers, and isn't claimed 894 * to support ISO transfers yet. 895 */ 896 if (int_usb & MUSB_INTR_SOF) { 897 void __iomem *mbase = musb->mregs; 898 struct musb_hw_ep *ep; 899 u8 epnum; 900 u16 frame; 901 902 dev_dbg(musb->controller, "START_OF_FRAME\n"); 903 handled = IRQ_HANDLED; 904 905 /* start any periodic Tx transfers waiting for current frame */ 906 frame = musb_readw(mbase, MUSB_FRAME); 907 ep = musb->endpoints; 908 for (epnum = 1; (epnum < musb->nr_endpoints) 909 && (musb->epmask >= (1 << epnum)); 910 epnum++, ep++) { 911 /* 912 * FIXME handle framecounter wraps (12 bits) 913 * eliminate duplicated StartUrb logic 914 */ 915 if (ep->dwWaitFrame >= frame) { 916 ep->dwWaitFrame = 0; 917 pr_debug("SOF --> periodic TX%s on %d\n", 918 ep->tx_channel ? " DMA" : "", 919 epnum); 920 if (!ep->tx_channel) 921 musb_h_tx_start(musb, epnum); 922 else 923 cppi_hostdma_start(musb, epnum); 924 } 925 } /* end of for loop */ 926 } 927 #endif 928 929 schedule_work(&musb->irq_work); 930 931 return handled; 932 } 933 934 /*-------------------------------------------------------------------------*/ 935 936 /* 937 * Program the HDRC to start (enable interrupts, dma, etc.). 938 */ 939 void musb_start(struct musb *musb) 940 { 941 void __iomem *regs = musb->mregs; 942 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 943 944 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 945 946 /* Set INT enable registers, enable interrupts */ 947 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 948 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 949 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 950 951 musb_writeb(regs, MUSB_TESTMODE, 0); 952 953 /* put into basic highspeed mode and start session */ 954 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 955 | MUSB_POWER_HSENAB 956 /* ENSUSPEND wedges tusb */ 957 /* | MUSB_POWER_ENSUSPEND */ 958 ); 959 960 musb->is_active = 0; 961 devctl = musb_readb(regs, MUSB_DEVCTL); 962 devctl &= ~MUSB_DEVCTL_SESSION; 963 964 /* session started after: 965 * (a) ID-grounded irq, host mode; 966 * (b) vbus present/connect IRQ, peripheral mode; 967 * (c) peripheral initiates, using SRP 968 */ 969 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 970 musb->is_active = 1; 971 else 972 devctl |= MUSB_DEVCTL_SESSION; 973 974 musb_platform_enable(musb); 975 musb_writeb(regs, MUSB_DEVCTL, devctl); 976 } 977 978 979 static void musb_generic_disable(struct musb *musb) 980 { 981 void __iomem *mbase = musb->mregs; 982 u16 temp; 983 984 /* disable interrupts */ 985 musb_writeb(mbase, MUSB_INTRUSBE, 0); 986 musb_writew(mbase, MUSB_INTRTXE, 0); 987 musb_writew(mbase, MUSB_INTRRXE, 0); 988 989 /* off */ 990 musb_writeb(mbase, MUSB_DEVCTL, 0); 991 992 /* flush pending interrupts */ 993 temp = musb_readb(mbase, MUSB_INTRUSB); 994 temp = musb_readw(mbase, MUSB_INTRTX); 995 temp = musb_readw(mbase, MUSB_INTRRX); 996 997 } 998 999 /* 1000 * Make the HDRC stop (disable interrupts, etc.); 1001 * reversible by musb_start 1002 * called on gadget driver unregister 1003 * with controller locked, irqs blocked 1004 * acts as a NOP unless some role activated the hardware 1005 */ 1006 void musb_stop(struct musb *musb) 1007 { 1008 /* stop IRQs, timers, ... */ 1009 musb_platform_disable(musb); 1010 musb_generic_disable(musb); 1011 dev_dbg(musb->controller, "HDRC disabled\n"); 1012 1013 /* FIXME 1014 * - mark host and/or peripheral drivers unusable/inactive 1015 * - disable DMA (and enable it in HdrcStart) 1016 * - make sure we can musb_start() after musb_stop(); with 1017 * OTG mode, gadget driver module rmmod/modprobe cycles that 1018 * - ... 1019 */ 1020 musb_platform_try_idle(musb, 0); 1021 } 1022 1023 static void musb_shutdown(struct platform_device *pdev) 1024 { 1025 struct musb *musb = dev_to_musb(&pdev->dev); 1026 unsigned long flags; 1027 1028 pm_runtime_get_sync(musb->controller); 1029 1030 musb_gadget_cleanup(musb); 1031 1032 spin_lock_irqsave(&musb->lock, flags); 1033 musb_platform_disable(musb); 1034 musb_generic_disable(musb); 1035 spin_unlock_irqrestore(&musb->lock, flags); 1036 1037 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1038 musb_platform_exit(musb); 1039 1040 pm_runtime_put(musb->controller); 1041 /* FIXME power down */ 1042 } 1043 1044 1045 /*-------------------------------------------------------------------------*/ 1046 1047 /* 1048 * The silicon either has hard-wired endpoint configurations, or else 1049 * "dynamic fifo" sizing. The driver has support for both, though at this 1050 * writing only the dynamic sizing is very well tested. Since we switched 1051 * away from compile-time hardware parameters, we can no longer rely on 1052 * dead code elimination to leave only the relevant one in the object file. 1053 * 1054 * We don't currently use dynamic fifo setup capability to do anything 1055 * more than selecting one of a bunch of predefined configurations. 1056 */ 1057 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1058 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1059 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1060 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1061 || defined(CONFIG_USB_MUSB_AM35X) \ 1062 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1063 || defined(CONFIG_USB_MUSB_DSPS) \ 1064 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1065 static ushort __devinitdata fifo_mode = 4; 1066 #elif defined(CONFIG_USB_MUSB_UX500) \ 1067 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1068 static ushort __devinitdata fifo_mode = 5; 1069 #else 1070 static ushort __devinitdata fifo_mode = 2; 1071 #endif 1072 1073 /* "modprobe ... fifo_mode=1" etc */ 1074 module_param(fifo_mode, ushort, 0); 1075 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1076 1077 /* 1078 * tables defining fifo_mode values. define more if you like. 1079 * for host side, make sure both halves of ep1 are set up. 1080 */ 1081 1082 /* mode 0 - fits in 2KB */ 1083 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1084 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1085 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1086 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1087 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1088 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1089 }; 1090 1091 /* mode 1 - fits in 4KB */ 1092 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1093 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1094 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1095 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1096 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1097 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1098 }; 1099 1100 /* mode 2 - fits in 4KB */ 1101 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1102 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1103 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1104 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1105 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1106 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1107 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1108 }; 1109 1110 /* mode 3 - fits in 4KB */ 1111 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1112 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1113 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1114 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1115 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1116 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1117 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1118 }; 1119 1120 /* mode 4 - fits in 16KB */ 1121 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1122 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1123 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1124 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1125 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1126 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1127 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1128 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1129 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1130 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1131 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1132 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1133 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1134 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1135 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1136 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1137 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1138 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1139 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1140 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1141 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1142 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1143 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1144 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1145 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1146 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1147 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1148 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1149 }; 1150 1151 /* mode 5 - fits in 8KB */ 1152 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1157 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1158 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1159 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1160 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1161 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1162 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1163 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1164 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1165 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1166 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1167 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1168 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1169 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1170 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1171 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1172 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1173 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1174 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1175 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1176 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1177 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1178 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1179 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1180 }; 1181 1182 /* 1183 * configure a fifo; for non-shared endpoints, this may be called 1184 * once for a tx fifo and once for an rx fifo. 1185 * 1186 * returns negative errno or offset for next fifo. 1187 */ 1188 static int __devinit 1189 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1190 const struct musb_fifo_cfg *cfg, u16 offset) 1191 { 1192 void __iomem *mbase = musb->mregs; 1193 int size = 0; 1194 u16 maxpacket = cfg->maxpacket; 1195 u16 c_off = offset >> 3; 1196 u8 c_size; 1197 1198 /* expect hw_ep has already been zero-initialized */ 1199 1200 size = ffs(max(maxpacket, (u16) 8)) - 1; 1201 maxpacket = 1 << size; 1202 1203 c_size = size - 3; 1204 if (cfg->mode == BUF_DOUBLE) { 1205 if ((offset + (maxpacket << 1)) > 1206 (1 << (musb->config->ram_bits + 2))) 1207 return -EMSGSIZE; 1208 c_size |= MUSB_FIFOSZ_DPB; 1209 } else { 1210 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1211 return -EMSGSIZE; 1212 } 1213 1214 /* configure the FIFO */ 1215 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1216 1217 /* EP0 reserved endpoint for control, bidirectional; 1218 * EP1 reserved for bulk, two unidirection halves. 1219 */ 1220 if (hw_ep->epnum == 1) 1221 musb->bulk_ep = hw_ep; 1222 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1223 switch (cfg->style) { 1224 case FIFO_TX: 1225 musb_write_txfifosz(mbase, c_size); 1226 musb_write_txfifoadd(mbase, c_off); 1227 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1228 hw_ep->max_packet_sz_tx = maxpacket; 1229 break; 1230 case FIFO_RX: 1231 musb_write_rxfifosz(mbase, c_size); 1232 musb_write_rxfifoadd(mbase, c_off); 1233 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1234 hw_ep->max_packet_sz_rx = maxpacket; 1235 break; 1236 case FIFO_RXTX: 1237 musb_write_txfifosz(mbase, c_size); 1238 musb_write_txfifoadd(mbase, c_off); 1239 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1240 hw_ep->max_packet_sz_rx = maxpacket; 1241 1242 musb_write_rxfifosz(mbase, c_size); 1243 musb_write_rxfifoadd(mbase, c_off); 1244 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1245 hw_ep->max_packet_sz_tx = maxpacket; 1246 1247 hw_ep->is_shared_fifo = true; 1248 break; 1249 } 1250 1251 /* NOTE rx and tx endpoint irqs aren't managed separately, 1252 * which happens to be ok 1253 */ 1254 musb->epmask |= (1 << hw_ep->epnum); 1255 1256 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1257 } 1258 1259 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1260 .style = FIFO_RXTX, .maxpacket = 64, 1261 }; 1262 1263 static int __devinit ep_config_from_table(struct musb *musb) 1264 { 1265 const struct musb_fifo_cfg *cfg; 1266 unsigned i, n; 1267 int offset; 1268 struct musb_hw_ep *hw_ep = musb->endpoints; 1269 1270 if (musb->config->fifo_cfg) { 1271 cfg = musb->config->fifo_cfg; 1272 n = musb->config->fifo_cfg_size; 1273 goto done; 1274 } 1275 1276 switch (fifo_mode) { 1277 default: 1278 fifo_mode = 0; 1279 /* FALLTHROUGH */ 1280 case 0: 1281 cfg = mode_0_cfg; 1282 n = ARRAY_SIZE(mode_0_cfg); 1283 break; 1284 case 1: 1285 cfg = mode_1_cfg; 1286 n = ARRAY_SIZE(mode_1_cfg); 1287 break; 1288 case 2: 1289 cfg = mode_2_cfg; 1290 n = ARRAY_SIZE(mode_2_cfg); 1291 break; 1292 case 3: 1293 cfg = mode_3_cfg; 1294 n = ARRAY_SIZE(mode_3_cfg); 1295 break; 1296 case 4: 1297 cfg = mode_4_cfg; 1298 n = ARRAY_SIZE(mode_4_cfg); 1299 break; 1300 case 5: 1301 cfg = mode_5_cfg; 1302 n = ARRAY_SIZE(mode_5_cfg); 1303 break; 1304 } 1305 1306 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1307 musb_driver_name, fifo_mode); 1308 1309 1310 done: 1311 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1312 /* assert(offset > 0) */ 1313 1314 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1315 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1316 */ 1317 1318 for (i = 0; i < n; i++) { 1319 u8 epn = cfg->hw_ep_num; 1320 1321 if (epn >= musb->config->num_eps) { 1322 pr_debug("%s: invalid ep %d\n", 1323 musb_driver_name, epn); 1324 return -EINVAL; 1325 } 1326 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1327 if (offset < 0) { 1328 pr_debug("%s: mem overrun, ep %d\n", 1329 musb_driver_name, epn); 1330 return offset; 1331 } 1332 epn++; 1333 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1334 } 1335 1336 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1337 musb_driver_name, 1338 n + 1, musb->config->num_eps * 2 - 1, 1339 offset, (1 << (musb->config->ram_bits + 2))); 1340 1341 if (!musb->bulk_ep) { 1342 pr_debug("%s: missing bulk\n", musb_driver_name); 1343 return -EINVAL; 1344 } 1345 1346 return 0; 1347 } 1348 1349 1350 /* 1351 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1352 * @param musb the controller 1353 */ 1354 static int __devinit ep_config_from_hw(struct musb *musb) 1355 { 1356 u8 epnum = 0; 1357 struct musb_hw_ep *hw_ep; 1358 void __iomem *mbase = musb->mregs; 1359 int ret = 0; 1360 1361 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1362 1363 /* FIXME pick up ep0 maxpacket size */ 1364 1365 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1366 musb_ep_select(mbase, epnum); 1367 hw_ep = musb->endpoints + epnum; 1368 1369 ret = musb_read_fifosize(musb, hw_ep, epnum); 1370 if (ret < 0) 1371 break; 1372 1373 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1374 1375 /* pick an RX/TX endpoint for bulk */ 1376 if (hw_ep->max_packet_sz_tx < 512 1377 || hw_ep->max_packet_sz_rx < 512) 1378 continue; 1379 1380 /* REVISIT: this algorithm is lazy, we should at least 1381 * try to pick a double buffered endpoint. 1382 */ 1383 if (musb->bulk_ep) 1384 continue; 1385 musb->bulk_ep = hw_ep; 1386 } 1387 1388 if (!musb->bulk_ep) { 1389 pr_debug("%s: missing bulk\n", musb_driver_name); 1390 return -EINVAL; 1391 } 1392 1393 return 0; 1394 } 1395 1396 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1397 1398 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1399 * configure endpoints, or take their config from silicon 1400 */ 1401 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1402 { 1403 u8 reg; 1404 char *type; 1405 char aInfo[90], aRevision[32], aDate[12]; 1406 void __iomem *mbase = musb->mregs; 1407 int status = 0; 1408 int i; 1409 1410 /* log core options (read using indexed model) */ 1411 reg = musb_read_configdata(mbase); 1412 1413 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1414 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1415 strcat(aInfo, ", dyn FIFOs"); 1416 musb->dyn_fifo = true; 1417 } 1418 if (reg & MUSB_CONFIGDATA_MPRXE) { 1419 strcat(aInfo, ", bulk combine"); 1420 musb->bulk_combine = true; 1421 } 1422 if (reg & MUSB_CONFIGDATA_MPTXE) { 1423 strcat(aInfo, ", bulk split"); 1424 musb->bulk_split = true; 1425 } 1426 if (reg & MUSB_CONFIGDATA_HBRXE) { 1427 strcat(aInfo, ", HB-ISO Rx"); 1428 musb->hb_iso_rx = true; 1429 } 1430 if (reg & MUSB_CONFIGDATA_HBTXE) { 1431 strcat(aInfo, ", HB-ISO Tx"); 1432 musb->hb_iso_tx = true; 1433 } 1434 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1435 strcat(aInfo, ", SoftConn"); 1436 1437 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1438 musb_driver_name, reg, aInfo); 1439 1440 aDate[0] = 0; 1441 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1442 musb->is_multipoint = 1; 1443 type = "M"; 1444 } else { 1445 musb->is_multipoint = 0; 1446 type = ""; 1447 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1448 printk(KERN_ERR 1449 "%s: kernel must blacklist external hubs\n", 1450 musb_driver_name); 1451 #endif 1452 } 1453 1454 /* log release info */ 1455 musb->hwvers = musb_read_hwvers(mbase); 1456 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1457 MUSB_HWVERS_MINOR(musb->hwvers), 1458 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1459 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1460 musb_driver_name, type, aRevision, aDate); 1461 1462 /* configure ep0 */ 1463 musb_configure_ep0(musb); 1464 1465 /* discover endpoint configuration */ 1466 musb->nr_endpoints = 1; 1467 musb->epmask = 1; 1468 1469 if (musb->dyn_fifo) 1470 status = ep_config_from_table(musb); 1471 else 1472 status = ep_config_from_hw(musb); 1473 1474 if (status < 0) 1475 return status; 1476 1477 /* finish init, and print endpoint config */ 1478 for (i = 0; i < musb->nr_endpoints; i++) { 1479 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1480 1481 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1482 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1483 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1484 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1485 hw_ep->fifo_sync_va = 1486 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1487 1488 if (i == 0) 1489 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1490 else 1491 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1492 #endif 1493 1494 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1495 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1496 hw_ep->rx_reinit = 1; 1497 hw_ep->tx_reinit = 1; 1498 1499 if (hw_ep->max_packet_sz_tx) { 1500 dev_dbg(musb->controller, 1501 "%s: hw_ep %d%s, %smax %d\n", 1502 musb_driver_name, i, 1503 hw_ep->is_shared_fifo ? "shared" : "tx", 1504 hw_ep->tx_double_buffered 1505 ? "doublebuffer, " : "", 1506 hw_ep->max_packet_sz_tx); 1507 } 1508 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1509 dev_dbg(musb->controller, 1510 "%s: hw_ep %d%s, %smax %d\n", 1511 musb_driver_name, i, 1512 "rx", 1513 hw_ep->rx_double_buffered 1514 ? "doublebuffer, " : "", 1515 hw_ep->max_packet_sz_rx); 1516 } 1517 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1518 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1519 } 1520 1521 return 0; 1522 } 1523 1524 /*-------------------------------------------------------------------------*/ 1525 1526 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1527 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1528 1529 static irqreturn_t generic_interrupt(int irq, void *__hci) 1530 { 1531 unsigned long flags; 1532 irqreturn_t retval = IRQ_NONE; 1533 struct musb *musb = __hci; 1534 1535 spin_lock_irqsave(&musb->lock, flags); 1536 1537 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1538 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1539 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1540 1541 if (musb->int_usb || musb->int_tx || musb->int_rx) 1542 retval = musb_interrupt(musb); 1543 1544 spin_unlock_irqrestore(&musb->lock, flags); 1545 1546 return retval; 1547 } 1548 1549 #else 1550 #define generic_interrupt NULL 1551 #endif 1552 1553 /* 1554 * handle all the irqs defined by the HDRC core. for now we expect: other 1555 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1556 * will be assigned, and the irq will already have been acked. 1557 * 1558 * called in irq context with spinlock held, irqs blocked 1559 */ 1560 irqreturn_t musb_interrupt(struct musb *musb) 1561 { 1562 irqreturn_t retval = IRQ_NONE; 1563 u8 devctl, power; 1564 int ep_num; 1565 u32 reg; 1566 1567 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1568 power = musb_readb(musb->mregs, MUSB_POWER); 1569 1570 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1571 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1572 musb->int_usb, musb->int_tx, musb->int_rx); 1573 1574 /* the core can interrupt us for multiple reasons; docs have 1575 * a generic interrupt flowchart to follow 1576 */ 1577 if (musb->int_usb) 1578 retval |= musb_stage0_irq(musb, musb->int_usb, 1579 devctl, power); 1580 1581 /* "stage 1" is handling endpoint irqs */ 1582 1583 /* handle endpoint 0 first */ 1584 if (musb->int_tx & 1) { 1585 if (devctl & MUSB_DEVCTL_HM) 1586 retval |= musb_h_ep0_irq(musb); 1587 else 1588 retval |= musb_g_ep0_irq(musb); 1589 } 1590 1591 /* RX on endpoints 1-15 */ 1592 reg = musb->int_rx >> 1; 1593 ep_num = 1; 1594 while (reg) { 1595 if (reg & 1) { 1596 /* musb_ep_select(musb->mregs, ep_num); */ 1597 /* REVISIT just retval = ep->rx_irq(...) */ 1598 retval = IRQ_HANDLED; 1599 if (devctl & MUSB_DEVCTL_HM) 1600 musb_host_rx(musb, ep_num); 1601 else 1602 musb_g_rx(musb, ep_num); 1603 } 1604 1605 reg >>= 1; 1606 ep_num++; 1607 } 1608 1609 /* TX on endpoints 1-15 */ 1610 reg = musb->int_tx >> 1; 1611 ep_num = 1; 1612 while (reg) { 1613 if (reg & 1) { 1614 /* musb_ep_select(musb->mregs, ep_num); */ 1615 /* REVISIT just retval |= ep->tx_irq(...) */ 1616 retval = IRQ_HANDLED; 1617 if (devctl & MUSB_DEVCTL_HM) 1618 musb_host_tx(musb, ep_num); 1619 else 1620 musb_g_tx(musb, ep_num); 1621 } 1622 reg >>= 1; 1623 ep_num++; 1624 } 1625 1626 return retval; 1627 } 1628 EXPORT_SYMBOL_GPL(musb_interrupt); 1629 1630 #ifndef CONFIG_MUSB_PIO_ONLY 1631 static bool __devinitdata use_dma = 1; 1632 1633 /* "modprobe ... use_dma=0" etc */ 1634 module_param(use_dma, bool, 0); 1635 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1636 1637 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1638 { 1639 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1640 1641 /* called with controller lock already held */ 1642 1643 if (!epnum) { 1644 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1645 if (!is_cppi_enabled()) { 1646 /* endpoint 0 */ 1647 if (devctl & MUSB_DEVCTL_HM) 1648 musb_h_ep0_irq(musb); 1649 else 1650 musb_g_ep0_irq(musb); 1651 } 1652 #endif 1653 } else { 1654 /* endpoints 1..15 */ 1655 if (transmit) { 1656 if (devctl & MUSB_DEVCTL_HM) 1657 musb_host_tx(musb, epnum); 1658 else 1659 musb_g_tx(musb, epnum); 1660 } else { 1661 /* receive */ 1662 if (devctl & MUSB_DEVCTL_HM) 1663 musb_host_rx(musb, epnum); 1664 else 1665 musb_g_rx(musb, epnum); 1666 } 1667 } 1668 } 1669 EXPORT_SYMBOL_GPL(musb_dma_completion); 1670 1671 #else 1672 #define use_dma 0 1673 #endif 1674 1675 /*-------------------------------------------------------------------------*/ 1676 1677 #ifdef CONFIG_SYSFS 1678 1679 static ssize_t 1680 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1681 { 1682 struct musb *musb = dev_to_musb(dev); 1683 unsigned long flags; 1684 int ret = -EINVAL; 1685 1686 spin_lock_irqsave(&musb->lock, flags); 1687 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1688 spin_unlock_irqrestore(&musb->lock, flags); 1689 1690 return ret; 1691 } 1692 1693 static ssize_t 1694 musb_mode_store(struct device *dev, struct device_attribute *attr, 1695 const char *buf, size_t n) 1696 { 1697 struct musb *musb = dev_to_musb(dev); 1698 unsigned long flags; 1699 int status; 1700 1701 spin_lock_irqsave(&musb->lock, flags); 1702 if (sysfs_streq(buf, "host")) 1703 status = musb_platform_set_mode(musb, MUSB_HOST); 1704 else if (sysfs_streq(buf, "peripheral")) 1705 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1706 else if (sysfs_streq(buf, "otg")) 1707 status = musb_platform_set_mode(musb, MUSB_OTG); 1708 else 1709 status = -EINVAL; 1710 spin_unlock_irqrestore(&musb->lock, flags); 1711 1712 return (status == 0) ? n : status; 1713 } 1714 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1715 1716 static ssize_t 1717 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1718 const char *buf, size_t n) 1719 { 1720 struct musb *musb = dev_to_musb(dev); 1721 unsigned long flags; 1722 unsigned long val; 1723 1724 if (sscanf(buf, "%lu", &val) < 1) { 1725 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1726 return -EINVAL; 1727 } 1728 1729 spin_lock_irqsave(&musb->lock, flags); 1730 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1731 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1732 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1733 musb->is_active = 0; 1734 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1735 spin_unlock_irqrestore(&musb->lock, flags); 1736 1737 return n; 1738 } 1739 1740 static ssize_t 1741 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1742 { 1743 struct musb *musb = dev_to_musb(dev); 1744 unsigned long flags; 1745 unsigned long val; 1746 int vbus; 1747 1748 spin_lock_irqsave(&musb->lock, flags); 1749 val = musb->a_wait_bcon; 1750 /* FIXME get_vbus_status() is normally #defined as false... 1751 * and is effectively TUSB-specific. 1752 */ 1753 vbus = musb_platform_get_vbus_status(musb); 1754 spin_unlock_irqrestore(&musb->lock, flags); 1755 1756 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1757 vbus ? "on" : "off", val); 1758 } 1759 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1760 1761 /* Gadget drivers can't know that a host is connected so they might want 1762 * to start SRP, but users can. This allows userspace to trigger SRP. 1763 */ 1764 static ssize_t 1765 musb_srp_store(struct device *dev, struct device_attribute *attr, 1766 const char *buf, size_t n) 1767 { 1768 struct musb *musb = dev_to_musb(dev); 1769 unsigned short srp; 1770 1771 if (sscanf(buf, "%hu", &srp) != 1 1772 || (srp != 1)) { 1773 dev_err(dev, "SRP: Value must be 1\n"); 1774 return -EINVAL; 1775 } 1776 1777 if (srp == 1) 1778 musb_g_wakeup(musb); 1779 1780 return n; 1781 } 1782 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1783 1784 static struct attribute *musb_attributes[] = { 1785 &dev_attr_mode.attr, 1786 &dev_attr_vbus.attr, 1787 &dev_attr_srp.attr, 1788 NULL 1789 }; 1790 1791 static const struct attribute_group musb_attr_group = { 1792 .attrs = musb_attributes, 1793 }; 1794 1795 #endif /* sysfs */ 1796 1797 /* Only used to provide driver mode change events */ 1798 static void musb_irq_work(struct work_struct *data) 1799 { 1800 struct musb *musb = container_of(data, struct musb, irq_work); 1801 1802 if (musb->xceiv->state != musb->xceiv_old_state) { 1803 musb->xceiv_old_state = musb->xceiv->state; 1804 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1805 } 1806 } 1807 1808 /* -------------------------------------------------------------------------- 1809 * Init support 1810 */ 1811 1812 static struct musb *__devinit 1813 allocate_instance(struct device *dev, 1814 struct musb_hdrc_config *config, void __iomem *mbase) 1815 { 1816 struct musb *musb; 1817 struct musb_hw_ep *ep; 1818 int epnum; 1819 struct usb_hcd *hcd; 1820 1821 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1822 if (!hcd) 1823 return NULL; 1824 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1825 1826 musb = hcd_to_musb(hcd); 1827 INIT_LIST_HEAD(&musb->control); 1828 INIT_LIST_HEAD(&musb->in_bulk); 1829 INIT_LIST_HEAD(&musb->out_bulk); 1830 1831 hcd->uses_new_polling = 1; 1832 hcd->has_tt = 1; 1833 1834 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1835 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1836 dev_set_drvdata(dev, musb); 1837 musb->mregs = mbase; 1838 musb->ctrl_base = mbase; 1839 musb->nIrq = -ENODEV; 1840 musb->config = config; 1841 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1842 for (epnum = 0, ep = musb->endpoints; 1843 epnum < musb->config->num_eps; 1844 epnum++, ep++) { 1845 ep->musb = musb; 1846 ep->epnum = epnum; 1847 } 1848 1849 musb->controller = dev; 1850 1851 return musb; 1852 } 1853 1854 static void musb_free(struct musb *musb) 1855 { 1856 /* this has multiple entry modes. it handles fault cleanup after 1857 * probe(), where things may be partially set up, as well as rmmod 1858 * cleanup after everything's been de-activated. 1859 */ 1860 1861 #ifdef CONFIG_SYSFS 1862 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1863 #endif 1864 1865 if (musb->nIrq >= 0) { 1866 if (musb->irq_wake) 1867 disable_irq_wake(musb->nIrq); 1868 free_irq(musb->nIrq, musb); 1869 } 1870 if (is_dma_capable() && musb->dma_controller) { 1871 struct dma_controller *c = musb->dma_controller; 1872 1873 (void) c->stop(c); 1874 dma_controller_destroy(c); 1875 } 1876 1877 usb_put_hcd(musb_to_hcd(musb)); 1878 } 1879 1880 /* 1881 * Perform generic per-controller initialization. 1882 * 1883 * @dev: the controller (already clocked, etc) 1884 * @nIrq: IRQ number 1885 * @ctrl: virtual address of controller registers, 1886 * not yet corrected for platform-specific offsets 1887 */ 1888 static int __devinit 1889 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1890 { 1891 int status; 1892 struct musb *musb; 1893 struct musb_hdrc_platform_data *plat = dev->platform_data; 1894 struct usb_hcd *hcd; 1895 1896 /* The driver might handle more features than the board; OK. 1897 * Fail when the board needs a feature that's not enabled. 1898 */ 1899 if (!plat) { 1900 dev_dbg(dev, "no platform_data?\n"); 1901 status = -ENODEV; 1902 goto fail0; 1903 } 1904 1905 /* allocate */ 1906 musb = allocate_instance(dev, plat->config, ctrl); 1907 if (!musb) { 1908 status = -ENOMEM; 1909 goto fail0; 1910 } 1911 1912 pm_runtime_use_autosuspend(musb->controller); 1913 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1914 pm_runtime_enable(musb->controller); 1915 1916 spin_lock_init(&musb->lock); 1917 musb->board_set_power = plat->set_power; 1918 musb->min_power = plat->min_power; 1919 musb->ops = plat->platform_ops; 1920 1921 /* The musb_platform_init() call: 1922 * - adjusts musb->mregs and musb->isr if needed, 1923 * - may initialize an integrated tranceiver 1924 * - initializes musb->xceiv, usually by otg_get_phy() 1925 * - stops powering VBUS 1926 * 1927 * There are various transceiver configurations. Blackfin, 1928 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1929 * external/discrete ones in various flavors (twl4030 family, 1930 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1931 */ 1932 musb->isr = generic_interrupt; 1933 status = musb_platform_init(musb); 1934 if (status < 0) 1935 goto fail1; 1936 1937 if (!musb->isr) { 1938 status = -ENODEV; 1939 goto fail2; 1940 } 1941 1942 if (!musb->xceiv->io_ops) { 1943 musb->xceiv->io_dev = musb->controller; 1944 musb->xceiv->io_priv = musb->mregs; 1945 musb->xceiv->io_ops = &musb_ulpi_access; 1946 } 1947 1948 pm_runtime_get_sync(musb->controller); 1949 1950 #ifndef CONFIG_MUSB_PIO_ONLY 1951 if (use_dma && dev->dma_mask) { 1952 struct dma_controller *c; 1953 1954 c = dma_controller_create(musb, musb->mregs); 1955 musb->dma_controller = c; 1956 if (c) 1957 (void) c->start(c); 1958 } 1959 #endif 1960 /* ideally this would be abstracted in platform setup */ 1961 if (!is_dma_capable() || !musb->dma_controller) 1962 dev->dma_mask = NULL; 1963 1964 /* be sure interrupts are disabled before connecting ISR */ 1965 musb_platform_disable(musb); 1966 musb_generic_disable(musb); 1967 1968 /* setup musb parts of the core (especially endpoints) */ 1969 status = musb_core_init(plat->config->multipoint 1970 ? MUSB_CONTROLLER_MHDRC 1971 : MUSB_CONTROLLER_HDRC, musb); 1972 if (status < 0) 1973 goto fail3; 1974 1975 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1976 1977 /* Init IRQ workqueue before request_irq */ 1978 INIT_WORK(&musb->irq_work, musb_irq_work); 1979 1980 /* attach to the IRQ */ 1981 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1982 dev_err(dev, "request_irq %d failed!\n", nIrq); 1983 status = -ENODEV; 1984 goto fail3; 1985 } 1986 musb->nIrq = nIrq; 1987 /* FIXME this handles wakeup irqs wrong */ 1988 if (enable_irq_wake(nIrq) == 0) { 1989 musb->irq_wake = 1; 1990 device_init_wakeup(dev, 1); 1991 } else { 1992 musb->irq_wake = 0; 1993 } 1994 1995 /* host side needs more setup */ 1996 hcd = musb_to_hcd(musb); 1997 otg_set_host(musb->xceiv->otg, &hcd->self); 1998 hcd->self.otg_port = 1; 1999 musb->xceiv->otg->host = &hcd->self; 2000 hcd->power_budget = 2 * (plat->power ? : 250); 2001 2002 /* program PHY to use external vBus if required */ 2003 if (plat->extvbus) { 2004 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2005 busctl |= MUSB_ULPI_USE_EXTVBUS; 2006 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2007 } 2008 2009 MUSB_DEV_MODE(musb); 2010 musb->xceiv->otg->default_a = 0; 2011 musb->xceiv->state = OTG_STATE_B_IDLE; 2012 2013 status = musb_gadget_setup(musb); 2014 2015 if (status < 0) 2016 goto fail3; 2017 2018 status = musb_init_debugfs(musb); 2019 if (status < 0) 2020 goto fail4; 2021 2022 #ifdef CONFIG_SYSFS 2023 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2024 if (status) 2025 goto fail5; 2026 #endif 2027 2028 pm_runtime_put(musb->controller); 2029 2030 return 0; 2031 2032 fail5: 2033 musb_exit_debugfs(musb); 2034 2035 fail4: 2036 musb_gadget_cleanup(musb); 2037 2038 fail3: 2039 pm_runtime_put_sync(musb->controller); 2040 2041 fail2: 2042 if (musb->irq_wake) 2043 device_init_wakeup(dev, 0); 2044 musb_platform_exit(musb); 2045 2046 fail1: 2047 dev_err(musb->controller, 2048 "musb_init_controller failed with status %d\n", status); 2049 2050 musb_free(musb); 2051 2052 fail0: 2053 2054 return status; 2055 2056 } 2057 2058 /*-------------------------------------------------------------------------*/ 2059 2060 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2061 * bridge to a platform device; this driver then suffices. 2062 */ 2063 static int __devinit musb_probe(struct platform_device *pdev) 2064 { 2065 struct device *dev = &pdev->dev; 2066 int irq = platform_get_irq_byname(pdev, "mc"); 2067 int status; 2068 struct resource *iomem; 2069 void __iomem *base; 2070 2071 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2072 if (!iomem || irq <= 0) 2073 return -ENODEV; 2074 2075 base = ioremap(iomem->start, resource_size(iomem)); 2076 if (!base) { 2077 dev_err(dev, "ioremap failed\n"); 2078 return -ENOMEM; 2079 } 2080 2081 status = musb_init_controller(dev, irq, base); 2082 if (status < 0) 2083 iounmap(base); 2084 2085 return status; 2086 } 2087 2088 static int __devexit musb_remove(struct platform_device *pdev) 2089 { 2090 struct device *dev = &pdev->dev; 2091 struct musb *musb = dev_to_musb(dev); 2092 void __iomem *ctrl_base = musb->ctrl_base; 2093 2094 /* this gets called on rmmod. 2095 * - Host mode: host may still be active 2096 * - Peripheral mode: peripheral is deactivated (or never-activated) 2097 * - OTG mode: both roles are deactivated (or never-activated) 2098 */ 2099 musb_exit_debugfs(musb); 2100 musb_shutdown(pdev); 2101 2102 musb_free(musb); 2103 iounmap(ctrl_base); 2104 device_init_wakeup(dev, 0); 2105 #ifndef CONFIG_MUSB_PIO_ONLY 2106 dma_set_mask(dev, *dev->parent->dma_mask); 2107 #endif 2108 return 0; 2109 } 2110 2111 #ifdef CONFIG_PM 2112 2113 static void musb_save_context(struct musb *musb) 2114 { 2115 int i; 2116 void __iomem *musb_base = musb->mregs; 2117 void __iomem *epio; 2118 2119 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2120 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2121 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2122 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2123 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2124 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2125 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2126 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2127 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2128 2129 for (i = 0; i < musb->config->num_eps; ++i) { 2130 struct musb_hw_ep *hw_ep; 2131 2132 hw_ep = &musb->endpoints[i]; 2133 if (!hw_ep) 2134 continue; 2135 2136 epio = hw_ep->regs; 2137 if (!epio) 2138 continue; 2139 2140 musb_writeb(musb_base, MUSB_INDEX, i); 2141 musb->context.index_regs[i].txmaxp = 2142 musb_readw(epio, MUSB_TXMAXP); 2143 musb->context.index_regs[i].txcsr = 2144 musb_readw(epio, MUSB_TXCSR); 2145 musb->context.index_regs[i].rxmaxp = 2146 musb_readw(epio, MUSB_RXMAXP); 2147 musb->context.index_regs[i].rxcsr = 2148 musb_readw(epio, MUSB_RXCSR); 2149 2150 if (musb->dyn_fifo) { 2151 musb->context.index_regs[i].txfifoadd = 2152 musb_read_txfifoadd(musb_base); 2153 musb->context.index_regs[i].rxfifoadd = 2154 musb_read_rxfifoadd(musb_base); 2155 musb->context.index_regs[i].txfifosz = 2156 musb_read_txfifosz(musb_base); 2157 musb->context.index_regs[i].rxfifosz = 2158 musb_read_rxfifosz(musb_base); 2159 } 2160 2161 musb->context.index_regs[i].txtype = 2162 musb_readb(epio, MUSB_TXTYPE); 2163 musb->context.index_regs[i].txinterval = 2164 musb_readb(epio, MUSB_TXINTERVAL); 2165 musb->context.index_regs[i].rxtype = 2166 musb_readb(epio, MUSB_RXTYPE); 2167 musb->context.index_regs[i].rxinterval = 2168 musb_readb(epio, MUSB_RXINTERVAL); 2169 2170 musb->context.index_regs[i].txfunaddr = 2171 musb_read_txfunaddr(musb_base, i); 2172 musb->context.index_regs[i].txhubaddr = 2173 musb_read_txhubaddr(musb_base, i); 2174 musb->context.index_regs[i].txhubport = 2175 musb_read_txhubport(musb_base, i); 2176 2177 musb->context.index_regs[i].rxfunaddr = 2178 musb_read_rxfunaddr(musb_base, i); 2179 musb->context.index_regs[i].rxhubaddr = 2180 musb_read_rxhubaddr(musb_base, i); 2181 musb->context.index_regs[i].rxhubport = 2182 musb_read_rxhubport(musb_base, i); 2183 } 2184 } 2185 2186 static void musb_restore_context(struct musb *musb) 2187 { 2188 int i; 2189 void __iomem *musb_base = musb->mregs; 2190 void __iomem *ep_target_regs; 2191 void __iomem *epio; 2192 2193 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2194 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2195 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2196 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2197 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2198 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2199 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2200 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2201 2202 for (i = 0; i < musb->config->num_eps; ++i) { 2203 struct musb_hw_ep *hw_ep; 2204 2205 hw_ep = &musb->endpoints[i]; 2206 if (!hw_ep) 2207 continue; 2208 2209 epio = hw_ep->regs; 2210 if (!epio) 2211 continue; 2212 2213 musb_writeb(musb_base, MUSB_INDEX, i); 2214 musb_writew(epio, MUSB_TXMAXP, 2215 musb->context.index_regs[i].txmaxp); 2216 musb_writew(epio, MUSB_TXCSR, 2217 musb->context.index_regs[i].txcsr); 2218 musb_writew(epio, MUSB_RXMAXP, 2219 musb->context.index_regs[i].rxmaxp); 2220 musb_writew(epio, MUSB_RXCSR, 2221 musb->context.index_regs[i].rxcsr); 2222 2223 if (musb->dyn_fifo) { 2224 musb_write_txfifosz(musb_base, 2225 musb->context.index_regs[i].txfifosz); 2226 musb_write_rxfifosz(musb_base, 2227 musb->context.index_regs[i].rxfifosz); 2228 musb_write_txfifoadd(musb_base, 2229 musb->context.index_regs[i].txfifoadd); 2230 musb_write_rxfifoadd(musb_base, 2231 musb->context.index_regs[i].rxfifoadd); 2232 } 2233 2234 musb_writeb(epio, MUSB_TXTYPE, 2235 musb->context.index_regs[i].txtype); 2236 musb_writeb(epio, MUSB_TXINTERVAL, 2237 musb->context.index_regs[i].txinterval); 2238 musb_writeb(epio, MUSB_RXTYPE, 2239 musb->context.index_regs[i].rxtype); 2240 musb_writeb(epio, MUSB_RXINTERVAL, 2241 2242 musb->context.index_regs[i].rxinterval); 2243 musb_write_txfunaddr(musb_base, i, 2244 musb->context.index_regs[i].txfunaddr); 2245 musb_write_txhubaddr(musb_base, i, 2246 musb->context.index_regs[i].txhubaddr); 2247 musb_write_txhubport(musb_base, i, 2248 musb->context.index_regs[i].txhubport); 2249 2250 ep_target_regs = 2251 musb_read_target_reg_base(i, musb_base); 2252 2253 musb_write_rxfunaddr(ep_target_regs, 2254 musb->context.index_regs[i].rxfunaddr); 2255 musb_write_rxhubaddr(ep_target_regs, 2256 musb->context.index_regs[i].rxhubaddr); 2257 musb_write_rxhubport(ep_target_regs, 2258 musb->context.index_regs[i].rxhubport); 2259 } 2260 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2261 } 2262 2263 static int musb_suspend(struct device *dev) 2264 { 2265 struct musb *musb = dev_to_musb(dev); 2266 unsigned long flags; 2267 2268 spin_lock_irqsave(&musb->lock, flags); 2269 2270 if (is_peripheral_active(musb)) { 2271 /* FIXME force disconnect unless we know USB will wake 2272 * the system up quickly enough to respond ... 2273 */ 2274 } else if (is_host_active(musb)) { 2275 /* we know all the children are suspended; sometimes 2276 * they will even be wakeup-enabled. 2277 */ 2278 } 2279 2280 spin_unlock_irqrestore(&musb->lock, flags); 2281 return 0; 2282 } 2283 2284 static int musb_resume_noirq(struct device *dev) 2285 { 2286 /* for static cmos like DaVinci, register values were preserved 2287 * unless for some reason the whole soc powered down or the USB 2288 * module got reset through the PSC (vs just being disabled). 2289 */ 2290 return 0; 2291 } 2292 2293 static int musb_runtime_suspend(struct device *dev) 2294 { 2295 struct musb *musb = dev_to_musb(dev); 2296 2297 musb_save_context(musb); 2298 2299 return 0; 2300 } 2301 2302 static int musb_runtime_resume(struct device *dev) 2303 { 2304 struct musb *musb = dev_to_musb(dev); 2305 static int first = 1; 2306 2307 /* 2308 * When pm_runtime_get_sync called for the first time in driver 2309 * init, some of the structure is still not initialized which is 2310 * used in restore function. But clock needs to be 2311 * enabled before any register access, so 2312 * pm_runtime_get_sync has to be called. 2313 * Also context restore without save does not make 2314 * any sense 2315 */ 2316 if (!first) 2317 musb_restore_context(musb); 2318 first = 0; 2319 2320 return 0; 2321 } 2322 2323 static const struct dev_pm_ops musb_dev_pm_ops = { 2324 .suspend = musb_suspend, 2325 .resume_noirq = musb_resume_noirq, 2326 .runtime_suspend = musb_runtime_suspend, 2327 .runtime_resume = musb_runtime_resume, 2328 }; 2329 2330 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2331 #else 2332 #define MUSB_DEV_PM_OPS NULL 2333 #endif 2334 2335 static struct platform_driver musb_driver = { 2336 .driver = { 2337 .name = (char *)musb_driver_name, 2338 .bus = &platform_bus_type, 2339 .owner = THIS_MODULE, 2340 .pm = MUSB_DEV_PM_OPS, 2341 }, 2342 .probe = musb_probe, 2343 .remove = __devexit_p(musb_remove), 2344 .shutdown = musb_shutdown, 2345 }; 2346 2347 /*-------------------------------------------------------------------------*/ 2348 2349 static int __init musb_init(void) 2350 { 2351 if (usb_disabled()) 2352 return 0; 2353 2354 pr_info("%s: version " MUSB_VERSION ", " 2355 "?dma?" 2356 ", " 2357 "otg (peripheral+host)", 2358 musb_driver_name); 2359 return platform_driver_register(&musb_driver); 2360 } 2361 module_init(musb_init); 2362 2363 static void __exit musb_cleanup(void) 2364 { 2365 platform_driver_unregister(&musb_driver); 2366 } 2367 module_exit(musb_cleanup); 2368