1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PolarFire SoC (MPFS) MUSB Glue Layer 4 * 5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved. 6 * Based on {omap2430,tusb6010,ux500}.c 7 * 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/usb/usb_phy_generic.h> 19 #include "musb_core.h" 20 #include "musb_dma.h" 21 22 #define MPFS_MUSB_MAX_EP_NUM 8 23 #define MPFS_MUSB_RAM_BITS 12 24 25 struct mpfs_glue { 26 struct device *dev; 27 struct platform_device *musb; 28 struct platform_device *phy; 29 struct clk *clk; 30 }; 31 32 static const struct musb_fifo_cfg mpfs_musb_mode_cfg[] = { 33 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 34 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 35 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 36 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 37 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 38 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 39 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 1024, }, 40 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 4096, }, 41 }; 42 43 static const struct musb_hdrc_config mpfs_musb_hdrc_config = { 44 .fifo_cfg = mpfs_musb_mode_cfg, 45 .fifo_cfg_size = ARRAY_SIZE(mpfs_musb_mode_cfg), 46 .multipoint = true, 47 .dyn_fifo = true, 48 .num_eps = MPFS_MUSB_MAX_EP_NUM, 49 .ram_bits = MPFS_MUSB_RAM_BITS, 50 }; 51 52 static void mpfs_musb_set_vbus(struct musb *musb, int is_on) 53 { 54 u8 devctl; 55 56 /* 57 * HDRC controls CPEN, but beware current surges during device 58 * connect. They can trigger transient overcurrent conditions 59 * that must be ignored. 60 */ 61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 62 63 if (is_on) { 64 musb->is_active = 1; 65 musb->xceiv->otg->default_a = 1; 66 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 67 devctl |= MUSB_DEVCTL_SESSION; 68 MUSB_HST_MODE(musb); 69 } else { 70 musb->is_active = 0; 71 72 /* 73 * NOTE: skipping A_WAIT_VFALL -> A_IDLE and 74 * jumping right to B_IDLE... 75 */ 76 musb->xceiv->otg->default_a = 0; 77 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 78 devctl &= ~MUSB_DEVCTL_SESSION; 79 80 MUSB_DEV_MODE(musb); 81 } 82 83 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 84 85 dev_dbg(musb->controller, "VBUS %s, devctl %02x\n", 86 usb_otg_state_string(musb->xceiv->otg->state), 87 musb_readb(musb->mregs, MUSB_DEVCTL)); 88 } 89 90 #define POLL_SECONDS 2 91 92 static void otg_timer(struct timer_list *t) 93 { 94 struct musb *musb = timer_container_of(musb, t, 95 dev_timer); 96 void __iomem *mregs = musb->mregs; 97 u8 devctl; 98 unsigned long flags; 99 100 /* 101 * We poll because PolarFire SoC won't expose several OTG-critical 102 * status change events (from the transceiver) otherwise. 103 */ 104 devctl = musb_readb(mregs, MUSB_DEVCTL); 105 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 106 usb_otg_state_string(musb->xceiv->otg->state)); 107 108 spin_lock_irqsave(&musb->lock, flags); 109 switch (musb->xceiv->otg->state) { 110 case OTG_STATE_A_WAIT_BCON: 111 devctl &= ~MUSB_DEVCTL_SESSION; 112 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 113 114 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 115 if (devctl & MUSB_DEVCTL_BDEVICE) { 116 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 117 MUSB_DEV_MODE(musb); 118 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); 119 } else { 120 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 121 MUSB_HST_MODE(musb); 122 } 123 break; 124 case OTG_STATE_A_WAIT_VFALL: 125 if (devctl & MUSB_DEVCTL_VBUS) { 126 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); 127 break; 128 } 129 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 130 break; 131 case OTG_STATE_B_IDLE: 132 /* 133 * There's no ID-changed IRQ, so we have no good way to tell 134 * when to switch to the A-Default state machine (by setting 135 * the DEVCTL.Session bit). 136 * 137 * Workaround: whenever we're in B_IDLE, try setting the 138 * session flag every few seconds. If it works, ID was 139 * grounded and we're now in the A-Default state machine. 140 * 141 * NOTE: setting the session flag is _supposed_ to trigger 142 * SRP but clearly it doesn't. 143 */ 144 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); 145 devctl = musb_readb(mregs, MUSB_DEVCTL); 146 if (devctl & MUSB_DEVCTL_BDEVICE) 147 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); 148 else 149 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 150 break; 151 default: 152 break; 153 } 154 spin_unlock_irqrestore(&musb->lock, flags); 155 } 156 157 static void __maybe_unused mpfs_musb_try_idle(struct musb *musb, unsigned long timeout) 158 { 159 static unsigned long last_timer; 160 161 if (timeout == 0) 162 timeout = jiffies + msecs_to_jiffies(3); 163 164 /* Never idle if active, or when VBUS timeout is not set as host */ 165 if (musb->is_active || (musb->a_wait_bcon == 0 && 166 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { 167 dev_dbg(musb->controller, "%s active, deleting timer\n", 168 usb_otg_state_string(musb->xceiv->otg->state)); 169 timer_delete(&musb->dev_timer); 170 last_timer = jiffies; 171 return; 172 } 173 174 if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) { 175 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 176 return; 177 } 178 last_timer = timeout; 179 180 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 181 usb_otg_state_string(musb->xceiv->otg->state), 182 jiffies_to_msecs(timeout - jiffies)); 183 mod_timer(&musb->dev_timer, timeout); 184 } 185 186 static irqreturn_t mpfs_musb_interrupt(int irq, void *__hci) 187 { 188 unsigned long flags; 189 irqreturn_t ret = IRQ_NONE; 190 struct musb *musb = __hci; 191 192 spin_lock_irqsave(&musb->lock, flags); 193 194 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 195 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 196 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 197 198 if (musb->int_usb || musb->int_tx || musb->int_rx) { 199 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); 200 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); 201 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); 202 ret = musb_interrupt(musb); 203 } 204 205 /* Poll for ID change */ 206 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 207 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); 208 209 spin_unlock_irqrestore(&musb->lock, flags); 210 211 return ret; 212 } 213 214 static int mpfs_musb_init(struct musb *musb) 215 { 216 struct device *dev = musb->controller; 217 218 musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 219 if (IS_ERR(musb->xceiv)) { 220 dev_err(dev, "HS UDC: no transceiver configured\n"); 221 return PTR_ERR(musb->xceiv); 222 } 223 224 timer_setup(&musb->dev_timer, otg_timer, 0); 225 226 musb->dyn_fifo = true; 227 musb->isr = mpfs_musb_interrupt; 228 229 musb_platform_set_vbus(musb, 1); 230 231 return 0; 232 } 233 234 static int mpfs_musb_exit(struct musb *musb) 235 { 236 timer_delete_sync(&musb->dev_timer); 237 238 return 0; 239 } 240 241 static const struct musb_platform_ops mpfs_ops = { 242 .quirks = MUSB_DMA_INVENTRA, 243 .init = mpfs_musb_init, 244 .exit = mpfs_musb_exit, 245 .fifo_mode = 2, 246 #ifdef CONFIG_USB_INVENTRA_DMA 247 .dma_init = musbhs_dma_controller_create, 248 .dma_exit = musbhs_dma_controller_destroy, 249 #endif 250 #ifndef CONFIG_USB_MUSB_HOST 251 .try_idle = mpfs_musb_try_idle, 252 #endif 253 .set_vbus = mpfs_musb_set_vbus 254 }; 255 256 static int mpfs_probe(struct platform_device *pdev) 257 { 258 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 259 struct mpfs_glue *glue; 260 struct platform_device *musb_pdev; 261 struct device *dev = &pdev->dev; 262 struct clk *clk; 263 int ret; 264 265 glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL); 266 if (!glue) 267 return -ENOMEM; 268 269 musb_pdev = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); 270 if (!musb_pdev) { 271 dev_err(dev, "failed to allocate musb device\n"); 272 return -ENOMEM; 273 } 274 275 clk = devm_clk_get(&pdev->dev, NULL); 276 if (IS_ERR(clk)) { 277 dev_err(&pdev->dev, "failed to get clock\n"); 278 ret = PTR_ERR(clk); 279 goto err_phy_release; 280 } 281 282 ret = clk_prepare_enable(clk); 283 if (ret) { 284 dev_err(&pdev->dev, "failed to enable clock\n"); 285 goto err_phy_release; 286 } 287 288 musb_pdev->dev.parent = dev; 289 musb_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(39); 290 musb_pdev->dev.dma_mask = &musb_pdev->dev.coherent_dma_mask; 291 device_set_of_node_from_dev(&musb_pdev->dev, dev); 292 293 glue->dev = dev; 294 glue->musb = musb_pdev; 295 glue->clk = clk; 296 297 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 298 if (!pdata) { 299 ret = -ENOMEM; 300 goto err_clk_disable; 301 } 302 303 pdata->config = &mpfs_musb_hdrc_config; 304 pdata->platform_ops = &mpfs_ops; 305 306 pdata->extvbus = device_property_read_bool(dev, "microchip,ext-vbus-drv"); 307 308 pdata->mode = usb_get_dr_mode(dev); 309 if (pdata->mode == USB_DR_MODE_UNKNOWN) { 310 dev_info(dev, "No dr_mode property found, defaulting to otg\n"); 311 pdata->mode = USB_DR_MODE_OTG; 312 } 313 314 glue->phy = usb_phy_generic_register(); 315 if (IS_ERR(glue->phy)) { 316 dev_err(dev, "failed to register usb-phy %ld\n", 317 PTR_ERR(glue->phy)); 318 ret = PTR_ERR(glue->phy); 319 goto err_clk_disable; 320 } 321 322 platform_set_drvdata(pdev, glue); 323 324 ret = platform_device_add_resources(musb_pdev, pdev->resource, pdev->num_resources); 325 if (ret) { 326 dev_err(dev, "failed to add resources\n"); 327 goto err_clk_disable; 328 } 329 330 ret = platform_device_add_data(musb_pdev, pdata, sizeof(*pdata)); 331 if (ret) { 332 dev_err(dev, "failed to add platform_data\n"); 333 goto err_clk_disable; 334 } 335 336 ret = platform_device_add(musb_pdev); 337 if (ret) { 338 dev_err(dev, "failed to register musb device\n"); 339 goto err_clk_disable; 340 } 341 342 dev_info(&pdev->dev, "Registered MPFS MUSB driver\n"); 343 return 0; 344 345 err_clk_disable: 346 clk_disable_unprepare(clk); 347 348 err_phy_release: 349 usb_phy_generic_unregister(glue->phy); 350 platform_device_put(musb_pdev); 351 return ret; 352 } 353 354 static void mpfs_remove(struct platform_device *pdev) 355 { 356 struct mpfs_glue *glue = platform_get_drvdata(pdev); 357 358 clk_disable_unprepare(glue->clk); 359 platform_device_unregister(glue->musb); 360 usb_phy_generic_unregister(pdev); 361 } 362 363 #ifdef CONFIG_OF 364 static const struct of_device_id mpfs_id_table[] = { 365 { .compatible = "microchip,mpfs-musb" }, 366 { } 367 }; 368 MODULE_DEVICE_TABLE(of, mpfs_id_table); 369 #endif 370 371 static struct platform_driver mpfs_musb_driver = { 372 .probe = mpfs_probe, 373 .remove = mpfs_remove, 374 .driver = { 375 .name = "mpfs-musb", 376 .of_match_table = of_match_ptr(mpfs_id_table) 377 }, 378 }; 379 380 module_platform_driver(mpfs_musb_driver); 381 382 MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer"); 383 MODULE_LICENSE("GPL"); 384