1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mtu3.h - MediaTek USB3 DRD header 4 * 5 * Copyright (C) 2016 MediaTek Inc. 6 * 7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #ifndef __MTU3_H__ 11 #define __MTU3_H__ 12 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/dmapool.h> 16 #include <linux/extcon.h> 17 #include <linux/interrupt.h> 18 #include <linux/list.h> 19 #include <linux/of.h> 20 #include <linux/phy/phy.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/usb.h> 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/gadget.h> 25 #include <linux/usb/otg.h> 26 #include <linux/usb/role.h> 27 28 struct mtu3; 29 struct mtu3_ep; 30 struct mtu3_request; 31 32 #include "mtu3_hw_regs.h" 33 #include "mtu3_qmu.h" 34 35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10)) 36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10)) 37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10)) 38 39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10)) 40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) 41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) 42 43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4)) 44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4)) 45 46 #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10)) 47 #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10)) 48 #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10)) 49 50 #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10)) 51 #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10)) 52 #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10)) 53 54 #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08)) 55 #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08)) 56 57 #define MTU3_DRIVER_NAME "mtu3" 58 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 59 60 #define MTU3_EP_ENABLED BIT(0) 61 #define MTU3_EP_STALL BIT(1) 62 #define MTU3_EP_WEDGE BIT(2) 63 #define MTU3_EP_BUSY BIT(3) 64 65 #define MTU3_U3_IP_SLOT_DEFAULT 2 66 #define MTU3_U2_IP_SLOT_DEFAULT 1 67 68 /** 69 * IP TRUNK version 70 * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver: 71 * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted, 72 * but not backward compatible 73 * 2. QMU extend buffer length supported 74 */ 75 #define MTU3_TRUNK_VERS_1003 0x1003 76 77 /** 78 * Normally the device works on HS or SS, to simplify fifo management, 79 * devide fifo into some 512B parts, use bitmap to manage it; And 80 * 128 bits size of bitmap is large enough, that means it can manage 81 * up to 64KB fifo size. 82 * NOTE: MTU3_EP_FIFO_UNIT should be power of two 83 */ 84 #define MTU3_EP_FIFO_UNIT (1 << 9) 85 #define MTU3_FIFO_BIT_SIZE 128 86 #define MTU3_U2_IP_EP0_FIFO_SIZE 64 87 88 /** 89 * Maximum size of ep0 response buffer for ch9 requests, 90 * the SET_SEL request uses 6 so far, and GET_STATUS is 2 91 */ 92 #define EP0_RESPONSE_BUF 6 93 94 #define BULK_CLKS_CNT 6 95 96 /* device operated link and speed got from DEVICE_CONF register */ 97 enum mtu3_speed { 98 MTU3_SPEED_INACTIVE = 0, 99 MTU3_SPEED_FULL = 1, 100 MTU3_SPEED_HIGH = 3, 101 MTU3_SPEED_SUPER = 4, 102 MTU3_SPEED_SUPER_PLUS = 5, 103 }; 104 105 /** 106 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP 107 * without data stage. 108 * @MU3D_EP0_STATE_TX: IN data stage 109 * @MU3D_EP0_STATE_RX: OUT data stage 110 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and 111 * waits for its completion interrupt 112 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared 113 * after receives a SETUP. 114 */ 115 enum mtu3_g_ep0_state { 116 MU3D_EP0_STATE_SETUP = 1, 117 MU3D_EP0_STATE_TX, 118 MU3D_EP0_STATE_RX, 119 MU3D_EP0_STATE_TX_END, 120 MU3D_EP0_STATE_STALL, 121 }; 122 123 /** 124 * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode 125 * by IDPIN signal. 126 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG 127 * IDPIN signal. 128 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode. 129 */ 130 enum mtu3_dr_force_mode { 131 MTU3_DR_FORCE_NONE = 0, 132 MTU3_DR_FORCE_HOST, 133 MTU3_DR_FORCE_DEVICE, 134 }; 135 136 /** 137 * @base: the base address of fifo 138 * @limit: the bitmap size in bits 139 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT 140 */ 141 struct mtu3_fifo_info { 142 u32 base; 143 u32 limit; 144 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE); 145 }; 146 147 /** 148 * General Purpose Descriptor (GPD): 149 * The format of TX GPD is a little different from RX one. 150 * And the size of GPD is 16 bytes. 151 * 152 * @dw0_info: 153 * bit0: Hardware Own (HWO) 154 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported 155 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1 156 * bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29] 157 * bit7: Interrupt On Completion (IOC) 158 * bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY), 159 * the buffer length of the data to receive 160 * bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY), 161 * lower 4 bits are extension bits of @buffer, 162 * upper 4 bits are extension bits of @next_gpd 163 * @next_gpd: Physical address of the next GPD 164 * @buffer: Physical address of the data buffer 165 * @dw3_info: 166 * bit[15:0]: ([EL] bit[19:0]) data buffer length, 167 * (TX): the buffer length of the data to transmit 168 * (RX): The total length of data received 169 * bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY), 170 * lower 4 bits are extension bits of @buffer, 171 * upper 4 bits are extension bits of @next_gpd 172 * bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY) 173 */ 174 struct qmu_gpd { 175 __le32 dw0_info; 176 __le32 next_gpd; 177 __le32 buffer; 178 __le32 dw3_info; 179 } __packed; 180 181 /** 182 * dma: physical base address of GPD segment 183 * start: virtual base address of GPD segment 184 * end: the last GPD element 185 * enqueue: the first empty GPD to use 186 * dequeue: the first completed GPD serviced by ISR 187 * NOTE: the size of GPD ring should be >= 2 188 */ 189 struct mtu3_gpd_ring { 190 dma_addr_t dma; 191 struct qmu_gpd *start; 192 struct qmu_gpd *end; 193 struct qmu_gpd *enqueue; 194 struct qmu_gpd *dequeue; 195 }; 196 197 /** 198 * @vbus: vbus 5V used by host mode 199 * @edev: external connector used to detect vbus and iddig changes 200 * @id_nb : notifier for iddig(idpin) detection 201 * @dr_work : work for drd mode switch, used to avoid sleep in atomic context 202 * @desired_role : role desired to switch 203 * @default_role : default mode while usb role is USB_ROLE_NONE 204 * @role_sw : use USB Role Switch to support dual-role switch, can't use 205 * extcon at the same time, and extcon is deprecated. 206 * @role_sw_used : true when the USB Role Switch is used. 207 * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not 208 * @manual_drd_enabled: it's true when supports dual-role device by debugfs 209 * to switch host/device modes depending on user input. 210 */ 211 struct otg_switch_mtk { 212 struct regulator *vbus; 213 struct extcon_dev *edev; 214 struct notifier_block id_nb; 215 struct work_struct dr_work; 216 enum usb_role desired_role; 217 enum usb_role default_role; 218 struct usb_role_switch *role_sw; 219 bool role_sw_used; 220 bool is_u3_drd; 221 bool manual_drd_enabled; 222 }; 223 224 /** 225 * @mac_base: register base address of device MAC, exclude xHCI's 226 * @ippc_base: register base address of IP Power and Clock interface (IPPC) 227 * @vusb33: usb3.3V shared by device/host IP 228 * @dr_mode: works in which mode: 229 * host only, device only or dual-role mode 230 * @u2_ports: number of usb2.0 host ports 231 * @u3_ports: number of usb3.0 host ports 232 * @u2p_dis_msk: mask of disabling usb2 ports, e.g. bit0==1 to 233 * disable u2port0, bit1==1 to disable u2port1,... etc, 234 * but when use dual-role mode, can't disable u2port0 235 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to 236 * disable u3port0, bit1==1 to disable u3port1,... etc 237 * @dbgfs_root: only used when supports manual dual-role switch via debugfs 238 * @uwk_en: it's true when supports remote wakeup in host mode 239 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM 240 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk 241 * @uwk_vers: the version of the wakeup glue layer 242 */ 243 struct ssusb_mtk { 244 struct device *dev; 245 struct mtu3 *u3d; 246 void __iomem *mac_base; 247 void __iomem *ippc_base; 248 struct phy **phys; 249 int num_phys; 250 int wakeup_irq; 251 /* common power & clock */ 252 struct regulator *vusb33; 253 struct clk_bulk_data clks[BULK_CLKS_CNT]; 254 /* otg */ 255 struct otg_switch_mtk otg_switch; 256 enum usb_dr_mode dr_mode; 257 bool is_host; 258 int u2_ports; 259 int u3_ports; 260 int u2p_dis_msk; 261 int u3p_dis_msk; 262 struct dentry *dbgfs_root; 263 /* usb wakeup for host mode */ 264 bool uwk_en; 265 struct regmap *uwk; 266 u32 uwk_reg_base; 267 u32 uwk_vers; 268 }; 269 270 /** 271 * @fifo_size: it is (@slot + 1) * @fifo_seg_size 272 * @fifo_seg_size: it is roundup_pow_of_two(@maxp) 273 */ 274 struct mtu3_ep { 275 struct usb_ep ep; 276 char name[12]; 277 struct mtu3 *mtu; 278 u8 epnum; 279 u8 type; 280 u8 is_in; 281 u16 maxp; 282 int slot; 283 u32 fifo_size; 284 u32 fifo_addr; 285 u32 fifo_seg_size; 286 struct mtu3_fifo_info *fifo; 287 288 struct list_head req_list; 289 struct mtu3_gpd_ring gpd_ring; 290 const struct usb_ss_ep_comp_descriptor *comp_desc; 291 const struct usb_endpoint_descriptor *desc; 292 293 int flags; 294 }; 295 296 struct mtu3_request { 297 struct usb_request request; 298 struct list_head list; 299 struct mtu3_ep *mep; 300 struct mtu3 *mtu; 301 struct qmu_gpd *gpd; 302 int epnum; 303 }; 304 305 static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev) 306 { 307 return dev_get_drvdata(dev); 308 } 309 310 /** 311 * struct mtu3 - device driver instance data. 312 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only, 313 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP 314 * @may_wakeup: means device's remote wakeup is enabled 315 * @is_self_powered: is reported in device status and the config descriptor 316 * @delayed_status: true when function drivers ask for delayed status 317 * @gen2cp: compatible with USB3 Gen2 IP 318 * @ep0_req: dummy request used while handling standard USB requests 319 * for GET_STATUS and SET_SEL 320 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests 321 * @u3_capable: is capable of supporting USB3 322 */ 323 struct mtu3 { 324 spinlock_t lock; 325 struct ssusb_mtk *ssusb; 326 struct device *dev; 327 void __iomem *mac_base; 328 void __iomem *ippc_base; 329 int irq; 330 331 struct mtu3_fifo_info tx_fifo; 332 struct mtu3_fifo_info rx_fifo; 333 334 struct mtu3_ep *ep_array; 335 struct mtu3_ep *in_eps; 336 struct mtu3_ep *out_eps; 337 struct mtu3_ep *ep0; 338 int num_eps; 339 int slot; 340 int active_ep; 341 342 struct dma_pool *qmu_gpd_pool; 343 enum mtu3_g_ep0_state ep0_state; 344 struct usb_gadget g; /* the gadget */ 345 struct usb_gadget_driver *gadget_driver; 346 struct mtu3_request ep0_req; 347 u8 setup_buf[EP0_RESPONSE_BUF]; 348 enum usb_device_speed max_speed; 349 enum usb_device_speed speed; 350 351 unsigned is_active:1; 352 unsigned may_wakeup:1; 353 unsigned is_self_powered:1; 354 unsigned test_mode:1; 355 unsigned softconnect:1; 356 unsigned u1_enable:1; 357 unsigned u2_enable:1; 358 unsigned u3_capable:1; 359 unsigned delayed_status:1; 360 unsigned gen2cp:1; 361 unsigned connected:1; 362 unsigned async_callbacks:1; 363 unsigned separate_fifo:1; 364 365 u8 address; 366 u8 test_mode_nr; 367 u32 hw_version; 368 }; 369 370 static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g) 371 { 372 return container_of(g, struct mtu3, g); 373 } 374 375 static inline struct mtu3_request *to_mtu3_request(struct usb_request *req) 376 { 377 return req ? container_of(req, struct mtu3_request, request) : NULL; 378 } 379 380 static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep) 381 { 382 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL; 383 } 384 385 static inline struct mtu3_request *next_request(struct mtu3_ep *mep) 386 { 387 return list_first_entry_or_null(&mep->req_list, struct mtu3_request, 388 list); 389 } 390 391 static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data) 392 { 393 writel(data, base + offset); 394 } 395 396 static inline u32 mtu3_readl(void __iomem *base, u32 offset) 397 { 398 return readl(base + offset); 399 } 400 401 static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits) 402 { 403 void __iomem *addr = base + offset; 404 u32 tmp = readl(addr); 405 406 writel((tmp | (bits)), addr); 407 } 408 409 static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits) 410 { 411 void __iomem *addr = base + offset; 412 u32 tmp = readl(addr); 413 414 writel((tmp & ~(bits)), addr); 415 } 416 417 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks); 418 struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); 419 void mtu3_free_request(struct usb_ep *ep, struct usb_request *req); 420 void mtu3_req_complete(struct mtu3_ep *mep, 421 struct usb_request *req, int status); 422 423 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 424 int interval, int burst, int mult); 425 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep); 426 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set); 427 void mtu3_start(struct mtu3 *mtu); 428 void mtu3_stop(struct mtu3 *mtu); 429 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on); 430 431 int mtu3_gadget_setup(struct mtu3 *mtu); 432 void mtu3_gadget_cleanup(struct mtu3 *mtu); 433 void mtu3_gadget_reset(struct mtu3 *mtu); 434 void mtu3_gadget_suspend(struct mtu3 *mtu); 435 void mtu3_gadget_resume(struct mtu3 *mtu); 436 void mtu3_gadget_disconnect(struct mtu3 *mtu); 437 438 irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu); 439 extern const struct usb_ep_ops mtu3_ep0_ops; 440 441 #endif 442