1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 21 /* Code sharing between pci-quirks and xhci hcd */ 22 #include "xhci-ext-caps.h" 23 #include "pci-quirks.h" 24 25 /* max buffer size for trace and debug messages */ 26 #define XHCI_MSG_MAX 500 27 28 /* xHCI PCI Configuration Registers */ 29 #define XHCI_SBRN_OFFSET (0x60) 30 31 /* Max number of USB devices for any host controller - limit in section 6.1 */ 32 #define MAX_HC_SLOTS 256 33 /* Section 5.3.3 - MaxPorts */ 34 #define MAX_HC_PORTS 127 35 36 /* 37 * xHCI register interface. 38 * This corresponds to the eXtensible Host Controller Interface (xHCI) 39 * Revision 0.95 specification 40 */ 41 42 /** 43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 44 * @hc_capbase: length of the capabilities register and HC version number 45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 48 * @hcc_params: HCCPARAMS - Capability Parameters 49 * @db_off: DBOFF - Doorbell array offset 50 * @run_regs_off: RTSOFF - Runtime register space offset 51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 52 */ 53 struct xhci_cap_regs { 54 __le32 hc_capbase; 55 __le32 hcs_params1; 56 __le32 hcs_params2; 57 __le32 hcs_params3; 58 __le32 hcc_params; 59 __le32 db_off; 60 __le32 run_regs_off; 61 __le32 hcc_params2; /* xhci 1.1 */ 62 /* Reserved up to (CAPLENGTH - 0x1C) */ 63 }; 64 65 /* hc_capbase bitmasks */ 66 /* bits 7:0 - how long is the Capabilities register */ 67 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 68 /* bits 31:16 */ 69 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 70 71 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 72 /* bits 0:7, Max Device Slots */ 73 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 74 #define HCS_SLOTS_MASK 0xff 75 /* bits 8:18, Max Interrupters */ 76 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 78 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 79 80 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 81 /* bits 0:3, frames or uframes that SW needs to queue transactions 82 * ahead of the HW to meet periodic deadlines */ 83 #define HCS_IST(p) (((p) >> 0) & 0xf) 84 /* bits 4:7, max number of Event Ring segments */ 85 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 86 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 88 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 89 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 90 91 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 92 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 93 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 94 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 95 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 96 97 /* HCCPARAMS - hcc_params - bitmasks */ 98 /* true: HC can use 64-bit address pointers */ 99 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 100 /* true: HC can do bandwidth negotiation */ 101 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 102 /* true: HC uses 64-byte Device Context structures 103 * FIXME 64-byte context structures aren't supported yet. 104 */ 105 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 106 /* true: HC has port power switches */ 107 #define HCC_PPC(p) ((p) & (1 << 3)) 108 /* true: HC has port indicators */ 109 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 110 /* true: HC has Light HC Reset Capability */ 111 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 112 /* true: HC supports latency tolerance messaging */ 113 #define HCC_LTC(p) ((p) & (1 << 6)) 114 /* true: no secondary Stream ID Support */ 115 #define HCC_NSS(p) ((p) & (1 << 7)) 116 /* true: HC supports Stopped - Short Packet */ 117 #define HCC_SPC(p) ((p) & (1 << 9)) 118 /* true: HC has Contiguous Frame ID Capability */ 119 #define HCC_CFC(p) ((p) & (1 << 11)) 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 124 125 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 126 127 /* db_off bitmask - bits 0:1 reserved */ 128 #define DBOFF_MASK (~0x3) 129 130 /* run_regs_off bitmask - bits 0:4 reserved */ 131 #define RTSOFF_MASK (~0x1f) 132 133 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 134 /* true: HC supports U3 entry Capability */ 135 #define HCC2_U3C(p) ((p) & (1 << 0)) 136 /* true: HC supports Configure endpoint command Max exit latency too large */ 137 #define HCC2_CMC(p) ((p) & (1 << 1)) 138 /* true: HC supports Force Save context Capability */ 139 #define HCC2_FSC(p) ((p) & (1 << 2)) 140 /* true: HC supports Compliance Transition Capability */ 141 #define HCC2_CTC(p) ((p) & (1 << 3)) 142 /* true: HC support Large ESIT payload Capability > 48k */ 143 #define HCC2_LEC(p) ((p) & (1 << 4)) 144 /* true: HC support Configuration Information Capability */ 145 #define HCC2_CIC(p) ((p) & (1 << 5)) 146 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 147 #define HCC2_ETC(p) ((p) & (1 << 6)) 148 149 /* Number of registers per port */ 150 #define NUM_PORT_REGS 4 151 152 #define PORTSC 0 153 #define PORTPMSC 1 154 #define PORTLI 2 155 #define PORTHLPMC 3 156 157 /** 158 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 159 * @command: USBCMD - xHC command register 160 * @status: USBSTS - xHC status register 161 * @page_size: This indicates the page size that the host controller 162 * supports. If bit n is set, the HC supports a page size 163 * of 2^(n+12), up to a 128MB page size. 164 * 4K is the minimum page size. 165 * @cmd_ring: CRP - 64-bit Command Ring Pointer 166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 167 * @config_reg: CONFIG - Configure Register 168 * @port_status_base: PORTSCn - base address for Port Status and Control 169 * Each port has a Port Status and Control register, 170 * followed by a Port Power Management Status and Control 171 * register, a Port Link Info register, and a reserved 172 * register. 173 * @port_power_base: PORTPMSCn - base address for 174 * Port Power Management Status and Control 175 * @port_link_base: PORTLIn - base address for Port Link Info (current 176 * Link PM state and control) for USB 2.1 and USB 3.0 177 * devices. 178 */ 179 struct xhci_op_regs { 180 __le32 command; 181 __le32 status; 182 __le32 page_size; 183 __le32 reserved1; 184 __le32 reserved2; 185 __le32 dev_notification; 186 __le64 cmd_ring; 187 /* rsvd: offset 0x20-2F */ 188 __le32 reserved3[4]; 189 __le64 dcbaa_ptr; 190 __le32 config_reg; 191 /* rsvd: offset 0x3C-3FF */ 192 __le32 reserved4[241]; 193 /* port 1 registers, which serve as a base address for other ports */ 194 __le32 port_status_base; 195 __le32 port_power_base; 196 __le32 port_link_base; 197 __le32 reserved5; 198 /* registers for ports 2-255 */ 199 __le32 reserved6[NUM_PORT_REGS*254]; 200 }; 201 202 /* USBCMD - USB command - command bitmasks */ 203 /* start/stop HC execution - do not write unless HC is halted*/ 204 #define CMD_RUN XHCI_CMD_RUN 205 /* Reset HC - resets internal HC state machine and all registers (except 206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 207 * The xHCI driver must reinitialize the xHC after setting this bit. 208 */ 209 #define CMD_RESET (1 << 1) 210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 211 #define CMD_EIE XHCI_CMD_EIE 212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 213 #define CMD_HSEIE XHCI_CMD_HSEIE 214 /* bits 4:6 are reserved (and should be preserved on writes). */ 215 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 216 #define CMD_LRESET (1 << 7) 217 /* host controller save/restore state. */ 218 #define CMD_CSS (1 << 8) 219 #define CMD_CRS (1 << 9) 220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 221 #define CMD_EWE XHCI_CMD_EWE 222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 224 * '0' means the xHC can power it off if all ports are in the disconnect, 225 * disabled, or powered-off state. 226 */ 227 #define CMD_PM_INDEX (1 << 11) 228 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 229 #define CMD_ETE (1 << 14) 230 /* bits 15:31 are reserved (and should be preserved on writes). */ 231 232 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 233 #define XHCI_RESET_SHORT_USEC (250 * 1000) 234 235 /* IMAN - Interrupt Management Register */ 236 #define IMAN_IE (1 << 1) 237 #define IMAN_IP (1 << 0) 238 239 /* USBSTS - USB status - status bitmasks */ 240 /* HC not running - set to 1 when run/stop bit is cleared. */ 241 #define STS_HALT XHCI_STS_HALT 242 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 243 #define STS_FATAL (1 << 2) 244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 245 #define STS_EINT (1 << 3) 246 /* port change detect */ 247 #define STS_PORT (1 << 4) 248 /* bits 5:7 reserved and zeroed */ 249 /* save state status - '1' means xHC is saving state */ 250 #define STS_SAVE (1 << 8) 251 /* restore state status - '1' means xHC is restoring state */ 252 #define STS_RESTORE (1 << 9) 253 /* true: save or restore error */ 254 #define STS_SRE (1 << 10) 255 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 256 #define STS_CNR XHCI_STS_CNR 257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 258 #define STS_HCE (1 << 12) 259 /* bits 13:31 reserved and should be preserved */ 260 261 /* 262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 263 * Generate a device notification event when the HC sees a transaction with a 264 * notification type that matches a bit set in this bit field. 265 */ 266 #define DEV_NOTE_MASK (0xffff) 267 #define ENABLE_DEV_NOTE(x) (1 << (x)) 268 /* Most of the device notification types should only be used for debug. 269 * SW does need to pay attention to function wake notifications. 270 */ 271 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 272 273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 274 /* bit 0 is the command ring cycle state */ 275 /* stop ring operation after completion of the currently executing command */ 276 #define CMD_RING_PAUSE (1 << 1) 277 /* stop ring immediately - abort the currently executing command */ 278 #define CMD_RING_ABORT (1 << 2) 279 /* true: command ring is running */ 280 #define CMD_RING_RUNNING (1 << 3) 281 /* bits 4:5 reserved and should be preserved */ 282 /* Command Ring pointer - bit mask for the lower 32 bits. */ 283 #define CMD_RING_RSVD_BITS (0x3f) 284 285 /* CONFIG - Configure Register - config_reg bitmasks */ 286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 287 #define MAX_DEVS(p) ((p) & 0xff) 288 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 289 #define CONFIG_U3E (1 << 8) 290 /* bit 9: Configuration Information Enable, xhci 1.1 */ 291 #define CONFIG_CIE (1 << 9) 292 /* bits 10:31 - reserved and should be preserved */ 293 294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 295 /* true: device connected */ 296 #define PORT_CONNECT (1 << 0) 297 /* true: port enabled */ 298 #define PORT_PE (1 << 1) 299 /* bit 2 reserved and zeroed */ 300 /* true: port has an over-current condition */ 301 #define PORT_OC (1 << 3) 302 /* true: port reset signaling asserted */ 303 #define PORT_RESET (1 << 4) 304 /* Port Link State - bits 5:8 305 * A read gives the current link PM state of the port, 306 * a write with Link State Write Strobe set sets the link state. 307 */ 308 #define PORT_PLS_MASK (0xf << 5) 309 #define XDEV_U0 (0x0 << 5) 310 #define XDEV_U1 (0x1 << 5) 311 #define XDEV_U2 (0x2 << 5) 312 #define XDEV_U3 (0x3 << 5) 313 #define XDEV_DISABLED (0x4 << 5) 314 #define XDEV_RXDETECT (0x5 << 5) 315 #define XDEV_INACTIVE (0x6 << 5) 316 #define XDEV_POLLING (0x7 << 5) 317 #define XDEV_RECOVERY (0x8 << 5) 318 #define XDEV_HOT_RESET (0x9 << 5) 319 #define XDEV_COMP_MODE (0xa << 5) 320 #define XDEV_TEST_MODE (0xb << 5) 321 #define XDEV_RESUME (0xf << 5) 322 323 /* true: port has power (see HCC_PPC) */ 324 #define PORT_POWER (1 << 9) 325 /* bits 10:13 indicate device speed: 326 * 0 - undefined speed - port hasn't be initialized by a reset yet 327 * 1 - full speed 328 * 2 - low speed 329 * 3 - high speed 330 * 4 - super speed 331 * 5-15 reserved 332 */ 333 #define DEV_SPEED_MASK (0xf << 10) 334 #define XDEV_FS (0x1 << 10) 335 #define XDEV_LS (0x2 << 10) 336 #define XDEV_HS (0x3 << 10) 337 #define XDEV_SS (0x4 << 10) 338 #define XDEV_SSP (0x5 << 10) 339 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 340 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 341 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 342 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 343 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 344 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 345 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 346 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 347 348 /* Bits 20:23 in the Slot Context are the speed for the device */ 349 #define SLOT_SPEED_FS (XDEV_FS << 10) 350 #define SLOT_SPEED_LS (XDEV_LS << 10) 351 #define SLOT_SPEED_HS (XDEV_HS << 10) 352 #define SLOT_SPEED_SS (XDEV_SS << 10) 353 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 354 /* Port Indicator Control */ 355 #define PORT_LED_OFF (0 << 14) 356 #define PORT_LED_AMBER (1 << 14) 357 #define PORT_LED_GREEN (2 << 14) 358 #define PORT_LED_MASK (3 << 14) 359 /* Port Link State Write Strobe - set this when changing link state */ 360 #define PORT_LINK_STROBE (1 << 16) 361 /* true: connect status change */ 362 #define PORT_CSC (1 << 17) 363 /* true: port enable change */ 364 #define PORT_PEC (1 << 18) 365 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 366 * into an enabled state, and the device into the default state. A "warm" reset 367 * also resets the link, forcing the device through the link training sequence. 368 * SW can also look at the Port Reset register to see when warm reset is done. 369 */ 370 #define PORT_WRC (1 << 19) 371 /* true: over-current change */ 372 #define PORT_OCC (1 << 20) 373 /* true: reset change - 1 to 0 transition of PORT_RESET */ 374 #define PORT_RC (1 << 21) 375 /* port link status change - set on some port link state transitions: 376 * Transition Reason 377 * ------------------------------------------------------------------------------ 378 * - U3 to Resume Wakeup signaling from a device 379 * - Resume to Recovery to U0 USB 3.0 device resume 380 * - Resume to U0 USB 2.0 device resume 381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 382 * - U3 to U0 Software resume of USB 2.0 device complete 383 * - U2 to U0 L1 resume of USB 2.1 device complete 384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 385 * - U0 to disabled L1 entry error with USB 2.1 device 386 * - Any state to inactive Error on USB 3.0 port 387 */ 388 #define PORT_PLC (1 << 22) 389 /* port configure error change - port failed to configure its link partner */ 390 #define PORT_CEC (1 << 23) 391 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 392 PORT_RC | PORT_PLC | PORT_CEC) 393 394 395 /* Cold Attach Status - xHC can set this bit to report device attached during 396 * Sx state. Warm port reset should be perfomed to clear this bit and move port 397 * to connected state. 398 */ 399 #define PORT_CAS (1 << 24) 400 /* wake on connect (enable) */ 401 #define PORT_WKCONN_E (1 << 25) 402 /* wake on disconnect (enable) */ 403 #define PORT_WKDISC_E (1 << 26) 404 /* wake on over-current (enable) */ 405 #define PORT_WKOC_E (1 << 27) 406 /* bits 28:29 reserved */ 407 /* true: device is non-removable - for USB 3.0 roothub emulation */ 408 #define PORT_DEV_REMOVE (1 << 30) 409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 410 #define PORT_WR (1 << 31) 411 412 /* We mark duplicate entries with -1 */ 413 #define DUPLICATE_ENTRY ((u8)(-1)) 414 415 /* Port Power Management Status and Control - port_power_base bitmasks */ 416 /* Inactivity timer value for transitions into U1, in microseconds. 417 * Timeout can be up to 127us. 0xFF means an infinite timeout. 418 */ 419 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 420 #define PORT_U1_TIMEOUT_MASK 0xff 421 /* Inactivity timer value for transitions into U2 */ 422 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 423 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 424 /* Bits 24:31 for port testing */ 425 426 /* USB2 Protocol PORTSPMSC */ 427 #define PORT_L1S_MASK 7 428 #define PORT_L1S_SUCCESS 1 429 #define PORT_RWE (1 << 3) 430 #define PORT_HIRD(p) (((p) & 0xf) << 4) 431 #define PORT_HIRD_MASK (0xf << 4) 432 #define PORT_L1DS_MASK (0xff << 8) 433 #define PORT_L1DS(p) (((p) & 0xff) << 8) 434 #define PORT_HLE (1 << 16) 435 #define PORT_TEST_MODE_SHIFT 28 436 437 /* USB3 Protocol PORTLI Port Link Information */ 438 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 439 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 440 441 /* USB2 Protocol PORTHLPMC */ 442 #define PORT_HIRDM(p)((p) & 3) 443 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 444 #define PORT_BESLD(p)(((p) & 0xf) << 10) 445 446 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 447 #define XHCI_L1_TIMEOUT 512 448 449 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 451 * by other operating systems. 452 * 453 * XHCI 1.0 errata 8/14/12 Table 13 notes: 454 * "Software should choose xHC BESL/BESLD field values that do not violate a 455 * device's resume latency requirements, 456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 457 * or not program values < '4' if BLC = '0' and a BESL device is attached. 458 */ 459 #define XHCI_DEFAULT_BESL 4 460 461 /* 462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports 463 * to complete link training. usually link trainig completes much faster 464 * so check status 10 times with 36ms sleep in places we need to wait for 465 * polling to complete. 466 */ 467 #define XHCI_PORT_POLLING_LFPS_TIME 36 468 469 /** 470 * struct xhci_intr_reg - Interrupt Register Set 471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 472 * interrupts and check for pending interrupts. 473 * @irq_control: IMOD - Interrupt Moderation Register. 474 * Used to throttle interrupts. 475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 476 * @erst_base: ERST base address. 477 * @erst_dequeue: Event ring dequeue pointer. 478 * 479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 481 * multiple segments of the same size. The HC places events on the ring and 482 * "updates the Cycle bit in the TRBs to indicate to software the current 483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 484 * updates the dequeue pointer. 485 */ 486 struct xhci_intr_reg { 487 __le32 irq_pending; 488 __le32 irq_control; 489 __le32 erst_size; 490 __le32 rsvd; 491 __le64 erst_base; 492 __le64 erst_dequeue; 493 }; 494 495 /* irq_pending bitmasks */ 496 #define ER_IRQ_PENDING(p) ((p) & 0x1) 497 /* bits 2:31 need to be preserved */ 498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 499 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 500 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 501 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 502 503 /* irq_control bitmasks */ 504 /* Minimum interval between interrupts (in 250ns intervals). The interval 505 * between interrupts will be longer if there are no events on the event ring. 506 * Default is 4000 (1 ms). 507 */ 508 #define ER_IRQ_INTERVAL_MASK (0xffff) 509 /* Counter used to count down the time to the next interrupt - HW use only */ 510 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 511 512 /* erst_size bitmasks */ 513 /* Preserve bits 16:31 of erst_size */ 514 #define ERST_SIZE_MASK (0xffff << 16) 515 516 /* erst_base bitmasks */ 517 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) 518 519 /* erst_dequeue bitmasks */ 520 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 521 * where the current dequeue pointer lies. This is an optional HW hint. 522 */ 523 #define ERST_DESI_MASK (0x7) 524 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 525 * a work queue (or delayed service routine)? 526 */ 527 #define ERST_EHB (1 << 3) 528 #define ERST_PTR_MASK (GENMASK_ULL(63, 4)) 529 530 /** 531 * struct xhci_run_regs 532 * @microframe_index: 533 * MFINDEX - current microframe number 534 * 535 * Section 5.5 Host Controller Runtime Registers: 536 * "Software should read and write these registers using only Dword (32 bit) 537 * or larger accesses" 538 */ 539 struct xhci_run_regs { 540 __le32 microframe_index; 541 __le32 rsvd[7]; 542 struct xhci_intr_reg ir_set[128]; 543 }; 544 545 /** 546 * struct doorbell_array 547 * 548 * Bits 0 - 7: Endpoint target 549 * Bits 8 - 15: RsvdZ 550 * Bits 16 - 31: Stream ID 551 * 552 * Section 5.6 553 */ 554 struct xhci_doorbell_array { 555 __le32 doorbell[256]; 556 }; 557 558 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 559 #define DB_VALUE_HOST 0x00000000 560 561 #define PLT_MASK (0x03 << 6) 562 #define PLT_SYM (0x00 << 6) 563 #define PLT_ASYM_RX (0x02 << 6) 564 #define PLT_ASYM_TX (0x03 << 6) 565 566 /** 567 * struct xhci_container_ctx 568 * @type: Type of context. Used to calculated offsets to contained contexts. 569 * @size: Size of the context data 570 * @bytes: The raw context data given to HW 571 * @dma: dma address of the bytes 572 * 573 * Represents either a Device or Input context. Holds a pointer to the raw 574 * memory used for the context (bytes) and dma address of it (dma). 575 */ 576 struct xhci_container_ctx { 577 unsigned type; 578 #define XHCI_CTX_TYPE_DEVICE 0x1 579 #define XHCI_CTX_TYPE_INPUT 0x2 580 581 int size; 582 583 u8 *bytes; 584 dma_addr_t dma; 585 }; 586 587 /** 588 * struct xhci_slot_ctx 589 * @dev_info: Route string, device speed, hub info, and last valid endpoint 590 * @dev_info2: Max exit latency for device number, root hub port number 591 * @tt_info: tt_info is used to construct split transaction tokens 592 * @dev_state: slot state and device address 593 * 594 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 596 * reserved at the end of the slot context for HC internal use. 597 */ 598 struct xhci_slot_ctx { 599 __le32 dev_info; 600 __le32 dev_info2; 601 __le32 tt_info; 602 __le32 dev_state; 603 /* offset 0x10 to 0x1f reserved for HC internal use */ 604 __le32 reserved[4]; 605 }; 606 607 /* dev_info bitmasks */ 608 /* Route String - 0:19 */ 609 #define ROUTE_STRING_MASK (0xfffff) 610 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 611 #define DEV_SPEED (0xf << 20) 612 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 613 /* bit 24 reserved */ 614 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 615 #define DEV_MTT (0x1 << 25) 616 /* Set if the device is a hub - bit 26 */ 617 #define DEV_HUB (0x1 << 26) 618 /* Index of the last valid endpoint context in this device context - 27:31 */ 619 #define LAST_CTX_MASK (0x1f << 27) 620 #define LAST_CTX(p) ((p) << 27) 621 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 622 #define SLOT_FLAG (1 << 0) 623 #define EP0_FLAG (1 << 1) 624 625 /* dev_info2 bitmasks */ 626 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 627 #define MAX_EXIT (0xffff) 628 /* Root hub port number that is needed to access the USB device */ 629 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 630 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 631 /* Maximum number of ports under a hub device */ 632 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 633 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 634 635 /* tt_info bitmasks */ 636 /* 637 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 638 * The Slot ID of the hub that isolates the high speed signaling from 639 * this low or full-speed device. '0' if attached to root hub port. 640 */ 641 #define TT_SLOT (0xff) 642 /* 643 * The number of the downstream facing port of the high-speed hub 644 * '0' if the device is not low or full speed. 645 */ 646 #define TT_PORT (0xff << 8) 647 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 648 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 649 650 /* dev_state bitmasks */ 651 /* USB device address - assigned by the HC */ 652 #define DEV_ADDR_MASK (0xff) 653 /* bits 8:26 reserved */ 654 /* Slot state */ 655 #define SLOT_STATE (0x1f << 27) 656 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 657 658 #define SLOT_STATE_DISABLED 0 659 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 660 #define SLOT_STATE_DEFAULT 1 661 #define SLOT_STATE_ADDRESSED 2 662 #define SLOT_STATE_CONFIGURED 3 663 664 /** 665 * struct xhci_ep_ctx 666 * @ep_info: endpoint state, streams, mult, and interval information. 667 * @ep_info2: information on endpoint type, max packet size, max burst size, 668 * error count, and whether the HC will force an event for all 669 * transactions. 670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 671 * defines one stream, this points to the endpoint transfer ring. 672 * Otherwise, it points to a stream context array, which has a 673 * ring pointer for each flow. 674 * @tx_info: 675 * Average TRB lengths for the endpoint ring and 676 * max payload within an Endpoint Service Interval Time (ESIT). 677 * 678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 680 * reserved at the end of the endpoint context for HC internal use. 681 */ 682 struct xhci_ep_ctx { 683 __le32 ep_info; 684 __le32 ep_info2; 685 __le64 deq; 686 __le32 tx_info; 687 /* offset 0x14 - 0x1f reserved for HC internal use */ 688 __le32 reserved[3]; 689 }; 690 691 /* ep_info bitmasks */ 692 /* 693 * Endpoint State - bits 0:2 694 * 0 - disabled 695 * 1 - running 696 * 2 - halted due to halt condition - ok to manipulate endpoint ring 697 * 3 - stopped 698 * 4 - TRB error 699 * 5-7 - reserved 700 */ 701 #define EP_STATE_MASK (0x7) 702 #define EP_STATE_DISABLED 0 703 #define EP_STATE_RUNNING 1 704 #define EP_STATE_HALTED 2 705 #define EP_STATE_STOPPED 3 706 #define EP_STATE_ERROR 4 707 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 708 709 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 710 #define EP_MULT(p) (((p) & 0x3) << 8) 711 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 712 /* bits 10:14 are Max Primary Streams */ 713 /* bit 15 is Linear Stream Array */ 714 /* Interval - period between requests to an endpoint - 125u increments. */ 715 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 716 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 717 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 718 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 719 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 720 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 721 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 722 #define EP_HAS_LSA (1 << 15) 723 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 724 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 725 726 /* ep_info2 bitmasks */ 727 /* 728 * Force Event - generate transfer events for all TRBs for this endpoint 729 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 730 */ 731 #define FORCE_EVENT (0x1) 732 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 733 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 734 #define EP_TYPE(p) ((p) << 3) 735 #define ISOC_OUT_EP 1 736 #define BULK_OUT_EP 2 737 #define INT_OUT_EP 3 738 #define CTRL_EP 4 739 #define ISOC_IN_EP 5 740 #define BULK_IN_EP 6 741 #define INT_IN_EP 7 742 /* bit 6 reserved */ 743 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 744 #define MAX_BURST(p) (((p)&0xff) << 8) 745 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 746 #define MAX_PACKET(p) (((p)&0xffff) << 16) 747 #define MAX_PACKET_MASK (0xffff << 16) 748 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 749 750 /* tx_info bitmasks */ 751 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 752 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 753 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 754 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 755 756 /* deq bitmasks */ 757 #define EP_CTX_CYCLE_MASK (1 << 0) 758 #define SCTX_DEQ_MASK (~0xfL) 759 760 761 /** 762 * struct xhci_input_control_context 763 * Input control context; see section 6.2.5. 764 * 765 * @drop_context: set the bit of the endpoint context you want to disable 766 * @add_context: set the bit of the endpoint context you want to enable 767 */ 768 struct xhci_input_control_ctx { 769 __le32 drop_flags; 770 __le32 add_flags; 771 __le32 rsvd2[6]; 772 }; 773 774 #define EP_IS_ADDED(ctrl_ctx, i) \ 775 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 776 #define EP_IS_DROPPED(ctrl_ctx, i) \ 777 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 778 779 /* Represents everything that is needed to issue a command on the command ring. 780 * It's useful to pre-allocate these for commands that cannot fail due to 781 * out-of-memory errors, like freeing streams. 782 */ 783 struct xhci_command { 784 /* Input context for changing device state */ 785 struct xhci_container_ctx *in_ctx; 786 u32 status; 787 int slot_id; 788 /* If completion is null, no one is waiting on this command 789 * and the structure can be freed after the command completes. 790 */ 791 struct completion *completion; 792 union xhci_trb *command_trb; 793 struct list_head cmd_list; 794 }; 795 796 /* drop context bitmasks */ 797 #define DROP_EP(x) (0x1 << x) 798 /* add context bitmasks */ 799 #define ADD_EP(x) (0x1 << x) 800 801 struct xhci_stream_ctx { 802 /* 64-bit stream ring address, cycle state, and stream type */ 803 __le64 stream_ring; 804 /* offset 0x14 - 0x1f reserved for HC internal use */ 805 __le32 reserved[2]; 806 }; 807 808 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 809 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 810 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 811 #define SCT_SEC_TR 0 812 /* Primary stream array type, dequeue pointer is to a transfer ring */ 813 #define SCT_PRI_TR 1 814 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 815 #define SCT_SSA_8 2 816 #define SCT_SSA_16 3 817 #define SCT_SSA_32 4 818 #define SCT_SSA_64 5 819 #define SCT_SSA_128 6 820 #define SCT_SSA_256 7 821 822 /* Assume no secondary streams for now */ 823 struct xhci_stream_info { 824 struct xhci_ring **stream_rings; 825 /* Number of streams, including stream 0 (which drivers can't use) */ 826 unsigned int num_streams; 827 /* The stream context array may be bigger than 828 * the number of streams the driver asked for 829 */ 830 struct xhci_stream_ctx *stream_ctx_array; 831 unsigned int num_stream_ctxs; 832 dma_addr_t ctx_array_dma; 833 /* For mapping physical TRB addresses to segments in stream rings */ 834 struct radix_tree_root trb_address_map; 835 struct xhci_command *free_streams_command; 836 }; 837 838 #define SMALL_STREAM_ARRAY_SIZE 256 839 #define MEDIUM_STREAM_ARRAY_SIZE 1024 840 841 /* Some Intel xHCI host controllers need software to keep track of the bus 842 * bandwidth. Keep track of endpoint info here. Each root port is allocated 843 * the full bus bandwidth. We must also treat TTs (including each port under a 844 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 845 * (DMI) also limits the total bandwidth (across all domains) that can be used. 846 */ 847 struct xhci_bw_info { 848 /* ep_interval is zero-based */ 849 unsigned int ep_interval; 850 /* mult and num_packets are one-based */ 851 unsigned int mult; 852 unsigned int num_packets; 853 unsigned int max_packet_size; 854 unsigned int max_esit_payload; 855 unsigned int type; 856 }; 857 858 /* "Block" sizes in bytes the hardware uses for different device speeds. 859 * The logic in this part of the hardware limits the number of bits the hardware 860 * can use, so must represent bandwidth in a less precise manner to mimic what 861 * the scheduler hardware computes. 862 */ 863 #define FS_BLOCK 1 864 #define HS_BLOCK 4 865 #define SS_BLOCK 16 866 #define DMI_BLOCK 32 867 868 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 869 * with each byte transferred. SuperSpeed devices have an initial overhead to 870 * set up bursts. These are in blocks, see above. LS overhead has already been 871 * translated into FS blocks. 872 */ 873 #define DMI_OVERHEAD 8 874 #define DMI_OVERHEAD_BURST 4 875 #define SS_OVERHEAD 8 876 #define SS_OVERHEAD_BURST 32 877 #define HS_OVERHEAD 26 878 #define FS_OVERHEAD 20 879 #define LS_OVERHEAD 128 880 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 881 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 882 * of overhead associated with split transfers crossing microframe boundaries. 883 * 31 blocks is pure protocol overhead. 884 */ 885 #define TT_HS_OVERHEAD (31 + 94) 886 #define TT_DMI_OVERHEAD (25 + 12) 887 888 /* Bandwidth limits in blocks */ 889 #define FS_BW_LIMIT 1285 890 #define TT_BW_LIMIT 1320 891 #define HS_BW_LIMIT 1607 892 #define SS_BW_LIMIT_IN 3906 893 #define DMI_BW_LIMIT_IN 3906 894 #define SS_BW_LIMIT_OUT 3906 895 #define DMI_BW_LIMIT_OUT 3906 896 897 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 898 #define FS_BW_RESERVED 10 899 #define HS_BW_RESERVED 20 900 #define SS_BW_RESERVED 10 901 902 struct xhci_virt_ep { 903 struct xhci_virt_device *vdev; /* parent */ 904 unsigned int ep_index; 905 struct xhci_ring *ring; 906 /* Related to endpoints that are configured to use stream IDs only */ 907 struct xhci_stream_info *stream_info; 908 /* Temporary storage in case the configure endpoint command fails and we 909 * have to restore the device state to the previous state 910 */ 911 struct xhci_ring *new_ring; 912 unsigned int err_count; 913 unsigned int ep_state; 914 #define SET_DEQ_PENDING (1 << 0) 915 #define EP_HALTED (1 << 1) /* For stall handling */ 916 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 917 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 918 #define EP_GETTING_STREAMS (1 << 3) 919 #define EP_HAS_STREAMS (1 << 4) 920 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 921 #define EP_GETTING_NO_STREAMS (1 << 5) 922 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 923 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 924 /* usb_hub_clear_tt_buffer is in progress */ 925 #define EP_CLEARING_TT (1 << 8) 926 /* ---- Related to URB cancellation ---- */ 927 struct list_head cancelled_td_list; 928 struct xhci_hcd *xhci; 929 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 930 * command. We'll need to update the ring's dequeue segment and dequeue 931 * pointer after the command completes. 932 */ 933 struct xhci_segment *queued_deq_seg; 934 union xhci_trb *queued_deq_ptr; 935 /* 936 * Sometimes the xHC can not process isochronous endpoint ring quickly 937 * enough, and it will miss some isoc tds on the ring and generate 938 * a Missed Service Error Event. 939 * Set skip flag when receive a Missed Service Error Event and 940 * process the missed tds on the endpoint ring. 941 */ 942 bool skip; 943 /* Bandwidth checking storage */ 944 struct xhci_bw_info bw_info; 945 struct list_head bw_endpoint_list; 946 /* Isoch Frame ID checking storage */ 947 int next_frame_id; 948 /* Use new Isoch TRB layout needed for extended TBC support */ 949 bool use_extended_tbc; 950 }; 951 952 enum xhci_overhead_type { 953 LS_OVERHEAD_TYPE = 0, 954 FS_OVERHEAD_TYPE, 955 HS_OVERHEAD_TYPE, 956 }; 957 958 struct xhci_interval_bw { 959 unsigned int num_packets; 960 /* Sorted by max packet size. 961 * Head of the list is the greatest max packet size. 962 */ 963 struct list_head endpoints; 964 /* How many endpoints of each speed are present. */ 965 unsigned int overhead[3]; 966 }; 967 968 #define XHCI_MAX_INTERVAL 16 969 970 struct xhci_interval_bw_table { 971 unsigned int interval0_esit_payload; 972 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 973 /* Includes reserved bandwidth for async endpoints */ 974 unsigned int bw_used; 975 unsigned int ss_bw_in; 976 unsigned int ss_bw_out; 977 }; 978 979 #define EP_CTX_PER_DEV 31 980 981 struct xhci_virt_device { 982 int slot_id; 983 struct usb_device *udev; 984 /* 985 * Commands to the hardware are passed an "input context" that 986 * tells the hardware what to change in its data structures. 987 * The hardware will return changes in an "output context" that 988 * software must allocate for the hardware. We need to keep 989 * track of input and output contexts separately because 990 * these commands might fail and we don't trust the hardware. 991 */ 992 struct xhci_container_ctx *out_ctx; 993 /* Used for addressing devices and configuration changes */ 994 struct xhci_container_ctx *in_ctx; 995 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 996 u8 fake_port; 997 u8 real_port; 998 struct xhci_interval_bw_table *bw_table; 999 struct xhci_tt_bw_info *tt_info; 1000 /* 1001 * flags for state tracking based on events and issued commands. 1002 * Software can not rely on states from output contexts because of 1003 * latency between events and xHC updating output context values. 1004 * See xhci 1.1 section 4.8.3 for more details 1005 */ 1006 unsigned long flags; 1007 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 1008 1009 /* The current max exit latency for the enabled USB3 link states. */ 1010 u16 current_mel; 1011 /* Used for the debugfs interfaces. */ 1012 void *debugfs_private; 1013 }; 1014 1015 /* 1016 * For each roothub, keep track of the bandwidth information for each periodic 1017 * interval. 1018 * 1019 * If a high speed hub is attached to the roothub, each TT associated with that 1020 * hub is a separate bandwidth domain. The interval information for the 1021 * endpoints on the devices under that TT will appear in the TT structure. 1022 */ 1023 struct xhci_root_port_bw_info { 1024 struct list_head tts; 1025 unsigned int num_active_tts; 1026 struct xhci_interval_bw_table bw_table; 1027 }; 1028 1029 struct xhci_tt_bw_info { 1030 struct list_head tt_list; 1031 int slot_id; 1032 int ttport; 1033 struct xhci_interval_bw_table bw_table; 1034 int active_eps; 1035 }; 1036 1037 1038 /** 1039 * struct xhci_device_context_array 1040 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1041 */ 1042 struct xhci_device_context_array { 1043 /* 64-bit device addresses; we only write 32-bit addresses */ 1044 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1045 /* private xHCD pointers */ 1046 dma_addr_t dma; 1047 }; 1048 /* TODO: write function to set the 64-bit device DMA address */ 1049 /* 1050 * TODO: change this to be dynamically sized at HC mem init time since the HC 1051 * might not be able to handle the maximum number of devices possible. 1052 */ 1053 1054 1055 struct xhci_transfer_event { 1056 /* 64-bit buffer address, or immediate data */ 1057 __le64 buffer; 1058 __le32 transfer_len; 1059 /* This field is interpreted differently based on the type of TRB */ 1060 __le32 flags; 1061 }; 1062 1063 /* Transfer event TRB length bit mask */ 1064 /* bits 0:23 */ 1065 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1066 1067 /** Transfer Event bit fields **/ 1068 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1069 1070 /* Completion Code - only applicable for some types of TRBs */ 1071 #define COMP_CODE_MASK (0xff << 24) 1072 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1073 #define COMP_INVALID 0 1074 #define COMP_SUCCESS 1 1075 #define COMP_DATA_BUFFER_ERROR 2 1076 #define COMP_BABBLE_DETECTED_ERROR 3 1077 #define COMP_USB_TRANSACTION_ERROR 4 1078 #define COMP_TRB_ERROR 5 1079 #define COMP_STALL_ERROR 6 1080 #define COMP_RESOURCE_ERROR 7 1081 #define COMP_BANDWIDTH_ERROR 8 1082 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1083 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1084 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1085 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1086 #define COMP_SHORT_PACKET 13 1087 #define COMP_RING_UNDERRUN 14 1088 #define COMP_RING_OVERRUN 15 1089 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1090 #define COMP_PARAMETER_ERROR 17 1091 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1092 #define COMP_CONTEXT_STATE_ERROR 19 1093 #define COMP_NO_PING_RESPONSE_ERROR 20 1094 #define COMP_EVENT_RING_FULL_ERROR 21 1095 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1096 #define COMP_MISSED_SERVICE_ERROR 23 1097 #define COMP_COMMAND_RING_STOPPED 24 1098 #define COMP_COMMAND_ABORTED 25 1099 #define COMP_STOPPED 26 1100 #define COMP_STOPPED_LENGTH_INVALID 27 1101 #define COMP_STOPPED_SHORT_PACKET 28 1102 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1103 #define COMP_ISOCH_BUFFER_OVERRUN 31 1104 #define COMP_EVENT_LOST_ERROR 32 1105 #define COMP_UNDEFINED_ERROR 33 1106 #define COMP_INVALID_STREAM_ID_ERROR 34 1107 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1108 #define COMP_SPLIT_TRANSACTION_ERROR 36 1109 1110 static inline const char *xhci_trb_comp_code_string(u8 status) 1111 { 1112 switch (status) { 1113 case COMP_INVALID: 1114 return "Invalid"; 1115 case COMP_SUCCESS: 1116 return "Success"; 1117 case COMP_DATA_BUFFER_ERROR: 1118 return "Data Buffer Error"; 1119 case COMP_BABBLE_DETECTED_ERROR: 1120 return "Babble Detected"; 1121 case COMP_USB_TRANSACTION_ERROR: 1122 return "USB Transaction Error"; 1123 case COMP_TRB_ERROR: 1124 return "TRB Error"; 1125 case COMP_STALL_ERROR: 1126 return "Stall Error"; 1127 case COMP_RESOURCE_ERROR: 1128 return "Resource Error"; 1129 case COMP_BANDWIDTH_ERROR: 1130 return "Bandwidth Error"; 1131 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1132 return "No Slots Available Error"; 1133 case COMP_INVALID_STREAM_TYPE_ERROR: 1134 return "Invalid Stream Type Error"; 1135 case COMP_SLOT_NOT_ENABLED_ERROR: 1136 return "Slot Not Enabled Error"; 1137 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1138 return "Endpoint Not Enabled Error"; 1139 case COMP_SHORT_PACKET: 1140 return "Short Packet"; 1141 case COMP_RING_UNDERRUN: 1142 return "Ring Underrun"; 1143 case COMP_RING_OVERRUN: 1144 return "Ring Overrun"; 1145 case COMP_VF_EVENT_RING_FULL_ERROR: 1146 return "VF Event Ring Full Error"; 1147 case COMP_PARAMETER_ERROR: 1148 return "Parameter Error"; 1149 case COMP_BANDWIDTH_OVERRUN_ERROR: 1150 return "Bandwidth Overrun Error"; 1151 case COMP_CONTEXT_STATE_ERROR: 1152 return "Context State Error"; 1153 case COMP_NO_PING_RESPONSE_ERROR: 1154 return "No Ping Response Error"; 1155 case COMP_EVENT_RING_FULL_ERROR: 1156 return "Event Ring Full Error"; 1157 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1158 return "Incompatible Device Error"; 1159 case COMP_MISSED_SERVICE_ERROR: 1160 return "Missed Service Error"; 1161 case COMP_COMMAND_RING_STOPPED: 1162 return "Command Ring Stopped"; 1163 case COMP_COMMAND_ABORTED: 1164 return "Command Aborted"; 1165 case COMP_STOPPED: 1166 return "Stopped"; 1167 case COMP_STOPPED_LENGTH_INVALID: 1168 return "Stopped - Length Invalid"; 1169 case COMP_STOPPED_SHORT_PACKET: 1170 return "Stopped - Short Packet"; 1171 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1172 return "Max Exit Latency Too Large Error"; 1173 case COMP_ISOCH_BUFFER_OVERRUN: 1174 return "Isoch Buffer Overrun"; 1175 case COMP_EVENT_LOST_ERROR: 1176 return "Event Lost Error"; 1177 case COMP_UNDEFINED_ERROR: 1178 return "Undefined Error"; 1179 case COMP_INVALID_STREAM_ID_ERROR: 1180 return "Invalid Stream ID Error"; 1181 case COMP_SECONDARY_BANDWIDTH_ERROR: 1182 return "Secondary Bandwidth Error"; 1183 case COMP_SPLIT_TRANSACTION_ERROR: 1184 return "Split Transaction Error"; 1185 default: 1186 return "Unknown!!"; 1187 } 1188 } 1189 1190 struct xhci_link_trb { 1191 /* 64-bit segment pointer*/ 1192 __le64 segment_ptr; 1193 __le32 intr_target; 1194 __le32 control; 1195 }; 1196 1197 /* control bitfields */ 1198 #define LINK_TOGGLE (0x1<<1) 1199 1200 /* Command completion event TRB */ 1201 struct xhci_event_cmd { 1202 /* Pointer to command TRB, or the value passed by the event data trb */ 1203 __le64 cmd_trb; 1204 __le32 status; 1205 __le32 flags; 1206 }; 1207 1208 /* flags bitmasks */ 1209 1210 /* Address device - disable SetAddress */ 1211 #define TRB_BSR (1<<9) 1212 1213 /* Configure Endpoint - Deconfigure */ 1214 #define TRB_DC (1<<9) 1215 1216 /* Stop Ring - Transfer State Preserve */ 1217 #define TRB_TSP (1<<9) 1218 1219 enum xhci_ep_reset_type { 1220 EP_HARD_RESET, 1221 EP_SOFT_RESET, 1222 }; 1223 1224 /* Force Event */ 1225 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1226 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1227 1228 /* Set Latency Tolerance Value */ 1229 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1230 1231 /* Get Port Bandwidth */ 1232 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1233 1234 /* Force Header */ 1235 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1236 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1237 1238 enum xhci_setup_dev { 1239 SETUP_CONTEXT_ONLY, 1240 SETUP_CONTEXT_ADDRESS, 1241 }; 1242 1243 /* bits 16:23 are the virtual function ID */ 1244 /* bits 24:31 are the slot ID */ 1245 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1246 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1247 1248 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1249 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1250 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1251 1252 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1253 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1254 #define LAST_EP_INDEX 30 1255 1256 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1257 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1258 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1259 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1260 1261 /* Link TRB specific fields */ 1262 #define TRB_TC (1<<1) 1263 1264 /* Port Status Change Event TRB fields */ 1265 /* Port ID - bits 31:24 */ 1266 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1267 1268 #define EVENT_DATA (1 << 2) 1269 1270 /* Normal TRB fields */ 1271 /* transfer_len bitmasks - bits 0:16 */ 1272 #define TRB_LEN(p) ((p) & 0x1ffff) 1273 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1274 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1275 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1276 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1277 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1278 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1279 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1280 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1281 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1282 #define TRB_TBC(p) (((p) & 0x3) << 7) 1283 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1284 1285 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1286 #define TRB_CYCLE (1<<0) 1287 /* 1288 * Force next event data TRB to be evaluated before task switch. 1289 * Used to pass OS data back after a TD completes. 1290 */ 1291 #define TRB_ENT (1<<1) 1292 /* Interrupt on short packet */ 1293 #define TRB_ISP (1<<2) 1294 /* Set PCIe no snoop attribute */ 1295 #define TRB_NO_SNOOP (1<<3) 1296 /* Chain multiple TRBs into a TD */ 1297 #define TRB_CHAIN (1<<4) 1298 /* Interrupt on completion */ 1299 #define TRB_IOC (1<<5) 1300 /* The buffer pointer contains immediate data */ 1301 #define TRB_IDT (1<<6) 1302 /* TDs smaller than this might use IDT */ 1303 #define TRB_IDT_MAX_SIZE 8 1304 1305 /* Block Event Interrupt */ 1306 #define TRB_BEI (1<<9) 1307 1308 /* Control transfer TRB specific fields */ 1309 #define TRB_DIR_IN (1<<16) 1310 #define TRB_TX_TYPE(p) ((p) << 16) 1311 #define TRB_DATA_OUT 2 1312 #define TRB_DATA_IN 3 1313 1314 /* Isochronous TRB specific fields */ 1315 #define TRB_SIA (1<<31) 1316 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1317 1318 /* TRB cache size for xHC with TRB cache */ 1319 #define TRB_CACHE_SIZE_HS 8 1320 #define TRB_CACHE_SIZE_SS 16 1321 1322 struct xhci_generic_trb { 1323 __le32 field[4]; 1324 }; 1325 1326 union xhci_trb { 1327 struct xhci_link_trb link; 1328 struct xhci_transfer_event trans_event; 1329 struct xhci_event_cmd event_cmd; 1330 struct xhci_generic_trb generic; 1331 }; 1332 1333 /* TRB bit mask */ 1334 #define TRB_TYPE_BITMASK (0xfc00) 1335 #define TRB_TYPE(p) ((p) << 10) 1336 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1337 /* TRB type IDs */ 1338 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1339 #define TRB_NORMAL 1 1340 /* setup stage for control transfers */ 1341 #define TRB_SETUP 2 1342 /* data stage for control transfers */ 1343 #define TRB_DATA 3 1344 /* status stage for control transfers */ 1345 #define TRB_STATUS 4 1346 /* isoc transfers */ 1347 #define TRB_ISOC 5 1348 /* TRB for linking ring segments */ 1349 #define TRB_LINK 6 1350 #define TRB_EVENT_DATA 7 1351 /* Transfer Ring No-op (not for the command ring) */ 1352 #define TRB_TR_NOOP 8 1353 /* Command TRBs */ 1354 /* Enable Slot Command */ 1355 #define TRB_ENABLE_SLOT 9 1356 /* Disable Slot Command */ 1357 #define TRB_DISABLE_SLOT 10 1358 /* Address Device Command */ 1359 #define TRB_ADDR_DEV 11 1360 /* Configure Endpoint Command */ 1361 #define TRB_CONFIG_EP 12 1362 /* Evaluate Context Command */ 1363 #define TRB_EVAL_CONTEXT 13 1364 /* Reset Endpoint Command */ 1365 #define TRB_RESET_EP 14 1366 /* Stop Transfer Ring Command */ 1367 #define TRB_STOP_RING 15 1368 /* Set Transfer Ring Dequeue Pointer Command */ 1369 #define TRB_SET_DEQ 16 1370 /* Reset Device Command */ 1371 #define TRB_RESET_DEV 17 1372 /* Force Event Command (opt) */ 1373 #define TRB_FORCE_EVENT 18 1374 /* Negotiate Bandwidth Command (opt) */ 1375 #define TRB_NEG_BANDWIDTH 19 1376 /* Set Latency Tolerance Value Command (opt) */ 1377 #define TRB_SET_LT 20 1378 /* Get port bandwidth Command */ 1379 #define TRB_GET_BW 21 1380 /* Force Header Command - generate a transaction or link management packet */ 1381 #define TRB_FORCE_HEADER 22 1382 /* No-op Command - not for transfer rings */ 1383 #define TRB_CMD_NOOP 23 1384 /* TRB IDs 24-31 reserved */ 1385 /* Event TRBS */ 1386 /* Transfer Event */ 1387 #define TRB_TRANSFER 32 1388 /* Command Completion Event */ 1389 #define TRB_COMPLETION 33 1390 /* Port Status Change Event */ 1391 #define TRB_PORT_STATUS 34 1392 /* Bandwidth Request Event (opt) */ 1393 #define TRB_BANDWIDTH_EVENT 35 1394 /* Doorbell Event (opt) */ 1395 #define TRB_DOORBELL 36 1396 /* Host Controller Event */ 1397 #define TRB_HC_EVENT 37 1398 /* Device Notification Event - device sent function wake notification */ 1399 #define TRB_DEV_NOTE 38 1400 /* MFINDEX Wrap Event - microframe counter wrapped */ 1401 #define TRB_MFINDEX_WRAP 39 1402 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1403 #define TRB_VENDOR_DEFINED_LOW 48 1404 /* Nec vendor-specific command completion event. */ 1405 #define TRB_NEC_CMD_COMP 48 1406 /* Get NEC firmware revision. */ 1407 #define TRB_NEC_GET_FW 49 1408 1409 static inline const char *xhci_trb_type_string(u8 type) 1410 { 1411 switch (type) { 1412 case TRB_NORMAL: 1413 return "Normal"; 1414 case TRB_SETUP: 1415 return "Setup Stage"; 1416 case TRB_DATA: 1417 return "Data Stage"; 1418 case TRB_STATUS: 1419 return "Status Stage"; 1420 case TRB_ISOC: 1421 return "Isoch"; 1422 case TRB_LINK: 1423 return "Link"; 1424 case TRB_EVENT_DATA: 1425 return "Event Data"; 1426 case TRB_TR_NOOP: 1427 return "No-Op"; 1428 case TRB_ENABLE_SLOT: 1429 return "Enable Slot Command"; 1430 case TRB_DISABLE_SLOT: 1431 return "Disable Slot Command"; 1432 case TRB_ADDR_DEV: 1433 return "Address Device Command"; 1434 case TRB_CONFIG_EP: 1435 return "Configure Endpoint Command"; 1436 case TRB_EVAL_CONTEXT: 1437 return "Evaluate Context Command"; 1438 case TRB_RESET_EP: 1439 return "Reset Endpoint Command"; 1440 case TRB_STOP_RING: 1441 return "Stop Ring Command"; 1442 case TRB_SET_DEQ: 1443 return "Set TR Dequeue Pointer Command"; 1444 case TRB_RESET_DEV: 1445 return "Reset Device Command"; 1446 case TRB_FORCE_EVENT: 1447 return "Force Event Command"; 1448 case TRB_NEG_BANDWIDTH: 1449 return "Negotiate Bandwidth Command"; 1450 case TRB_SET_LT: 1451 return "Set Latency Tolerance Value Command"; 1452 case TRB_GET_BW: 1453 return "Get Port Bandwidth Command"; 1454 case TRB_FORCE_HEADER: 1455 return "Force Header Command"; 1456 case TRB_CMD_NOOP: 1457 return "No-Op Command"; 1458 case TRB_TRANSFER: 1459 return "Transfer Event"; 1460 case TRB_COMPLETION: 1461 return "Command Completion Event"; 1462 case TRB_PORT_STATUS: 1463 return "Port Status Change Event"; 1464 case TRB_BANDWIDTH_EVENT: 1465 return "Bandwidth Request Event"; 1466 case TRB_DOORBELL: 1467 return "Doorbell Event"; 1468 case TRB_HC_EVENT: 1469 return "Host Controller Event"; 1470 case TRB_DEV_NOTE: 1471 return "Device Notification Event"; 1472 case TRB_MFINDEX_WRAP: 1473 return "MFINDEX Wrap Event"; 1474 case TRB_NEC_CMD_COMP: 1475 return "NEC Command Completion Event"; 1476 case TRB_NEC_GET_FW: 1477 return "NET Get Firmware Revision Command"; 1478 default: 1479 return "UNKNOWN"; 1480 } 1481 } 1482 1483 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1484 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1485 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1486 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1487 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1488 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1489 1490 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1491 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1492 1493 /* 1494 * TRBS_PER_SEGMENT must be a multiple of 4, 1495 * since the command ring is 64-byte aligned. 1496 * It must also be greater than 16. 1497 */ 1498 #define TRBS_PER_SEGMENT 256 1499 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1500 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1501 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1502 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1503 /* TRB buffer pointers can't cross 64KB boundaries */ 1504 #define TRB_MAX_BUFF_SHIFT 16 1505 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1506 /* How much data is left before the 64KB boundary? */ 1507 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1508 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1509 #define MAX_SOFT_RETRY 3 1510 /* 1511 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1512 * XHCI_AVOID_BEI quirk is in use. 1513 */ 1514 #define AVOID_BEI_INTERVAL_MIN 8 1515 #define AVOID_BEI_INTERVAL_MAX 32 1516 1517 struct xhci_segment { 1518 union xhci_trb *trbs; 1519 /* private to HCD */ 1520 struct xhci_segment *next; 1521 unsigned int num; 1522 dma_addr_t dma; 1523 /* Max packet sized bounce buffer for td-fragmant alignment */ 1524 dma_addr_t bounce_dma; 1525 void *bounce_buf; 1526 unsigned int bounce_offs; 1527 unsigned int bounce_len; 1528 }; 1529 1530 enum xhci_cancelled_td_status { 1531 TD_DIRTY = 0, 1532 TD_HALTED, 1533 TD_CLEARING_CACHE, 1534 TD_CLEARED, 1535 }; 1536 1537 struct xhci_td { 1538 struct list_head td_list; 1539 struct list_head cancelled_td_list; 1540 int status; 1541 enum xhci_cancelled_td_status cancel_status; 1542 struct urb *urb; 1543 struct xhci_segment *start_seg; 1544 union xhci_trb *first_trb; 1545 union xhci_trb *last_trb; 1546 struct xhci_segment *last_trb_seg; 1547 struct xhci_segment *bounce_seg; 1548 /* actual_length of the URB has already been set */ 1549 bool urb_length_set; 1550 unsigned int num_trbs; 1551 }; 1552 1553 /* xHCI command default timeout value */ 1554 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1555 1556 /* command descriptor */ 1557 struct xhci_cd { 1558 struct xhci_command *command; 1559 union xhci_trb *cmd_trb; 1560 }; 1561 1562 enum xhci_ring_type { 1563 TYPE_CTRL = 0, 1564 TYPE_ISOC, 1565 TYPE_BULK, 1566 TYPE_INTR, 1567 TYPE_STREAM, 1568 TYPE_COMMAND, 1569 TYPE_EVENT, 1570 }; 1571 1572 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1573 { 1574 switch (type) { 1575 case TYPE_CTRL: 1576 return "CTRL"; 1577 case TYPE_ISOC: 1578 return "ISOC"; 1579 case TYPE_BULK: 1580 return "BULK"; 1581 case TYPE_INTR: 1582 return "INTR"; 1583 case TYPE_STREAM: 1584 return "STREAM"; 1585 case TYPE_COMMAND: 1586 return "CMD"; 1587 case TYPE_EVENT: 1588 return "EVENT"; 1589 } 1590 1591 return "UNKNOWN"; 1592 } 1593 1594 struct xhci_ring { 1595 struct xhci_segment *first_seg; 1596 struct xhci_segment *last_seg; 1597 union xhci_trb *enqueue; 1598 struct xhci_segment *enq_seg; 1599 union xhci_trb *dequeue; 1600 struct xhci_segment *deq_seg; 1601 struct list_head td_list; 1602 /* 1603 * Write the cycle state into the TRB cycle field to give ownership of 1604 * the TRB to the host controller (if we are the producer), or to check 1605 * if we own the TRB (if we are the consumer). See section 4.9.1. 1606 */ 1607 u32 cycle_state; 1608 unsigned int stream_id; 1609 unsigned int num_segs; 1610 unsigned int num_trbs_free; /* used only by xhci DbC */ 1611 unsigned int bounce_buf_len; 1612 enum xhci_ring_type type; 1613 bool last_td_was_short; 1614 struct radix_tree_root *trb_address_map; 1615 }; 1616 1617 struct xhci_erst_entry { 1618 /* 64-bit event ring segment address */ 1619 __le64 seg_addr; 1620 __le32 seg_size; 1621 /* Set to zero */ 1622 __le32 rsvd; 1623 }; 1624 1625 struct xhci_erst { 1626 struct xhci_erst_entry *entries; 1627 unsigned int num_entries; 1628 /* xhci->event_ring keeps track of segment dma addresses */ 1629 dma_addr_t erst_dma_addr; 1630 /* Num entries the ERST can contain */ 1631 unsigned int erst_size; 1632 }; 1633 1634 struct xhci_scratchpad { 1635 u64 *sp_array; 1636 dma_addr_t sp_dma; 1637 void **sp_buffers; 1638 }; 1639 1640 struct urb_priv { 1641 int num_tds; 1642 int num_tds_done; 1643 struct xhci_td td[] __counted_by(num_tds); 1644 }; 1645 1646 /* Reasonable limit for number of Event Ring segments (spec allows 32k) */ 1647 #define ERST_MAX_SEGS 2 1648 /* Poll every 60 seconds */ 1649 #define POLL_TIMEOUT 60 1650 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1651 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1652 /* XXX: Make these module parameters */ 1653 1654 struct s3_save { 1655 u32 command; 1656 u32 dev_nt; 1657 u64 dcbaa_ptr; 1658 u32 config_reg; 1659 }; 1660 1661 /* Use for lpm */ 1662 struct dev_info { 1663 u32 dev_id; 1664 struct list_head list; 1665 }; 1666 1667 struct xhci_bus_state { 1668 unsigned long bus_suspended; 1669 unsigned long next_statechange; 1670 1671 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1672 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1673 u32 port_c_suspend; 1674 u32 suspended_ports; 1675 u32 port_remote_wakeup; 1676 /* which ports have started to resume */ 1677 unsigned long resuming_ports; 1678 }; 1679 1680 struct xhci_interrupter { 1681 struct xhci_ring *event_ring; 1682 struct xhci_erst erst; 1683 struct xhci_intr_reg __iomem *ir_set; 1684 unsigned int intr_num; 1685 /* For interrupter registers save and restore over suspend/resume */ 1686 u32 s3_irq_pending; 1687 u32 s3_irq_control; 1688 u32 s3_erst_size; 1689 u64 s3_erst_base; 1690 u64 s3_erst_dequeue; 1691 }; 1692 /* 1693 * It can take up to 20 ms to transition from RExit to U0 on the 1694 * Intel Lynx Point LP xHCI host. 1695 */ 1696 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1697 struct xhci_port_cap { 1698 u32 *psi; /* array of protocol speed ID entries */ 1699 u8 psi_count; 1700 u8 psi_uid_count; 1701 u8 maj_rev; 1702 u8 min_rev; 1703 }; 1704 1705 struct xhci_port { 1706 __le32 __iomem *addr; 1707 int hw_portnum; 1708 int hcd_portnum; 1709 struct xhci_hub *rhub; 1710 struct xhci_port_cap *port_cap; 1711 unsigned int lpm_incapable:1; 1712 unsigned long resume_timestamp; 1713 bool rexit_active; 1714 struct completion rexit_done; 1715 struct completion u3exit_done; 1716 }; 1717 1718 struct xhci_hub { 1719 struct xhci_port **ports; 1720 unsigned int num_ports; 1721 struct usb_hcd *hcd; 1722 /* keep track of bus suspend info */ 1723 struct xhci_bus_state bus_state; 1724 /* supported prococol extended capabiliy values */ 1725 u8 maj_rev; 1726 u8 min_rev; 1727 }; 1728 1729 /* There is one xhci_hcd structure per controller */ 1730 struct xhci_hcd { 1731 struct usb_hcd *main_hcd; 1732 struct usb_hcd *shared_hcd; 1733 /* glue to PCI and HCD framework */ 1734 struct xhci_cap_regs __iomem *cap_regs; 1735 struct xhci_op_regs __iomem *op_regs; 1736 struct xhci_run_regs __iomem *run_regs; 1737 struct xhci_doorbell_array __iomem *dba; 1738 1739 /* Cached register copies of read-only HC data */ 1740 __u32 hcs_params1; 1741 __u32 hcs_params2; 1742 __u32 hcs_params3; 1743 __u32 hcc_params; 1744 __u32 hcc_params2; 1745 1746 spinlock_t lock; 1747 1748 /* packed release number */ 1749 u8 sbrn; 1750 u16 hci_version; 1751 u8 max_slots; 1752 u16 max_interrupters; 1753 u8 max_ports; 1754 u8 isoc_threshold; 1755 /* imod_interval in ns (I * 250ns) */ 1756 u32 imod_interval; 1757 u32 isoc_bei_interval; 1758 int event_ring_max; 1759 /* 4KB min, 128MB max */ 1760 int page_size; 1761 /* Valid values are 12 to 20, inclusive */ 1762 int page_shift; 1763 /* msi-x vectors */ 1764 int msix_count; 1765 /* optional clocks */ 1766 struct clk *clk; 1767 struct clk *reg_clk; 1768 /* optional reset controller */ 1769 struct reset_control *reset; 1770 /* data structures */ 1771 struct xhci_device_context_array *dcbaa; 1772 struct xhci_interrupter *interrupter; 1773 struct xhci_ring *cmd_ring; 1774 unsigned int cmd_ring_state; 1775 #define CMD_RING_STATE_RUNNING (1 << 0) 1776 #define CMD_RING_STATE_ABORTED (1 << 1) 1777 #define CMD_RING_STATE_STOPPED (1 << 2) 1778 struct list_head cmd_list; 1779 unsigned int cmd_ring_reserved_trbs; 1780 struct delayed_work cmd_timer; 1781 struct completion cmd_ring_stop_completion; 1782 struct xhci_command *current_cmd; 1783 1784 /* Scratchpad */ 1785 struct xhci_scratchpad *scratchpad; 1786 1787 /* slot enabling and address device helpers */ 1788 /* these are not thread safe so use mutex */ 1789 struct mutex mutex; 1790 /* Internal mirror of the HW's dcbaa */ 1791 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1792 /* For keeping track of bandwidth domains per roothub. */ 1793 struct xhci_root_port_bw_info *rh_bw; 1794 1795 /* DMA pools */ 1796 struct dma_pool *device_pool; 1797 struct dma_pool *segment_pool; 1798 struct dma_pool *small_streams_pool; 1799 struct dma_pool *medium_streams_pool; 1800 1801 /* Host controller watchdog timer structures */ 1802 unsigned int xhc_state; 1803 unsigned long run_graceperiod; 1804 struct s3_save s3; 1805 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1806 * 1807 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1808 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1809 * that sees this status (other than the timer that set it) should stop touching 1810 * hardware immediately. Interrupt handlers should return immediately when 1811 * they see this status (any time they drop and re-acquire xhci->lock). 1812 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1813 * putting the TD on the canceled list, etc. 1814 * 1815 * There are no reports of xHCI host controllers that display this issue. 1816 */ 1817 #define XHCI_STATE_DYING (1 << 0) 1818 #define XHCI_STATE_HALTED (1 << 1) 1819 #define XHCI_STATE_REMOVING (1 << 2) 1820 unsigned long long quirks; 1821 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1822 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1823 #define XHCI_NEC_HOST BIT_ULL(2) 1824 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1825 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1826 /* 1827 * Certain Intel host controllers have a limit to the number of endpoint 1828 * contexts they can handle. Ideally, they would signal that they can't handle 1829 * anymore endpoint contexts by returning a Resource Error for the Configure 1830 * Endpoint command, but they don't. Instead they expect software to keep track 1831 * of the number of active endpoints for them, across configure endpoint 1832 * commands, reset device commands, disable slot commands, and address device 1833 * commands. 1834 */ 1835 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1836 #define XHCI_BROKEN_MSI BIT_ULL(6) 1837 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1838 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1839 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1840 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) 1841 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1842 #define XHCI_INTEL_HOST BIT_ULL(12) 1843 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1844 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1845 #define XHCI_AVOID_BEI BIT_ULL(15) 1846 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1847 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1848 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1849 /* For controllers with a broken beyond repair streams implementation */ 1850 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1851 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1852 #define XHCI_MTK_HOST BIT_ULL(21) 1853 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1854 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1855 #define XHCI_MISSING_CAS BIT_ULL(24) 1856 /* For controller with a broken Port Disable implementation */ 1857 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1858 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1859 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1860 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1861 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1862 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1863 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1864 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1865 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1866 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1867 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1868 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) 1869 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1870 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1871 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1872 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1873 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1874 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1875 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1876 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1877 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) 1878 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1879 1880 unsigned int num_active_eps; 1881 unsigned int limit_active_eps; 1882 struct xhci_port *hw_ports; 1883 struct xhci_hub usb2_rhub; 1884 struct xhci_hub usb3_rhub; 1885 /* support xHCI 1.0 spec USB2 hardware LPM */ 1886 unsigned hw_lpm_support:1; 1887 /* Broken Suspend flag for SNPS Suspend resume issue */ 1888 unsigned broken_suspend:1; 1889 /* Indicates that omitting hcd is supported if root hub has no ports */ 1890 unsigned allow_single_roothub:1; 1891 /* cached usb2 extened protocol capabilites */ 1892 u32 *ext_caps; 1893 unsigned int num_ext_caps; 1894 /* cached extended protocol port capabilities */ 1895 struct xhci_port_cap *port_caps; 1896 unsigned int num_port_caps; 1897 /* Compliance Mode Recovery Data */ 1898 struct timer_list comp_mode_recovery_timer; 1899 u32 port_status_u0; 1900 u16 test_mode; 1901 /* Compliance Mode Timer Triggered every 2 seconds */ 1902 #define COMP_MODE_RCVRY_MSECS 2000 1903 1904 struct dentry *debugfs_root; 1905 struct dentry *debugfs_slots; 1906 struct list_head regset_list; 1907 1908 void *dbc; 1909 /* platform-specific data -- must come last */ 1910 unsigned long priv[] __aligned(sizeof(s64)); 1911 }; 1912 1913 /* Platform specific overrides to generic XHCI hc_driver ops */ 1914 struct xhci_driver_overrides { 1915 size_t extra_priv_size; 1916 int (*reset)(struct usb_hcd *hcd); 1917 int (*start)(struct usb_hcd *hcd); 1918 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1919 struct usb_host_endpoint *ep); 1920 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1921 struct usb_host_endpoint *ep); 1922 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1923 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1924 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1925 struct usb_tt *tt, gfp_t mem_flags); 1926 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1927 u16 wIndex, char *buf, u16 wLength); 1928 }; 1929 1930 #define XHCI_CFC_DELAY 10 1931 1932 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1933 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1934 { 1935 struct usb_hcd *primary_hcd; 1936 1937 if (usb_hcd_is_primary_hcd(hcd)) 1938 primary_hcd = hcd; 1939 else 1940 primary_hcd = hcd->primary_hcd; 1941 1942 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1943 } 1944 1945 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1946 { 1947 return xhci->main_hcd; 1948 } 1949 1950 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1951 { 1952 if (xhci->shared_hcd) 1953 return xhci->shared_hcd; 1954 1955 if (!xhci->usb2_rhub.num_ports) 1956 return xhci->main_hcd; 1957 1958 return NULL; 1959 } 1960 1961 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1962 { 1963 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1964 1965 return hcd == xhci_get_usb3_hcd(xhci); 1966 } 1967 1968 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1969 { 1970 return xhci->allow_single_roothub && 1971 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1972 } 1973 1974 #define xhci_dbg(xhci, fmt, args...) \ 1975 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1976 #define xhci_err(xhci, fmt, args...) \ 1977 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1978 #define xhci_warn(xhci, fmt, args...) \ 1979 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1980 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1981 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1982 #define xhci_info(xhci, fmt, args...) \ 1983 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1984 1985 /* 1986 * Registers should always be accessed with double word or quad word accesses. 1987 * 1988 * Some xHCI implementations may support 64-bit address pointers. Registers 1989 * with 64-bit address pointers should be written to with dword accesses by 1990 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1991 * xHCI implementations that do not support 64-bit address pointers will ignore 1992 * the high dword, and write order is irrelevant. 1993 */ 1994 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1995 __le64 __iomem *regs) 1996 { 1997 return lo_hi_readq(regs); 1998 } 1999 static inline void xhci_write_64(struct xhci_hcd *xhci, 2000 const u64 val, __le64 __iomem *regs) 2001 { 2002 lo_hi_writeq(val, regs); 2003 } 2004 2005 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 2006 { 2007 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 2008 } 2009 2010 /* xHCI debugging */ 2011 char *xhci_get_slot_state(struct xhci_hcd *xhci, 2012 struct xhci_container_ctx *ctx); 2013 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 2014 const char *fmt, ...); 2015 2016 /* xHCI memory management */ 2017 void xhci_mem_cleanup(struct xhci_hcd *xhci); 2018 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 2019 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 2020 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 2021 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 2022 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 2023 struct usb_device *udev); 2024 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 2025 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 2026 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 2027 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 2028 struct xhci_virt_device *virt_dev, 2029 int old_active_eps); 2030 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 2031 void xhci_update_bw_info(struct xhci_hcd *xhci, 2032 struct xhci_container_ctx *in_ctx, 2033 struct xhci_input_control_ctx *ctrl_ctx, 2034 struct xhci_virt_device *virt_dev); 2035 void xhci_endpoint_copy(struct xhci_hcd *xhci, 2036 struct xhci_container_ctx *in_ctx, 2037 struct xhci_container_ctx *out_ctx, 2038 unsigned int ep_index); 2039 void xhci_slot_copy(struct xhci_hcd *xhci, 2040 struct xhci_container_ctx *in_ctx, 2041 struct xhci_container_ctx *out_ctx); 2042 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 2043 struct usb_device *udev, struct usb_host_endpoint *ep, 2044 gfp_t mem_flags); 2045 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 2046 unsigned int num_segs, unsigned int cycle_state, 2047 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 2048 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 2049 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 2050 unsigned int num_trbs, gfp_t flags); 2051 void xhci_initialize_ring_info(struct xhci_ring *ring, 2052 unsigned int cycle_state); 2053 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 2054 struct xhci_virt_device *virt_dev, 2055 unsigned int ep_index); 2056 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 2057 unsigned int num_stream_ctxs, 2058 unsigned int num_streams, 2059 unsigned int max_packet, gfp_t flags); 2060 void xhci_free_stream_info(struct xhci_hcd *xhci, 2061 struct xhci_stream_info *stream_info); 2062 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 2063 struct xhci_ep_ctx *ep_ctx, 2064 struct xhci_stream_info *stream_info); 2065 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 2066 struct xhci_virt_ep *ep); 2067 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 2068 struct xhci_virt_device *virt_dev, bool drop_control_ep); 2069 struct xhci_ring *xhci_dma_to_transfer_ring( 2070 struct xhci_virt_ep *ep, 2071 u64 address); 2072 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2073 bool allocate_completion, gfp_t mem_flags); 2074 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 2075 bool allocate_completion, gfp_t mem_flags); 2076 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2077 void xhci_free_command(struct xhci_hcd *xhci, 2078 struct xhci_command *command); 2079 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 2080 int type, gfp_t flags); 2081 void xhci_free_container_ctx(struct xhci_hcd *xhci, 2082 struct xhci_container_ctx *ctx); 2083 2084 /* xHCI host controller glue */ 2085 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2086 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 2087 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, 2088 u32 mask, u32 done, int usec, unsigned int exit_state); 2089 void xhci_quiesce(struct xhci_hcd *xhci); 2090 int xhci_halt(struct xhci_hcd *xhci); 2091 int xhci_start(struct xhci_hcd *xhci); 2092 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 2093 int xhci_run(struct usb_hcd *hcd); 2094 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2095 void xhci_shutdown(struct usb_hcd *hcd); 2096 void xhci_stop(struct usb_hcd *hcd); 2097 void xhci_init_driver(struct hc_driver *drv, 2098 const struct xhci_driver_overrides *over); 2099 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2100 struct usb_host_endpoint *ep); 2101 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2102 struct usb_host_endpoint *ep); 2103 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2104 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2105 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 2106 struct usb_tt *tt, gfp_t mem_flags); 2107 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 2108 int xhci_ext_cap_init(struct xhci_hcd *xhci); 2109 2110 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2111 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg); 2112 2113 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2114 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2115 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2116 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2117 struct xhci_virt_device *virt_dev, 2118 struct usb_device *hdev, 2119 struct usb_tt *tt, gfp_t mem_flags); 2120 2121 /* xHCI ring, segment, TRB, and TD functions */ 2122 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2123 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2124 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2125 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2126 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2127 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2128 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2129 u32 trb_type, u32 slot_id); 2130 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2131 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2132 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2133 u32 field1, u32 field2, u32 field3, u32 field4); 2134 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2135 int slot_id, unsigned int ep_index, int suspend); 2136 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2137 int slot_id, unsigned int ep_index); 2138 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2139 int slot_id, unsigned int ep_index); 2140 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2141 int slot_id, unsigned int ep_index); 2142 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2143 struct urb *urb, int slot_id, unsigned int ep_index); 2144 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2145 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2146 bool command_must_succeed); 2147 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2148 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2149 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2150 int slot_id, unsigned int ep_index, 2151 enum xhci_ep_reset_type reset_type); 2152 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2153 u32 slot_id); 2154 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id, 2155 unsigned int ep_index, unsigned int stream_id, 2156 struct xhci_td *td); 2157 void xhci_stop_endpoint_command_watchdog(struct timer_list *t); 2158 void xhci_handle_command_timeout(struct work_struct *work); 2159 2160 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2161 unsigned int ep_index, unsigned int stream_id); 2162 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 2163 unsigned int slot_id, 2164 unsigned int ep_index); 2165 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2166 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 2167 unsigned int count_trbs(u64 addr, u64 len); 2168 2169 /* xHCI roothub code */ 2170 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 2171 u32 link_state); 2172 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 2173 u32 port_bit); 2174 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2175 char *buf, u16 wLength); 2176 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2177 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2178 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 2179 2180 void xhci_hc_died(struct xhci_hcd *xhci); 2181 2182 #ifdef CONFIG_PM 2183 int xhci_bus_suspend(struct usb_hcd *hcd); 2184 int xhci_bus_resume(struct usb_hcd *hcd); 2185 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 2186 #else 2187 #define xhci_bus_suspend NULL 2188 #define xhci_bus_resume NULL 2189 #define xhci_get_resuming_ports NULL 2190 #endif /* CONFIG_PM */ 2191 2192 u32 xhci_port_state_to_neutral(u32 state); 2193 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2194 u16 port); 2195 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2196 2197 /* xHCI contexts */ 2198 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2199 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2200 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2201 2202 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2203 unsigned int slot_id, unsigned int ep_index, 2204 unsigned int stream_id); 2205 2206 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2207 struct urb *urb) 2208 { 2209 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2210 xhci_get_endpoint_index(&urb->ep->desc), 2211 urb->stream_id); 2212 } 2213 2214 /* 2215 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2216 * them anyways as we where unable to find a device that matches the 2217 * constraints. 2218 */ 2219 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2220 { 2221 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2222 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2223 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2224 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2225 !urb->num_sgs) 2226 return true; 2227 2228 return false; 2229 } 2230 2231 static inline char *xhci_slot_state_string(u32 state) 2232 { 2233 switch (state) { 2234 case SLOT_STATE_ENABLED: 2235 return "enabled/disabled"; 2236 case SLOT_STATE_DEFAULT: 2237 return "default"; 2238 case SLOT_STATE_ADDRESSED: 2239 return "addressed"; 2240 case SLOT_STATE_CONFIGURED: 2241 return "configured"; 2242 default: 2243 return "reserved"; 2244 } 2245 } 2246 2247 static inline const char *xhci_decode_trb(char *str, size_t size, 2248 u32 field0, u32 field1, u32 field2, u32 field3) 2249 { 2250 int type = TRB_FIELD_TO_TYPE(field3); 2251 2252 switch (type) { 2253 case TRB_LINK: 2254 snprintf(str, size, 2255 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2256 field1, field0, GET_INTR_TARGET(field2), 2257 xhci_trb_type_string(type), 2258 field3 & TRB_IOC ? 'I' : 'i', 2259 field3 & TRB_CHAIN ? 'C' : 'c', 2260 field3 & TRB_TC ? 'T' : 't', 2261 field3 & TRB_CYCLE ? 'C' : 'c'); 2262 break; 2263 case TRB_TRANSFER: 2264 case TRB_COMPLETION: 2265 case TRB_PORT_STATUS: 2266 case TRB_BANDWIDTH_EVENT: 2267 case TRB_DOORBELL: 2268 case TRB_HC_EVENT: 2269 case TRB_DEV_NOTE: 2270 case TRB_MFINDEX_WRAP: 2271 snprintf(str, size, 2272 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2273 field1, field0, 2274 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2275 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2276 /* Macro decrements 1, maybe it shouldn't?!? */ 2277 TRB_TO_EP_INDEX(field3) + 1, 2278 xhci_trb_type_string(type), 2279 field3 & EVENT_DATA ? 'E' : 'e', 2280 field3 & TRB_CYCLE ? 'C' : 'c'); 2281 2282 break; 2283 case TRB_SETUP: 2284 snprintf(str, size, 2285 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2286 field0 & 0xff, 2287 (field0 & 0xff00) >> 8, 2288 (field0 & 0xff000000) >> 24, 2289 (field0 & 0xff0000) >> 16, 2290 (field1 & 0xff00) >> 8, 2291 field1 & 0xff, 2292 (field1 & 0xff000000) >> 16 | 2293 (field1 & 0xff0000) >> 16, 2294 TRB_LEN(field2), GET_TD_SIZE(field2), 2295 GET_INTR_TARGET(field2), 2296 xhci_trb_type_string(type), 2297 field3 & TRB_IDT ? 'I' : 'i', 2298 field3 & TRB_IOC ? 'I' : 'i', 2299 field3 & TRB_CYCLE ? 'C' : 'c'); 2300 break; 2301 case TRB_DATA: 2302 snprintf(str, size, 2303 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2304 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2305 GET_INTR_TARGET(field2), 2306 xhci_trb_type_string(type), 2307 field3 & TRB_IDT ? 'I' : 'i', 2308 field3 & TRB_IOC ? 'I' : 'i', 2309 field3 & TRB_CHAIN ? 'C' : 'c', 2310 field3 & TRB_NO_SNOOP ? 'S' : 's', 2311 field3 & TRB_ISP ? 'I' : 'i', 2312 field3 & TRB_ENT ? 'E' : 'e', 2313 field3 & TRB_CYCLE ? 'C' : 'c'); 2314 break; 2315 case TRB_STATUS: 2316 snprintf(str, size, 2317 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2318 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2319 GET_INTR_TARGET(field2), 2320 xhci_trb_type_string(type), 2321 field3 & TRB_IOC ? 'I' : 'i', 2322 field3 & TRB_CHAIN ? 'C' : 'c', 2323 field3 & TRB_ENT ? 'E' : 'e', 2324 field3 & TRB_CYCLE ? 'C' : 'c'); 2325 break; 2326 case TRB_NORMAL: 2327 case TRB_ISOC: 2328 case TRB_EVENT_DATA: 2329 case TRB_TR_NOOP: 2330 snprintf(str, size, 2331 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2332 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2333 GET_INTR_TARGET(field2), 2334 xhci_trb_type_string(type), 2335 field3 & TRB_BEI ? 'B' : 'b', 2336 field3 & TRB_IDT ? 'I' : 'i', 2337 field3 & TRB_IOC ? 'I' : 'i', 2338 field3 & TRB_CHAIN ? 'C' : 'c', 2339 field3 & TRB_NO_SNOOP ? 'S' : 's', 2340 field3 & TRB_ISP ? 'I' : 'i', 2341 field3 & TRB_ENT ? 'E' : 'e', 2342 field3 & TRB_CYCLE ? 'C' : 'c'); 2343 break; 2344 2345 case TRB_CMD_NOOP: 2346 case TRB_ENABLE_SLOT: 2347 snprintf(str, size, 2348 "%s: flags %c", 2349 xhci_trb_type_string(type), 2350 field3 & TRB_CYCLE ? 'C' : 'c'); 2351 break; 2352 case TRB_DISABLE_SLOT: 2353 case TRB_NEG_BANDWIDTH: 2354 snprintf(str, size, 2355 "%s: slot %d flags %c", 2356 xhci_trb_type_string(type), 2357 TRB_TO_SLOT_ID(field3), 2358 field3 & TRB_CYCLE ? 'C' : 'c'); 2359 break; 2360 case TRB_ADDR_DEV: 2361 snprintf(str, size, 2362 "%s: ctx %08x%08x slot %d flags %c:%c", 2363 xhci_trb_type_string(type), 2364 field1, field0, 2365 TRB_TO_SLOT_ID(field3), 2366 field3 & TRB_BSR ? 'B' : 'b', 2367 field3 & TRB_CYCLE ? 'C' : 'c'); 2368 break; 2369 case TRB_CONFIG_EP: 2370 snprintf(str, size, 2371 "%s: ctx %08x%08x slot %d flags %c:%c", 2372 xhci_trb_type_string(type), 2373 field1, field0, 2374 TRB_TO_SLOT_ID(field3), 2375 field3 & TRB_DC ? 'D' : 'd', 2376 field3 & TRB_CYCLE ? 'C' : 'c'); 2377 break; 2378 case TRB_EVAL_CONTEXT: 2379 snprintf(str, size, 2380 "%s: ctx %08x%08x slot %d flags %c", 2381 xhci_trb_type_string(type), 2382 field1, field0, 2383 TRB_TO_SLOT_ID(field3), 2384 field3 & TRB_CYCLE ? 'C' : 'c'); 2385 break; 2386 case TRB_RESET_EP: 2387 snprintf(str, size, 2388 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2389 xhci_trb_type_string(type), 2390 field1, field0, 2391 TRB_TO_SLOT_ID(field3), 2392 /* Macro decrements 1, maybe it shouldn't?!? */ 2393 TRB_TO_EP_INDEX(field3) + 1, 2394 field3 & TRB_TSP ? 'T' : 't', 2395 field3 & TRB_CYCLE ? 'C' : 'c'); 2396 break; 2397 case TRB_STOP_RING: 2398 snprintf(str, size, 2399 "%s: slot %d sp %d ep %d flags %c", 2400 xhci_trb_type_string(type), 2401 TRB_TO_SLOT_ID(field3), 2402 TRB_TO_SUSPEND_PORT(field3), 2403 /* Macro decrements 1, maybe it shouldn't?!? */ 2404 TRB_TO_EP_INDEX(field3) + 1, 2405 field3 & TRB_CYCLE ? 'C' : 'c'); 2406 break; 2407 case TRB_SET_DEQ: 2408 snprintf(str, size, 2409 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2410 xhci_trb_type_string(type), 2411 field1, field0, 2412 TRB_TO_STREAM_ID(field2), 2413 TRB_TO_SLOT_ID(field3), 2414 /* Macro decrements 1, maybe it shouldn't?!? */ 2415 TRB_TO_EP_INDEX(field3) + 1, 2416 field3 & TRB_CYCLE ? 'C' : 'c'); 2417 break; 2418 case TRB_RESET_DEV: 2419 snprintf(str, size, 2420 "%s: slot %d flags %c", 2421 xhci_trb_type_string(type), 2422 TRB_TO_SLOT_ID(field3), 2423 field3 & TRB_CYCLE ? 'C' : 'c'); 2424 break; 2425 case TRB_FORCE_EVENT: 2426 snprintf(str, size, 2427 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2428 xhci_trb_type_string(type), 2429 field1, field0, 2430 TRB_TO_VF_INTR_TARGET(field2), 2431 TRB_TO_VF_ID(field3), 2432 field3 & TRB_CYCLE ? 'C' : 'c'); 2433 break; 2434 case TRB_SET_LT: 2435 snprintf(str, size, 2436 "%s: belt %d flags %c", 2437 xhci_trb_type_string(type), 2438 TRB_TO_BELT(field3), 2439 field3 & TRB_CYCLE ? 'C' : 'c'); 2440 break; 2441 case TRB_GET_BW: 2442 snprintf(str, size, 2443 "%s: ctx %08x%08x slot %d speed %d flags %c", 2444 xhci_trb_type_string(type), 2445 field1, field0, 2446 TRB_TO_SLOT_ID(field3), 2447 TRB_TO_DEV_SPEED(field3), 2448 field3 & TRB_CYCLE ? 'C' : 'c'); 2449 break; 2450 case TRB_FORCE_HEADER: 2451 snprintf(str, size, 2452 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2453 xhci_trb_type_string(type), 2454 field2, field1, field0 & 0xffffffe0, 2455 TRB_TO_PACKET_TYPE(field0), 2456 TRB_TO_ROOTHUB_PORT(field3), 2457 field3 & TRB_CYCLE ? 'C' : 'c'); 2458 break; 2459 default: 2460 snprintf(str, size, 2461 "type '%s' -> raw %08x %08x %08x %08x", 2462 xhci_trb_type_string(type), 2463 field0, field1, field2, field3); 2464 } 2465 2466 return str; 2467 } 2468 2469 static inline const char *xhci_decode_ctrl_ctx(char *str, 2470 unsigned long drop, unsigned long add) 2471 { 2472 unsigned int bit; 2473 int ret = 0; 2474 2475 str[0] = '\0'; 2476 2477 if (drop) { 2478 ret = sprintf(str, "Drop:"); 2479 for_each_set_bit(bit, &drop, 32) 2480 ret += sprintf(str + ret, " %d%s", 2481 bit / 2, 2482 bit % 2 ? "in":"out"); 2483 ret += sprintf(str + ret, ", "); 2484 } 2485 2486 if (add) { 2487 ret += sprintf(str + ret, "Add:%s%s", 2488 (add & SLOT_FLAG) ? " slot":"", 2489 (add & EP0_FLAG) ? " ep0":""); 2490 add &= ~(SLOT_FLAG | EP0_FLAG); 2491 for_each_set_bit(bit, &add, 32) 2492 ret += sprintf(str + ret, " %d%s", 2493 bit / 2, 2494 bit % 2 ? "in":"out"); 2495 } 2496 return str; 2497 } 2498 2499 static inline const char *xhci_decode_slot_context(char *str, 2500 u32 info, u32 info2, u32 tt_info, u32 state) 2501 { 2502 u32 speed; 2503 u32 hub; 2504 u32 mtt; 2505 int ret = 0; 2506 2507 speed = info & DEV_SPEED; 2508 hub = info & DEV_HUB; 2509 mtt = info & DEV_MTT; 2510 2511 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2512 info & ROUTE_STRING_MASK, 2513 ({ char *s; 2514 switch (speed) { 2515 case SLOT_SPEED_FS: 2516 s = "full-speed"; 2517 break; 2518 case SLOT_SPEED_LS: 2519 s = "low-speed"; 2520 break; 2521 case SLOT_SPEED_HS: 2522 s = "high-speed"; 2523 break; 2524 case SLOT_SPEED_SS: 2525 s = "super-speed"; 2526 break; 2527 case SLOT_SPEED_SSP: 2528 s = "super-speed plus"; 2529 break; 2530 default: 2531 s = "UNKNOWN speed"; 2532 } s; }), 2533 mtt ? " multi-TT" : "", 2534 hub ? " Hub" : "", 2535 (info & LAST_CTX_MASK) >> 27, 2536 info2 & MAX_EXIT, 2537 DEVINFO_TO_ROOT_HUB_PORT(info2), 2538 DEVINFO_TO_MAX_PORTS(info2)); 2539 2540 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2541 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2542 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2543 state & DEV_ADDR_MASK, 2544 xhci_slot_state_string(GET_SLOT_STATE(state))); 2545 2546 return str; 2547 } 2548 2549 2550 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2551 { 2552 switch (portsc & PORT_PLS_MASK) { 2553 case XDEV_U0: 2554 return "U0"; 2555 case XDEV_U1: 2556 return "U1"; 2557 case XDEV_U2: 2558 return "U2"; 2559 case XDEV_U3: 2560 return "U3"; 2561 case XDEV_DISABLED: 2562 return "Disabled"; 2563 case XDEV_RXDETECT: 2564 return "RxDetect"; 2565 case XDEV_INACTIVE: 2566 return "Inactive"; 2567 case XDEV_POLLING: 2568 return "Polling"; 2569 case XDEV_RECOVERY: 2570 return "Recovery"; 2571 case XDEV_HOT_RESET: 2572 return "Hot Reset"; 2573 case XDEV_COMP_MODE: 2574 return "Compliance mode"; 2575 case XDEV_TEST_MODE: 2576 return "Test mode"; 2577 case XDEV_RESUME: 2578 return "Resume"; 2579 default: 2580 break; 2581 } 2582 return "Unknown"; 2583 } 2584 2585 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2586 { 2587 int ret; 2588 2589 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", 2590 portsc & PORT_POWER ? "Powered" : "Powered-off", 2591 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2592 portsc & PORT_PE ? "Enabled" : "Disabled", 2593 xhci_portsc_link_state_string(portsc), 2594 DEV_PORT_SPEED(portsc)); 2595 2596 if (portsc & PORT_OC) 2597 ret += sprintf(str + ret, "OverCurrent "); 2598 if (portsc & PORT_RESET) 2599 ret += sprintf(str + ret, "In-Reset "); 2600 2601 ret += sprintf(str + ret, "Change: "); 2602 if (portsc & PORT_CSC) 2603 ret += sprintf(str + ret, "CSC "); 2604 if (portsc & PORT_PEC) 2605 ret += sprintf(str + ret, "PEC "); 2606 if (portsc & PORT_WRC) 2607 ret += sprintf(str + ret, "WRC "); 2608 if (portsc & PORT_OCC) 2609 ret += sprintf(str + ret, "OCC "); 2610 if (portsc & PORT_RC) 2611 ret += sprintf(str + ret, "PRC "); 2612 if (portsc & PORT_PLC) 2613 ret += sprintf(str + ret, "PLC "); 2614 if (portsc & PORT_CEC) 2615 ret += sprintf(str + ret, "CEC "); 2616 if (portsc & PORT_CAS) 2617 ret += sprintf(str + ret, "CAS "); 2618 2619 ret += sprintf(str + ret, "Wake: "); 2620 if (portsc & PORT_WKCONN_E) 2621 ret += sprintf(str + ret, "WCE "); 2622 if (portsc & PORT_WKDISC_E) 2623 ret += sprintf(str + ret, "WDE "); 2624 if (portsc & PORT_WKOC_E) 2625 ret += sprintf(str + ret, "WOE "); 2626 2627 return str; 2628 } 2629 2630 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2631 { 2632 int ret = 0; 2633 2634 ret = sprintf(str, " 0x%08x", usbsts); 2635 2636 if (usbsts == ~(u32)0) 2637 return str; 2638 2639 if (usbsts & STS_HALT) 2640 ret += sprintf(str + ret, " HCHalted"); 2641 if (usbsts & STS_FATAL) 2642 ret += sprintf(str + ret, " HSE"); 2643 if (usbsts & STS_EINT) 2644 ret += sprintf(str + ret, " EINT"); 2645 if (usbsts & STS_PORT) 2646 ret += sprintf(str + ret, " PCD"); 2647 if (usbsts & STS_SAVE) 2648 ret += sprintf(str + ret, " SSS"); 2649 if (usbsts & STS_RESTORE) 2650 ret += sprintf(str + ret, " RSS"); 2651 if (usbsts & STS_SRE) 2652 ret += sprintf(str + ret, " SRE"); 2653 if (usbsts & STS_CNR) 2654 ret += sprintf(str + ret, " CNR"); 2655 if (usbsts & STS_HCE) 2656 ret += sprintf(str + ret, " HCE"); 2657 2658 return str; 2659 } 2660 2661 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2662 { 2663 u8 ep; 2664 u16 stream; 2665 int ret; 2666 2667 ep = (doorbell & 0xff); 2668 stream = doorbell >> 16; 2669 2670 if (slot == 0) { 2671 sprintf(str, "Command Ring %d", doorbell); 2672 return str; 2673 } 2674 ret = sprintf(str, "Slot %d ", slot); 2675 if (ep > 0 && ep < 32) 2676 ret = sprintf(str + ret, "ep%d%s", 2677 ep / 2, 2678 ep % 2 ? "in" : "out"); 2679 else if (ep == 0 || ep < 248) 2680 ret = sprintf(str + ret, "Reserved %d", ep); 2681 else 2682 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2683 if (stream) 2684 ret = sprintf(str + ret, " Stream %d", stream); 2685 2686 return str; 2687 } 2688 2689 static inline const char *xhci_ep_state_string(u8 state) 2690 { 2691 switch (state) { 2692 case EP_STATE_DISABLED: 2693 return "disabled"; 2694 case EP_STATE_RUNNING: 2695 return "running"; 2696 case EP_STATE_HALTED: 2697 return "halted"; 2698 case EP_STATE_STOPPED: 2699 return "stopped"; 2700 case EP_STATE_ERROR: 2701 return "error"; 2702 default: 2703 return "INVALID"; 2704 } 2705 } 2706 2707 static inline const char *xhci_ep_type_string(u8 type) 2708 { 2709 switch (type) { 2710 case ISOC_OUT_EP: 2711 return "Isoc OUT"; 2712 case BULK_OUT_EP: 2713 return "Bulk OUT"; 2714 case INT_OUT_EP: 2715 return "Int OUT"; 2716 case CTRL_EP: 2717 return "Ctrl"; 2718 case ISOC_IN_EP: 2719 return "Isoc IN"; 2720 case BULK_IN_EP: 2721 return "Bulk IN"; 2722 case INT_IN_EP: 2723 return "Int IN"; 2724 default: 2725 return "INVALID"; 2726 } 2727 } 2728 2729 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2730 u32 info2, u64 deq, u32 tx_info) 2731 { 2732 int ret; 2733 2734 u32 esit; 2735 u16 maxp; 2736 u16 avg; 2737 2738 u8 max_pstr; 2739 u8 ep_state; 2740 u8 interval; 2741 u8 ep_type; 2742 u8 burst; 2743 u8 cerr; 2744 u8 mult; 2745 2746 bool lsa; 2747 bool hid; 2748 2749 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2750 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2751 2752 ep_state = info & EP_STATE_MASK; 2753 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2754 interval = CTX_TO_EP_INTERVAL(info); 2755 mult = CTX_TO_EP_MULT(info) + 1; 2756 lsa = !!(info & EP_HAS_LSA); 2757 2758 cerr = (info2 & (3 << 1)) >> 1; 2759 ep_type = CTX_TO_EP_TYPE(info2); 2760 hid = !!(info2 & (1 << 7)); 2761 burst = CTX_TO_MAX_BURST(info2); 2762 maxp = MAX_PACKET_DECODED(info2); 2763 2764 avg = EP_AVG_TRB_LENGTH(tx_info); 2765 2766 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2767 xhci_ep_state_string(ep_state), mult, 2768 max_pstr, lsa ? "LSA " : ""); 2769 2770 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2771 (1 << interval) * 125, esit, cerr); 2772 2773 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2774 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2775 burst, maxp, deq); 2776 2777 ret += sprintf(str + ret, "avg trb len %d", avg); 2778 2779 return str; 2780 } 2781 2782 #endif /* __LINUX_XHCI_HCD_H */ 2783