1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 #include "xhci-port.h" 27 #include "xhci-caps.h" 28 29 /* max buffer size for trace and debug messages */ 30 #define XHCI_MSG_MAX 500 31 32 /* xHCI PCI Configuration Registers */ 33 #define XHCI_SBRN_OFFSET (0x60) 34 35 /* Max number of USB devices for any host controller - limit in section 6.1 */ 36 #define MAX_HC_SLOTS 256 37 /* Section 5.3.3 - MaxPorts */ 38 #define MAX_HC_PORTS 127 39 40 /* 41 * xHCI register interface. 42 * This corresponds to the eXtensible Host Controller Interface (xHCI) 43 * Revision 0.95 specification 44 */ 45 46 /** 47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 48 * @hc_capbase: length of the capabilities register and HC version number 49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 52 * @hcc_params: HCCPARAMS - Capability Parameters 53 * @db_off: DBOFF - Doorbell array offset 54 * @run_regs_off: RTSOFF - Runtime register space offset 55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 56 */ 57 struct xhci_cap_regs { 58 __le32 hc_capbase; 59 __le32 hcs_params1; 60 __le32 hcs_params2; 61 __le32 hcs_params3; 62 __le32 hcc_params; 63 __le32 db_off; 64 __le32 run_regs_off; 65 __le32 hcc_params2; /* xhci 1.1 */ 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* Number of registers per port */ 70 #define NUM_PORT_REGS 4 71 72 #define PORTSC 0 73 #define PORTPMSC 1 74 #define PORTLI 2 75 #define PORTHLPMC 3 76 77 /** 78 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 79 * @command: USBCMD - xHC command register 80 * @status: USBSTS - xHC status register 81 * @page_size: This indicates the page size that the host controller 82 * supports. If bit n is set, the HC supports a page size 83 * of 2^(n+12), up to a 128MB page size. 84 * 4K is the minimum page size. 85 * @cmd_ring: CRP - 64-bit Command Ring Pointer 86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 87 * @config_reg: CONFIG - Configure Register 88 * @port_status_base: PORTSCn - base address for Port Status and Control 89 * Each port has a Port Status and Control register, 90 * followed by a Port Power Management Status and Control 91 * register, a Port Link Info register, and a reserved 92 * register. 93 * @port_power_base: PORTPMSCn - base address for 94 * Port Power Management Status and Control 95 * @port_link_base: PORTLIn - base address for Port Link Info (current 96 * Link PM state and control) for USB 2.1 and USB 3.0 97 * devices. 98 */ 99 struct xhci_op_regs { 100 __le32 command; 101 __le32 status; 102 __le32 page_size; 103 __le32 reserved1; 104 __le32 reserved2; 105 __le32 dev_notification; 106 __le64 cmd_ring; 107 /* rsvd: offset 0x20-2F */ 108 __le32 reserved3[4]; 109 __le64 dcbaa_ptr; 110 __le32 config_reg; 111 /* rsvd: offset 0x3C-3FF */ 112 __le32 reserved4[241]; 113 /* port 1 registers, which serve as a base address for other ports */ 114 __le32 port_status_base; 115 __le32 port_power_base; 116 __le32 port_link_base; 117 __le32 reserved5; 118 /* registers for ports 2-255 */ 119 __le32 reserved6[NUM_PORT_REGS*254]; 120 }; 121 122 /* USBCMD - USB command - command bitmasks */ 123 /* start/stop HC execution - do not write unless HC is halted*/ 124 #define CMD_RUN XHCI_CMD_RUN 125 /* Reset HC - resets internal HC state machine and all registers (except 126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 127 * The xHCI driver must reinitialize the xHC after setting this bit. 128 */ 129 #define CMD_RESET (1 << 1) 130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 131 #define CMD_EIE XHCI_CMD_EIE 132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 133 #define CMD_HSEIE XHCI_CMD_HSEIE 134 /* bits 4:6 are reserved (and should be preserved on writes). */ 135 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 136 #define CMD_LRESET (1 << 7) 137 /* host controller save/restore state. */ 138 #define CMD_CSS (1 << 8) 139 #define CMD_CRS (1 << 9) 140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 141 #define CMD_EWE XHCI_CMD_EWE 142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 144 * '0' means the xHC can power it off if all ports are in the disconnect, 145 * disabled, or powered-off state. 146 */ 147 #define CMD_PM_INDEX (1 << 11) 148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 149 #define CMD_ETE (1 << 14) 150 /* bits 15:31 are reserved (and should be preserved on writes). */ 151 152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 153 #define XHCI_RESET_SHORT_USEC (250 * 1000) 154 155 /* IMAN - Interrupt Management Register */ 156 #define IMAN_IE (1 << 1) 157 #define IMAN_IP (1 << 0) 158 159 /* USBSTS - USB status - status bitmasks */ 160 /* HC not running - set to 1 when run/stop bit is cleared. */ 161 #define STS_HALT XHCI_STS_HALT 162 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 163 #define STS_FATAL (1 << 2) 164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 165 #define STS_EINT (1 << 3) 166 /* port change detect */ 167 #define STS_PORT (1 << 4) 168 /* bits 5:7 reserved and zeroed */ 169 /* save state status - '1' means xHC is saving state */ 170 #define STS_SAVE (1 << 8) 171 /* restore state status - '1' means xHC is restoring state */ 172 #define STS_RESTORE (1 << 9) 173 /* true: save or restore error */ 174 #define STS_SRE (1 << 10) 175 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 176 #define STS_CNR XHCI_STS_CNR 177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 178 #define STS_HCE (1 << 12) 179 /* bits 13:31 reserved and should be preserved */ 180 181 /* 182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 183 * Generate a device notification event when the HC sees a transaction with a 184 * notification type that matches a bit set in this bit field. 185 */ 186 #define DEV_NOTE_MASK (0xffff) 187 #define ENABLE_DEV_NOTE(x) (1 << (x)) 188 /* Most of the device notification types should only be used for debug. 189 * SW does need to pay attention to function wake notifications. 190 */ 191 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 192 193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 194 /* bit 0 is the command ring cycle state */ 195 /* stop ring operation after completion of the currently executing command */ 196 #define CMD_RING_PAUSE (1 << 1) 197 /* stop ring immediately - abort the currently executing command */ 198 #define CMD_RING_ABORT (1 << 2) 199 /* true: command ring is running */ 200 #define CMD_RING_RUNNING (1 << 3) 201 /* bits 4:5 reserved and should be preserved */ 202 /* Command Ring pointer - bit mask for the lower 32 bits. */ 203 #define CMD_RING_RSVD_BITS (0x3f) 204 205 /* CONFIG - Configure Register - config_reg bitmasks */ 206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 207 #define MAX_DEVS(p) ((p) & 0xff) 208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 209 #define CONFIG_U3E (1 << 8) 210 /* bit 9: Configuration Information Enable, xhci 1.1 */ 211 #define CONFIG_CIE (1 << 9) 212 /* bits 10:31 - reserved and should be preserved */ 213 214 /* bits 15:0 - HCD page shift bit */ 215 #define XHCI_PAGE_SIZE_MASK 0xffff 216 217 /** 218 * struct xhci_intr_reg - Interrupt Register Set 219 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 220 * interrupts and check for pending interrupts. 221 * @irq_control: IMOD - Interrupt Moderation Register. 222 * Used to throttle interrupts. 223 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 224 * @erst_base: ERST base address. 225 * @erst_dequeue: Event ring dequeue pointer. 226 * 227 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 228 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 229 * multiple segments of the same size. The HC places events on the ring and 230 * "updates the Cycle bit in the TRBs to indicate to software the current 231 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 232 * updates the dequeue pointer. 233 */ 234 struct xhci_intr_reg { 235 __le32 irq_pending; 236 __le32 irq_control; 237 __le32 erst_size; 238 __le32 rsvd; 239 __le64 erst_base; 240 __le64 erst_dequeue; 241 }; 242 243 /* irq_pending bitmasks */ 244 #define ER_IRQ_PENDING(p) ((p) & 0x1) 245 /* bits 2:31 need to be preserved */ 246 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 247 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 248 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 249 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 250 251 /* irq_control bitmasks */ 252 /* Minimum interval between interrupts (in 250ns intervals). The interval 253 * between interrupts will be longer if there are no events on the event ring. 254 * Default is 4000 (1 ms). 255 */ 256 #define ER_IRQ_INTERVAL_MASK (0xffff) 257 /* Counter used to count down the time to the next interrupt - HW use only */ 258 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 259 260 /* erst_size bitmasks */ 261 /* Preserve bits 16:31 of erst_size */ 262 #define ERST_SIZE_MASK (0xffff << 16) 263 264 /* erst_base bitmasks */ 265 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) 266 267 /* erst_dequeue bitmasks */ 268 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 269 * where the current dequeue pointer lies. This is an optional HW hint. 270 */ 271 #define ERST_DESI_MASK (0x7) 272 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 273 * a work queue (or delayed service routine)? 274 */ 275 #define ERST_EHB (1 << 3) 276 #define ERST_PTR_MASK (GENMASK_ULL(63, 4)) 277 278 /** 279 * struct xhci_run_regs 280 * @microframe_index: 281 * MFINDEX - current microframe number 282 * 283 * Section 5.5 Host Controller Runtime Registers: 284 * "Software should read and write these registers using only Dword (32 bit) 285 * or larger accesses" 286 */ 287 struct xhci_run_regs { 288 __le32 microframe_index; 289 __le32 rsvd[7]; 290 struct xhci_intr_reg ir_set[128]; 291 }; 292 293 /** 294 * struct doorbell_array 295 * 296 * Bits 0 - 7: Endpoint target 297 * Bits 8 - 15: RsvdZ 298 * Bits 16 - 31: Stream ID 299 * 300 * Section 5.6 301 */ 302 struct xhci_doorbell_array { 303 __le32 doorbell[256]; 304 }; 305 306 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 307 #define DB_VALUE_HOST 0x00000000 308 309 #define PLT_MASK (0x03 << 6) 310 #define PLT_SYM (0x00 << 6) 311 #define PLT_ASYM_RX (0x02 << 6) 312 #define PLT_ASYM_TX (0x03 << 6) 313 314 /** 315 * struct xhci_container_ctx 316 * @type: Type of context. Used to calculated offsets to contained contexts. 317 * @size: Size of the context data 318 * @bytes: The raw context data given to HW 319 * @dma: dma address of the bytes 320 * 321 * Represents either a Device or Input context. Holds a pointer to the raw 322 * memory used for the context (bytes) and dma address of it (dma). 323 */ 324 struct xhci_container_ctx { 325 unsigned type; 326 #define XHCI_CTX_TYPE_DEVICE 0x1 327 #define XHCI_CTX_TYPE_INPUT 0x2 328 329 int size; 330 331 u8 *bytes; 332 dma_addr_t dma; 333 }; 334 335 /** 336 * struct xhci_slot_ctx 337 * @dev_info: Route string, device speed, hub info, and last valid endpoint 338 * @dev_info2: Max exit latency for device number, root hub port number 339 * @tt_info: tt_info is used to construct split transaction tokens 340 * @dev_state: slot state and device address 341 * 342 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 343 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 344 * reserved at the end of the slot context for HC internal use. 345 */ 346 struct xhci_slot_ctx { 347 __le32 dev_info; 348 __le32 dev_info2; 349 __le32 tt_info; 350 __le32 dev_state; 351 /* offset 0x10 to 0x1f reserved for HC internal use */ 352 __le32 reserved[4]; 353 }; 354 355 /* dev_info bitmasks */ 356 /* Route String - 0:19 */ 357 #define ROUTE_STRING_MASK (0xfffff) 358 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 359 #define DEV_SPEED (0xf << 20) 360 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 361 /* bit 24 reserved */ 362 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 363 #define DEV_MTT (0x1 << 25) 364 /* Set if the device is a hub - bit 26 */ 365 #define DEV_HUB (0x1 << 26) 366 /* Index of the last valid endpoint context in this device context - 27:31 */ 367 #define LAST_CTX_MASK (0x1f << 27) 368 #define LAST_CTX(p) ((p) << 27) 369 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 370 #define SLOT_FLAG (1 << 0) 371 #define EP0_FLAG (1 << 1) 372 373 /* dev_info2 bitmasks */ 374 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 375 #define MAX_EXIT (0xffff) 376 /* Root hub port number that is needed to access the USB device */ 377 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 378 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 379 /* Maximum number of ports under a hub device */ 380 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 381 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 382 383 /* tt_info bitmasks */ 384 /* 385 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 386 * The Slot ID of the hub that isolates the high speed signaling from 387 * this low or full-speed device. '0' if attached to root hub port. 388 */ 389 #define TT_SLOT (0xff) 390 /* 391 * The number of the downstream facing port of the high-speed hub 392 * '0' if the device is not low or full speed. 393 */ 394 #define TT_PORT (0xff << 8) 395 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 396 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 397 398 /* dev_state bitmasks */ 399 /* USB device address - assigned by the HC */ 400 #define DEV_ADDR_MASK (0xff) 401 /* bits 8:26 reserved */ 402 /* Slot state */ 403 #define SLOT_STATE (0x1f << 27) 404 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 405 406 #define SLOT_STATE_DISABLED 0 407 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 408 #define SLOT_STATE_DEFAULT 1 409 #define SLOT_STATE_ADDRESSED 2 410 #define SLOT_STATE_CONFIGURED 3 411 412 /** 413 * struct xhci_ep_ctx 414 * @ep_info: endpoint state, streams, mult, and interval information. 415 * @ep_info2: information on endpoint type, max packet size, max burst size, 416 * error count, and whether the HC will force an event for all 417 * transactions. 418 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 419 * defines one stream, this points to the endpoint transfer ring. 420 * Otherwise, it points to a stream context array, which has a 421 * ring pointer for each flow. 422 * @tx_info: 423 * Average TRB lengths for the endpoint ring and 424 * max payload within an Endpoint Service Interval Time (ESIT). 425 * 426 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 427 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 428 * reserved at the end of the endpoint context for HC internal use. 429 */ 430 struct xhci_ep_ctx { 431 __le32 ep_info; 432 __le32 ep_info2; 433 __le64 deq; 434 __le32 tx_info; 435 /* offset 0x14 - 0x1f reserved for HC internal use */ 436 __le32 reserved[3]; 437 }; 438 439 /* ep_info bitmasks */ 440 /* 441 * Endpoint State - bits 0:2 442 * 0 - disabled 443 * 1 - running 444 * 2 - halted due to halt condition - ok to manipulate endpoint ring 445 * 3 - stopped 446 * 4 - TRB error 447 * 5-7 - reserved 448 */ 449 #define EP_STATE_MASK (0x7) 450 #define EP_STATE_DISABLED 0 451 #define EP_STATE_RUNNING 1 452 #define EP_STATE_HALTED 2 453 #define EP_STATE_STOPPED 3 454 #define EP_STATE_ERROR 4 455 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 456 457 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 458 #define EP_MULT(p) (((p) & 0x3) << 8) 459 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 460 /* bits 10:14 are Max Primary Streams */ 461 /* bit 15 is Linear Stream Array */ 462 /* Interval - period between requests to an endpoint - 125u increments. */ 463 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 464 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 465 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 466 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 467 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 468 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 469 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 470 #define EP_HAS_LSA (1 << 15) 471 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 472 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 473 474 /* ep_info2 bitmasks */ 475 /* 476 * Force Event - generate transfer events for all TRBs for this endpoint 477 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 478 */ 479 #define FORCE_EVENT (0x1) 480 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 481 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 482 #define EP_TYPE(p) ((p) << 3) 483 #define ISOC_OUT_EP 1 484 #define BULK_OUT_EP 2 485 #define INT_OUT_EP 3 486 #define CTRL_EP 4 487 #define ISOC_IN_EP 5 488 #define BULK_IN_EP 6 489 #define INT_IN_EP 7 490 /* bit 6 reserved */ 491 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 492 #define MAX_BURST(p) (((p)&0xff) << 8) 493 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 494 #define MAX_PACKET(p) (((p)&0xffff) << 16) 495 #define MAX_PACKET_MASK (0xffff << 16) 496 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 497 498 /* tx_info bitmasks */ 499 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 500 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 501 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 502 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 503 504 /* deq bitmasks */ 505 #define EP_CTX_CYCLE_MASK (1 << 0) 506 #define SCTX_DEQ_MASK (~0xfL) 507 508 509 /** 510 * struct xhci_input_control_context 511 * Input control context; see section 6.2.5. 512 * 513 * @drop_context: set the bit of the endpoint context you want to disable 514 * @add_context: set the bit of the endpoint context you want to enable 515 */ 516 struct xhci_input_control_ctx { 517 __le32 drop_flags; 518 __le32 add_flags; 519 __le32 rsvd2[6]; 520 }; 521 522 #define EP_IS_ADDED(ctrl_ctx, i) \ 523 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 524 #define EP_IS_DROPPED(ctrl_ctx, i) \ 525 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 526 527 /* Represents everything that is needed to issue a command on the command ring. 528 * It's useful to pre-allocate these for commands that cannot fail due to 529 * out-of-memory errors, like freeing streams. 530 */ 531 struct xhci_command { 532 /* Input context for changing device state */ 533 struct xhci_container_ctx *in_ctx; 534 u32 status; 535 u32 comp_param; 536 int slot_id; 537 /* If completion is null, no one is waiting on this command 538 * and the structure can be freed after the command completes. 539 */ 540 struct completion *completion; 541 union xhci_trb *command_trb; 542 struct list_head cmd_list; 543 /* xHCI command response timeout in milliseconds */ 544 unsigned int timeout_ms; 545 }; 546 547 /* drop context bitmasks */ 548 #define DROP_EP(x) (0x1 << x) 549 /* add context bitmasks */ 550 #define ADD_EP(x) (0x1 << x) 551 552 struct xhci_stream_ctx { 553 /* 64-bit stream ring address, cycle state, and stream type */ 554 __le64 stream_ring; 555 /* offset 0x14 - 0x1f reserved for HC internal use */ 556 __le32 reserved[2]; 557 }; 558 559 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 560 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 561 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 562 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 563 #define SCT_SEC_TR 0 564 /* Primary stream array type, dequeue pointer is to a transfer ring */ 565 #define SCT_PRI_TR 1 566 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 567 #define SCT_SSA_8 2 568 #define SCT_SSA_16 3 569 #define SCT_SSA_32 4 570 #define SCT_SSA_64 5 571 #define SCT_SSA_128 6 572 #define SCT_SSA_256 7 573 574 /* Assume no secondary streams for now */ 575 struct xhci_stream_info { 576 struct xhci_ring **stream_rings; 577 /* Number of streams, including stream 0 (which drivers can't use) */ 578 unsigned int num_streams; 579 /* The stream context array may be bigger than 580 * the number of streams the driver asked for 581 */ 582 struct xhci_stream_ctx *stream_ctx_array; 583 unsigned int num_stream_ctxs; 584 dma_addr_t ctx_array_dma; 585 /* For mapping physical TRB addresses to segments in stream rings */ 586 struct radix_tree_root trb_address_map; 587 struct xhci_command *free_streams_command; 588 }; 589 590 #define SMALL_STREAM_ARRAY_SIZE 256 591 #define MEDIUM_STREAM_ARRAY_SIZE 1024 592 593 /* Some Intel xHCI host controllers need software to keep track of the bus 594 * bandwidth. Keep track of endpoint info here. Each root port is allocated 595 * the full bus bandwidth. We must also treat TTs (including each port under a 596 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 597 * (DMI) also limits the total bandwidth (across all domains) that can be used. 598 */ 599 struct xhci_bw_info { 600 /* ep_interval is zero-based */ 601 unsigned int ep_interval; 602 /* mult and num_packets are one-based */ 603 unsigned int mult; 604 unsigned int num_packets; 605 unsigned int max_packet_size; 606 unsigned int max_esit_payload; 607 unsigned int type; 608 }; 609 610 /* "Block" sizes in bytes the hardware uses for different device speeds. 611 * The logic in this part of the hardware limits the number of bits the hardware 612 * can use, so must represent bandwidth in a less precise manner to mimic what 613 * the scheduler hardware computes. 614 */ 615 #define FS_BLOCK 1 616 #define HS_BLOCK 4 617 #define SS_BLOCK 16 618 #define DMI_BLOCK 32 619 620 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 621 * with each byte transferred. SuperSpeed devices have an initial overhead to 622 * set up bursts. These are in blocks, see above. LS overhead has already been 623 * translated into FS blocks. 624 */ 625 #define DMI_OVERHEAD 8 626 #define DMI_OVERHEAD_BURST 4 627 #define SS_OVERHEAD 8 628 #define SS_OVERHEAD_BURST 32 629 #define HS_OVERHEAD 26 630 #define FS_OVERHEAD 20 631 #define LS_OVERHEAD 128 632 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 633 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 634 * of overhead associated with split transfers crossing microframe boundaries. 635 * 31 blocks is pure protocol overhead. 636 */ 637 #define TT_HS_OVERHEAD (31 + 94) 638 #define TT_DMI_OVERHEAD (25 + 12) 639 640 /* Bandwidth limits in blocks */ 641 #define FS_BW_LIMIT 1285 642 #define TT_BW_LIMIT 1320 643 #define HS_BW_LIMIT 1607 644 #define SS_BW_LIMIT_IN 3906 645 #define DMI_BW_LIMIT_IN 3906 646 #define SS_BW_LIMIT_OUT 3906 647 #define DMI_BW_LIMIT_OUT 3906 648 649 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 650 #define FS_BW_RESERVED 10 651 #define HS_BW_RESERVED 20 652 #define SS_BW_RESERVED 10 653 654 struct xhci_virt_ep { 655 struct xhci_virt_device *vdev; /* parent */ 656 unsigned int ep_index; 657 struct xhci_ring *ring; 658 /* Related to endpoints that are configured to use stream IDs only */ 659 struct xhci_stream_info *stream_info; 660 /* Temporary storage in case the configure endpoint command fails and we 661 * have to restore the device state to the previous state 662 */ 663 struct xhci_ring *new_ring; 664 unsigned int err_count; 665 unsigned int ep_state; 666 #define SET_DEQ_PENDING (1 << 0) 667 #define EP_HALTED (1 << 1) /* Halted host ep handling */ 668 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 669 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 670 #define EP_GETTING_STREAMS (1 << 3) 671 #define EP_HAS_STREAMS (1 << 4) 672 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 673 #define EP_GETTING_NO_STREAMS (1 << 5) 674 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 675 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 676 /* usb_hub_clear_tt_buffer is in progress */ 677 #define EP_CLEARING_TT (1 << 8) 678 #define EP_STALLED (1 << 9) /* For stall handling */ 679 /* ---- Related to URB cancellation ---- */ 680 struct list_head cancelled_td_list; 681 struct xhci_hcd *xhci; 682 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 683 * command. We'll need to update the ring's dequeue segment and dequeue 684 * pointer after the command completes. 685 */ 686 struct xhci_segment *queued_deq_seg; 687 union xhci_trb *queued_deq_ptr; 688 /* 689 * Sometimes the xHC can not process isochronous endpoint ring quickly 690 * enough, and it will miss some isoc tds on the ring and generate 691 * a Missed Service Error Event. 692 * Set skip flag when receive a Missed Service Error Event and 693 * process the missed tds on the endpoint ring. 694 */ 695 bool skip; 696 /* Bandwidth checking storage */ 697 struct xhci_bw_info bw_info; 698 struct list_head bw_endpoint_list; 699 unsigned long stop_time; 700 /* Isoch Frame ID checking storage */ 701 int next_frame_id; 702 /* Use new Isoch TRB layout needed for extended TBC support */ 703 bool use_extended_tbc; 704 }; 705 706 enum xhci_overhead_type { 707 LS_OVERHEAD_TYPE = 0, 708 FS_OVERHEAD_TYPE, 709 HS_OVERHEAD_TYPE, 710 }; 711 712 struct xhci_interval_bw { 713 unsigned int num_packets; 714 /* Sorted by max packet size. 715 * Head of the list is the greatest max packet size. 716 */ 717 struct list_head endpoints; 718 /* How many endpoints of each speed are present. */ 719 unsigned int overhead[3]; 720 }; 721 722 #define XHCI_MAX_INTERVAL 16 723 724 struct xhci_interval_bw_table { 725 unsigned int interval0_esit_payload; 726 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 727 /* Includes reserved bandwidth for async endpoints */ 728 unsigned int bw_used; 729 unsigned int ss_bw_in; 730 unsigned int ss_bw_out; 731 }; 732 733 #define EP_CTX_PER_DEV 31 734 735 struct xhci_virt_device { 736 int slot_id; 737 struct usb_device *udev; 738 /* 739 * Commands to the hardware are passed an "input context" that 740 * tells the hardware what to change in its data structures. 741 * The hardware will return changes in an "output context" that 742 * software must allocate for the hardware. We need to keep 743 * track of input and output contexts separately because 744 * these commands might fail and we don't trust the hardware. 745 */ 746 struct xhci_container_ctx *out_ctx; 747 /* Used for addressing devices and configuration changes */ 748 struct xhci_container_ctx *in_ctx; 749 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 750 struct xhci_port *rhub_port; 751 struct xhci_interval_bw_table *bw_table; 752 struct xhci_tt_bw_info *tt_info; 753 /* 754 * flags for state tracking based on events and issued commands. 755 * Software can not rely on states from output contexts because of 756 * latency between events and xHC updating output context values. 757 * See xhci 1.1 section 4.8.3 for more details 758 */ 759 unsigned long flags; 760 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 761 762 /* The current max exit latency for the enabled USB3 link states. */ 763 u16 current_mel; 764 /* Used for the debugfs interfaces. */ 765 void *debugfs_private; 766 }; 767 768 /* 769 * For each roothub, keep track of the bandwidth information for each periodic 770 * interval. 771 * 772 * If a high speed hub is attached to the roothub, each TT associated with that 773 * hub is a separate bandwidth domain. The interval information for the 774 * endpoints on the devices under that TT will appear in the TT structure. 775 */ 776 struct xhci_root_port_bw_info { 777 struct list_head tts; 778 unsigned int num_active_tts; 779 struct xhci_interval_bw_table bw_table; 780 }; 781 782 struct xhci_tt_bw_info { 783 struct list_head tt_list; 784 int slot_id; 785 int ttport; 786 struct xhci_interval_bw_table bw_table; 787 int active_eps; 788 }; 789 790 791 /** 792 * struct xhci_device_context_array 793 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 794 */ 795 struct xhci_device_context_array { 796 /* 64-bit device addresses; we only write 32-bit addresses */ 797 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 798 /* private xHCD pointers */ 799 dma_addr_t dma; 800 }; 801 /* TODO: write function to set the 64-bit device DMA address */ 802 /* 803 * TODO: change this to be dynamically sized at HC mem init time since the HC 804 * might not be able to handle the maximum number of devices possible. 805 */ 806 807 808 struct xhci_transfer_event { 809 /* 64-bit buffer address, or immediate data */ 810 __le64 buffer; 811 __le32 transfer_len; 812 /* This field is interpreted differently based on the type of TRB */ 813 __le32 flags; 814 }; 815 816 /* Transfer event flags bitfield, also for select command completion events */ 817 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 818 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 819 820 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 821 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 822 823 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 824 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 825 826 /* Transfer event TRB length bit mask */ 827 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 828 829 /* Completion Code - only applicable for some types of TRBs */ 830 #define COMP_CODE_MASK (0xff << 24) 831 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 832 #define COMP_INVALID 0 833 #define COMP_SUCCESS 1 834 #define COMP_DATA_BUFFER_ERROR 2 835 #define COMP_BABBLE_DETECTED_ERROR 3 836 #define COMP_USB_TRANSACTION_ERROR 4 837 #define COMP_TRB_ERROR 5 838 #define COMP_STALL_ERROR 6 839 #define COMP_RESOURCE_ERROR 7 840 #define COMP_BANDWIDTH_ERROR 8 841 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 842 #define COMP_INVALID_STREAM_TYPE_ERROR 10 843 #define COMP_SLOT_NOT_ENABLED_ERROR 11 844 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 845 #define COMP_SHORT_PACKET 13 846 #define COMP_RING_UNDERRUN 14 847 #define COMP_RING_OVERRUN 15 848 #define COMP_VF_EVENT_RING_FULL_ERROR 16 849 #define COMP_PARAMETER_ERROR 17 850 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 851 #define COMP_CONTEXT_STATE_ERROR 19 852 #define COMP_NO_PING_RESPONSE_ERROR 20 853 #define COMP_EVENT_RING_FULL_ERROR 21 854 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 855 #define COMP_MISSED_SERVICE_ERROR 23 856 #define COMP_COMMAND_RING_STOPPED 24 857 #define COMP_COMMAND_ABORTED 25 858 #define COMP_STOPPED 26 859 #define COMP_STOPPED_LENGTH_INVALID 27 860 #define COMP_STOPPED_SHORT_PACKET 28 861 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 862 #define COMP_ISOCH_BUFFER_OVERRUN 31 863 #define COMP_EVENT_LOST_ERROR 32 864 #define COMP_UNDEFINED_ERROR 33 865 #define COMP_INVALID_STREAM_ID_ERROR 34 866 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 867 #define COMP_SPLIT_TRANSACTION_ERROR 36 868 869 static inline const char *xhci_trb_comp_code_string(u8 status) 870 { 871 switch (status) { 872 case COMP_INVALID: 873 return "Invalid"; 874 case COMP_SUCCESS: 875 return "Success"; 876 case COMP_DATA_BUFFER_ERROR: 877 return "Data Buffer Error"; 878 case COMP_BABBLE_DETECTED_ERROR: 879 return "Babble Detected"; 880 case COMP_USB_TRANSACTION_ERROR: 881 return "USB Transaction Error"; 882 case COMP_TRB_ERROR: 883 return "TRB Error"; 884 case COMP_STALL_ERROR: 885 return "Stall Error"; 886 case COMP_RESOURCE_ERROR: 887 return "Resource Error"; 888 case COMP_BANDWIDTH_ERROR: 889 return "Bandwidth Error"; 890 case COMP_NO_SLOTS_AVAILABLE_ERROR: 891 return "No Slots Available Error"; 892 case COMP_INVALID_STREAM_TYPE_ERROR: 893 return "Invalid Stream Type Error"; 894 case COMP_SLOT_NOT_ENABLED_ERROR: 895 return "Slot Not Enabled Error"; 896 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 897 return "Endpoint Not Enabled Error"; 898 case COMP_SHORT_PACKET: 899 return "Short Packet"; 900 case COMP_RING_UNDERRUN: 901 return "Ring Underrun"; 902 case COMP_RING_OVERRUN: 903 return "Ring Overrun"; 904 case COMP_VF_EVENT_RING_FULL_ERROR: 905 return "VF Event Ring Full Error"; 906 case COMP_PARAMETER_ERROR: 907 return "Parameter Error"; 908 case COMP_BANDWIDTH_OVERRUN_ERROR: 909 return "Bandwidth Overrun Error"; 910 case COMP_CONTEXT_STATE_ERROR: 911 return "Context State Error"; 912 case COMP_NO_PING_RESPONSE_ERROR: 913 return "No Ping Response Error"; 914 case COMP_EVENT_RING_FULL_ERROR: 915 return "Event Ring Full Error"; 916 case COMP_INCOMPATIBLE_DEVICE_ERROR: 917 return "Incompatible Device Error"; 918 case COMP_MISSED_SERVICE_ERROR: 919 return "Missed Service Error"; 920 case COMP_COMMAND_RING_STOPPED: 921 return "Command Ring Stopped"; 922 case COMP_COMMAND_ABORTED: 923 return "Command Aborted"; 924 case COMP_STOPPED: 925 return "Stopped"; 926 case COMP_STOPPED_LENGTH_INVALID: 927 return "Stopped - Length Invalid"; 928 case COMP_STOPPED_SHORT_PACKET: 929 return "Stopped - Short Packet"; 930 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 931 return "Max Exit Latency Too Large Error"; 932 case COMP_ISOCH_BUFFER_OVERRUN: 933 return "Isoch Buffer Overrun"; 934 case COMP_EVENT_LOST_ERROR: 935 return "Event Lost Error"; 936 case COMP_UNDEFINED_ERROR: 937 return "Undefined Error"; 938 case COMP_INVALID_STREAM_ID_ERROR: 939 return "Invalid Stream ID Error"; 940 case COMP_SECONDARY_BANDWIDTH_ERROR: 941 return "Secondary Bandwidth Error"; 942 case COMP_SPLIT_TRANSACTION_ERROR: 943 return "Split Transaction Error"; 944 default: 945 return "Unknown!!"; 946 } 947 } 948 949 struct xhci_link_trb { 950 /* 64-bit segment pointer*/ 951 __le64 segment_ptr; 952 __le32 intr_target; 953 __le32 control; 954 }; 955 956 /* control bitfields */ 957 #define LINK_TOGGLE (0x1<<1) 958 959 /* Command completion event TRB */ 960 struct xhci_event_cmd { 961 /* Pointer to command TRB, or the value passed by the event data trb */ 962 __le64 cmd_trb; 963 __le32 status; 964 __le32 flags; 965 }; 966 967 /* status bitmasks */ 968 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 969 970 /* Address device - disable SetAddress */ 971 #define TRB_BSR (1<<9) 972 973 /* Configure Endpoint - Deconfigure */ 974 #define TRB_DC (1<<9) 975 976 /* Stop Ring - Transfer State Preserve */ 977 #define TRB_TSP (1<<9) 978 979 enum xhci_ep_reset_type { 980 EP_HARD_RESET, 981 EP_SOFT_RESET, 982 }; 983 984 /* Force Event */ 985 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 986 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 987 988 /* Set Latency Tolerance Value */ 989 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 990 991 /* Get Port Bandwidth */ 992 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 993 994 /* Force Header */ 995 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 996 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 997 998 enum xhci_setup_dev { 999 SETUP_CONTEXT_ONLY, 1000 SETUP_CONTEXT_ADDRESS, 1001 }; 1002 1003 /* bits 16:23 are the virtual function ID */ 1004 /* bits 24:31 are the slot ID */ 1005 1006 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1007 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1008 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1009 #define LAST_EP_INDEX 30 1010 1011 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1012 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1013 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1014 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1015 1016 /* Link TRB specific fields */ 1017 #define TRB_TC (1<<1) 1018 1019 /* Port Status Change Event TRB fields */ 1020 /* Port ID - bits 31:24 */ 1021 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1022 1023 #define EVENT_DATA (1 << 2) 1024 1025 /* Normal TRB fields */ 1026 /* transfer_len bitmasks - bits 0:16 */ 1027 #define TRB_LEN(p) ((p) & 0x1ffff) 1028 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1029 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1030 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1031 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1032 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1033 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1034 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1035 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1036 1037 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1038 #define TRB_CYCLE (1<<0) 1039 /* 1040 * Force next event data TRB to be evaluated before task switch. 1041 * Used to pass OS data back after a TD completes. 1042 */ 1043 #define TRB_ENT (1<<1) 1044 /* Interrupt on short packet */ 1045 #define TRB_ISP (1<<2) 1046 /* Set PCIe no snoop attribute */ 1047 #define TRB_NO_SNOOP (1<<3) 1048 /* Chain multiple TRBs into a TD */ 1049 #define TRB_CHAIN (1<<4) 1050 /* Interrupt on completion */ 1051 #define TRB_IOC (1<<5) 1052 /* The buffer pointer contains immediate data */ 1053 #define TRB_IDT (1<<6) 1054 /* TDs smaller than this might use IDT */ 1055 #define TRB_IDT_MAX_SIZE 8 1056 1057 /* Block Event Interrupt */ 1058 #define TRB_BEI (1<<9) 1059 1060 /* Control transfer TRB specific fields */ 1061 #define TRB_DIR_IN (1<<16) 1062 #define TRB_TX_TYPE(p) ((p) << 16) 1063 #define TRB_DATA_OUT 2 1064 #define TRB_DATA_IN 3 1065 1066 /* Isochronous TRB specific fields */ 1067 #define TRB_SIA (1<<31) 1068 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1069 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1070 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1071 #define TRB_TBC(p) (((p) & 0x3) << 7) 1072 #define GET_TBC(p) (((p) >> 7) & 0x3) 1073 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1074 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1075 1076 /* TRB cache size for xHC with TRB cache */ 1077 #define TRB_CACHE_SIZE_HS 8 1078 #define TRB_CACHE_SIZE_SS 16 1079 1080 struct xhci_generic_trb { 1081 __le32 field[4]; 1082 }; 1083 1084 union xhci_trb { 1085 struct xhci_link_trb link; 1086 struct xhci_transfer_event trans_event; 1087 struct xhci_event_cmd event_cmd; 1088 struct xhci_generic_trb generic; 1089 }; 1090 1091 /* TRB bit mask */ 1092 #define TRB_TYPE_BITMASK (0xfc00) 1093 #define TRB_TYPE(p) ((p) << 10) 1094 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1095 /* TRB type IDs */ 1096 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1097 #define TRB_NORMAL 1 1098 /* setup stage for control transfers */ 1099 #define TRB_SETUP 2 1100 /* data stage for control transfers */ 1101 #define TRB_DATA 3 1102 /* status stage for control transfers */ 1103 #define TRB_STATUS 4 1104 /* isoc transfers */ 1105 #define TRB_ISOC 5 1106 /* TRB for linking ring segments */ 1107 #define TRB_LINK 6 1108 #define TRB_EVENT_DATA 7 1109 /* Transfer Ring No-op (not for the command ring) */ 1110 #define TRB_TR_NOOP 8 1111 /* Command TRBs */ 1112 /* Enable Slot Command */ 1113 #define TRB_ENABLE_SLOT 9 1114 /* Disable Slot Command */ 1115 #define TRB_DISABLE_SLOT 10 1116 /* Address Device Command */ 1117 #define TRB_ADDR_DEV 11 1118 /* Configure Endpoint Command */ 1119 #define TRB_CONFIG_EP 12 1120 /* Evaluate Context Command */ 1121 #define TRB_EVAL_CONTEXT 13 1122 /* Reset Endpoint Command */ 1123 #define TRB_RESET_EP 14 1124 /* Stop Transfer Ring Command */ 1125 #define TRB_STOP_RING 15 1126 /* Set Transfer Ring Dequeue Pointer Command */ 1127 #define TRB_SET_DEQ 16 1128 /* Reset Device Command */ 1129 #define TRB_RESET_DEV 17 1130 /* Force Event Command (opt) */ 1131 #define TRB_FORCE_EVENT 18 1132 /* Negotiate Bandwidth Command (opt) */ 1133 #define TRB_NEG_BANDWIDTH 19 1134 /* Set Latency Tolerance Value Command (opt) */ 1135 #define TRB_SET_LT 20 1136 /* Get port bandwidth Command */ 1137 #define TRB_GET_BW 21 1138 /* Force Header Command - generate a transaction or link management packet */ 1139 #define TRB_FORCE_HEADER 22 1140 /* No-op Command - not for transfer rings */ 1141 #define TRB_CMD_NOOP 23 1142 /* TRB IDs 24-31 reserved */ 1143 /* Event TRBS */ 1144 /* Transfer Event */ 1145 #define TRB_TRANSFER 32 1146 /* Command Completion Event */ 1147 #define TRB_COMPLETION 33 1148 /* Port Status Change Event */ 1149 #define TRB_PORT_STATUS 34 1150 /* Bandwidth Request Event (opt) */ 1151 #define TRB_BANDWIDTH_EVENT 35 1152 /* Doorbell Event (opt) */ 1153 #define TRB_DOORBELL 36 1154 /* Host Controller Event */ 1155 #define TRB_HC_EVENT 37 1156 /* Device Notification Event - device sent function wake notification */ 1157 #define TRB_DEV_NOTE 38 1158 /* MFINDEX Wrap Event - microframe counter wrapped */ 1159 #define TRB_MFINDEX_WRAP 39 1160 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1161 #define TRB_VENDOR_DEFINED_LOW 48 1162 /* Nec vendor-specific command completion event. */ 1163 #define TRB_NEC_CMD_COMP 48 1164 /* Get NEC firmware revision. */ 1165 #define TRB_NEC_GET_FW 49 1166 1167 static inline const char *xhci_trb_type_string(u8 type) 1168 { 1169 switch (type) { 1170 case TRB_NORMAL: 1171 return "Normal"; 1172 case TRB_SETUP: 1173 return "Setup Stage"; 1174 case TRB_DATA: 1175 return "Data Stage"; 1176 case TRB_STATUS: 1177 return "Status Stage"; 1178 case TRB_ISOC: 1179 return "Isoch"; 1180 case TRB_LINK: 1181 return "Link"; 1182 case TRB_EVENT_DATA: 1183 return "Event Data"; 1184 case TRB_TR_NOOP: 1185 return "No-Op"; 1186 case TRB_ENABLE_SLOT: 1187 return "Enable Slot Command"; 1188 case TRB_DISABLE_SLOT: 1189 return "Disable Slot Command"; 1190 case TRB_ADDR_DEV: 1191 return "Address Device Command"; 1192 case TRB_CONFIG_EP: 1193 return "Configure Endpoint Command"; 1194 case TRB_EVAL_CONTEXT: 1195 return "Evaluate Context Command"; 1196 case TRB_RESET_EP: 1197 return "Reset Endpoint Command"; 1198 case TRB_STOP_RING: 1199 return "Stop Ring Command"; 1200 case TRB_SET_DEQ: 1201 return "Set TR Dequeue Pointer Command"; 1202 case TRB_RESET_DEV: 1203 return "Reset Device Command"; 1204 case TRB_FORCE_EVENT: 1205 return "Force Event Command"; 1206 case TRB_NEG_BANDWIDTH: 1207 return "Negotiate Bandwidth Command"; 1208 case TRB_SET_LT: 1209 return "Set Latency Tolerance Value Command"; 1210 case TRB_GET_BW: 1211 return "Get Port Bandwidth Command"; 1212 case TRB_FORCE_HEADER: 1213 return "Force Header Command"; 1214 case TRB_CMD_NOOP: 1215 return "No-Op Command"; 1216 case TRB_TRANSFER: 1217 return "Transfer Event"; 1218 case TRB_COMPLETION: 1219 return "Command Completion Event"; 1220 case TRB_PORT_STATUS: 1221 return "Port Status Change Event"; 1222 case TRB_BANDWIDTH_EVENT: 1223 return "Bandwidth Request Event"; 1224 case TRB_DOORBELL: 1225 return "Doorbell Event"; 1226 case TRB_HC_EVENT: 1227 return "Host Controller Event"; 1228 case TRB_DEV_NOTE: 1229 return "Device Notification Event"; 1230 case TRB_MFINDEX_WRAP: 1231 return "MFINDEX Wrap Event"; 1232 case TRB_NEC_CMD_COMP: 1233 return "NEC Command Completion Event"; 1234 case TRB_NEC_GET_FW: 1235 return "NET Get Firmware Revision Command"; 1236 default: 1237 return "UNKNOWN"; 1238 } 1239 } 1240 1241 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1242 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1243 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1244 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1245 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1246 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1247 1248 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1249 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1250 1251 /* 1252 * TRBS_PER_SEGMENT must be a multiple of 4, 1253 * since the command ring is 64-byte aligned. 1254 * It must also be greater than 16. 1255 */ 1256 #define TRBS_PER_SEGMENT 256 1257 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1258 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1259 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1260 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1261 /* TRB buffer pointers can't cross 64KB boundaries */ 1262 #define TRB_MAX_BUFF_SHIFT 16 1263 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1264 /* How much data is left before the 64KB boundary? */ 1265 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1266 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1267 #define MAX_SOFT_RETRY 3 1268 /* 1269 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1270 * XHCI_AVOID_BEI quirk is in use. 1271 */ 1272 #define AVOID_BEI_INTERVAL_MIN 8 1273 #define AVOID_BEI_INTERVAL_MAX 32 1274 1275 #define xhci_for_each_ring_seg(head, seg) \ 1276 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1277 1278 struct xhci_segment { 1279 union xhci_trb *trbs; 1280 /* private to HCD */ 1281 struct xhci_segment *next; 1282 unsigned int num; 1283 dma_addr_t dma; 1284 /* Max packet sized bounce buffer for td-fragmant alignment */ 1285 dma_addr_t bounce_dma; 1286 void *bounce_buf; 1287 unsigned int bounce_offs; 1288 unsigned int bounce_len; 1289 }; 1290 1291 enum xhci_cancelled_td_status { 1292 TD_DIRTY = 0, 1293 TD_HALTED, 1294 TD_CLEARING_CACHE, 1295 TD_CLEARING_CACHE_DEFERRED, 1296 TD_CLEARED, 1297 }; 1298 1299 struct xhci_td { 1300 struct list_head td_list; 1301 struct list_head cancelled_td_list; 1302 int status; 1303 enum xhci_cancelled_td_status cancel_status; 1304 struct urb *urb; 1305 struct xhci_segment *start_seg; 1306 union xhci_trb *start_trb; 1307 struct xhci_segment *end_seg; 1308 union xhci_trb *end_trb; 1309 struct xhci_segment *bounce_seg; 1310 /* actual_length of the URB has already been set */ 1311 bool urb_length_set; 1312 bool error_mid_td; 1313 }; 1314 1315 /* 1316 * xHCI command default timeout value in milliseconds. 1317 * USB 3.2 spec, section 9.2.6.1 1318 */ 1319 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1320 1321 /* command descriptor */ 1322 struct xhci_cd { 1323 struct xhci_command *command; 1324 union xhci_trb *cmd_trb; 1325 }; 1326 1327 enum xhci_ring_type { 1328 TYPE_CTRL = 0, 1329 TYPE_ISOC, 1330 TYPE_BULK, 1331 TYPE_INTR, 1332 TYPE_STREAM, 1333 TYPE_COMMAND, 1334 TYPE_EVENT, 1335 }; 1336 1337 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1338 { 1339 switch (type) { 1340 case TYPE_CTRL: 1341 return "CTRL"; 1342 case TYPE_ISOC: 1343 return "ISOC"; 1344 case TYPE_BULK: 1345 return "BULK"; 1346 case TYPE_INTR: 1347 return "INTR"; 1348 case TYPE_STREAM: 1349 return "STREAM"; 1350 case TYPE_COMMAND: 1351 return "CMD"; 1352 case TYPE_EVENT: 1353 return "EVENT"; 1354 } 1355 1356 return "UNKNOWN"; 1357 } 1358 1359 struct xhci_ring { 1360 struct xhci_segment *first_seg; 1361 struct xhci_segment *last_seg; 1362 union xhci_trb *enqueue; 1363 struct xhci_segment *enq_seg; 1364 union xhci_trb *dequeue; 1365 struct xhci_segment *deq_seg; 1366 struct list_head td_list; 1367 /* 1368 * Write the cycle state into the TRB cycle field to give ownership of 1369 * the TRB to the host controller (if we are the producer), or to check 1370 * if we own the TRB (if we are the consumer). See section 4.9.1. 1371 */ 1372 u32 cycle_state; 1373 unsigned int stream_id; 1374 unsigned int num_segs; 1375 unsigned int num_trbs_free; /* used only by xhci DbC */ 1376 unsigned int bounce_buf_len; 1377 enum xhci_ring_type type; 1378 u32 old_trb_comp_code; 1379 struct radix_tree_root *trb_address_map; 1380 }; 1381 1382 struct xhci_erst_entry { 1383 /* 64-bit event ring segment address */ 1384 __le64 seg_addr; 1385 __le32 seg_size; 1386 /* Set to zero */ 1387 __le32 rsvd; 1388 }; 1389 1390 struct xhci_erst { 1391 struct xhci_erst_entry *entries; 1392 unsigned int num_entries; 1393 /* xhci->event_ring keeps track of segment dma addresses */ 1394 dma_addr_t erst_dma_addr; 1395 }; 1396 1397 struct xhci_scratchpad { 1398 u64 *sp_array; 1399 dma_addr_t sp_dma; 1400 void **sp_buffers; 1401 }; 1402 1403 struct urb_priv { 1404 int num_tds; 1405 int num_tds_done; 1406 struct xhci_td td[] __counted_by(num_tds); 1407 }; 1408 1409 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1410 #define ERST_DEFAULT_SEGS 2 1411 /* Poll every 60 seconds */ 1412 #define POLL_TIMEOUT 60 1413 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1414 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1415 /* XXX: Make these module parameters */ 1416 1417 struct s3_save { 1418 u32 command; 1419 u32 dev_nt; 1420 u64 dcbaa_ptr; 1421 u32 config_reg; 1422 }; 1423 1424 /* Use for lpm */ 1425 struct dev_info { 1426 u32 dev_id; 1427 struct list_head list; 1428 }; 1429 1430 struct xhci_bus_state { 1431 unsigned long bus_suspended; 1432 unsigned long next_statechange; 1433 1434 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1435 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1436 u32 port_c_suspend; 1437 u32 suspended_ports; 1438 u32 port_remote_wakeup; 1439 /* which ports have started to resume */ 1440 unsigned long resuming_ports; 1441 }; 1442 1443 struct xhci_interrupter { 1444 struct xhci_ring *event_ring; 1445 struct xhci_erst erst; 1446 struct xhci_intr_reg __iomem *ir_set; 1447 unsigned int intr_num; 1448 bool ip_autoclear; 1449 u32 isoc_bei_interval; 1450 /* For interrupter registers save and restore over suspend/resume */ 1451 u32 s3_irq_pending; 1452 u32 s3_irq_control; 1453 u32 s3_erst_size; 1454 u64 s3_erst_base; 1455 u64 s3_erst_dequeue; 1456 }; 1457 /* 1458 * It can take up to 20 ms to transition from RExit to U0 on the 1459 * Intel Lynx Point LP xHCI host. 1460 */ 1461 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1462 struct xhci_port_cap { 1463 u32 *psi; /* array of protocol speed ID entries */ 1464 u8 psi_count; 1465 u8 psi_uid_count; 1466 u8 maj_rev; 1467 u8 min_rev; 1468 u32 protocol_caps; 1469 }; 1470 1471 struct xhci_port { 1472 __le32 __iomem *addr; 1473 int hw_portnum; 1474 int hcd_portnum; 1475 struct xhci_hub *rhub; 1476 struct xhci_port_cap *port_cap; 1477 unsigned int lpm_incapable:1; 1478 unsigned long resume_timestamp; 1479 bool rexit_active; 1480 /* Slot ID is the index of the device directly connected to the port */ 1481 int slot_id; 1482 struct completion rexit_done; 1483 struct completion u3exit_done; 1484 }; 1485 1486 struct xhci_hub { 1487 struct xhci_port **ports; 1488 unsigned int num_ports; 1489 struct usb_hcd *hcd; 1490 /* keep track of bus suspend info */ 1491 struct xhci_bus_state bus_state; 1492 /* supported prococol extended capabiliy values */ 1493 u8 maj_rev; 1494 u8 min_rev; 1495 }; 1496 1497 /* There is one xhci_hcd structure per controller */ 1498 struct xhci_hcd { 1499 struct usb_hcd *main_hcd; 1500 struct usb_hcd *shared_hcd; 1501 /* glue to PCI and HCD framework */ 1502 struct xhci_cap_regs __iomem *cap_regs; 1503 struct xhci_op_regs __iomem *op_regs; 1504 struct xhci_run_regs __iomem *run_regs; 1505 struct xhci_doorbell_array __iomem *dba; 1506 1507 /* Cached register copies of read-only HC data */ 1508 __u32 hcs_params1; 1509 __u32 hcs_params2; 1510 __u32 hcs_params3; 1511 __u32 hcc_params; 1512 __u32 hcc_params2; 1513 1514 spinlock_t lock; 1515 1516 /* packed release number */ 1517 u16 hci_version; 1518 u16 max_interrupters; 1519 /* imod_interval in ns (I * 250ns) */ 1520 u32 imod_interval; 1521 u32 page_size; 1522 /* MSI-X/MSI vectors */ 1523 int nvecs; 1524 /* optional clocks */ 1525 struct clk *clk; 1526 struct clk *reg_clk; 1527 /* optional reset controller */ 1528 struct reset_control *reset; 1529 /* data structures */ 1530 struct xhci_device_context_array *dcbaa; 1531 struct xhci_interrupter **interrupters; 1532 struct xhci_ring *cmd_ring; 1533 unsigned int cmd_ring_state; 1534 #define CMD_RING_STATE_RUNNING (1 << 0) 1535 #define CMD_RING_STATE_ABORTED (1 << 1) 1536 #define CMD_RING_STATE_STOPPED (1 << 2) 1537 struct list_head cmd_list; 1538 unsigned int cmd_ring_reserved_trbs; 1539 struct delayed_work cmd_timer; 1540 struct completion cmd_ring_stop_completion; 1541 struct xhci_command *current_cmd; 1542 1543 /* Scratchpad */ 1544 struct xhci_scratchpad *scratchpad; 1545 1546 /* slot enabling and address device helpers */ 1547 /* these are not thread safe so use mutex */ 1548 struct mutex mutex; 1549 /* Internal mirror of the HW's dcbaa */ 1550 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1551 /* For keeping track of bandwidth domains per roothub. */ 1552 struct xhci_root_port_bw_info *rh_bw; 1553 1554 /* DMA pools */ 1555 struct dma_pool *device_pool; 1556 struct dma_pool *segment_pool; 1557 struct dma_pool *small_streams_pool; 1558 struct dma_pool *medium_streams_pool; 1559 1560 /* Host controller watchdog timer structures */ 1561 unsigned int xhc_state; 1562 unsigned long run_graceperiod; 1563 struct s3_save s3; 1564 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1565 * 1566 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1567 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1568 * that sees this status (other than the timer that set it) should stop touching 1569 * hardware immediately. Interrupt handlers should return immediately when 1570 * they see this status (any time they drop and re-acquire xhci->lock). 1571 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1572 * putting the TD on the canceled list, etc. 1573 * 1574 * There are no reports of xHCI host controllers that display this issue. 1575 */ 1576 #define XHCI_STATE_DYING (1 << 0) 1577 #define XHCI_STATE_HALTED (1 << 1) 1578 #define XHCI_STATE_REMOVING (1 << 2) 1579 unsigned long long quirks; 1580 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1581 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1582 #define XHCI_NEC_HOST BIT_ULL(2) 1583 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1584 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1585 /* 1586 * Certain Intel host controllers have a limit to the number of endpoint 1587 * contexts they can handle. Ideally, they would signal that they can't handle 1588 * anymore endpoint contexts by returning a Resource Error for the Configure 1589 * Endpoint command, but they don't. Instead they expect software to keep track 1590 * of the number of active endpoints for them, across configure endpoint 1591 * commands, reset device commands, disable slot commands, and address device 1592 * commands. 1593 */ 1594 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1595 #define XHCI_BROKEN_MSI BIT_ULL(6) 1596 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1597 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1598 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1599 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1600 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1601 #define XHCI_INTEL_HOST BIT_ULL(12) 1602 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1603 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1604 #define XHCI_AVOID_BEI BIT_ULL(15) 1605 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1606 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1607 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1608 /* For controllers with a broken beyond repair streams implementation */ 1609 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1610 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1611 #define XHCI_MTK_HOST BIT_ULL(21) 1612 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1613 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1614 #define XHCI_MISSING_CAS BIT_ULL(24) 1615 /* For controller with a broken Port Disable implementation */ 1616 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1617 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1618 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1619 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1620 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1621 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1622 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1623 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1624 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1625 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1626 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1627 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1628 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1629 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1630 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1631 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1632 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1633 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1634 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1635 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1636 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1637 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1638 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1639 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1640 #define XHCI_ETRON_HOST BIT_ULL(49) 1641 1642 unsigned int num_active_eps; 1643 unsigned int limit_active_eps; 1644 struct xhci_port *hw_ports; 1645 struct xhci_hub usb2_rhub; 1646 struct xhci_hub usb3_rhub; 1647 /* support xHCI 1.0 spec USB2 hardware LPM */ 1648 unsigned hw_lpm_support:1; 1649 /* Broken Suspend flag for SNPS Suspend resume issue */ 1650 unsigned broken_suspend:1; 1651 /* Indicates that omitting hcd is supported if root hub has no ports */ 1652 unsigned allow_single_roothub:1; 1653 /* cached extended protocol port capabilities */ 1654 struct xhci_port_cap *port_caps; 1655 unsigned int num_port_caps; 1656 /* Compliance Mode Recovery Data */ 1657 struct timer_list comp_mode_recovery_timer; 1658 u32 port_status_u0; 1659 u16 test_mode; 1660 /* Compliance Mode Timer Triggered every 2 seconds */ 1661 #define COMP_MODE_RCVRY_MSECS 2000 1662 1663 struct dentry *debugfs_root; 1664 struct dentry *debugfs_slots; 1665 struct list_head regset_list; 1666 1667 void *dbc; 1668 /* platform-specific data -- must come last */ 1669 unsigned long priv[] __aligned(sizeof(s64)); 1670 }; 1671 1672 /* Platform specific overrides to generic XHCI hc_driver ops */ 1673 struct xhci_driver_overrides { 1674 size_t extra_priv_size; 1675 int (*reset)(struct usb_hcd *hcd); 1676 int (*start)(struct usb_hcd *hcd); 1677 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1678 struct usb_host_endpoint *ep); 1679 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1680 struct usb_host_endpoint *ep); 1681 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1682 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1683 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1684 struct usb_tt *tt, gfp_t mem_flags); 1685 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1686 u16 wIndex, char *buf, u16 wLength); 1687 }; 1688 1689 #define XHCI_CFC_DELAY 10 1690 1691 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1692 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1693 { 1694 struct usb_hcd *primary_hcd; 1695 1696 if (usb_hcd_is_primary_hcd(hcd)) 1697 primary_hcd = hcd; 1698 else 1699 primary_hcd = hcd->primary_hcd; 1700 1701 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1702 } 1703 1704 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1705 { 1706 return xhci->main_hcd; 1707 } 1708 1709 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1710 { 1711 if (xhci->shared_hcd) 1712 return xhci->shared_hcd; 1713 1714 if (!xhci->usb2_rhub.num_ports) 1715 return xhci->main_hcd; 1716 1717 return NULL; 1718 } 1719 1720 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1721 { 1722 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1723 1724 return hcd == xhci_get_usb3_hcd(xhci); 1725 } 1726 1727 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1728 { 1729 return xhci->allow_single_roothub && 1730 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1731 } 1732 1733 #define xhci_dbg(xhci, fmt, args...) \ 1734 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1735 #define xhci_err(xhci, fmt, args...) \ 1736 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1737 #define xhci_warn(xhci, fmt, args...) \ 1738 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1739 #define xhci_info(xhci, fmt, args...) \ 1740 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1741 1742 /* 1743 * Registers should always be accessed with double word or quad word accesses. 1744 * 1745 * Some xHCI implementations may support 64-bit address pointers. Registers 1746 * with 64-bit address pointers should be written to with dword accesses by 1747 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1748 * xHCI implementations that do not support 64-bit address pointers will ignore 1749 * the high dword, and write order is irrelevant. 1750 */ 1751 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1752 __le64 __iomem *regs) 1753 { 1754 return lo_hi_readq(regs); 1755 } 1756 static inline void xhci_write_64(struct xhci_hcd *xhci, 1757 const u64 val, __le64 __iomem *regs) 1758 { 1759 lo_hi_writeq(val, regs); 1760 } 1761 1762 1763 /* 1764 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1765 * Other chapters and later specs say that it should only be set if the link is inside a TD 1766 * which continues from the end of one segment to the next segment. 1767 * 1768 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1769 * 1770 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1771 * "resynchronizing the pipe" after a Missed Service Error. 1772 */ 1773 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1774 { 1775 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1776 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1777 } 1778 1779 /* xHCI debugging */ 1780 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1781 struct xhci_container_ctx *ctx); 1782 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1783 const char *fmt, ...); 1784 1785 /* xHCI memory management */ 1786 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1787 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1788 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1789 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1790 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1791 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1792 struct usb_device *udev); 1793 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1794 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1795 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1796 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1797 struct xhci_virt_device *virt_dev, 1798 int old_active_eps); 1799 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1800 void xhci_update_bw_info(struct xhci_hcd *xhci, 1801 struct xhci_container_ctx *in_ctx, 1802 struct xhci_input_control_ctx *ctrl_ctx, 1803 struct xhci_virt_device *virt_dev); 1804 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1805 struct xhci_container_ctx *in_ctx, 1806 struct xhci_container_ctx *out_ctx, 1807 unsigned int ep_index); 1808 void xhci_slot_copy(struct xhci_hcd *xhci, 1809 struct xhci_container_ctx *in_ctx, 1810 struct xhci_container_ctx *out_ctx); 1811 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1812 struct usb_device *udev, struct usb_host_endpoint *ep, 1813 gfp_t mem_flags); 1814 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1815 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1816 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1817 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1818 unsigned int num_trbs, gfp_t flags); 1819 void xhci_initialize_ring_info(struct xhci_ring *ring); 1820 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1821 struct xhci_virt_device *virt_dev, 1822 unsigned int ep_index); 1823 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1824 unsigned int num_stream_ctxs, 1825 unsigned int num_streams, 1826 unsigned int max_packet, gfp_t flags); 1827 void xhci_free_stream_info(struct xhci_hcd *xhci, 1828 struct xhci_stream_info *stream_info); 1829 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1830 struct xhci_ep_ctx *ep_ctx, 1831 struct xhci_stream_info *stream_info); 1832 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1833 struct xhci_virt_ep *ep); 1834 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1835 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1836 struct xhci_ring *xhci_dma_to_transfer_ring( 1837 struct xhci_virt_ep *ep, 1838 u64 address); 1839 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1840 bool allocate_completion, gfp_t mem_flags); 1841 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1842 bool allocate_completion, gfp_t mem_flags); 1843 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1844 void xhci_free_command(struct xhci_hcd *xhci, 1845 struct xhci_command *command); 1846 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1847 int type, gfp_t flags); 1848 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1849 struct xhci_container_ctx *ctx); 1850 struct xhci_interrupter * 1851 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1852 u32 imod_interval); 1853 void xhci_remove_secondary_interrupter(struct usb_hcd 1854 *hcd, struct xhci_interrupter *ir); 1855 1856 /* xHCI host controller glue */ 1857 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1858 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1859 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, 1860 u32 mask, u32 done, int usec, unsigned int exit_state); 1861 void xhci_quiesce(struct xhci_hcd *xhci); 1862 int xhci_halt(struct xhci_hcd *xhci); 1863 int xhci_start(struct xhci_hcd *xhci); 1864 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1865 int xhci_run(struct usb_hcd *hcd); 1866 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1867 void xhci_shutdown(struct usb_hcd *hcd); 1868 void xhci_stop(struct usb_hcd *hcd); 1869 void xhci_init_driver(struct hc_driver *drv, 1870 const struct xhci_driver_overrides *over); 1871 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1872 struct usb_host_endpoint *ep); 1873 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1874 struct usb_host_endpoint *ep); 1875 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1876 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1877 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1878 struct usb_tt *tt, gfp_t mem_flags); 1879 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1880 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1881 1882 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1883 int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1884 1885 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1886 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1887 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1888 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1889 struct xhci_virt_device *virt_dev, 1890 struct usb_device *hdev, 1891 struct usb_tt *tt, gfp_t mem_flags); 1892 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1893 u32 imod_interval); 1894 1895 /* xHCI ring, segment, TRB, and TD functions */ 1896 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1897 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1898 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1899 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1900 u32 trb_type, u32 slot_id); 1901 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1902 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1903 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1904 u32 field1, u32 field2, u32 field3, u32 field4); 1905 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1906 int slot_id, unsigned int ep_index, int suspend); 1907 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1908 int slot_id, unsigned int ep_index); 1909 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1910 int slot_id, unsigned int ep_index); 1911 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1912 int slot_id, unsigned int ep_index); 1913 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1914 struct urb *urb, int slot_id, unsigned int ep_index); 1915 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1916 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1917 bool command_must_succeed); 1918 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1919 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1920 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1921 int slot_id, unsigned int ep_index, 1922 enum xhci_ep_reset_type reset_type); 1923 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1924 u32 slot_id); 1925 void xhci_handle_command_timeout(struct work_struct *work); 1926 1927 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1928 unsigned int ep_index, unsigned int stream_id); 1929 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1930 unsigned int slot_id, 1931 unsigned int ep_index); 1932 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1933 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1934 unsigned int count_trbs(u64 addr, u64 len); 1935 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1936 int suspend, gfp_t gfp_flags); 1937 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1938 1939 /* xHCI roothub code */ 1940 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1941 u32 link_state); 1942 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1943 u32 port_bit); 1944 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1945 char *buf, u16 wLength); 1946 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1947 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1948 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1949 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1950 struct xhci_port *port); 1951 void xhci_hc_died(struct xhci_hcd *xhci); 1952 1953 #ifdef CONFIG_PM 1954 int xhci_bus_suspend(struct usb_hcd *hcd); 1955 int xhci_bus_resume(struct usb_hcd *hcd); 1956 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1957 #else 1958 #define xhci_bus_suspend NULL 1959 #define xhci_bus_resume NULL 1960 #define xhci_get_resuming_ports NULL 1961 #endif /* CONFIG_PM */ 1962 1963 u32 xhci_port_state_to_neutral(u32 state); 1964 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1965 1966 /* xHCI contexts */ 1967 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1968 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1969 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1970 1971 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1972 unsigned int slot_id, unsigned int ep_index, 1973 unsigned int stream_id); 1974 1975 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 1976 struct urb *urb) 1977 { 1978 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 1979 xhci_get_endpoint_index(&urb->ep->desc), 1980 urb->stream_id); 1981 } 1982 1983 /* 1984 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 1985 * them anyways as we where unable to find a device that matches the 1986 * constraints. 1987 */ 1988 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 1989 { 1990 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 1991 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 1992 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 1993 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 1994 !urb->num_sgs) 1995 return true; 1996 1997 return false; 1998 } 1999 2000 static inline char *xhci_slot_state_string(u32 state) 2001 { 2002 switch (state) { 2003 case SLOT_STATE_ENABLED: 2004 return "enabled/disabled"; 2005 case SLOT_STATE_DEFAULT: 2006 return "default"; 2007 case SLOT_STATE_ADDRESSED: 2008 return "addressed"; 2009 case SLOT_STATE_CONFIGURED: 2010 return "configured"; 2011 default: 2012 return "reserved"; 2013 } 2014 } 2015 2016 static inline const char *xhci_decode_trb(char *str, size_t size, 2017 u32 field0, u32 field1, u32 field2, u32 field3) 2018 { 2019 int type = TRB_FIELD_TO_TYPE(field3); 2020 2021 switch (type) { 2022 case TRB_LINK: 2023 snprintf(str, size, 2024 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2025 field1, field0, GET_INTR_TARGET(field2), 2026 xhci_trb_type_string(type), 2027 field3 & TRB_IOC ? 'I' : 'i', 2028 field3 & TRB_CHAIN ? 'C' : 'c', 2029 field3 & TRB_TC ? 'T' : 't', 2030 field3 & TRB_CYCLE ? 'C' : 'c'); 2031 break; 2032 case TRB_TRANSFER: 2033 case TRB_COMPLETION: 2034 case TRB_PORT_STATUS: 2035 case TRB_BANDWIDTH_EVENT: 2036 case TRB_DOORBELL: 2037 case TRB_HC_EVENT: 2038 case TRB_DEV_NOTE: 2039 case TRB_MFINDEX_WRAP: 2040 snprintf(str, size, 2041 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2042 field1, field0, 2043 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2044 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2045 TRB_TO_EP_ID(field3), 2046 xhci_trb_type_string(type), 2047 field3 & EVENT_DATA ? 'E' : 'e', 2048 field3 & TRB_CYCLE ? 'C' : 'c'); 2049 2050 break; 2051 case TRB_SETUP: 2052 snprintf(str, size, 2053 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2054 field0 & 0xff, 2055 (field0 & 0xff00) >> 8, 2056 (field0 & 0xff000000) >> 24, 2057 (field0 & 0xff0000) >> 16, 2058 (field1 & 0xff00) >> 8, 2059 field1 & 0xff, 2060 (field1 & 0xff000000) >> 16 | 2061 (field1 & 0xff0000) >> 16, 2062 TRB_LEN(field2), GET_TD_SIZE(field2), 2063 GET_INTR_TARGET(field2), 2064 xhci_trb_type_string(type), 2065 field3 & TRB_IDT ? 'I' : 'i', 2066 field3 & TRB_IOC ? 'I' : 'i', 2067 field3 & TRB_CYCLE ? 'C' : 'c'); 2068 break; 2069 case TRB_DATA: 2070 snprintf(str, size, 2071 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2072 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2073 GET_INTR_TARGET(field2), 2074 xhci_trb_type_string(type), 2075 field3 & TRB_IDT ? 'I' : 'i', 2076 field3 & TRB_IOC ? 'I' : 'i', 2077 field3 & TRB_CHAIN ? 'C' : 'c', 2078 field3 & TRB_NO_SNOOP ? 'S' : 's', 2079 field3 & TRB_ISP ? 'I' : 'i', 2080 field3 & TRB_ENT ? 'E' : 'e', 2081 field3 & TRB_CYCLE ? 'C' : 'c'); 2082 break; 2083 case TRB_STATUS: 2084 snprintf(str, size, 2085 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2086 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2087 GET_INTR_TARGET(field2), 2088 xhci_trb_type_string(type), 2089 field3 & TRB_IOC ? 'I' : 'i', 2090 field3 & TRB_CHAIN ? 'C' : 'c', 2091 field3 & TRB_ENT ? 'E' : 'e', 2092 field3 & TRB_CYCLE ? 'C' : 'c'); 2093 break; 2094 case TRB_NORMAL: 2095 case TRB_EVENT_DATA: 2096 case TRB_TR_NOOP: 2097 snprintf(str, size, 2098 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2099 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2100 GET_INTR_TARGET(field2), 2101 xhci_trb_type_string(type), 2102 field3 & TRB_BEI ? 'B' : 'b', 2103 field3 & TRB_IDT ? 'I' : 'i', 2104 field3 & TRB_IOC ? 'I' : 'i', 2105 field3 & TRB_CHAIN ? 'C' : 'c', 2106 field3 & TRB_NO_SNOOP ? 'S' : 's', 2107 field3 & TRB_ISP ? 'I' : 'i', 2108 field3 & TRB_ENT ? 'E' : 'e', 2109 field3 & TRB_CYCLE ? 'C' : 'c'); 2110 break; 2111 case TRB_ISOC: 2112 snprintf(str, size, 2113 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2114 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2115 GET_INTR_TARGET(field2), 2116 xhci_trb_type_string(type), 2117 GET_TBC(field3), 2118 GET_TLBPC(field3), 2119 GET_FRAME_ID(field3), 2120 field3 & TRB_SIA ? 'S' : 's', 2121 field3 & TRB_BEI ? 'B' : 'b', 2122 field3 & TRB_IDT ? 'I' : 'i', 2123 field3 & TRB_IOC ? 'I' : 'i', 2124 field3 & TRB_CHAIN ? 'C' : 'c', 2125 field3 & TRB_NO_SNOOP ? 'S' : 's', 2126 field3 & TRB_ISP ? 'I' : 'i', 2127 field3 & TRB_ENT ? 'E' : 'e', 2128 field3 & TRB_CYCLE ? 'C' : 'c'); 2129 break; 2130 case TRB_CMD_NOOP: 2131 case TRB_ENABLE_SLOT: 2132 snprintf(str, size, 2133 "%s: flags %c", 2134 xhci_trb_type_string(type), 2135 field3 & TRB_CYCLE ? 'C' : 'c'); 2136 break; 2137 case TRB_DISABLE_SLOT: 2138 case TRB_NEG_BANDWIDTH: 2139 snprintf(str, size, 2140 "%s: slot %d flags %c", 2141 xhci_trb_type_string(type), 2142 TRB_TO_SLOT_ID(field3), 2143 field3 & TRB_CYCLE ? 'C' : 'c'); 2144 break; 2145 case TRB_ADDR_DEV: 2146 snprintf(str, size, 2147 "%s: ctx %08x%08x slot %d flags %c:%c", 2148 xhci_trb_type_string(type), 2149 field1, field0, 2150 TRB_TO_SLOT_ID(field3), 2151 field3 & TRB_BSR ? 'B' : 'b', 2152 field3 & TRB_CYCLE ? 'C' : 'c'); 2153 break; 2154 case TRB_CONFIG_EP: 2155 snprintf(str, size, 2156 "%s: ctx %08x%08x slot %d flags %c:%c", 2157 xhci_trb_type_string(type), 2158 field1, field0, 2159 TRB_TO_SLOT_ID(field3), 2160 field3 & TRB_DC ? 'D' : 'd', 2161 field3 & TRB_CYCLE ? 'C' : 'c'); 2162 break; 2163 case TRB_EVAL_CONTEXT: 2164 snprintf(str, size, 2165 "%s: ctx %08x%08x slot %d flags %c", 2166 xhci_trb_type_string(type), 2167 field1, field0, 2168 TRB_TO_SLOT_ID(field3), 2169 field3 & TRB_CYCLE ? 'C' : 'c'); 2170 break; 2171 case TRB_RESET_EP: 2172 snprintf(str, size, 2173 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2174 xhci_trb_type_string(type), 2175 field1, field0, 2176 TRB_TO_SLOT_ID(field3), 2177 TRB_TO_EP_ID(field3), 2178 field3 & TRB_TSP ? 'T' : 't', 2179 field3 & TRB_CYCLE ? 'C' : 'c'); 2180 break; 2181 case TRB_STOP_RING: 2182 snprintf(str, size, 2183 "%s: slot %d sp %d ep %d flags %c", 2184 xhci_trb_type_string(type), 2185 TRB_TO_SLOT_ID(field3), 2186 TRB_TO_SUSPEND_PORT(field3), 2187 TRB_TO_EP_ID(field3), 2188 field3 & TRB_CYCLE ? 'C' : 'c'); 2189 break; 2190 case TRB_SET_DEQ: 2191 snprintf(str, size, 2192 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2193 xhci_trb_type_string(type), 2194 field1, field0, 2195 TRB_TO_STREAM_ID(field2), 2196 TRB_TO_SLOT_ID(field3), 2197 TRB_TO_EP_ID(field3), 2198 field3 & TRB_CYCLE ? 'C' : 'c'); 2199 break; 2200 case TRB_RESET_DEV: 2201 snprintf(str, size, 2202 "%s: slot %d flags %c", 2203 xhci_trb_type_string(type), 2204 TRB_TO_SLOT_ID(field3), 2205 field3 & TRB_CYCLE ? 'C' : 'c'); 2206 break; 2207 case TRB_FORCE_EVENT: 2208 snprintf(str, size, 2209 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2210 xhci_trb_type_string(type), 2211 field1, field0, 2212 TRB_TO_VF_INTR_TARGET(field2), 2213 TRB_TO_VF_ID(field3), 2214 field3 & TRB_CYCLE ? 'C' : 'c'); 2215 break; 2216 case TRB_SET_LT: 2217 snprintf(str, size, 2218 "%s: belt %d flags %c", 2219 xhci_trb_type_string(type), 2220 TRB_TO_BELT(field3), 2221 field3 & TRB_CYCLE ? 'C' : 'c'); 2222 break; 2223 case TRB_GET_BW: 2224 snprintf(str, size, 2225 "%s: ctx %08x%08x slot %d speed %d flags %c", 2226 xhci_trb_type_string(type), 2227 field1, field0, 2228 TRB_TO_SLOT_ID(field3), 2229 TRB_TO_DEV_SPEED(field3), 2230 field3 & TRB_CYCLE ? 'C' : 'c'); 2231 break; 2232 case TRB_FORCE_HEADER: 2233 snprintf(str, size, 2234 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2235 xhci_trb_type_string(type), 2236 field2, field1, field0 & 0xffffffe0, 2237 TRB_TO_PACKET_TYPE(field0), 2238 TRB_TO_ROOTHUB_PORT(field3), 2239 field3 & TRB_CYCLE ? 'C' : 'c'); 2240 break; 2241 default: 2242 snprintf(str, size, 2243 "type '%s' -> raw %08x %08x %08x %08x", 2244 xhci_trb_type_string(type), 2245 field0, field1, field2, field3); 2246 } 2247 2248 return str; 2249 } 2250 2251 static inline const char *xhci_decode_ctrl_ctx(char *str, 2252 unsigned long drop, unsigned long add) 2253 { 2254 unsigned int bit; 2255 int ret = 0; 2256 2257 str[0] = '\0'; 2258 2259 if (drop) { 2260 ret = sprintf(str, "Drop:"); 2261 for_each_set_bit(bit, &drop, 32) 2262 ret += sprintf(str + ret, " %d%s", 2263 bit / 2, 2264 bit % 2 ? "in":"out"); 2265 ret += sprintf(str + ret, ", "); 2266 } 2267 2268 if (add) { 2269 ret += sprintf(str + ret, "Add:%s%s", 2270 (add & SLOT_FLAG) ? " slot":"", 2271 (add & EP0_FLAG) ? " ep0":""); 2272 add &= ~(SLOT_FLAG | EP0_FLAG); 2273 for_each_set_bit(bit, &add, 32) 2274 ret += sprintf(str + ret, " %d%s", 2275 bit / 2, 2276 bit % 2 ? "in":"out"); 2277 } 2278 return str; 2279 } 2280 2281 static inline const char *xhci_decode_slot_context(char *str, 2282 u32 info, u32 info2, u32 tt_info, u32 state) 2283 { 2284 u32 speed; 2285 u32 hub; 2286 u32 mtt; 2287 int ret = 0; 2288 2289 speed = info & DEV_SPEED; 2290 hub = info & DEV_HUB; 2291 mtt = info & DEV_MTT; 2292 2293 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2294 info & ROUTE_STRING_MASK, 2295 ({ char *s; 2296 switch (speed) { 2297 case SLOT_SPEED_FS: 2298 s = "full-speed"; 2299 break; 2300 case SLOT_SPEED_LS: 2301 s = "low-speed"; 2302 break; 2303 case SLOT_SPEED_HS: 2304 s = "high-speed"; 2305 break; 2306 case SLOT_SPEED_SS: 2307 s = "super-speed"; 2308 break; 2309 case SLOT_SPEED_SSP: 2310 s = "super-speed plus"; 2311 break; 2312 default: 2313 s = "UNKNOWN speed"; 2314 } s; }), 2315 mtt ? " multi-TT" : "", 2316 hub ? " Hub" : "", 2317 (info & LAST_CTX_MASK) >> 27, 2318 info2 & MAX_EXIT, 2319 DEVINFO_TO_ROOT_HUB_PORT(info2), 2320 DEVINFO_TO_MAX_PORTS(info2)); 2321 2322 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2323 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2324 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2325 state & DEV_ADDR_MASK, 2326 xhci_slot_state_string(GET_SLOT_STATE(state))); 2327 2328 return str; 2329 } 2330 2331 2332 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2333 { 2334 switch (portsc & PORT_PLS_MASK) { 2335 case XDEV_U0: 2336 return "U0"; 2337 case XDEV_U1: 2338 return "U1"; 2339 case XDEV_U2: 2340 return "U2"; 2341 case XDEV_U3: 2342 return "U3"; 2343 case XDEV_DISABLED: 2344 return "Disabled"; 2345 case XDEV_RXDETECT: 2346 return "RxDetect"; 2347 case XDEV_INACTIVE: 2348 return "Inactive"; 2349 case XDEV_POLLING: 2350 return "Polling"; 2351 case XDEV_RECOVERY: 2352 return "Recovery"; 2353 case XDEV_HOT_RESET: 2354 return "Hot Reset"; 2355 case XDEV_COMP_MODE: 2356 return "Compliance mode"; 2357 case XDEV_TEST_MODE: 2358 return "Test mode"; 2359 case XDEV_RESUME: 2360 return "Resume"; 2361 default: 2362 break; 2363 } 2364 return "Unknown"; 2365 } 2366 2367 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2368 { 2369 int ret; 2370 2371 ret = sprintf(str, "0x%08x ", portsc); 2372 2373 if (portsc == ~(u32)0) 2374 return str; 2375 2376 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ", 2377 portsc & PORT_POWER ? "Powered" : "Powered-off", 2378 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2379 portsc & PORT_PE ? "Enabled" : "Disabled", 2380 xhci_portsc_link_state_string(portsc), 2381 DEV_PORT_SPEED(portsc)); 2382 2383 if (portsc & PORT_OC) 2384 ret += sprintf(str + ret, "OverCurrent "); 2385 if (portsc & PORT_RESET) 2386 ret += sprintf(str + ret, "In-Reset "); 2387 2388 ret += sprintf(str + ret, "Change: "); 2389 if (portsc & PORT_CSC) 2390 ret += sprintf(str + ret, "CSC "); 2391 if (portsc & PORT_PEC) 2392 ret += sprintf(str + ret, "PEC "); 2393 if (portsc & PORT_WRC) 2394 ret += sprintf(str + ret, "WRC "); 2395 if (portsc & PORT_OCC) 2396 ret += sprintf(str + ret, "OCC "); 2397 if (portsc & PORT_RC) 2398 ret += sprintf(str + ret, "PRC "); 2399 if (portsc & PORT_PLC) 2400 ret += sprintf(str + ret, "PLC "); 2401 if (portsc & PORT_CEC) 2402 ret += sprintf(str + ret, "CEC "); 2403 if (portsc & PORT_CAS) 2404 ret += sprintf(str + ret, "CAS "); 2405 2406 ret += sprintf(str + ret, "Wake: "); 2407 if (portsc & PORT_WKCONN_E) 2408 ret += sprintf(str + ret, "WCE "); 2409 if (portsc & PORT_WKDISC_E) 2410 ret += sprintf(str + ret, "WDE "); 2411 if (portsc & PORT_WKOC_E) 2412 ret += sprintf(str + ret, "WOE "); 2413 2414 return str; 2415 } 2416 2417 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2418 { 2419 int ret = 0; 2420 2421 ret = sprintf(str, " 0x%08x", usbsts); 2422 2423 if (usbsts == ~(u32)0) 2424 return str; 2425 2426 if (usbsts & STS_HALT) 2427 ret += sprintf(str + ret, " HCHalted"); 2428 if (usbsts & STS_FATAL) 2429 ret += sprintf(str + ret, " HSE"); 2430 if (usbsts & STS_EINT) 2431 ret += sprintf(str + ret, " EINT"); 2432 if (usbsts & STS_PORT) 2433 ret += sprintf(str + ret, " PCD"); 2434 if (usbsts & STS_SAVE) 2435 ret += sprintf(str + ret, " SSS"); 2436 if (usbsts & STS_RESTORE) 2437 ret += sprintf(str + ret, " RSS"); 2438 if (usbsts & STS_SRE) 2439 ret += sprintf(str + ret, " SRE"); 2440 if (usbsts & STS_CNR) 2441 ret += sprintf(str + ret, " CNR"); 2442 if (usbsts & STS_HCE) 2443 ret += sprintf(str + ret, " HCE"); 2444 2445 return str; 2446 } 2447 2448 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2449 { 2450 u8 ep; 2451 u16 stream; 2452 int ret; 2453 2454 ep = (doorbell & 0xff); 2455 stream = doorbell >> 16; 2456 2457 if (slot == 0) { 2458 sprintf(str, "Command Ring %d", doorbell); 2459 return str; 2460 } 2461 ret = sprintf(str, "Slot %d ", slot); 2462 if (ep > 0 && ep < 32) 2463 ret = sprintf(str + ret, "ep%d%s", 2464 ep / 2, 2465 ep % 2 ? "in" : "out"); 2466 else if (ep == 0 || ep < 248) 2467 ret = sprintf(str + ret, "Reserved %d", ep); 2468 else 2469 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2470 if (stream) 2471 ret = sprintf(str + ret, " Stream %d", stream); 2472 2473 return str; 2474 } 2475 2476 static inline const char *xhci_ep_state_string(u8 state) 2477 { 2478 switch (state) { 2479 case EP_STATE_DISABLED: 2480 return "disabled"; 2481 case EP_STATE_RUNNING: 2482 return "running"; 2483 case EP_STATE_HALTED: 2484 return "halted"; 2485 case EP_STATE_STOPPED: 2486 return "stopped"; 2487 case EP_STATE_ERROR: 2488 return "error"; 2489 default: 2490 return "INVALID"; 2491 } 2492 } 2493 2494 static inline const char *xhci_ep_type_string(u8 type) 2495 { 2496 switch (type) { 2497 case ISOC_OUT_EP: 2498 return "Isoc OUT"; 2499 case BULK_OUT_EP: 2500 return "Bulk OUT"; 2501 case INT_OUT_EP: 2502 return "Int OUT"; 2503 case CTRL_EP: 2504 return "Ctrl"; 2505 case ISOC_IN_EP: 2506 return "Isoc IN"; 2507 case BULK_IN_EP: 2508 return "Bulk IN"; 2509 case INT_IN_EP: 2510 return "Int IN"; 2511 default: 2512 return "INVALID"; 2513 } 2514 } 2515 2516 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2517 u32 info2, u64 deq, u32 tx_info) 2518 { 2519 int ret; 2520 2521 u32 esit; 2522 u16 maxp; 2523 u16 avg; 2524 2525 u8 max_pstr; 2526 u8 ep_state; 2527 u8 interval; 2528 u8 ep_type; 2529 u8 burst; 2530 u8 cerr; 2531 u8 mult; 2532 2533 bool lsa; 2534 bool hid; 2535 2536 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2537 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2538 2539 ep_state = info & EP_STATE_MASK; 2540 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2541 interval = CTX_TO_EP_INTERVAL(info); 2542 mult = CTX_TO_EP_MULT(info) + 1; 2543 lsa = !!(info & EP_HAS_LSA); 2544 2545 cerr = (info2 & (3 << 1)) >> 1; 2546 ep_type = CTX_TO_EP_TYPE(info2); 2547 hid = !!(info2 & (1 << 7)); 2548 burst = CTX_TO_MAX_BURST(info2); 2549 maxp = MAX_PACKET_DECODED(info2); 2550 2551 avg = EP_AVG_TRB_LENGTH(tx_info); 2552 2553 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2554 xhci_ep_state_string(ep_state), mult, 2555 max_pstr, lsa ? "LSA " : ""); 2556 2557 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2558 (1 << interval) * 125, esit, cerr); 2559 2560 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2561 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2562 burst, maxp, deq); 2563 2564 ret += sprintf(str + ret, "avg trb len %d", avg); 2565 2566 return str; 2567 } 2568 2569 #endif /* __LINUX_XHCI_HCD_H */ 2570