1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 34 /* xHCI PCI Configuration Registers */ 35 #define XHCI_SBRN_OFFSET (0x60) 36 37 /* Max number of USB devices for any host controller - limit in section 6.1 */ 38 #define MAX_HC_SLOTS 256 39 /* Section 5.3.3 - MaxPorts */ 40 #define MAX_HC_PORTS 127 41 42 /* 43 * xHCI register interface. 44 * This corresponds to the eXtensible Host Controller Interface (xHCI) 45 * Revision 0.95 specification 46 */ 47 48 /** 49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 50 * @hc_capbase: length of the capabilities register and HC version number 51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 54 * @hcc_params: HCCPARAMS - Capability Parameters 55 * @db_off: DBOFF - Doorbell array offset 56 * @run_regs_off: RTSOFF - Runtime register space offset 57 */ 58 struct xhci_cap_regs { 59 u32 hc_capbase; 60 u32 hcs_params1; 61 u32 hcs_params2; 62 u32 hcs_params3; 63 u32 hcc_params; 64 u32 db_off; 65 u32 run_regs_off; 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* hc_capbase bitmasks */ 70 /* bits 7:0 - how long is the Capabilities register */ 71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 72 /* bits 31:16 */ 73 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 74 75 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 76 /* bits 0:7, Max Device Slots */ 77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 78 #define HCS_SLOTS_MASK 0xff 79 /* bits 8:18, Max Interrupters */ 80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 83 84 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 85 /* bits 0:3, frames or uframes that SW needs to queue transactions 86 * ahead of the HW to meet periodic deadlines */ 87 #define HCS_IST(p) (((p) >> 0) & 0xf) 88 /* bits 4:7, max number of Event Ring segments */ 89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 93 94 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 99 100 /* HCCPARAMS - hcc_params - bitmasks */ 101 /* true: HC can use 64-bit address pointers */ 102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 103 /* true: HC can do bandwidth negotiation */ 104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 105 /* true: HC uses 64-byte Device Context structures 106 * FIXME 64-byte context structures aren't supported yet. 107 */ 108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 109 /* true: HC has port power switches */ 110 #define HCC_PPC(p) ((p) & (1 << 3)) 111 /* true: HC has port indicators */ 112 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 113 /* true: HC has Light HC Reset Capability */ 114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 115 /* true: HC supports latency tolerance messaging */ 116 #define HCC_LTC(p) ((p) & (1 << 6)) 117 /* true: no secondary Stream ID Support */ 118 #define HCC_NSS(p) ((p) & (1 << 7)) 119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 120 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 123 124 /* db_off bitmask - bits 0:1 reserved */ 125 #define DBOFF_MASK (~0x3) 126 127 /* run_regs_off bitmask - bits 0:4 reserved */ 128 #define RTSOFF_MASK (~0x1f) 129 130 131 /* Number of registers per port */ 132 #define NUM_PORT_REGS 4 133 134 /** 135 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 136 * @command: USBCMD - xHC command register 137 * @status: USBSTS - xHC status register 138 * @page_size: This indicates the page size that the host controller 139 * supports. If bit n is set, the HC supports a page size 140 * of 2^(n+12), up to a 128MB page size. 141 * 4K is the minimum page size. 142 * @cmd_ring: CRP - 64-bit Command Ring Pointer 143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 144 * @config_reg: CONFIG - Configure Register 145 * @port_status_base: PORTSCn - base address for Port Status and Control 146 * Each port has a Port Status and Control register, 147 * followed by a Port Power Management Status and Control 148 * register, a Port Link Info register, and a reserved 149 * register. 150 * @port_power_base: PORTPMSCn - base address for 151 * Port Power Management Status and Control 152 * @port_link_base: PORTLIn - base address for Port Link Info (current 153 * Link PM state and control) for USB 2.1 and USB 3.0 154 * devices. 155 */ 156 struct xhci_op_regs { 157 u32 command; 158 u32 status; 159 u32 page_size; 160 u32 reserved1; 161 u32 reserved2; 162 u32 dev_notification; 163 u64 cmd_ring; 164 /* rsvd: offset 0x20-2F */ 165 u32 reserved3[4]; 166 u64 dcbaa_ptr; 167 u32 config_reg; 168 /* rsvd: offset 0x3C-3FF */ 169 u32 reserved4[241]; 170 /* port 1 registers, which serve as a base address for other ports */ 171 u32 port_status_base; 172 u32 port_power_base; 173 u32 port_link_base; 174 u32 reserved5; 175 /* registers for ports 2-255 */ 176 u32 reserved6[NUM_PORT_REGS*254]; 177 }; 178 179 /* USBCMD - USB command - command bitmasks */ 180 /* start/stop HC execution - do not write unless HC is halted*/ 181 #define CMD_RUN XHCI_CMD_RUN 182 /* Reset HC - resets internal HC state machine and all registers (except 183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 184 * The xHCI driver must reinitialize the xHC after setting this bit. 185 */ 186 #define CMD_RESET (1 << 1) 187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 188 #define CMD_EIE XHCI_CMD_EIE 189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 190 #define CMD_HSEIE XHCI_CMD_HSEIE 191 /* bits 4:6 are reserved (and should be preserved on writes). */ 192 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 193 #define CMD_LRESET (1 << 7) 194 /* FIXME: ignoring host controller save/restore state for now. */ 195 #define CMD_CSS (1 << 8) 196 #define CMD_CRS (1 << 9) 197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 198 #define CMD_EWE XHCI_CMD_EWE 199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 201 * '0' means the xHC can power it off if all ports are in the disconnect, 202 * disabled, or powered-off state. 203 */ 204 #define CMD_PM_INDEX (1 << 11) 205 /* bits 12:31 are reserved (and should be preserved on writes). */ 206 207 /* USBSTS - USB status - status bitmasks */ 208 /* HC not running - set to 1 when run/stop bit is cleared. */ 209 #define STS_HALT XHCI_STS_HALT 210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 211 #define STS_FATAL (1 << 2) 212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 213 #define STS_EINT (1 << 3) 214 /* port change detect */ 215 #define STS_PORT (1 << 4) 216 /* bits 5:7 reserved and zeroed */ 217 /* save state status - '1' means xHC is saving state */ 218 #define STS_SAVE (1 << 8) 219 /* restore state status - '1' means xHC is restoring state */ 220 #define STS_RESTORE (1 << 9) 221 /* true: save or restore error */ 222 #define STS_SRE (1 << 10) 223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 224 #define STS_CNR XHCI_STS_CNR 225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 226 #define STS_HCE (1 << 12) 227 /* bits 13:31 reserved and should be preserved */ 228 229 /* 230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 231 * Generate a device notification event when the HC sees a transaction with a 232 * notification type that matches a bit set in this bit field. 233 */ 234 #define DEV_NOTE_MASK (0xffff) 235 #define ENABLE_DEV_NOTE(x) (1 << x) 236 /* Most of the device notification types should only be used for debug. 237 * SW does need to pay attention to function wake notifications. 238 */ 239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 240 241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 242 /* bit 0 is the command ring cycle state */ 243 /* stop ring operation after completion of the currently executing command */ 244 #define CMD_RING_PAUSE (1 << 1) 245 /* stop ring immediately - abort the currently executing command */ 246 #define CMD_RING_ABORT (1 << 2) 247 /* true: command ring is running */ 248 #define CMD_RING_RUNNING (1 << 3) 249 /* bits 4:5 reserved and should be preserved */ 250 /* Command Ring pointer - bit mask for the lower 32 bits. */ 251 #define CMD_RING_RSVD_BITS (0x3f) 252 253 /* CONFIG - Configure Register - config_reg bitmasks */ 254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 255 #define MAX_DEVS(p) ((p) & 0xff) 256 /* bits 8:31 - reserved and should be preserved */ 257 258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 259 /* true: device connected */ 260 #define PORT_CONNECT (1 << 0) 261 /* true: port enabled */ 262 #define PORT_PE (1 << 1) 263 /* bit 2 reserved and zeroed */ 264 /* true: port has an over-current condition */ 265 #define PORT_OC (1 << 3) 266 /* true: port reset signaling asserted */ 267 #define PORT_RESET (1 << 4) 268 /* Port Link State - bits 5:8 269 * A read gives the current link PM state of the port, 270 * a write with Link State Write Strobe set sets the link state. 271 */ 272 /* true: port has power (see HCC_PPC) */ 273 #define PORT_POWER (1 << 9) 274 /* bits 10:13 indicate device speed: 275 * 0 - undefined speed - port hasn't be initialized by a reset yet 276 * 1 - full speed 277 * 2 - low speed 278 * 3 - high speed 279 * 4 - super speed 280 * 5-15 reserved 281 */ 282 #define DEV_SPEED_MASK (0xf << 10) 283 #define XDEV_FS (0x1 << 10) 284 #define XDEV_LS (0x2 << 10) 285 #define XDEV_HS (0x3 << 10) 286 #define XDEV_SS (0x4 << 10) 287 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 288 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 289 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 290 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 291 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 292 /* Bits 20:23 in the Slot Context are the speed for the device */ 293 #define SLOT_SPEED_FS (XDEV_FS << 10) 294 #define SLOT_SPEED_LS (XDEV_LS << 10) 295 #define SLOT_SPEED_HS (XDEV_HS << 10) 296 #define SLOT_SPEED_SS (XDEV_SS << 10) 297 /* Port Indicator Control */ 298 #define PORT_LED_OFF (0 << 14) 299 #define PORT_LED_AMBER (1 << 14) 300 #define PORT_LED_GREEN (2 << 14) 301 #define PORT_LED_MASK (3 << 14) 302 /* Port Link State Write Strobe - set this when changing link state */ 303 #define PORT_LINK_STROBE (1 << 16) 304 /* true: connect status change */ 305 #define PORT_CSC (1 << 17) 306 /* true: port enable change */ 307 #define PORT_PEC (1 << 18) 308 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 309 * into an enabled state, and the device into the default state. A "warm" reset 310 * also resets the link, forcing the device through the link training sequence. 311 * SW can also look at the Port Reset register to see when warm reset is done. 312 */ 313 #define PORT_WRC (1 << 19) 314 /* true: over-current change */ 315 #define PORT_OCC (1 << 20) 316 /* true: reset change - 1 to 0 transition of PORT_RESET */ 317 #define PORT_RC (1 << 21) 318 /* port link status change - set on some port link state transitions: 319 * Transition Reason 320 * ------------------------------------------------------------------------------ 321 * - U3 to Resume Wakeup signaling from a device 322 * - Resume to Recovery to U0 USB 3.0 device resume 323 * - Resume to U0 USB 2.0 device resume 324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 325 * - U3 to U0 Software resume of USB 2.0 device complete 326 * - U2 to U0 L1 resume of USB 2.1 device complete 327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 328 * - U0 to disabled L1 entry error with USB 2.1 device 329 * - Any state to inactive Error on USB 3.0 port 330 */ 331 #define PORT_PLC (1 << 22) 332 /* port configure error change - port failed to configure its link partner */ 333 #define PORT_CEC (1 << 23) 334 /* bit 24 reserved */ 335 /* wake on connect (enable) */ 336 #define PORT_WKCONN_E (1 << 25) 337 /* wake on disconnect (enable) */ 338 #define PORT_WKDISC_E (1 << 26) 339 /* wake on over-current (enable) */ 340 #define PORT_WKOC_E (1 << 27) 341 /* bits 28:29 reserved */ 342 /* true: device is removable - for USB 3.0 roothub emulation */ 343 #define PORT_DEV_REMOVE (1 << 30) 344 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 345 #define PORT_WR (1 << 31) 346 347 /* Port Power Management Status and Control - port_power_base bitmasks */ 348 /* Inactivity timer value for transitions into U1, in microseconds. 349 * Timeout can be up to 127us. 0xFF means an infinite timeout. 350 */ 351 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 352 /* Inactivity timer value for transitions into U2 */ 353 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 354 /* Bits 24:31 for port testing */ 355 356 357 /** 358 * struct xhci_intr_reg - Interrupt Register Set 359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 360 * interrupts and check for pending interrupts. 361 * @irq_control: IMOD - Interrupt Moderation Register. 362 * Used to throttle interrupts. 363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 364 * @erst_base: ERST base address. 365 * @erst_dequeue: Event ring dequeue pointer. 366 * 367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 369 * multiple segments of the same size. The HC places events on the ring and 370 * "updates the Cycle bit in the TRBs to indicate to software the current 371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 372 * updates the dequeue pointer. 373 */ 374 struct xhci_intr_reg { 375 u32 irq_pending; 376 u32 irq_control; 377 u32 erst_size; 378 u32 rsvd; 379 u64 erst_base; 380 u64 erst_dequeue; 381 }; 382 383 /* irq_pending bitmasks */ 384 #define ER_IRQ_PENDING(p) ((p) & 0x1) 385 /* bits 2:31 need to be preserved */ 386 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 387 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 388 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 389 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 390 391 /* irq_control bitmasks */ 392 /* Minimum interval between interrupts (in 250ns intervals). The interval 393 * between interrupts will be longer if there are no events on the event ring. 394 * Default is 4000 (1 ms). 395 */ 396 #define ER_IRQ_INTERVAL_MASK (0xffff) 397 /* Counter used to count down the time to the next interrupt - HW use only */ 398 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 399 400 /* erst_size bitmasks */ 401 /* Preserve bits 16:31 of erst_size */ 402 #define ERST_SIZE_MASK (0xffff << 16) 403 404 /* erst_dequeue bitmasks */ 405 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 406 * where the current dequeue pointer lies. This is an optional HW hint. 407 */ 408 #define ERST_DESI_MASK (0x7) 409 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 410 * a work queue (or delayed service routine)? 411 */ 412 #define ERST_EHB (1 << 3) 413 #define ERST_PTR_MASK (0xf) 414 415 /** 416 * struct xhci_run_regs 417 * @microframe_index: 418 * MFINDEX - current microframe number 419 * 420 * Section 5.5 Host Controller Runtime Registers: 421 * "Software should read and write these registers using only Dword (32 bit) 422 * or larger accesses" 423 */ 424 struct xhci_run_regs { 425 u32 microframe_index; 426 u32 rsvd[7]; 427 struct xhci_intr_reg ir_set[128]; 428 }; 429 430 /** 431 * struct doorbell_array 432 * 433 * Section 5.6 434 */ 435 struct xhci_doorbell_array { 436 u32 doorbell[256]; 437 }; 438 439 #define DB_TARGET_MASK 0xFFFFFF00 440 #define DB_STREAM_ID_MASK 0x0000FFFF 441 #define DB_TARGET_HOST 0x0 442 #define DB_STREAM_ID_HOST 0x0 443 #define DB_MASK (0xff << 8) 444 445 /* Endpoint Target - bits 0:7 */ 446 #define EPI_TO_DB(p) (((p) + 1) & 0xff) 447 #define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16) 448 449 450 /** 451 * struct xhci_container_ctx 452 * @type: Type of context. Used to calculated offsets to contained contexts. 453 * @size: Size of the context data 454 * @bytes: The raw context data given to HW 455 * @dma: dma address of the bytes 456 * 457 * Represents either a Device or Input context. Holds a pointer to the raw 458 * memory used for the context (bytes) and dma address of it (dma). 459 */ 460 struct xhci_container_ctx { 461 unsigned type; 462 #define XHCI_CTX_TYPE_DEVICE 0x1 463 #define XHCI_CTX_TYPE_INPUT 0x2 464 465 int size; 466 467 u8 *bytes; 468 dma_addr_t dma; 469 }; 470 471 /** 472 * struct xhci_slot_ctx 473 * @dev_info: Route string, device speed, hub info, and last valid endpoint 474 * @dev_info2: Max exit latency for device number, root hub port number 475 * @tt_info: tt_info is used to construct split transaction tokens 476 * @dev_state: slot state and device address 477 * 478 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 479 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 480 * reserved at the end of the slot context for HC internal use. 481 */ 482 struct xhci_slot_ctx { 483 u32 dev_info; 484 u32 dev_info2; 485 u32 tt_info; 486 u32 dev_state; 487 /* offset 0x10 to 0x1f reserved for HC internal use */ 488 u32 reserved[4]; 489 }; 490 491 /* dev_info bitmasks */ 492 /* Route String - 0:19 */ 493 #define ROUTE_STRING_MASK (0xfffff) 494 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 495 #define DEV_SPEED (0xf << 20) 496 /* bit 24 reserved */ 497 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 498 #define DEV_MTT (0x1 << 25) 499 /* Set if the device is a hub - bit 26 */ 500 #define DEV_HUB (0x1 << 26) 501 /* Index of the last valid endpoint context in this device context - 27:31 */ 502 #define LAST_CTX_MASK (0x1f << 27) 503 #define LAST_CTX(p) ((p) << 27) 504 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 505 #define SLOT_FLAG (1 << 0) 506 #define EP0_FLAG (1 << 1) 507 508 /* dev_info2 bitmasks */ 509 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 510 #define MAX_EXIT (0xffff) 511 /* Root hub port number that is needed to access the USB device */ 512 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 513 /* Maximum number of ports under a hub device */ 514 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 515 516 /* tt_info bitmasks */ 517 /* 518 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 519 * The Slot ID of the hub that isolates the high speed signaling from 520 * this low or full-speed device. '0' if attached to root hub port. 521 */ 522 #define TT_SLOT (0xff) 523 /* 524 * The number of the downstream facing port of the high-speed hub 525 * '0' if the device is not low or full speed. 526 */ 527 #define TT_PORT (0xff << 8) 528 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 529 530 /* dev_state bitmasks */ 531 /* USB device address - assigned by the HC */ 532 #define DEV_ADDR_MASK (0xff) 533 /* bits 8:26 reserved */ 534 /* Slot state */ 535 #define SLOT_STATE (0x1f << 27) 536 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 537 538 539 /** 540 * struct xhci_ep_ctx 541 * @ep_info: endpoint state, streams, mult, and interval information. 542 * @ep_info2: information on endpoint type, max packet size, max burst size, 543 * error count, and whether the HC will force an event for all 544 * transactions. 545 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 546 * defines one stream, this points to the endpoint transfer ring. 547 * Otherwise, it points to a stream context array, which has a 548 * ring pointer for each flow. 549 * @tx_info: 550 * Average TRB lengths for the endpoint ring and 551 * max payload within an Endpoint Service Interval Time (ESIT). 552 * 553 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 554 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 555 * reserved at the end of the endpoint context for HC internal use. 556 */ 557 struct xhci_ep_ctx { 558 u32 ep_info; 559 u32 ep_info2; 560 u64 deq; 561 u32 tx_info; 562 /* offset 0x14 - 0x1f reserved for HC internal use */ 563 u32 reserved[3]; 564 }; 565 566 /* ep_info bitmasks */ 567 /* 568 * Endpoint State - bits 0:2 569 * 0 - disabled 570 * 1 - running 571 * 2 - halted due to halt condition - ok to manipulate endpoint ring 572 * 3 - stopped 573 * 4 - TRB error 574 * 5-7 - reserved 575 */ 576 #define EP_STATE_MASK (0xf) 577 #define EP_STATE_DISABLED 0 578 #define EP_STATE_RUNNING 1 579 #define EP_STATE_HALTED 2 580 #define EP_STATE_STOPPED 3 581 #define EP_STATE_ERROR 4 582 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 583 #define EP_MULT(p) ((p & 0x3) << 8) 584 /* bits 10:14 are Max Primary Streams */ 585 /* bit 15 is Linear Stream Array */ 586 /* Interval - period between requests to an endpoint - 125u increments. */ 587 #define EP_INTERVAL(p) ((p & 0xff) << 16) 588 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 589 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 590 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 591 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 592 #define EP_HAS_LSA (1 << 15) 593 594 /* ep_info2 bitmasks */ 595 /* 596 * Force Event - generate transfer events for all TRBs for this endpoint 597 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 598 */ 599 #define FORCE_EVENT (0x1) 600 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 601 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 602 #define EP_TYPE(p) ((p) << 3) 603 #define ISOC_OUT_EP 1 604 #define BULK_OUT_EP 2 605 #define INT_OUT_EP 3 606 #define CTRL_EP 4 607 #define ISOC_IN_EP 5 608 #define BULK_IN_EP 6 609 #define INT_IN_EP 7 610 /* bit 6 reserved */ 611 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 612 #define MAX_BURST(p) (((p)&0xff) << 8) 613 #define MAX_PACKET(p) (((p)&0xffff) << 16) 614 #define MAX_PACKET_MASK (0xffff << 16) 615 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 616 617 /* tx_info bitmasks */ 618 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 619 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 620 621 622 /** 623 * struct xhci_input_control_context 624 * Input control context; see section 6.2.5. 625 * 626 * @drop_context: set the bit of the endpoint context you want to disable 627 * @add_context: set the bit of the endpoint context you want to enable 628 */ 629 struct xhci_input_control_ctx { 630 u32 drop_flags; 631 u32 add_flags; 632 u32 rsvd2[6]; 633 }; 634 635 /* Represents everything that is needed to issue a command on the command ring. 636 * It's useful to pre-allocate these for commands that cannot fail due to 637 * out-of-memory errors, like freeing streams. 638 */ 639 struct xhci_command { 640 /* Input context for changing device state */ 641 struct xhci_container_ctx *in_ctx; 642 u32 status; 643 /* If completion is null, no one is waiting on this command 644 * and the structure can be freed after the command completes. 645 */ 646 struct completion *completion; 647 union xhci_trb *command_trb; 648 struct list_head cmd_list; 649 }; 650 651 /* drop context bitmasks */ 652 #define DROP_EP(x) (0x1 << x) 653 /* add context bitmasks */ 654 #define ADD_EP(x) (0x1 << x) 655 656 struct xhci_stream_ctx { 657 /* 64-bit stream ring address, cycle state, and stream type */ 658 u64 stream_ring; 659 /* offset 0x14 - 0x1f reserved for HC internal use */ 660 u32 reserved[2]; 661 }; 662 663 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 664 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 665 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 666 #define SCT_SEC_TR 0 667 /* Primary stream array type, dequeue pointer is to a transfer ring */ 668 #define SCT_PRI_TR 1 669 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 670 #define SCT_SSA_8 2 671 #define SCT_SSA_16 3 672 #define SCT_SSA_32 4 673 #define SCT_SSA_64 5 674 #define SCT_SSA_128 6 675 #define SCT_SSA_256 7 676 677 /* Assume no secondary streams for now */ 678 struct xhci_stream_info { 679 struct xhci_ring **stream_rings; 680 /* Number of streams, including stream 0 (which drivers can't use) */ 681 unsigned int num_streams; 682 /* The stream context array may be bigger than 683 * the number of streams the driver asked for 684 */ 685 struct xhci_stream_ctx *stream_ctx_array; 686 unsigned int num_stream_ctxs; 687 dma_addr_t ctx_array_dma; 688 /* For mapping physical TRB addresses to segments in stream rings */ 689 struct radix_tree_root trb_address_map; 690 struct xhci_command *free_streams_command; 691 }; 692 693 #define SMALL_STREAM_ARRAY_SIZE 256 694 #define MEDIUM_STREAM_ARRAY_SIZE 1024 695 696 struct xhci_virt_ep { 697 struct xhci_ring *ring; 698 /* Related to endpoints that are configured to use stream IDs only */ 699 struct xhci_stream_info *stream_info; 700 /* Temporary storage in case the configure endpoint command fails and we 701 * have to restore the device state to the previous state 702 */ 703 struct xhci_ring *new_ring; 704 unsigned int ep_state; 705 #define SET_DEQ_PENDING (1 << 0) 706 #define EP_HALTED (1 << 1) /* For stall handling */ 707 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 708 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 709 #define EP_GETTING_STREAMS (1 << 3) 710 #define EP_HAS_STREAMS (1 << 4) 711 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 712 #define EP_GETTING_NO_STREAMS (1 << 5) 713 /* ---- Related to URB cancellation ---- */ 714 struct list_head cancelled_td_list; 715 /* The TRB that was last reported in a stopped endpoint ring */ 716 union xhci_trb *stopped_trb; 717 struct xhci_td *stopped_td; 718 unsigned int stopped_stream; 719 /* Watchdog timer for stop endpoint command to cancel URBs */ 720 struct timer_list stop_cmd_timer; 721 int stop_cmds_pending; 722 struct xhci_hcd *xhci; 723 /* 724 * Sometimes the xHC can not process isochronous endpoint ring quickly 725 * enough, and it will miss some isoc tds on the ring and generate 726 * a Missed Service Error Event. 727 * Set skip flag when receive a Missed Service Error Event and 728 * process the missed tds on the endpoint ring. 729 */ 730 bool skip; 731 }; 732 733 struct xhci_virt_device { 734 /* 735 * Commands to the hardware are passed an "input context" that 736 * tells the hardware what to change in its data structures. 737 * The hardware will return changes in an "output context" that 738 * software must allocate for the hardware. We need to keep 739 * track of input and output contexts separately because 740 * these commands might fail and we don't trust the hardware. 741 */ 742 struct xhci_container_ctx *out_ctx; 743 /* Used for addressing devices and configuration changes */ 744 struct xhci_container_ctx *in_ctx; 745 /* Rings saved to ensure old alt settings can be re-instated */ 746 struct xhci_ring **ring_cache; 747 int num_rings_cached; 748 #define XHCI_MAX_RINGS_CACHED 31 749 struct xhci_virt_ep eps[31]; 750 struct completion cmd_completion; 751 /* Status of the last command issued for this device */ 752 u32 cmd_status; 753 struct list_head cmd_list; 754 }; 755 756 757 /** 758 * struct xhci_device_context_array 759 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 760 */ 761 struct xhci_device_context_array { 762 /* 64-bit device addresses; we only write 32-bit addresses */ 763 u64 dev_context_ptrs[MAX_HC_SLOTS]; 764 /* private xHCD pointers */ 765 dma_addr_t dma; 766 }; 767 /* TODO: write function to set the 64-bit device DMA address */ 768 /* 769 * TODO: change this to be dynamically sized at HC mem init time since the HC 770 * might not be able to handle the maximum number of devices possible. 771 */ 772 773 774 struct xhci_transfer_event { 775 /* 64-bit buffer address, or immediate data */ 776 u64 buffer; 777 u32 transfer_len; 778 /* This field is interpreted differently based on the type of TRB */ 779 u32 flags; 780 }; 781 782 /** Transfer Event bit fields **/ 783 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 784 785 /* Completion Code - only applicable for some types of TRBs */ 786 #define COMP_CODE_MASK (0xff << 24) 787 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 788 #define COMP_SUCCESS 1 789 /* Data Buffer Error */ 790 #define COMP_DB_ERR 2 791 /* Babble Detected Error */ 792 #define COMP_BABBLE 3 793 /* USB Transaction Error */ 794 #define COMP_TX_ERR 4 795 /* TRB Error - some TRB field is invalid */ 796 #define COMP_TRB_ERR 5 797 /* Stall Error - USB device is stalled */ 798 #define COMP_STALL 6 799 /* Resource Error - HC doesn't have memory for that device configuration */ 800 #define COMP_ENOMEM 7 801 /* Bandwidth Error - not enough room in schedule for this dev config */ 802 #define COMP_BW_ERR 8 803 /* No Slots Available Error - HC ran out of device slots */ 804 #define COMP_ENOSLOTS 9 805 /* Invalid Stream Type Error */ 806 #define COMP_STREAM_ERR 10 807 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 808 #define COMP_EBADSLT 11 809 /* Endpoint Not Enabled Error */ 810 #define COMP_EBADEP 12 811 /* Short Packet */ 812 #define COMP_SHORT_TX 13 813 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 814 #define COMP_UNDERRUN 14 815 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 816 #define COMP_OVERRUN 15 817 /* Virtual Function Event Ring Full Error */ 818 #define COMP_VF_FULL 16 819 /* Parameter Error - Context parameter is invalid */ 820 #define COMP_EINVAL 17 821 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 822 #define COMP_BW_OVER 18 823 /* Context State Error - illegal context state transition requested */ 824 #define COMP_CTX_STATE 19 825 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 826 #define COMP_PING_ERR 20 827 /* Event Ring is full */ 828 #define COMP_ER_FULL 21 829 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 830 #define COMP_MISSED_INT 23 831 /* Successfully stopped command ring */ 832 #define COMP_CMD_STOP 24 833 /* Successfully aborted current command and stopped command ring */ 834 #define COMP_CMD_ABORT 25 835 /* Stopped - transfer was terminated by a stop endpoint command */ 836 #define COMP_STOP 26 837 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ 838 #define COMP_STOP_INVAL 27 839 /* Control Abort Error - Debug Capability - control pipe aborted */ 840 #define COMP_DBG_ABORT 28 841 /* TRB type 29 and 30 reserved */ 842 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 843 #define COMP_BUFF_OVER 31 844 /* Event Lost Error - xHC has an "internal event overrun condition" */ 845 #define COMP_ISSUES 32 846 /* Undefined Error - reported when other error codes don't apply */ 847 #define COMP_UNKNOWN 33 848 /* Invalid Stream ID Error */ 849 #define COMP_STRID_ERR 34 850 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 851 /* FIXME - check for this */ 852 #define COMP_2ND_BW_ERR 35 853 /* Split Transaction Error */ 854 #define COMP_SPLIT_ERR 36 855 856 struct xhci_link_trb { 857 /* 64-bit segment pointer*/ 858 u64 segment_ptr; 859 u32 intr_target; 860 u32 control; 861 }; 862 863 /* control bitfields */ 864 #define LINK_TOGGLE (0x1<<1) 865 866 /* Command completion event TRB */ 867 struct xhci_event_cmd { 868 /* Pointer to command TRB, or the value passed by the event data trb */ 869 u64 cmd_trb; 870 u32 status; 871 u32 flags; 872 }; 873 874 /* flags bitmasks */ 875 /* bits 16:23 are the virtual function ID */ 876 /* bits 24:31 are the slot ID */ 877 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 878 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 879 880 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 881 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 882 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 883 884 /* Set TR Dequeue Pointer command TRB fields */ 885 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 886 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 887 888 889 /* Port Status Change Event TRB fields */ 890 /* Port ID - bits 31:24 */ 891 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 892 893 /* Normal TRB fields */ 894 /* transfer_len bitmasks - bits 0:16 */ 895 #define TRB_LEN(p) ((p) & 0x1ffff) 896 /* Interrupter Target - which MSI-X vector to target the completion event at */ 897 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 898 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 899 900 /* Cycle bit - indicates TRB ownership by HC or HCD */ 901 #define TRB_CYCLE (1<<0) 902 /* 903 * Force next event data TRB to be evaluated before task switch. 904 * Used to pass OS data back after a TD completes. 905 */ 906 #define TRB_ENT (1<<1) 907 /* Interrupt on short packet */ 908 #define TRB_ISP (1<<2) 909 /* Set PCIe no snoop attribute */ 910 #define TRB_NO_SNOOP (1<<3) 911 /* Chain multiple TRBs into a TD */ 912 #define TRB_CHAIN (1<<4) 913 /* Interrupt on completion */ 914 #define TRB_IOC (1<<5) 915 /* The buffer pointer contains immediate data */ 916 #define TRB_IDT (1<<6) 917 918 919 /* Control transfer TRB specific fields */ 920 #define TRB_DIR_IN (1<<16) 921 922 /* Isochronous TRB specific fields */ 923 #define TRB_SIA (1<<31) 924 925 struct xhci_generic_trb { 926 u32 field[4]; 927 }; 928 929 union xhci_trb { 930 struct xhci_link_trb link; 931 struct xhci_transfer_event trans_event; 932 struct xhci_event_cmd event_cmd; 933 struct xhci_generic_trb generic; 934 }; 935 936 /* TRB bit mask */ 937 #define TRB_TYPE_BITMASK (0xfc00) 938 #define TRB_TYPE(p) ((p) << 10) 939 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 940 /* TRB type IDs */ 941 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 942 #define TRB_NORMAL 1 943 /* setup stage for control transfers */ 944 #define TRB_SETUP 2 945 /* data stage for control transfers */ 946 #define TRB_DATA 3 947 /* status stage for control transfers */ 948 #define TRB_STATUS 4 949 /* isoc transfers */ 950 #define TRB_ISOC 5 951 /* TRB for linking ring segments */ 952 #define TRB_LINK 6 953 #define TRB_EVENT_DATA 7 954 /* Transfer Ring No-op (not for the command ring) */ 955 #define TRB_TR_NOOP 8 956 /* Command TRBs */ 957 /* Enable Slot Command */ 958 #define TRB_ENABLE_SLOT 9 959 /* Disable Slot Command */ 960 #define TRB_DISABLE_SLOT 10 961 /* Address Device Command */ 962 #define TRB_ADDR_DEV 11 963 /* Configure Endpoint Command */ 964 #define TRB_CONFIG_EP 12 965 /* Evaluate Context Command */ 966 #define TRB_EVAL_CONTEXT 13 967 /* Reset Endpoint Command */ 968 #define TRB_RESET_EP 14 969 /* Stop Transfer Ring Command */ 970 #define TRB_STOP_RING 15 971 /* Set Transfer Ring Dequeue Pointer Command */ 972 #define TRB_SET_DEQ 16 973 /* Reset Device Command */ 974 #define TRB_RESET_DEV 17 975 /* Force Event Command (opt) */ 976 #define TRB_FORCE_EVENT 18 977 /* Negotiate Bandwidth Command (opt) */ 978 #define TRB_NEG_BANDWIDTH 19 979 /* Set Latency Tolerance Value Command (opt) */ 980 #define TRB_SET_LT 20 981 /* Get port bandwidth Command */ 982 #define TRB_GET_BW 21 983 /* Force Header Command - generate a transaction or link management packet */ 984 #define TRB_FORCE_HEADER 22 985 /* No-op Command - not for transfer rings */ 986 #define TRB_CMD_NOOP 23 987 /* TRB IDs 24-31 reserved */ 988 /* Event TRBS */ 989 /* Transfer Event */ 990 #define TRB_TRANSFER 32 991 /* Command Completion Event */ 992 #define TRB_COMPLETION 33 993 /* Port Status Change Event */ 994 #define TRB_PORT_STATUS 34 995 /* Bandwidth Request Event (opt) */ 996 #define TRB_BANDWIDTH_EVENT 35 997 /* Doorbell Event (opt) */ 998 #define TRB_DOORBELL 36 999 /* Host Controller Event */ 1000 #define TRB_HC_EVENT 37 1001 /* Device Notification Event - device sent function wake notification */ 1002 #define TRB_DEV_NOTE 38 1003 /* MFINDEX Wrap Event - microframe counter wrapped */ 1004 #define TRB_MFINDEX_WRAP 39 1005 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1006 1007 /* Nec vendor-specific command completion event. */ 1008 #define TRB_NEC_CMD_COMP 48 1009 /* Get NEC firmware revision. */ 1010 #define TRB_NEC_GET_FW 49 1011 1012 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1013 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1014 1015 /* 1016 * TRBS_PER_SEGMENT must be a multiple of 4, 1017 * since the command ring is 64-byte aligned. 1018 * It must also be greater than 16. 1019 */ 1020 #define TRBS_PER_SEGMENT 64 1021 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1022 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1023 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1024 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 1025 * Change this if you change TRBS_PER_SEGMENT! 1026 */ 1027 #define SEGMENT_SHIFT 10 1028 /* TRB buffer pointers can't cross 64KB boundaries */ 1029 #define TRB_MAX_BUFF_SHIFT 16 1030 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1031 1032 struct xhci_segment { 1033 union xhci_trb *trbs; 1034 /* private to HCD */ 1035 struct xhci_segment *next; 1036 dma_addr_t dma; 1037 }; 1038 1039 struct xhci_td { 1040 struct list_head td_list; 1041 struct list_head cancelled_td_list; 1042 struct urb *urb; 1043 struct xhci_segment *start_seg; 1044 union xhci_trb *first_trb; 1045 union xhci_trb *last_trb; 1046 }; 1047 1048 struct xhci_dequeue_state { 1049 struct xhci_segment *new_deq_seg; 1050 union xhci_trb *new_deq_ptr; 1051 int new_cycle_state; 1052 }; 1053 1054 struct xhci_ring { 1055 struct xhci_segment *first_seg; 1056 union xhci_trb *enqueue; 1057 struct xhci_segment *enq_seg; 1058 unsigned int enq_updates; 1059 union xhci_trb *dequeue; 1060 struct xhci_segment *deq_seg; 1061 unsigned int deq_updates; 1062 struct list_head td_list; 1063 /* 1064 * Write the cycle state into the TRB cycle field to give ownership of 1065 * the TRB to the host controller (if we are the producer), or to check 1066 * if we own the TRB (if we are the consumer). See section 4.9.1. 1067 */ 1068 u32 cycle_state; 1069 unsigned int stream_id; 1070 }; 1071 1072 struct xhci_erst_entry { 1073 /* 64-bit event ring segment address */ 1074 u64 seg_addr; 1075 u32 seg_size; 1076 /* Set to zero */ 1077 u32 rsvd; 1078 }; 1079 1080 struct xhci_erst { 1081 struct xhci_erst_entry *entries; 1082 unsigned int num_entries; 1083 /* xhci->event_ring keeps track of segment dma addresses */ 1084 dma_addr_t erst_dma_addr; 1085 /* Num entries the ERST can contain */ 1086 unsigned int erst_size; 1087 }; 1088 1089 struct xhci_scratchpad { 1090 u64 *sp_array; 1091 dma_addr_t sp_dma; 1092 void **sp_buffers; 1093 dma_addr_t *sp_dma_buffers; 1094 }; 1095 1096 struct urb_priv { 1097 int length; 1098 int td_cnt; 1099 struct xhci_td *td[0]; 1100 }; 1101 1102 /* 1103 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1104 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1105 * meaning 64 ring segments. 1106 * Initial allocated size of the ERST, in number of entries */ 1107 #define ERST_NUM_SEGS 1 1108 /* Initial allocated size of the ERST, in number of entries */ 1109 #define ERST_SIZE 64 1110 /* Initial number of event segment rings allocated */ 1111 #define ERST_ENTRIES 1 1112 /* Poll every 60 seconds */ 1113 #define POLL_TIMEOUT 60 1114 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1115 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1116 /* XXX: Make these module parameters */ 1117 1118 1119 /* There is one ehci_hci structure per controller */ 1120 struct xhci_hcd { 1121 /* glue to PCI and HCD framework */ 1122 struct xhci_cap_regs __iomem *cap_regs; 1123 struct xhci_op_regs __iomem *op_regs; 1124 struct xhci_run_regs __iomem *run_regs; 1125 struct xhci_doorbell_array __iomem *dba; 1126 /* Our HCD's current interrupter register set */ 1127 struct xhci_intr_reg __iomem *ir_set; 1128 1129 /* Cached register copies of read-only HC data */ 1130 __u32 hcs_params1; 1131 __u32 hcs_params2; 1132 __u32 hcs_params3; 1133 __u32 hcc_params; 1134 1135 spinlock_t lock; 1136 1137 /* packed release number */ 1138 u8 sbrn; 1139 u16 hci_version; 1140 u8 max_slots; 1141 u8 max_interrupters; 1142 u8 max_ports; 1143 u8 isoc_threshold; 1144 int event_ring_max; 1145 int addr_64; 1146 /* 4KB min, 128MB max */ 1147 int page_size; 1148 /* Valid values are 12 to 20, inclusive */ 1149 int page_shift; 1150 /* msi-x vectors */ 1151 int msix_count; 1152 struct msix_entry *msix_entries; 1153 /* data structures */ 1154 struct xhci_device_context_array *dcbaa; 1155 struct xhci_ring *cmd_ring; 1156 unsigned int cmd_ring_reserved_trbs; 1157 struct xhci_ring *event_ring; 1158 struct xhci_erst erst; 1159 /* Scratchpad */ 1160 struct xhci_scratchpad *scratchpad; 1161 1162 /* slot enabling and address device helpers */ 1163 struct completion addr_dev; 1164 int slot_id; 1165 /* Internal mirror of the HW's dcbaa */ 1166 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1167 1168 /* DMA pools */ 1169 struct dma_pool *device_pool; 1170 struct dma_pool *segment_pool; 1171 struct dma_pool *small_streams_pool; 1172 struct dma_pool *medium_streams_pool; 1173 1174 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1175 /* Poll the rings - for debugging */ 1176 struct timer_list event_ring_timer; 1177 int zombie; 1178 #endif 1179 /* Host controller watchdog timer structures */ 1180 unsigned int xhc_state; 1181 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1182 * 1183 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1184 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1185 * that sees this status (other than the timer that set it) should stop touching 1186 * hardware immediately. Interrupt handlers should return immediately when 1187 * they see this status (any time they drop and re-acquire xhci->lock). 1188 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1189 * putting the TD on the canceled list, etc. 1190 * 1191 * There are no reports of xHCI host controllers that display this issue. 1192 */ 1193 #define XHCI_STATE_DYING (1 << 0) 1194 /* Statistics */ 1195 int noops_submitted; 1196 int noops_handled; 1197 int error_bitmask; 1198 unsigned int quirks; 1199 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1200 #define XHCI_RESET_EP_QUIRK (1 << 1) 1201 #define XHCI_NEC_HOST (1 << 2) 1202 }; 1203 1204 /* For testing purposes */ 1205 #define NUM_TEST_NOOPS 0 1206 1207 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1208 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1209 { 1210 return (struct xhci_hcd *) (hcd->hcd_priv); 1211 } 1212 1213 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1214 { 1215 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1216 } 1217 1218 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1219 #define XHCI_DEBUG 1 1220 #else 1221 #define XHCI_DEBUG 0 1222 #endif 1223 1224 #define xhci_dbg(xhci, fmt, args...) \ 1225 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1226 #define xhci_info(xhci, fmt, args...) \ 1227 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1228 #define xhci_err(xhci, fmt, args...) \ 1229 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1230 #define xhci_warn(xhci, fmt, args...) \ 1231 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1232 1233 /* TODO: copied from ehci.h - can be refactored? */ 1234 /* xHCI spec says all registers are little endian */ 1235 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1236 __u32 __iomem *regs) 1237 { 1238 return readl(regs); 1239 } 1240 static inline void xhci_writel(struct xhci_hcd *xhci, 1241 const unsigned int val, __u32 __iomem *regs) 1242 { 1243 xhci_dbg(xhci, 1244 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1245 regs, val); 1246 writel(val, regs); 1247 } 1248 1249 /* 1250 * Registers should always be accessed with double word or quad word accesses. 1251 * 1252 * Some xHCI implementations may support 64-bit address pointers. Registers 1253 * with 64-bit address pointers should be written to with dword accesses by 1254 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1255 * xHCI implementations that do not support 64-bit address pointers will ignore 1256 * the high dword, and write order is irrelevant. 1257 */ 1258 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1259 __u64 __iomem *regs) 1260 { 1261 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1262 u64 val_lo = readl(ptr); 1263 u64 val_hi = readl(ptr + 1); 1264 return val_lo + (val_hi << 32); 1265 } 1266 static inline void xhci_write_64(struct xhci_hcd *xhci, 1267 const u64 val, __u64 __iomem *regs) 1268 { 1269 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1270 u32 val_lo = lower_32_bits(val); 1271 u32 val_hi = upper_32_bits(val); 1272 1273 xhci_dbg(xhci, 1274 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", 1275 regs, (long unsigned int) val); 1276 writel(val_lo, ptr); 1277 writel(val_hi, ptr + 1); 1278 } 1279 1280 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1281 { 1282 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 1283 return ((HC_VERSION(temp) == 0x95) && 1284 (xhci->quirks & XHCI_LINK_TRB_QUIRK)); 1285 } 1286 1287 /* xHCI debugging */ 1288 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); 1289 void xhci_print_registers(struct xhci_hcd *xhci); 1290 void xhci_dbg_regs(struct xhci_hcd *xhci); 1291 void xhci_print_run_regs(struct xhci_hcd *xhci); 1292 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1293 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1294 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1295 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1296 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1297 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1298 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1299 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1300 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1301 struct xhci_container_ctx *ctx); 1302 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1303 unsigned int slot_id, unsigned int ep_index, 1304 struct xhci_virt_ep *ep); 1305 1306 /* xHCI memory management */ 1307 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1308 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1309 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1310 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1311 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1312 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1313 struct usb_device *udev); 1314 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1315 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1316 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1317 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1318 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1319 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1320 struct xhci_container_ctx *in_ctx, 1321 struct xhci_container_ctx *out_ctx, 1322 unsigned int ep_index); 1323 void xhci_slot_copy(struct xhci_hcd *xhci, 1324 struct xhci_container_ctx *in_ctx, 1325 struct xhci_container_ctx *out_ctx); 1326 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1327 struct usb_device *udev, struct usb_host_endpoint *ep, 1328 gfp_t mem_flags); 1329 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1330 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1331 struct xhci_virt_device *virt_dev, 1332 unsigned int ep_index); 1333 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1334 unsigned int num_stream_ctxs, 1335 unsigned int num_streams, gfp_t flags); 1336 void xhci_free_stream_info(struct xhci_hcd *xhci, 1337 struct xhci_stream_info *stream_info); 1338 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1339 struct xhci_ep_ctx *ep_ctx, 1340 struct xhci_stream_info *stream_info); 1341 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1342 struct xhci_ep_ctx *ep_ctx, 1343 struct xhci_virt_ep *ep); 1344 struct xhci_ring *xhci_dma_to_transfer_ring( 1345 struct xhci_virt_ep *ep, 1346 u64 address); 1347 struct xhci_ring *xhci_stream_id_to_ring( 1348 struct xhci_virt_device *dev, 1349 unsigned int ep_index, 1350 unsigned int stream_id); 1351 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1352 bool allocate_in_ctx, bool allocate_completion, 1353 gfp_t mem_flags); 1354 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1355 void xhci_free_command(struct xhci_hcd *xhci, 1356 struct xhci_command *command); 1357 1358 #ifdef CONFIG_PCI 1359 /* xHCI PCI glue */ 1360 int xhci_register_pci(void); 1361 void xhci_unregister_pci(void); 1362 #endif 1363 1364 /* xHCI host controller glue */ 1365 void xhci_quiesce(struct xhci_hcd *xhci); 1366 int xhci_halt(struct xhci_hcd *xhci); 1367 int xhci_reset(struct xhci_hcd *xhci); 1368 int xhci_init(struct usb_hcd *hcd); 1369 int xhci_run(struct usb_hcd *hcd); 1370 void xhci_stop(struct usb_hcd *hcd); 1371 void xhci_shutdown(struct usb_hcd *hcd); 1372 int xhci_get_frame(struct usb_hcd *hcd); 1373 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1374 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1375 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1376 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1377 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1378 struct usb_host_endpoint **eps, unsigned int num_eps, 1379 unsigned int num_streams, gfp_t mem_flags); 1380 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1381 struct usb_host_endpoint **eps, unsigned int num_eps, 1382 gfp_t mem_flags); 1383 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1384 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1385 struct usb_tt *tt, gfp_t mem_flags); 1386 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1387 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1388 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1389 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1390 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1391 int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1392 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1393 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1394 1395 /* xHCI ring, segment, TRB, and TD functions */ 1396 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1397 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1398 union xhci_trb *start_trb, union xhci_trb *end_trb, 1399 dma_addr_t suspect_dma); 1400 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1401 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1402 void *xhci_setup_one_noop(struct xhci_hcd *xhci); 1403 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1404 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1405 u32 slot_id); 1406 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1407 u32 field1, u32 field2, u32 field3, u32 field4); 1408 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1409 unsigned int ep_index); 1410 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1411 int slot_id, unsigned int ep_index); 1412 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1413 int slot_id, unsigned int ep_index); 1414 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1415 int slot_id, unsigned int ep_index); 1416 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1417 struct urb *urb, int slot_id, unsigned int ep_index); 1418 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1419 u32 slot_id, bool command_must_succeed); 1420 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1421 u32 slot_id); 1422 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1423 unsigned int ep_index); 1424 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1425 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1426 unsigned int slot_id, unsigned int ep_index, 1427 unsigned int stream_id, struct xhci_td *cur_td, 1428 struct xhci_dequeue_state *state); 1429 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1430 unsigned int slot_id, unsigned int ep_index, 1431 unsigned int stream_id, 1432 struct xhci_dequeue_state *deq_state); 1433 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1434 struct usb_device *udev, unsigned int ep_index); 1435 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1436 unsigned int slot_id, unsigned int ep_index, 1437 struct xhci_dequeue_state *deq_state); 1438 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1439 1440 /* xHCI roothub code */ 1441 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1442 char *buf, u16 wLength); 1443 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1444 1445 /* xHCI contexts */ 1446 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1447 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1448 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1449 1450 #endif /* __LINUX_XHCI_HCD_H */ 1451