1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/bits.h> 16 #include <linux/usb.h> 17 #include <linux/timer.h> 18 #include <linux/kernel.h> 19 #include <linux/usb/hcd.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/io-64-nonatomic-hi-lo.h> 22 23 /* Code sharing between pci-quirks and xhci hcd */ 24 #include "xhci-ext-caps.h" 25 #include "pci-quirks.h" 26 27 #include "xhci-port.h" 28 #include "xhci-caps.h" 29 30 /* max buffer size for trace and debug messages */ 31 #define XHCI_MSG_MAX 500 32 33 /* xHCI PCI Configuration Registers */ 34 #define XHCI_SBRN_OFFSET (0x60) 35 36 /* 37 * Max number of Devices Slots. xHCI specification section 5.3.3 38 * Valid values are in the range of 1 to 255. 39 */ 40 #define MAX_HC_SLOTS 255 41 /* 42 * Max Number of Ports. xHCI specification section 5.3.3 43 * Valid values are in the range of 1 to 255. 44 */ 45 #define MAX_HC_PORTS 127 46 /* 47 * Max number of Interrupter Register Sets. xHCI specification section 5.3.3 48 * Valid values are in the range of 1 to 1024. 49 */ 50 #define MAX_HC_INTRS 128 51 52 /* 53 * xHCI register interface. 54 * This corresponds to the eXtensible Host Controller Interface (xHCI) 55 * Revision 0.95 specification 56 */ 57 58 /** 59 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 60 * @hc_capbase: length of the capabilities register and HC version number 61 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 62 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 63 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 64 * @hcc_params: HCCPARAMS - Capability Parameters 65 * @db_off: DBOFF - Doorbell array offset 66 * @run_regs_off: RTSOFF - Runtime register space offset 67 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 68 */ 69 struct xhci_cap_regs { 70 __le32 hc_capbase; 71 __le32 hcs_params1; 72 __le32 hcs_params2; 73 __le32 hcs_params3; 74 __le32 hcc_params; 75 __le32 db_off; 76 __le32 run_regs_off; 77 __le32 hcc_params2; /* xhci 1.1 */ 78 /* Reserved up to (CAPLENGTH - 0x1C) */ 79 }; 80 81 /* 82 * struct xhci_port_regs - Host Controller USB Port Register Set. xHCI spec 5.4.8 83 * @portsc: Port Status and Control 84 * @portpmsc: Port Power Management Status and Control 85 * @portli: Port Link Info 86 * @porthlmpc: Port Hardware LPM Control 87 */ 88 struct xhci_port_regs { 89 __le32 portsc; 90 __le32 portpmsc; 91 __le32 portli; 92 __le32 porthlmpc; 93 }; 94 95 /** 96 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 97 * @command: USBCMD - xHC command register 98 * @status: USBSTS - xHC status register 99 * @page_size: This indicates the page size that the host controller 100 * supports. If bit n is set, the HC supports a page size 101 * of 2^(n+12), up to a 128MB page size. 102 * 4K is the minimum page size. 103 * @cmd_ring: CRP - 64-bit Command Ring Pointer 104 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 105 * @config_reg: CONFIG - Configure Register 106 * @port_regs: Port Register Sets, from 1 to MaxPorts (defined by HCSPARAMS1). 107 */ 108 struct xhci_op_regs { 109 __le32 command; 110 __le32 status; 111 __le32 page_size; 112 __le32 reserved1; 113 __le32 reserved2; 114 __le32 dev_notification; 115 __le64 cmd_ring; 116 /* rsvd: offset 0x20-2F */ 117 __le32 reserved3[4]; 118 __le64 dcbaa_ptr; 119 __le32 config_reg; 120 /* rsvd: offset 0x3C-3FF */ 121 __le32 reserved4[241]; 122 struct xhci_port_regs port_regs[]; 123 }; 124 125 /* USBCMD - USB command - command bitmasks */ 126 /* start/stop HC execution - do not write unless HC is halted*/ 127 #define CMD_RUN XHCI_CMD_RUN 128 /* Reset HC - resets internal HC state machine and all registers (except 129 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 130 * The xHCI driver must reinitialize the xHC after setting this bit. 131 */ 132 #define CMD_RESET BIT(1) 133 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 134 #define CMD_EIE XHCI_CMD_EIE 135 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 136 #define CMD_HSEIE XHCI_CMD_HSEIE 137 /* bits 4:6 are reserved (and should be preserved on writes). */ 138 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 139 #define CMD_LRESET BIT(7) 140 /* host controller save/restore state. */ 141 #define CMD_CSS BIT(8) 142 #define CMD_CRS BIT(9) 143 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 144 #define CMD_EWE XHCI_CMD_EWE 145 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 146 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 147 * '0' means the xHC can power it off if all ports are in the disconnect, 148 * disabled, or powered-off state. 149 */ 150 #define CMD_PM_INDEX BIT(11) 151 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 152 #define CMD_ETE BIT(14) 153 /* bits 15:31 are reserved (and should be preserved on writes). */ 154 155 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 156 #define XHCI_RESET_SHORT_USEC (250 * 1000) 157 158 /* USBSTS - USB status - status bitmasks */ 159 /* HC not running - set to 1 when run/stop bit is cleared. */ 160 #define STS_HALT XHCI_STS_HALT 161 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 162 #define STS_FATAL BIT(2) 163 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 164 #define STS_EINT BIT(3) 165 /* port change detect */ 166 #define STS_PORT BIT(4) 167 /* bits 5:7 reserved and zeroed */ 168 /* save state status - '1' means xHC is saving state */ 169 #define STS_SAVE BIT(8) 170 /* restore state status - '1' means xHC is restoring state */ 171 #define STS_RESTORE BIT(9) 172 /* true: save or restore error */ 173 #define STS_SRE BIT(10) 174 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 175 #define STS_CNR XHCI_STS_CNR 176 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 177 #define STS_HCE BIT(12) 178 /* bits 13:31 reserved and should be preserved */ 179 180 /* 181 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 182 * Generate a device notification event when the HC sees a transaction with a 183 * notification type that matches a bit set in this bit field. 184 */ 185 #define DEV_NOTE_MASK (0xffff) 186 /* Most of the device notification types should only be used for debug. 187 * SW does need to pay attention to function wake notifications. 188 */ 189 #define DEV_NOTE_FWAKE BIT(1) 190 191 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 192 /* bit 0 - Cycle bit indicates the ownership of the command ring */ 193 #define CMD_RING_CYCLE BIT_ULL(0) 194 /* stop ring operation after completion of the currently executing command */ 195 #define CMD_RING_PAUSE BIT_ULL(1) 196 /* stop ring immediately - abort the currently executing command */ 197 #define CMD_RING_ABORT BIT_ULL(2) 198 /* true: command ring is running */ 199 #define CMD_RING_RUNNING BIT_ULL(3) 200 /* bits 63:6 - Command Ring pointer */ 201 #define CMD_RING_PTR_MASK GENMASK_ULL(63, 6) 202 203 /* CONFIG - Configure Register - config_reg bitmasks */ 204 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 205 #define MAX_DEVS(p) ((p) & 0xff) 206 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 207 #define CONFIG_U3E BIT(8) 208 /* bit 9: Configuration Information Enable, xhci 1.1 */ 209 #define CONFIG_CIE BIT(9) 210 /* bits 10:31 - reserved and should be preserved */ 211 212 /* bits 15:0 - HCD page shift bit */ 213 #define XHCI_PAGE_SIZE_MASK 0xffff 214 215 /** 216 * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2. 217 * @iman: IMAN - Interrupt Management Register. Used to enable 218 * interrupts and check for pending interrupts. 219 * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts. 220 * @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST). 221 * @erst_base: ERSTBA - Event ring segment table base address. 222 * @erst_dequeue: ERDP - Event ring dequeue pointer. 223 * 224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 225 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 226 * multiple segments of the same size. The HC places events on the ring and 227 * "updates the Cycle bit in the TRBs to indicate to software the current 228 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 229 * updates the dequeue pointer. 230 */ 231 struct xhci_intr_reg { 232 __le32 iman; 233 __le32 imod; 234 __le32 erst_size; 235 __le32 rsvd; 236 __le64 erst_base; 237 __le64 erst_dequeue; 238 }; 239 240 /* iman bitmasks */ 241 /* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */ 242 #define IMAN_IP BIT(0) 243 /* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */ 244 #define IMAN_IE BIT(1) 245 246 /* imod bitmasks */ 247 /* 248 * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts 249 * (in 250ns intervals). The interval between interrupts will be longer if there are no 250 * events on the event ring. Default is 4000 (1 ms). 251 */ 252 #define IMODI_MASK (0xffff) 253 /* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */ 254 #define IMODC_MASK (0xffff << 16) 255 256 /* erst_size bitmasks */ 257 /* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */ 258 #define ERST_SIZE_MASK (0xffff) 259 260 /* erst_base bitmasks */ 261 /* bits 63:6 - Event Ring Segment Table Base Address Register */ 262 #define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6) 263 264 /* erst_dequeue bitmasks */ 265 /* 266 * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the 267 * current dequeue pointer lies. This is an optional HW hint. 268 */ 269 #define ERST_DESI_MASK (0x7) 270 /* 271 * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by 272 * a work queue (or delayed service routine)? 273 */ 274 #define ERST_EHB BIT_ULL(3) 275 /* bits 63:4 - Event Ring Dequeue Pointer */ 276 #define ERST_PTR_MASK GENMASK_ULL(63, 4) 277 278 /** 279 * struct xhci_run_regs 280 * @microframe_index: 281 * MFINDEX - current microframe number 282 * 283 * Section 5.5 Host Controller Runtime Registers: 284 * "Software should read and write these registers using only Dword (32 bit) 285 * or larger accesses" 286 */ 287 struct xhci_run_regs { 288 __le32 microframe_index; 289 __le32 rsvd[7]; 290 struct xhci_intr_reg ir_set[1024]; 291 }; 292 293 /** 294 * struct doorbell_array 295 * 296 * Bits 0 - 7: Endpoint target 297 * Bits 8 - 15: RsvdZ 298 * Bits 16 - 31: Stream ID 299 * 300 * Section 5.6 301 */ 302 struct xhci_doorbell_array { 303 __le32 doorbell[256]; 304 }; 305 306 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 307 #define DB_VALUE_HOST 0x00000000 308 309 #define PLT_MASK (0x03 << 6) 310 #define PLT_SYM (0x00 << 6) 311 #define PLT_ASYM_RX (0x02 << 6) 312 #define PLT_ASYM_TX (0x03 << 6) 313 314 /** 315 * struct xhci_container_ctx 316 * @type: Type of context. Used to calculated offsets to contained contexts. 317 * @size: Size of the context data 318 * @bytes: The raw context data given to HW 319 * @dma: dma address of the bytes 320 * 321 * Represents either a Device or Input context. Holds a pointer to the raw 322 * memory used for the context (bytes) and dma address of it (dma). 323 */ 324 struct xhci_container_ctx { 325 unsigned type; 326 #define XHCI_CTX_TYPE_DEVICE 0x1 327 #define XHCI_CTX_TYPE_INPUT 0x2 328 329 int size; 330 331 u8 *bytes; 332 dma_addr_t dma; 333 }; 334 335 /** 336 * struct xhci_slot_ctx 337 * @dev_info: Route string, device speed, hub info, and last valid endpoint 338 * @dev_info2: Max exit latency for device number, root hub port number 339 * @tt_info: tt_info is used to construct split transaction tokens 340 * @dev_state: slot state and device address 341 * 342 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 343 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 344 * reserved at the end of the slot context for HC internal use. 345 */ 346 struct xhci_slot_ctx { 347 __le32 dev_info; 348 __le32 dev_info2; 349 __le32 tt_info; 350 __le32 dev_state; 351 /* offset 0x10 to 0x1f reserved for HC internal use */ 352 __le32 reserved[4]; 353 }; 354 355 /* dev_info bitmasks */ 356 /* Route String - 0:19 */ 357 #define ROUTE_STRING_MASK (0xfffff) 358 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 359 #define DEV_SPEED (0xf << 20) 360 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 361 /* bit 24 reserved */ 362 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 363 #define DEV_MTT BIT(25) 364 /* Set if the device is a hub - bit 26 */ 365 #define DEV_HUB BIT(26) 366 /* Index of the last valid endpoint context in this device context - 27:31 */ 367 #define LAST_CTX_MASK (0x1f << 27) 368 #define LAST_CTX(p) ((p) << 27) 369 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 370 #define SLOT_FLAG BIT(0) 371 #define EP0_FLAG BIT(1) 372 373 /* dev_info2 bitmasks */ 374 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 375 #define MAX_EXIT (0xffff) 376 /* Root hub port number that is needed to access the USB device */ 377 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 378 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 379 /* Maximum number of ports under a hub device */ 380 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 381 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 382 383 /* tt_info bitmasks */ 384 /* 385 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 386 * The Slot ID of the hub that isolates the high speed signaling from 387 * this low or full-speed device. '0' if attached to root hub port. 388 */ 389 #define TT_SLOT (0xff) 390 /* 391 * The number of the downstream facing port of the high-speed hub 392 * '0' if the device is not low or full speed. 393 */ 394 #define TT_PORT (0xff << 8) 395 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 396 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 397 398 /* dev_state bitmasks */ 399 /* USB device address - assigned by the HC */ 400 #define DEV_ADDR_MASK (0xff) 401 /* bits 8:26 reserved */ 402 /* Slot state */ 403 #define SLOT_STATE (0x1f << 27) 404 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 405 406 #define SLOT_STATE_DISABLED 0 407 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 408 #define SLOT_STATE_DEFAULT 1 409 #define SLOT_STATE_ADDRESSED 2 410 #define SLOT_STATE_CONFIGURED 3 411 412 /** 413 * struct xhci_ep_ctx 414 * @ep_info: endpoint state, streams, mult, and interval information. 415 * @ep_info2: information on endpoint type, max packet size, max burst size, 416 * error count, and whether the HC will force an event for all 417 * transactions. 418 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 419 * defines one stream, this points to the endpoint transfer ring. 420 * Otherwise, it points to a stream context array, which has a 421 * ring pointer for each flow. 422 * @tx_info: 423 * Average TRB lengths for the endpoint ring and 424 * max payload within an Endpoint Service Interval Time (ESIT). 425 * 426 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 427 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 428 * reserved at the end of the endpoint context for HC internal use. 429 */ 430 struct xhci_ep_ctx { 431 __le32 ep_info; 432 __le32 ep_info2; 433 __le64 deq; 434 __le32 tx_info; 435 /* offset 0x14 - 0x1f reserved for HC internal use */ 436 __le32 reserved[3]; 437 }; 438 439 /* ep_info bitmasks */ 440 /* 441 * Endpoint State - bits 0:2 442 * 0 - disabled 443 * 1 - running 444 * 2 - halted due to halt condition - ok to manipulate endpoint ring 445 * 3 - stopped 446 * 4 - TRB error 447 * 5-7 - reserved 448 */ 449 #define EP_STATE_MASK (0x7) 450 #define EP_STATE_DISABLED 0 451 #define EP_STATE_RUNNING 1 452 #define EP_STATE_HALTED 2 453 #define EP_STATE_STOPPED 3 454 #define EP_STATE_ERROR 4 455 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 456 457 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 458 #define EP_MULT(p) (((p) & 0x3) << 8) 459 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 460 /* bits 10:14 are Max Primary Streams */ 461 /* bit 15 is Linear Stream Array */ 462 /* Interval - period between requests to an endpoint - 125u increments. */ 463 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 464 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 465 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 466 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 467 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 468 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 469 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 470 #define EP_HAS_LSA BIT(15) 471 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 472 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 473 474 /* ep_info2 bitmasks */ 475 /* 476 * Force Event - generate transfer events for all TRBs for this endpoint 477 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 478 */ 479 #define FORCE_EVENT (0x1) 480 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 481 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 482 #define EP_TYPE(p) ((p) << 3) 483 #define ISOC_OUT_EP 1 484 #define BULK_OUT_EP 2 485 #define INT_OUT_EP 3 486 #define CTRL_EP 4 487 #define ISOC_IN_EP 5 488 #define BULK_IN_EP 6 489 #define INT_IN_EP 7 490 /* bit 6 reserved */ 491 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 492 #define MAX_BURST(p) (((p)&0xff) << 8) 493 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 494 #define MAX_PACKET(p) (((p)&0xffff) << 16) 495 #define MAX_PACKET_MASK (0xffff << 16) 496 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 497 498 /* tx_info bitmasks */ 499 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 500 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 501 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 502 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 503 504 /* deq bitmasks */ 505 #define EP_CTX_CYCLE_MASK BIT_ULL(0) 506 /* bits 63:4 - TR Dequeue Pointer */ 507 #define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4) 508 509 510 /** 511 * struct xhci_input_control_context 512 * Input control context; see section 6.2.5. 513 * 514 * @drop_context: set the bit of the endpoint context you want to disable 515 * @add_context: set the bit of the endpoint context you want to enable 516 */ 517 struct xhci_input_control_ctx { 518 __le32 drop_flags; 519 __le32 add_flags; 520 __le32 rsvd2[6]; 521 }; 522 523 #define EP_IS_ADDED(ctrl_ctx, i) \ 524 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 525 #define EP_IS_DROPPED(ctrl_ctx, i) \ 526 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 527 528 /* Represents everything that is needed to issue a command on the command ring. 529 * It's useful to pre-allocate these for commands that cannot fail due to 530 * out-of-memory errors, like freeing streams. 531 */ 532 struct xhci_command { 533 /* Input context for changing device state */ 534 struct xhci_container_ctx *in_ctx; 535 u32 status; 536 u32 comp_param; 537 int slot_id; 538 /* If completion is null, no one is waiting on this command 539 * and the structure can be freed after the command completes. 540 */ 541 struct completion *completion; 542 union xhci_trb *command_trb; 543 struct list_head cmd_list; 544 /* xHCI command response timeout in milliseconds */ 545 unsigned int timeout_ms; 546 }; 547 548 /* drop context bitmasks */ 549 #define DROP_EP(x) (0x1 << x) 550 /* add context bitmasks */ 551 #define ADD_EP(x) (0x1 << x) 552 553 struct xhci_stream_ctx { 554 /* 64-bit stream ring address, cycle state, and stream type */ 555 __le64 stream_ring; 556 /* offset 0x14 - 0x1f reserved for HC internal use */ 557 __le32 reserved[2]; 558 }; 559 560 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 561 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 562 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 563 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 564 #define SCT_SEC_TR 0 565 /* Primary stream array type, dequeue pointer is to a transfer ring */ 566 #define SCT_PRI_TR 1 567 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 568 #define SCT_SSA_8 2 569 #define SCT_SSA_16 3 570 #define SCT_SSA_32 4 571 #define SCT_SSA_64 5 572 #define SCT_SSA_128 6 573 #define SCT_SSA_256 7 574 575 /* Assume no secondary streams for now */ 576 struct xhci_stream_info { 577 struct xhci_ring **stream_rings; 578 /* Number of streams, including stream 0 (which drivers can't use) */ 579 unsigned int num_streams; 580 /* The stream context array may be bigger than 581 * the number of streams the driver asked for 582 */ 583 struct xhci_stream_ctx *stream_ctx_array; 584 unsigned int num_stream_ctxs; 585 dma_addr_t ctx_array_dma; 586 /* For mapping physical TRB addresses to segments in stream rings */ 587 struct radix_tree_root trb_address_map; 588 struct xhci_command *free_streams_command; 589 }; 590 591 #define SMALL_STREAM_ARRAY_SIZE 256 592 #define MEDIUM_STREAM_ARRAY_SIZE 1024 593 #define GET_PORT_BW_ARRAY_SIZE 256 594 595 /* Some Intel xHCI host controllers need software to keep track of the bus 596 * bandwidth. Keep track of endpoint info here. Each root port is allocated 597 * the full bus bandwidth. We must also treat TTs (including each port under a 598 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 599 * (DMI) also limits the total bandwidth (across all domains) that can be used. 600 */ 601 struct xhci_bw_info { 602 /* ep_interval is zero-based */ 603 unsigned int ep_interval; 604 /* mult and num_packets are one-based */ 605 unsigned int mult; 606 unsigned int num_packets; 607 unsigned int max_packet_size; 608 unsigned int max_esit_payload; 609 unsigned int type; 610 }; 611 612 /* "Block" sizes in bytes the hardware uses for different device speeds. 613 * The logic in this part of the hardware limits the number of bits the hardware 614 * can use, so must represent bandwidth in a less precise manner to mimic what 615 * the scheduler hardware computes. 616 */ 617 #define FS_BLOCK 1 618 #define HS_BLOCK 4 619 #define SS_BLOCK 16 620 #define DMI_BLOCK 32 621 622 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 623 * with each byte transferred. SuperSpeed devices have an initial overhead to 624 * set up bursts. These are in blocks, see above. LS overhead has already been 625 * translated into FS blocks. 626 */ 627 #define DMI_OVERHEAD 8 628 #define DMI_OVERHEAD_BURST 4 629 #define SS_OVERHEAD 8 630 #define SS_OVERHEAD_BURST 32 631 #define HS_OVERHEAD 26 632 #define FS_OVERHEAD 20 633 #define LS_OVERHEAD 128 634 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 635 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 636 * of overhead associated with split transfers crossing microframe boundaries. 637 * 31 blocks is pure protocol overhead. 638 */ 639 #define TT_HS_OVERHEAD (31 + 94) 640 #define TT_DMI_OVERHEAD (25 + 12) 641 642 /* Bandwidth limits in blocks */ 643 #define FS_BW_LIMIT 1285 644 #define TT_BW_LIMIT 1320 645 #define HS_BW_LIMIT 1607 646 #define SS_BW_LIMIT_IN 3906 647 #define DMI_BW_LIMIT_IN 3906 648 #define SS_BW_LIMIT_OUT 3906 649 #define DMI_BW_LIMIT_OUT 3906 650 651 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 652 #define FS_BW_RESERVED 10 653 #define HS_BW_RESERVED 20 654 #define SS_BW_RESERVED 10 655 656 struct xhci_virt_ep { 657 struct xhci_virt_device *vdev; /* parent */ 658 unsigned int ep_index; 659 struct xhci_ring *ring; 660 /* Related to endpoints that are configured to use stream IDs only */ 661 struct xhci_stream_info *stream_info; 662 /* Temporary storage in case the configure endpoint command fails and we 663 * have to restore the device state to the previous state 664 */ 665 struct xhci_ring *new_ring; 666 unsigned int err_count; 667 unsigned int ep_state; 668 #define SET_DEQ_PENDING BIT(0) 669 #define EP_HALTED BIT(1) /* For stall handling */ 670 #define EP_STOP_CMD_PENDING BIT(2) /* For URB cancellation */ 671 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 672 #define EP_GETTING_STREAMS BIT(3) 673 #define EP_HAS_STREAMS BIT(4) 674 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 675 #define EP_GETTING_NO_STREAMS BIT(5) 676 #define EP_HARD_CLEAR_TOGGLE BIT(6) 677 #define EP_SOFT_CLEAR_TOGGLE BIT(7) 678 /* usb_hub_clear_tt_buffer is in progress */ 679 #define EP_CLEARING_TT BIT(8) 680 /* ---- Related to URB cancellation ---- */ 681 struct list_head cancelled_td_list; 682 struct xhci_hcd *xhci; 683 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 684 * command. We'll need to update the ring's dequeue segment and dequeue 685 * pointer after the command completes. 686 */ 687 struct xhci_segment *queued_deq_seg; 688 union xhci_trb *queued_deq_ptr; 689 /* 690 * Sometimes the xHC can not process isochronous endpoint ring quickly 691 * enough, and it will miss some isoc tds on the ring and generate 692 * a Missed Service Error Event. 693 * Set skip flag when receive a Missed Service Error Event and 694 * process the missed tds on the endpoint ring. 695 */ 696 bool skip; 697 /* Bandwidth checking storage */ 698 struct xhci_bw_info bw_info; 699 struct list_head bw_endpoint_list; 700 unsigned long stop_time; 701 /* Isoch Frame ID checking storage */ 702 int next_frame_id; 703 /* Use new Isoch TRB layout needed for extended TBC support */ 704 bool use_extended_tbc; 705 /* set if this endpoint is controlled via sideband access*/ 706 struct xhci_sideband *sideband; 707 }; 708 709 enum xhci_overhead_type { 710 LS_OVERHEAD_TYPE = 0, 711 FS_OVERHEAD_TYPE, 712 HS_OVERHEAD_TYPE, 713 }; 714 715 struct xhci_interval_bw { 716 unsigned int num_packets; 717 /* Sorted by max packet size. 718 * Head of the list is the greatest max packet size. 719 */ 720 struct list_head endpoints; 721 /* How many endpoints of each speed are present. */ 722 unsigned int overhead[3]; 723 }; 724 725 #define XHCI_MAX_INTERVAL 16 726 727 struct xhci_interval_bw_table { 728 unsigned int interval0_esit_payload; 729 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 730 /* Includes reserved bandwidth for async endpoints */ 731 unsigned int bw_used; 732 unsigned int ss_bw_in; 733 unsigned int ss_bw_out; 734 }; 735 736 #define EP_CTX_PER_DEV 31 737 738 struct xhci_virt_device { 739 int slot_id; 740 struct usb_device *udev; 741 /* 742 * Commands to the hardware are passed an "input context" that 743 * tells the hardware what to change in its data structures. 744 * The hardware will return changes in an "output context" that 745 * software must allocate for the hardware. We need to keep 746 * track of input and output contexts separately because 747 * these commands might fail and we don't trust the hardware. 748 */ 749 struct xhci_container_ctx *out_ctx; 750 /* Used for addressing devices and configuration changes */ 751 struct xhci_container_ctx *in_ctx; 752 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 753 struct xhci_port *rhub_port; 754 struct xhci_interval_bw_table *bw_table; 755 struct xhci_tt_bw_info *tt_info; 756 /* 757 * flags for state tracking based on events and issued commands. 758 * Software can not rely on states from output contexts because of 759 * latency between events and xHC updating output context values. 760 * See xhci 1.1 section 4.8.3 for more details 761 */ 762 unsigned long flags; 763 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 764 765 /* The current max exit latency for the enabled USB3 link states. */ 766 u16 current_mel; 767 /* Used for the debugfs interfaces. */ 768 void *debugfs_private; 769 /* set if this endpoint is controlled via sideband access*/ 770 struct xhci_sideband *sideband; 771 }; 772 773 /* 774 * For each roothub, keep track of the bandwidth information for each periodic 775 * interval. 776 * 777 * If a high speed hub is attached to the roothub, each TT associated with that 778 * hub is a separate bandwidth domain. The interval information for the 779 * endpoints on the devices under that TT will appear in the TT structure. 780 */ 781 struct xhci_root_port_bw_info { 782 struct list_head tts; 783 unsigned int num_active_tts; 784 struct xhci_interval_bw_table bw_table; 785 }; 786 787 struct xhci_tt_bw_info { 788 struct list_head tt_list; 789 int slot_id; 790 int ttport; 791 struct xhci_interval_bw_table bw_table; 792 int active_eps; 793 }; 794 795 796 /** 797 * struct xhci_device_context_array 798 * @ctx_array: Pointer to an array of addresses. The array size depends on Max 799 * Slots read from HCSPARAMS1. 800 * @dma: DMA address to @ctx_array 801 * 802 * Device Context Base Address Array (DCBAA) - Section 6.1. 803 * ctx_array[0]: Scratchpad Buffer Array Base Address 804 * ctx_array[1-MaxSlots]: Device Context Base Address 805 */ 806 struct xhci_device_context_array { 807 __le64 *ctx_array; 808 dma_addr_t dma; 809 }; 810 811 812 struct xhci_transfer_event { 813 /* 64-bit buffer address, or immediate data */ 814 __le64 buffer; 815 __le32 transfer_len; 816 /* This field is interpreted differently based on the type of TRB */ 817 __le32 flags; 818 }; 819 820 /* Transfer event flags bitfield, also for select command completion events */ 821 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 822 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 823 824 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 825 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 826 827 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 828 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 829 830 /* Transfer event TRB length bit mask */ 831 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 832 833 /* Completion Code - only applicable for some types of TRBs */ 834 #define COMP_CODE_MASK (0xff << 24) 835 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 836 #define COMP_INVALID 0 837 #define COMP_SUCCESS 1 838 #define COMP_DATA_BUFFER_ERROR 2 839 #define COMP_BABBLE_DETECTED_ERROR 3 840 #define COMP_USB_TRANSACTION_ERROR 4 841 #define COMP_TRB_ERROR 5 842 #define COMP_STALL_ERROR 6 843 #define COMP_RESOURCE_ERROR 7 844 #define COMP_BANDWIDTH_ERROR 8 845 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 846 #define COMP_INVALID_STREAM_TYPE_ERROR 10 847 #define COMP_SLOT_NOT_ENABLED_ERROR 11 848 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 849 #define COMP_SHORT_PACKET 13 850 #define COMP_RING_UNDERRUN 14 851 #define COMP_RING_OVERRUN 15 852 #define COMP_VF_EVENT_RING_FULL_ERROR 16 853 #define COMP_PARAMETER_ERROR 17 854 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 855 #define COMP_CONTEXT_STATE_ERROR 19 856 #define COMP_NO_PING_RESPONSE_ERROR 20 857 #define COMP_EVENT_RING_FULL_ERROR 21 858 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 859 #define COMP_MISSED_SERVICE_ERROR 23 860 #define COMP_COMMAND_RING_STOPPED 24 861 #define COMP_COMMAND_ABORTED 25 862 #define COMP_STOPPED 26 863 #define COMP_STOPPED_LENGTH_INVALID 27 864 #define COMP_STOPPED_SHORT_PACKET 28 865 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 866 #define COMP_ISOCH_BUFFER_OVERRUN 31 867 #define COMP_EVENT_LOST_ERROR 32 868 #define COMP_UNDEFINED_ERROR 33 869 #define COMP_INVALID_STREAM_ID_ERROR 34 870 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 871 #define COMP_SPLIT_TRANSACTION_ERROR 36 872 873 static inline const char *xhci_trb_comp_code_string(u8 status) 874 { 875 switch (status) { 876 case COMP_INVALID: 877 return "Invalid"; 878 case COMP_SUCCESS: 879 return "Success"; 880 case COMP_DATA_BUFFER_ERROR: 881 return "Data Buffer Error"; 882 case COMP_BABBLE_DETECTED_ERROR: 883 return "Babble Detected"; 884 case COMP_USB_TRANSACTION_ERROR: 885 return "USB Transaction Error"; 886 case COMP_TRB_ERROR: 887 return "TRB Error"; 888 case COMP_STALL_ERROR: 889 return "Stall Error"; 890 case COMP_RESOURCE_ERROR: 891 return "Resource Error"; 892 case COMP_BANDWIDTH_ERROR: 893 return "Bandwidth Error"; 894 case COMP_NO_SLOTS_AVAILABLE_ERROR: 895 return "No Slots Available Error"; 896 case COMP_INVALID_STREAM_TYPE_ERROR: 897 return "Invalid Stream Type Error"; 898 case COMP_SLOT_NOT_ENABLED_ERROR: 899 return "Slot Not Enabled Error"; 900 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 901 return "Endpoint Not Enabled Error"; 902 case COMP_SHORT_PACKET: 903 return "Short Packet"; 904 case COMP_RING_UNDERRUN: 905 return "Ring Underrun"; 906 case COMP_RING_OVERRUN: 907 return "Ring Overrun"; 908 case COMP_VF_EVENT_RING_FULL_ERROR: 909 return "VF Event Ring Full Error"; 910 case COMP_PARAMETER_ERROR: 911 return "Parameter Error"; 912 case COMP_BANDWIDTH_OVERRUN_ERROR: 913 return "Bandwidth Overrun Error"; 914 case COMP_CONTEXT_STATE_ERROR: 915 return "Context State Error"; 916 case COMP_NO_PING_RESPONSE_ERROR: 917 return "No Ping Response Error"; 918 case COMP_EVENT_RING_FULL_ERROR: 919 return "Event Ring Full Error"; 920 case COMP_INCOMPATIBLE_DEVICE_ERROR: 921 return "Incompatible Device Error"; 922 case COMP_MISSED_SERVICE_ERROR: 923 return "Missed Service Error"; 924 case COMP_COMMAND_RING_STOPPED: 925 return "Command Ring Stopped"; 926 case COMP_COMMAND_ABORTED: 927 return "Command Aborted"; 928 case COMP_STOPPED: 929 return "Stopped"; 930 case COMP_STOPPED_LENGTH_INVALID: 931 return "Stopped - Length Invalid"; 932 case COMP_STOPPED_SHORT_PACKET: 933 return "Stopped - Short Packet"; 934 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 935 return "Max Exit Latency Too Large Error"; 936 case COMP_ISOCH_BUFFER_OVERRUN: 937 return "Isoch Buffer Overrun"; 938 case COMP_EVENT_LOST_ERROR: 939 return "Event Lost Error"; 940 case COMP_UNDEFINED_ERROR: 941 return "Undefined Error"; 942 case COMP_INVALID_STREAM_ID_ERROR: 943 return "Invalid Stream ID Error"; 944 case COMP_SECONDARY_BANDWIDTH_ERROR: 945 return "Secondary Bandwidth Error"; 946 case COMP_SPLIT_TRANSACTION_ERROR: 947 return "Split Transaction Error"; 948 default: 949 return "Unknown!!"; 950 } 951 } 952 953 struct xhci_link_trb { 954 /* 64-bit segment pointer*/ 955 __le64 segment_ptr; 956 __le32 intr_target; 957 __le32 control; 958 }; 959 960 /* control bitfields */ 961 #define LINK_TOGGLE BIT(1) 962 963 /* Command completion event TRB */ 964 struct xhci_event_cmd { 965 /* Pointer to command TRB, or the value passed by the event data trb */ 966 __le64 cmd_trb; 967 __le32 status; 968 __le32 flags; 969 }; 970 971 /* status bitmasks */ 972 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 973 974 /* Address device - disable SetAddress */ 975 #define TRB_BSR BIT(9) 976 977 /* Configure Endpoint - Deconfigure */ 978 #define TRB_DC BIT(9) 979 980 /* Stop Ring - Transfer State Preserve */ 981 #define TRB_TSP BIT(9) 982 983 enum xhci_ep_reset_type { 984 EP_HARD_RESET, 985 EP_SOFT_RESET, 986 }; 987 988 /* Force Event */ 989 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 990 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 991 992 /* Set Latency Tolerance Value */ 993 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 994 995 /* Get Port Bandwidth */ 996 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 997 998 /* Force Header */ 999 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1000 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1001 1002 enum xhci_setup_dev { 1003 SETUP_CONTEXT_ONLY, 1004 SETUP_CONTEXT_ADDRESS, 1005 }; 1006 1007 /* bits 16:23 are the virtual function ID */ 1008 /* bits 24:31 are the slot ID */ 1009 1010 /* bits 19:16 are the dev speed */ 1011 #define DEV_SPEED_FOR_TRB(p) ((p) << 16) 1012 1013 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1014 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1015 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1016 #define LAST_EP_INDEX 30 1017 1018 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1019 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1020 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1021 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1022 1023 /* Link TRB specific fields */ 1024 #define TRB_TC BIT(1) 1025 1026 /* Port Status Change Event TRB fields */ 1027 /* Port ID - bits 31:24 */ 1028 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1029 1030 #define EVENT_DATA BIT(2) 1031 1032 /* Normal TRB fields */ 1033 /* transfer_len bitmasks - bits 0:16 */ 1034 #define TRB_LEN(p) ((p) & 0x1ffff) 1035 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1036 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1037 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1038 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1039 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1040 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1041 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1042 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1043 1044 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1045 #define TRB_CYCLE BIT(0) 1046 /* 1047 * Force next event data TRB to be evaluated before task switch. 1048 * Used to pass OS data back after a TD completes. 1049 */ 1050 #define TRB_ENT BIT(1) 1051 /* Interrupt on short packet */ 1052 #define TRB_ISP BIT(2) 1053 /* Set PCIe no snoop attribute */ 1054 #define TRB_NO_SNOOP BIT(3) 1055 /* Chain multiple TRBs into a TD */ 1056 #define TRB_CHAIN BIT(4) 1057 /* Interrupt on completion */ 1058 #define TRB_IOC BIT(5) 1059 /* The buffer pointer contains immediate data */ 1060 #define TRB_IDT BIT(6) 1061 /* TDs smaller than this might use IDT */ 1062 #define TRB_IDT_MAX_SIZE 8 1063 1064 /* Block Event Interrupt */ 1065 #define TRB_BEI BIT(9) 1066 1067 /* Control transfer TRB specific fields */ 1068 #define TRB_DIR_IN BIT(16) 1069 #define TRB_TX_TYPE(p) ((p) << 16) 1070 #define TRB_DATA_OUT 2 1071 #define TRB_DATA_IN 3 1072 1073 /* Isochronous TRB specific fields */ 1074 #define TRB_SIA BIT(31) 1075 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1076 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1077 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1078 #define TRB_TBC(p) (((p) & 0x3) << 7) 1079 #define GET_TBC(p) (((p) >> 7) & 0x3) 1080 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1081 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1082 1083 /* TRB cache size for xHC with TRB cache */ 1084 #define TRB_CACHE_SIZE_HS 8 1085 #define TRB_CACHE_SIZE_SS 16 1086 1087 struct xhci_generic_trb { 1088 __le32 field[4]; 1089 }; 1090 1091 union xhci_trb { 1092 struct xhci_link_trb link; 1093 struct xhci_transfer_event trans_event; 1094 struct xhci_event_cmd event_cmd; 1095 struct xhci_generic_trb generic; 1096 }; 1097 1098 /* TRB bit mask */ 1099 #define TRB_TYPE_BITMASK (0xfc00) 1100 #define TRB_TYPE(p) ((p) << 10) 1101 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1102 /* TRB type IDs */ 1103 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1104 #define TRB_NORMAL 1 1105 /* setup stage for control transfers */ 1106 #define TRB_SETUP 2 1107 /* data stage for control transfers */ 1108 #define TRB_DATA 3 1109 /* status stage for control transfers */ 1110 #define TRB_STATUS 4 1111 /* isoc transfers */ 1112 #define TRB_ISOC 5 1113 /* TRB for linking ring segments */ 1114 #define TRB_LINK 6 1115 #define TRB_EVENT_DATA 7 1116 /* Transfer Ring No-op (not for the command ring) */ 1117 #define TRB_TR_NOOP 8 1118 /* Command TRBs */ 1119 /* Enable Slot Command */ 1120 #define TRB_ENABLE_SLOT 9 1121 /* Disable Slot Command */ 1122 #define TRB_DISABLE_SLOT 10 1123 /* Address Device Command */ 1124 #define TRB_ADDR_DEV 11 1125 /* Configure Endpoint Command */ 1126 #define TRB_CONFIG_EP 12 1127 /* Evaluate Context Command */ 1128 #define TRB_EVAL_CONTEXT 13 1129 /* Reset Endpoint Command */ 1130 #define TRB_RESET_EP 14 1131 /* Stop Transfer Ring Command */ 1132 #define TRB_STOP_RING 15 1133 /* Set Transfer Ring Dequeue Pointer Command */ 1134 #define TRB_SET_DEQ 16 1135 /* Reset Device Command */ 1136 #define TRB_RESET_DEV 17 1137 /* Force Event Command (opt) */ 1138 #define TRB_FORCE_EVENT 18 1139 /* Negotiate Bandwidth Command (opt) */ 1140 #define TRB_NEG_BANDWIDTH 19 1141 /* Set Latency Tolerance Value Command (opt) */ 1142 #define TRB_SET_LT 20 1143 /* Get port bandwidth Command */ 1144 #define TRB_GET_BW 21 1145 /* Force Header Command - generate a transaction or link management packet */ 1146 #define TRB_FORCE_HEADER 22 1147 /* No-op Command - not for transfer rings */ 1148 #define TRB_CMD_NOOP 23 1149 /* TRB IDs 24-31 reserved */ 1150 /* Event TRBS */ 1151 /* Transfer Event */ 1152 #define TRB_TRANSFER 32 1153 /* Command Completion Event */ 1154 #define TRB_COMPLETION 33 1155 /* Port Status Change Event */ 1156 #define TRB_PORT_STATUS 34 1157 /* Bandwidth Request Event (opt) */ 1158 #define TRB_BANDWIDTH_EVENT 35 1159 /* Doorbell Event (opt) */ 1160 #define TRB_DOORBELL 36 1161 /* Host Controller Event */ 1162 #define TRB_HC_EVENT 37 1163 /* Device Notification Event - device sent function wake notification */ 1164 #define TRB_DEV_NOTE 38 1165 /* MFINDEX Wrap Event - microframe counter wrapped */ 1166 #define TRB_MFINDEX_WRAP 39 1167 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1168 #define TRB_VENDOR_DEFINED_LOW 48 1169 /* Nec vendor-specific command completion event. */ 1170 #define TRB_NEC_CMD_COMP 48 1171 /* Get NEC firmware revision. */ 1172 #define TRB_NEC_GET_FW 49 1173 1174 static inline const char *xhci_trb_type_string(u8 type) 1175 { 1176 switch (type) { 1177 case TRB_NORMAL: 1178 return "Normal"; 1179 case TRB_SETUP: 1180 return "Setup Stage"; 1181 case TRB_DATA: 1182 return "Data Stage"; 1183 case TRB_STATUS: 1184 return "Status Stage"; 1185 case TRB_ISOC: 1186 return "Isoch"; 1187 case TRB_LINK: 1188 return "Link"; 1189 case TRB_EVENT_DATA: 1190 return "Event Data"; 1191 case TRB_TR_NOOP: 1192 return "No-Op"; 1193 case TRB_ENABLE_SLOT: 1194 return "Enable Slot Command"; 1195 case TRB_DISABLE_SLOT: 1196 return "Disable Slot Command"; 1197 case TRB_ADDR_DEV: 1198 return "Address Device Command"; 1199 case TRB_CONFIG_EP: 1200 return "Configure Endpoint Command"; 1201 case TRB_EVAL_CONTEXT: 1202 return "Evaluate Context Command"; 1203 case TRB_RESET_EP: 1204 return "Reset Endpoint Command"; 1205 case TRB_STOP_RING: 1206 return "Stop Ring Command"; 1207 case TRB_SET_DEQ: 1208 return "Set TR Dequeue Pointer Command"; 1209 case TRB_RESET_DEV: 1210 return "Reset Device Command"; 1211 case TRB_FORCE_EVENT: 1212 return "Force Event Command"; 1213 case TRB_NEG_BANDWIDTH: 1214 return "Negotiate Bandwidth Command"; 1215 case TRB_SET_LT: 1216 return "Set Latency Tolerance Value Command"; 1217 case TRB_GET_BW: 1218 return "Get Port Bandwidth Command"; 1219 case TRB_FORCE_HEADER: 1220 return "Force Header Command"; 1221 case TRB_CMD_NOOP: 1222 return "No-Op Command"; 1223 case TRB_TRANSFER: 1224 return "Transfer Event"; 1225 case TRB_COMPLETION: 1226 return "Command Completion Event"; 1227 case TRB_PORT_STATUS: 1228 return "Port Status Change Event"; 1229 case TRB_BANDWIDTH_EVENT: 1230 return "Bandwidth Request Event"; 1231 case TRB_DOORBELL: 1232 return "Doorbell Event"; 1233 case TRB_HC_EVENT: 1234 return "Host Controller Event"; 1235 case TRB_DEV_NOTE: 1236 return "Device Notification Event"; 1237 case TRB_MFINDEX_WRAP: 1238 return "MFINDEX Wrap Event"; 1239 case TRB_NEC_CMD_COMP: 1240 return "NEC Command Completion Event"; 1241 case TRB_NEC_GET_FW: 1242 return "NET Get Firmware Revision Command"; 1243 default: 1244 return "UNKNOWN"; 1245 } 1246 } 1247 1248 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1249 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1250 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1251 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1252 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1253 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1254 1255 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1256 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1257 1258 /* 1259 * TRBS_PER_SEGMENT must be a multiple of 4, 1260 * since the command ring is 64-byte aligned. 1261 * It must also be greater than 16. 1262 */ 1263 #define TRBS_PER_SEGMENT 256 1264 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1265 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1266 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1267 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1268 /* TRB buffer pointers can't cross 64KB boundaries */ 1269 #define TRB_MAX_BUFF_SHIFT 16 1270 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1271 /* How much data is left before the 64KB boundary? */ 1272 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1273 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1274 #define MAX_SOFT_RETRY 3 1275 /* 1276 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1277 * XHCI_AVOID_BEI quirk is in use. 1278 */ 1279 #define AVOID_BEI_INTERVAL_MIN 8 1280 #define AVOID_BEI_INTERVAL_MAX 32 1281 1282 #define xhci_for_each_ring_seg(head, seg) \ 1283 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1284 1285 struct xhci_segment { 1286 union xhci_trb *trbs; 1287 /* private to HCD */ 1288 struct xhci_segment *next; 1289 unsigned int num; 1290 dma_addr_t dma; 1291 /* Max packet sized bounce buffer for td-fragmant alignment */ 1292 dma_addr_t bounce_dma; 1293 void *bounce_buf; 1294 unsigned int bounce_offs; 1295 unsigned int bounce_len; 1296 }; 1297 1298 enum xhci_cancelled_td_status { 1299 TD_DIRTY = 0, 1300 TD_HALTED, 1301 TD_CLEARING_CACHE, 1302 TD_CLEARING_CACHE_DEFERRED, 1303 TD_CLEARED, 1304 }; 1305 1306 struct xhci_td { 1307 struct list_head td_list; 1308 struct list_head cancelled_td_list; 1309 int status; 1310 enum xhci_cancelled_td_status cancel_status; 1311 struct urb *urb; 1312 struct xhci_segment *start_seg; 1313 union xhci_trb *start_trb; 1314 struct xhci_segment *end_seg; 1315 union xhci_trb *end_trb; 1316 struct xhci_segment *bounce_seg; 1317 /* actual_length of the URB has already been set */ 1318 bool urb_length_set; 1319 bool error_mid_td; 1320 }; 1321 1322 /* 1323 * xHCI command default timeout value in milliseconds. 1324 * USB 3.2 spec, section 9.2.6.1 1325 */ 1326 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1327 1328 /* command descriptor */ 1329 struct xhci_cd { 1330 struct xhci_command *command; 1331 union xhci_trb *cmd_trb; 1332 }; 1333 1334 enum xhci_ring_type { 1335 TYPE_CTRL = 0, 1336 TYPE_ISOC, 1337 TYPE_BULK, 1338 TYPE_INTR, 1339 TYPE_STREAM, 1340 TYPE_COMMAND, 1341 TYPE_EVENT, 1342 }; 1343 1344 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1345 { 1346 switch (type) { 1347 case TYPE_CTRL: 1348 return "CTRL"; 1349 case TYPE_ISOC: 1350 return "ISOC"; 1351 case TYPE_BULK: 1352 return "BULK"; 1353 case TYPE_INTR: 1354 return "INTR"; 1355 case TYPE_STREAM: 1356 return "STREAM"; 1357 case TYPE_COMMAND: 1358 return "CMD"; 1359 case TYPE_EVENT: 1360 return "EVENT"; 1361 } 1362 1363 return "UNKNOWN"; 1364 } 1365 1366 struct xhci_ring { 1367 struct xhci_segment *first_seg; 1368 struct xhci_segment *last_seg; 1369 union xhci_trb *enqueue; 1370 struct xhci_segment *enq_seg; 1371 union xhci_trb *dequeue; 1372 struct xhci_segment *deq_seg; 1373 struct list_head td_list; 1374 /* 1375 * Write the cycle state into the TRB cycle field to give ownership of 1376 * the TRB to the host controller (if we are the producer), or to check 1377 * if we own the TRB (if we are the consumer). See section 4.9.1. 1378 */ 1379 u32 cycle_state; 1380 unsigned int stream_id; 1381 unsigned int num_segs; 1382 unsigned int bounce_buf_len; 1383 enum xhci_ring_type type; 1384 u32 old_trb_comp_code; 1385 struct radix_tree_root *trb_address_map; 1386 }; 1387 1388 struct xhci_erst_entry { 1389 /* 64-bit event ring segment address */ 1390 __le64 seg_addr; 1391 __le32 seg_size; 1392 /* Set to zero */ 1393 __le32 rsvd; 1394 }; 1395 1396 struct xhci_erst { 1397 struct xhci_erst_entry *entries; 1398 unsigned int num_entries; 1399 /* xhci->event_ring keeps track of segment dma addresses */ 1400 dma_addr_t erst_dma_addr; 1401 }; 1402 1403 struct xhci_scratchpad { 1404 u64 *sp_array; 1405 dma_addr_t sp_dma; 1406 void **sp_buffers; 1407 }; 1408 1409 struct urb_priv { 1410 int num_tds; 1411 int num_tds_done; 1412 struct xhci_td td[] __counted_by(num_tds); 1413 }; 1414 1415 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1416 #define ERST_DEFAULT_SEGS 2 1417 /* Poll every 60 seconds */ 1418 #define POLL_TIMEOUT 60 1419 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1420 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1421 /* XXX: Make these module parameters */ 1422 1423 struct s3_save { 1424 u32 command; 1425 u32 dev_nt; 1426 u64 dcbaa_ptr; 1427 u32 config_reg; 1428 }; 1429 1430 /* Use for lpm */ 1431 struct dev_info { 1432 u32 dev_id; 1433 struct list_head list; 1434 }; 1435 1436 struct xhci_bus_state { 1437 unsigned long bus_suspended; 1438 unsigned long next_statechange; 1439 1440 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1441 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1442 u32 port_c_suspend; 1443 u32 suspended_ports; 1444 u32 port_remote_wakeup; 1445 /* which ports have started to resume */ 1446 unsigned long resuming_ports; 1447 }; 1448 1449 struct xhci_interrupter { 1450 struct xhci_ring *event_ring; 1451 struct xhci_erst erst; 1452 struct xhci_intr_reg __iomem *ir_set; 1453 unsigned int intr_num; 1454 bool ip_autoclear; 1455 u32 isoc_bei_interval; 1456 /* For interrupter registers save and restore over suspend/resume */ 1457 u32 s3_iman; 1458 u32 s3_imod; 1459 u32 s3_erst_size; 1460 u64 s3_erst_base; 1461 u64 s3_erst_dequeue; 1462 }; 1463 /* 1464 * It can take up to 20 ms to transition from RExit to U0 on the 1465 * Intel Lynx Point LP xHCI host. 1466 */ 1467 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1468 struct xhci_port_cap { 1469 u32 *psi; /* array of protocol speed ID entries */ 1470 u8 psi_count; 1471 u8 psi_uid_count; 1472 u8 maj_rev; 1473 u8 min_rev; 1474 u32 protocol_caps; 1475 }; 1476 1477 struct xhci_port { 1478 struct xhci_port_regs __iomem *port_reg; 1479 int hw_portnum; 1480 int hcd_portnum; 1481 struct xhci_hub *rhub; 1482 struct xhci_port_cap *port_cap; 1483 unsigned int lpm_incapable:1; 1484 unsigned long resume_timestamp; 1485 bool rexit_active; 1486 /* Slot ID is the index of the device directly connected to the port */ 1487 int slot_id; 1488 struct completion rexit_done; 1489 struct completion u3exit_done; 1490 }; 1491 1492 struct xhci_hub { 1493 struct xhci_port **ports; 1494 unsigned int num_ports; 1495 struct usb_hcd *hcd; 1496 /* keep track of bus suspend info */ 1497 struct xhci_bus_state bus_state; 1498 /* supported prococol extended capabiliy values */ 1499 u8 maj_rev; 1500 u8 min_rev; 1501 }; 1502 1503 /* There is one xhci_hcd structure per controller */ 1504 struct xhci_hcd { 1505 struct usb_hcd *main_hcd; 1506 struct usb_hcd *shared_hcd; 1507 /* glue to PCI and HCD framework */ 1508 struct xhci_cap_regs __iomem *cap_regs; 1509 struct xhci_op_regs __iomem *op_regs; 1510 struct xhci_run_regs __iomem *run_regs; 1511 struct xhci_doorbell_array __iomem *dba; 1512 1513 /* Cached register copies of read-only HC data */ 1514 __u32 hcs_params2; 1515 __u32 hcs_params3; 1516 __u32 hcc_params; 1517 __u32 hcc_params2; 1518 1519 spinlock_t lock; 1520 1521 /* packed release number */ 1522 u16 hci_version; 1523 u16 max_interrupters; 1524 u8 max_slots; 1525 u8 max_ports; 1526 /* imod_interval in ns (I * 250ns) */ 1527 u32 imod_interval; 1528 u32 page_size; 1529 unsigned int dma_mask_bits; 1530 /* MSI-X/MSI vectors */ 1531 int nvecs; 1532 /* optional clocks */ 1533 struct clk *clk; 1534 struct clk *reg_clk; 1535 /* optional reset controller */ 1536 struct reset_control *reset; 1537 /* data structures */ 1538 struct xhci_device_context_array dcbaa; 1539 struct xhci_interrupter **interrupters; 1540 struct xhci_ring *cmd_ring; 1541 unsigned int cmd_ring_state; 1542 #define CMD_RING_STATE_RUNNING BIT(0) 1543 #define CMD_RING_STATE_ABORTED BIT(1) 1544 #define CMD_RING_STATE_STOPPED BIT(2) 1545 struct list_head cmd_list; 1546 unsigned int cmd_ring_reserved_trbs; 1547 struct delayed_work cmd_timer; 1548 struct completion cmd_ring_stop_completion; 1549 struct xhci_command *current_cmd; 1550 1551 /* Scratchpad */ 1552 struct xhci_scratchpad *scratchpad; 1553 1554 /* slot enabling and address device helpers */ 1555 /* these are not thread safe so use mutex */ 1556 struct mutex mutex; 1557 /* Internal mirror of the HW's dcbaa */ 1558 struct xhci_virt_device **devs; 1559 /* For keeping track of bandwidth domains per roothub. */ 1560 struct xhci_root_port_bw_info *rh_bw; 1561 1562 /* DMA pools */ 1563 struct dma_pool *device_pool; 1564 struct dma_pool *segment_pool; 1565 struct dma_pool *small_streams_pool; 1566 struct dma_pool *port_bw_pool; 1567 struct dma_pool *medium_streams_pool; 1568 1569 /* Host controller watchdog timer structures */ 1570 unsigned int xhc_state; 1571 unsigned long run_graceperiod; 1572 struct s3_save s3; 1573 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1574 * 1575 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1576 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1577 * that sees this status (other than the timer that set it) should stop touching 1578 * hardware immediately. Interrupt handlers should return immediately when 1579 * they see this status (any time they drop and re-acquire xhci->lock). 1580 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1581 * putting the TD on the canceled list, etc. 1582 * 1583 * There are no reports of xHCI host controllers that display this issue. 1584 */ 1585 #define XHCI_STATE_DYING BIT(0) 1586 #define XHCI_STATE_HALTED BIT(1) 1587 #define XHCI_STATE_REMOVING BIT(2) 1588 unsigned long long quirks; 1589 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1590 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1591 #define XHCI_NEC_HOST BIT_ULL(2) 1592 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1593 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1594 /* 1595 * Certain Intel host controllers have a limit to the number of endpoint 1596 * contexts they can handle. Ideally, they would signal that they can't handle 1597 * anymore endpoint contexts by returning a Resource Error for the Configure 1598 * Endpoint command, but they don't. Instead they expect software to keep track 1599 * of the number of active endpoints for them, across configure endpoint 1600 * commands, reset device commands, disable slot commands, and address device 1601 * commands. 1602 */ 1603 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1604 #define XHCI_BROKEN_MSI BIT_ULL(6) 1605 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1606 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1607 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1608 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1609 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1610 #define XHCI_INTEL_HOST BIT_ULL(12) 1611 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1612 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1613 #define XHCI_AVOID_BEI BIT_ULL(15) 1614 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1615 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1616 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1617 /* For controllers with a broken beyond repair streams implementation */ 1618 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1619 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1620 #define XHCI_MTK_HOST BIT_ULL(21) 1621 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1622 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1623 #define XHCI_MISSING_CAS BIT_ULL(24) 1624 /* For controller with a broken Port Disable implementation */ 1625 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1626 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1627 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1628 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1629 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1630 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1631 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1632 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1633 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1634 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1635 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1636 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1637 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1638 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1639 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1640 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1641 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1642 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1643 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1644 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1645 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1646 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1647 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1648 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1649 #define XHCI_ETRON_HOST BIT_ULL(49) 1650 #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50) 1651 1652 unsigned int num_active_eps; 1653 unsigned int limit_active_eps; 1654 struct xhci_port *hw_ports; 1655 struct xhci_hub usb2_rhub; 1656 struct xhci_hub usb3_rhub; 1657 /* support xHCI 1.0 spec USB2 hardware LPM */ 1658 unsigned hw_lpm_support:1; 1659 /* Broken Suspend flag for SNPS Suspend resume issue */ 1660 unsigned broken_suspend:1; 1661 /* Indicates that omitting hcd is supported if root hub has no ports */ 1662 unsigned allow_single_roothub:1; 1663 /* cached extended protocol port capabilities */ 1664 struct xhci_port_cap *port_caps; 1665 unsigned int num_port_caps; 1666 /* Compliance Mode Recovery Data */ 1667 struct timer_list comp_mode_recovery_timer; 1668 u32 port_status_u0; 1669 u16 test_mode; 1670 /* Compliance Mode Timer Triggered every 2 seconds */ 1671 #define COMP_MODE_RCVRY_MSECS 2000 1672 1673 struct dentry *debugfs_root; 1674 struct dentry *debugfs_slots; 1675 struct list_head regset_list; 1676 1677 void *dbc; 1678 /* platform-specific data -- must come last */ 1679 unsigned long priv[] __aligned(sizeof(s64)); 1680 }; 1681 1682 /* Platform specific overrides to generic XHCI hc_driver ops */ 1683 struct xhci_driver_overrides { 1684 size_t extra_priv_size; 1685 int (*reset)(struct usb_hcd *hcd); 1686 int (*start)(struct usb_hcd *hcd); 1687 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1688 struct usb_host_endpoint *ep); 1689 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1690 struct usb_host_endpoint *ep); 1691 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1692 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1693 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1694 struct usb_tt *tt, gfp_t mem_flags); 1695 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1696 u16 wIndex, char *buf, u16 wLength); 1697 }; 1698 1699 #define XHCI_CFC_DELAY 10 1700 1701 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1702 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1703 { 1704 struct usb_hcd *primary_hcd; 1705 1706 if (usb_hcd_is_primary_hcd(hcd)) 1707 primary_hcd = hcd; 1708 else 1709 primary_hcd = hcd->primary_hcd; 1710 1711 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1712 } 1713 1714 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1715 { 1716 return xhci->main_hcd; 1717 } 1718 1719 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1720 { 1721 if (xhci->shared_hcd) 1722 return xhci->shared_hcd; 1723 1724 if (!xhci->usb2_rhub.num_ports) 1725 return xhci->main_hcd; 1726 1727 return NULL; 1728 } 1729 1730 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1731 { 1732 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1733 1734 return hcd == xhci_get_usb3_hcd(xhci); 1735 } 1736 1737 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1738 { 1739 return xhci->allow_single_roothub && 1740 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1741 } 1742 1743 #define xhci_dbg(xhci, fmt, args...) \ 1744 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1745 #define xhci_err(xhci, fmt, args...) \ 1746 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1747 #define xhci_warn(xhci, fmt, args...) \ 1748 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1749 #define xhci_info(xhci, fmt, args...) \ 1750 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1751 1752 /* 1753 * Registers should always be accessed with double word or quad word accesses. 1754 * 1755 * Some xHCI implementations may support 64-bit address pointers. Registers 1756 * with 64-bit address pointers should be written to with dword accesses by 1757 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1758 * xHCI implementations that do not support 64-bit address pointers will ignore 1759 * the high dword, and write order is irrelevant. 1760 */ 1761 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1762 __le64 __iomem *regs) 1763 { 1764 return lo_hi_readq(regs); 1765 } 1766 static inline void xhci_write_64(struct xhci_hcd *xhci, 1767 const u64 val, __le64 __iomem *regs) 1768 { 1769 lo_hi_writeq(val, regs); 1770 } 1771 1772 1773 /* 1774 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1775 * Other chapters and later specs say that it should only be set if the link is inside a TD 1776 * which continues from the end of one segment to the next segment. 1777 * 1778 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1779 * 1780 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1781 * "resynchronizing the pipe" after a Missed Service Error. 1782 */ 1783 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1784 { 1785 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1786 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1787 } 1788 1789 /* xHCI debugging */ 1790 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1791 struct xhci_container_ctx *ctx); 1792 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1793 const char *fmt, ...); 1794 1795 /* xHCI memory management */ 1796 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1797 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1798 void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev, int slot_id); 1799 void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id); 1800 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1801 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1802 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1803 struct usb_device *udev); 1804 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1805 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1806 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1807 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1808 struct xhci_virt_device *virt_dev, 1809 int old_active_eps); 1810 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1811 void xhci_rh_bw_cleanup(struct xhci_hcd *xhci); 1812 void xhci_update_bw_info(struct xhci_hcd *xhci, 1813 struct xhci_container_ctx *in_ctx, 1814 struct xhci_input_control_ctx *ctrl_ctx, 1815 struct xhci_virt_device *virt_dev); 1816 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1817 struct xhci_container_ctx *in_ctx, 1818 struct xhci_container_ctx *out_ctx, 1819 unsigned int ep_index); 1820 void xhci_slot_copy(struct xhci_hcd *xhci, 1821 struct xhci_container_ctx *in_ctx, 1822 struct xhci_container_ctx *out_ctx); 1823 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1824 struct usb_device *udev, struct usb_host_endpoint *ep, 1825 gfp_t mem_flags); 1826 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1827 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1828 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1829 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1830 unsigned int num_trbs, gfp_t flags); 1831 void xhci_initialize_ring_info(struct xhci_ring *ring); 1832 void xhci_ring_init(struct xhci_hcd *xhci, struct xhci_ring *ring); 1833 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1834 struct xhci_virt_device *virt_dev, 1835 unsigned int ep_index); 1836 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1837 unsigned int num_stream_ctxs, 1838 unsigned int num_streams, 1839 unsigned int max_packet, gfp_t flags); 1840 void xhci_free_stream_info(struct xhci_hcd *xhci, 1841 struct xhci_stream_info *stream_info); 1842 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1843 struct xhci_ep_ctx *ep_ctx, 1844 struct xhci_stream_info *stream_info); 1845 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1846 struct xhci_virt_ep *ep); 1847 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1848 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1849 struct xhci_ring *xhci_dma_to_transfer_ring( 1850 struct xhci_virt_ep *ep, 1851 u64 address); 1852 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1853 bool allocate_completion, gfp_t mem_flags); 1854 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1855 bool allocate_completion, gfp_t mem_flags); 1856 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1857 void xhci_free_command(struct xhci_hcd *xhci, 1858 struct xhci_command *command); 1859 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1860 int type, gfp_t flags); 1861 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1862 struct xhci_container_ctx *ctx); 1863 struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci, 1864 gfp_t flags); 1865 void xhci_free_port_bw_ctx(struct xhci_hcd *xhci, 1866 struct xhci_container_ctx *ctx); 1867 struct xhci_interrupter * 1868 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1869 u32 imod_interval, unsigned int intr_num); 1870 void xhci_remove_secondary_interrupter(struct usb_hcd 1871 *hcd, struct xhci_interrupter *ir); 1872 void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, 1873 struct xhci_ring *ring, 1874 struct xhci_interrupter *ir); 1875 1876 /* xHCI host controller glue */ 1877 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1878 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1879 void xhci_quiesce(struct xhci_hcd *xhci); 1880 int xhci_halt(struct xhci_hcd *xhci); 1881 int xhci_start(struct xhci_hcd *xhci); 1882 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1883 int xhci_run(struct usb_hcd *hcd); 1884 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1885 void xhci_shutdown(struct usb_hcd *hcd); 1886 void xhci_stop(struct usb_hcd *hcd); 1887 void xhci_init_driver(struct hc_driver *drv, 1888 const struct xhci_driver_overrides *over); 1889 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1890 struct usb_host_endpoint *ep); 1891 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1892 struct usb_host_endpoint *ep); 1893 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1894 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1895 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1896 struct usb_tt *tt, gfp_t mem_flags); 1897 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1898 int xhci_disable_and_free_slot(struct xhci_hcd *xhci, u32 slot_id); 1899 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1900 1901 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1902 int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1903 1904 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1905 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1906 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1907 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1908 struct xhci_virt_device *virt_dev, 1909 struct usb_device *hdev, 1910 struct usb_tt *tt, gfp_t mem_flags); 1911 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1912 u32 imod_interval); 1913 int xhci_enable_interrupter(struct xhci_interrupter *ir); 1914 int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir); 1915 1916 /* xHCI ring, segment, TRB, and TD functions */ 1917 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1918 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1919 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1920 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1921 u32 trb_type, u32 slot_id); 1922 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1923 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1924 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1925 u32 field1, u32 field2, u32 field3, u32 field4); 1926 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1927 int slot_id, unsigned int ep_index, int suspend); 1928 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1929 int slot_id, unsigned int ep_index); 1930 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1931 int slot_id, unsigned int ep_index); 1932 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1933 int slot_id, unsigned int ep_index); 1934 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1935 struct urb *urb, int slot_id, unsigned int ep_index); 1936 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1937 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1938 bool command_must_succeed); 1939 int xhci_queue_get_port_bw(struct xhci_hcd *xhci, 1940 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 1941 u8 dev_speed, bool command_must_succeed); 1942 int xhci_get_port_bandwidth(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, 1943 u8 dev_speed); 1944 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1945 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1946 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1947 int slot_id, unsigned int ep_index, 1948 enum xhci_ep_reset_type reset_type); 1949 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1950 u32 slot_id); 1951 void xhci_handle_command_timeout(struct work_struct *work); 1952 1953 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1954 unsigned int ep_index, unsigned int stream_id); 1955 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1956 unsigned int slot_id, 1957 unsigned int ep_index); 1958 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1959 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1960 unsigned int count_trbs(u64 addr, u64 len); 1961 unsigned int xhci_num_trbs_free(struct xhci_ring *ring); 1962 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1963 int suspend, gfp_t gfp_flags); 1964 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1965 void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 1966 struct xhci_interrupter *ir, 1967 bool clear_ehb); 1968 void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num); 1969 int xhci_usb_endpoint_maxp(struct usb_device *udev, 1970 struct usb_host_endpoint *host_ep); 1971 void xhci_portsc_writel(struct xhci_port *port, u32 val); 1972 u32 xhci_portsc_readl(struct xhci_port *port); 1973 1974 /* xHCI roothub code */ 1975 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1976 u32 link_state); 1977 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1978 u32 port_bit); 1979 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1980 char *buf, u16 wLength); 1981 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1982 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1983 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1984 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1985 struct xhci_port *port); 1986 void xhci_hc_died(struct xhci_hcd *xhci); 1987 1988 #ifdef CONFIG_PM 1989 int xhci_bus_suspend(struct usb_hcd *hcd); 1990 int xhci_bus_resume(struct usb_hcd *hcd); 1991 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1992 #else 1993 #define xhci_bus_suspend NULL 1994 #define xhci_bus_resume NULL 1995 #define xhci_get_resuming_ports NULL 1996 #endif /* CONFIG_PM */ 1997 1998 u32 xhci_port_state_to_neutral(u32 state); 1999 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2000 2001 /* xHCI contexts */ 2002 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2003 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2004 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2005 2006 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2007 unsigned int slot_id, unsigned int ep_index, 2008 unsigned int stream_id); 2009 2010 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2011 struct urb *urb) 2012 { 2013 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2014 xhci_get_endpoint_index(&urb->ep->desc), 2015 urb->stream_id); 2016 } 2017 2018 /* 2019 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2020 * them anyways as we where unable to find a device that matches the 2021 * constraints. 2022 */ 2023 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2024 { 2025 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2026 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2027 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2028 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2029 !urb->num_sgs) 2030 return true; 2031 2032 return false; 2033 } 2034 2035 static inline char *xhci_slot_state_string(u32 state) 2036 { 2037 switch (state) { 2038 case SLOT_STATE_ENABLED: 2039 return "enabled/disabled"; 2040 case SLOT_STATE_DEFAULT: 2041 return "default"; 2042 case SLOT_STATE_ADDRESSED: 2043 return "addressed"; 2044 case SLOT_STATE_CONFIGURED: 2045 return "configured"; 2046 default: 2047 return "reserved"; 2048 } 2049 } 2050 2051 static inline const char *xhci_decode_trb(char *str, size_t size, 2052 u32 field0, u32 field1, u32 field2, u32 field3) 2053 { 2054 int type = TRB_FIELD_TO_TYPE(field3); 2055 2056 switch (type) { 2057 case TRB_LINK: 2058 snprintf(str, size, 2059 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2060 field1, field0, GET_INTR_TARGET(field2), 2061 xhci_trb_type_string(type), 2062 field3 & TRB_IOC ? 'I' : 'i', 2063 field3 & TRB_CHAIN ? 'C' : 'c', 2064 field3 & TRB_TC ? 'T' : 't', 2065 field3 & TRB_CYCLE ? 'C' : 'c'); 2066 break; 2067 case TRB_TRANSFER: 2068 case TRB_COMPLETION: 2069 case TRB_PORT_STATUS: 2070 case TRB_BANDWIDTH_EVENT: 2071 case TRB_DOORBELL: 2072 case TRB_HC_EVENT: 2073 case TRB_DEV_NOTE: 2074 case TRB_MFINDEX_WRAP: 2075 snprintf(str, size, 2076 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2077 field1, field0, 2078 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2079 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2080 TRB_TO_EP_ID(field3), 2081 xhci_trb_type_string(type), 2082 field3 & EVENT_DATA ? 'E' : 'e', 2083 field3 & TRB_CYCLE ? 'C' : 'c'); 2084 2085 break; 2086 case TRB_SETUP: 2087 snprintf(str, size, 2088 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2089 field0 & 0xff, 2090 (field0 & 0xff00) >> 8, 2091 (field0 & 0xff000000) >> 24, 2092 (field0 & 0xff0000) >> 16, 2093 (field1 & 0xff00) >> 8, 2094 field1 & 0xff, 2095 (field1 & 0xff000000) >> 16 | 2096 (field1 & 0xff0000) >> 16, 2097 TRB_LEN(field2), GET_TD_SIZE(field2), 2098 GET_INTR_TARGET(field2), 2099 xhci_trb_type_string(type), 2100 field3 & TRB_IDT ? 'I' : 'i', 2101 field3 & TRB_IOC ? 'I' : 'i', 2102 field3 & TRB_CYCLE ? 'C' : 'c'); 2103 break; 2104 case TRB_DATA: 2105 snprintf(str, size, 2106 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2107 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2108 GET_INTR_TARGET(field2), 2109 xhci_trb_type_string(type), 2110 field3 & TRB_IDT ? 'I' : 'i', 2111 field3 & TRB_IOC ? 'I' : 'i', 2112 field3 & TRB_CHAIN ? 'C' : 'c', 2113 field3 & TRB_NO_SNOOP ? 'S' : 's', 2114 field3 & TRB_ISP ? 'I' : 'i', 2115 field3 & TRB_ENT ? 'E' : 'e', 2116 field3 & TRB_CYCLE ? 'C' : 'c'); 2117 break; 2118 case TRB_STATUS: 2119 snprintf(str, size, 2120 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2121 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2122 GET_INTR_TARGET(field2), 2123 xhci_trb_type_string(type), 2124 field3 & TRB_IOC ? 'I' : 'i', 2125 field3 & TRB_CHAIN ? 'C' : 'c', 2126 field3 & TRB_ENT ? 'E' : 'e', 2127 field3 & TRB_CYCLE ? 'C' : 'c'); 2128 break; 2129 case TRB_NORMAL: 2130 case TRB_EVENT_DATA: 2131 case TRB_TR_NOOP: 2132 snprintf(str, size, 2133 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2134 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2135 GET_INTR_TARGET(field2), 2136 xhci_trb_type_string(type), 2137 field3 & TRB_BEI ? 'B' : 'b', 2138 field3 & TRB_IDT ? 'I' : 'i', 2139 field3 & TRB_IOC ? 'I' : 'i', 2140 field3 & TRB_CHAIN ? 'C' : 'c', 2141 field3 & TRB_NO_SNOOP ? 'S' : 's', 2142 field3 & TRB_ISP ? 'I' : 'i', 2143 field3 & TRB_ENT ? 'E' : 'e', 2144 field3 & TRB_CYCLE ? 'C' : 'c'); 2145 break; 2146 case TRB_ISOC: 2147 snprintf(str, size, 2148 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2149 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2150 GET_INTR_TARGET(field2), 2151 xhci_trb_type_string(type), 2152 GET_TBC(field3), 2153 GET_TLBPC(field3), 2154 GET_FRAME_ID(field3), 2155 field3 & TRB_SIA ? 'S' : 's', 2156 field3 & TRB_BEI ? 'B' : 'b', 2157 field3 & TRB_IDT ? 'I' : 'i', 2158 field3 & TRB_IOC ? 'I' : 'i', 2159 field3 & TRB_CHAIN ? 'C' : 'c', 2160 field3 & TRB_NO_SNOOP ? 'S' : 's', 2161 field3 & TRB_ISP ? 'I' : 'i', 2162 field3 & TRB_ENT ? 'E' : 'e', 2163 field3 & TRB_CYCLE ? 'C' : 'c'); 2164 break; 2165 case TRB_CMD_NOOP: 2166 case TRB_ENABLE_SLOT: 2167 snprintf(str, size, 2168 "%s: flags %c", 2169 xhci_trb_type_string(type), 2170 field3 & TRB_CYCLE ? 'C' : 'c'); 2171 break; 2172 case TRB_DISABLE_SLOT: 2173 case TRB_NEG_BANDWIDTH: 2174 snprintf(str, size, 2175 "%s: slot %d flags %c", 2176 xhci_trb_type_string(type), 2177 TRB_TO_SLOT_ID(field3), 2178 field3 & TRB_CYCLE ? 'C' : 'c'); 2179 break; 2180 case TRB_ADDR_DEV: 2181 snprintf(str, size, 2182 "%s: ctx %08x%08x slot %d flags %c:%c", 2183 xhci_trb_type_string(type), 2184 field1, field0, 2185 TRB_TO_SLOT_ID(field3), 2186 field3 & TRB_BSR ? 'B' : 'b', 2187 field3 & TRB_CYCLE ? 'C' : 'c'); 2188 break; 2189 case TRB_CONFIG_EP: 2190 snprintf(str, size, 2191 "%s: ctx %08x%08x slot %d flags %c:%c", 2192 xhci_trb_type_string(type), 2193 field1, field0, 2194 TRB_TO_SLOT_ID(field3), 2195 field3 & TRB_DC ? 'D' : 'd', 2196 field3 & TRB_CYCLE ? 'C' : 'c'); 2197 break; 2198 case TRB_EVAL_CONTEXT: 2199 snprintf(str, size, 2200 "%s: ctx %08x%08x slot %d flags %c", 2201 xhci_trb_type_string(type), 2202 field1, field0, 2203 TRB_TO_SLOT_ID(field3), 2204 field3 & TRB_CYCLE ? 'C' : 'c'); 2205 break; 2206 case TRB_RESET_EP: 2207 snprintf(str, size, 2208 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2209 xhci_trb_type_string(type), 2210 field1, field0, 2211 TRB_TO_SLOT_ID(field3), 2212 TRB_TO_EP_ID(field3), 2213 field3 & TRB_TSP ? 'T' : 't', 2214 field3 & TRB_CYCLE ? 'C' : 'c'); 2215 break; 2216 case TRB_STOP_RING: 2217 snprintf(str, size, 2218 "%s: slot %d sp %d ep %d flags %c", 2219 xhci_trb_type_string(type), 2220 TRB_TO_SLOT_ID(field3), 2221 TRB_TO_SUSPEND_PORT(field3), 2222 TRB_TO_EP_ID(field3), 2223 field3 & TRB_CYCLE ? 'C' : 'c'); 2224 break; 2225 case TRB_SET_DEQ: 2226 snprintf(str, size, 2227 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2228 xhci_trb_type_string(type), 2229 field1, field0, 2230 TRB_TO_STREAM_ID(field2), 2231 TRB_TO_SLOT_ID(field3), 2232 TRB_TO_EP_ID(field3), 2233 field3 & TRB_CYCLE ? 'C' : 'c'); 2234 break; 2235 case TRB_RESET_DEV: 2236 snprintf(str, size, 2237 "%s: slot %d flags %c", 2238 xhci_trb_type_string(type), 2239 TRB_TO_SLOT_ID(field3), 2240 field3 & TRB_CYCLE ? 'C' : 'c'); 2241 break; 2242 case TRB_FORCE_EVENT: 2243 snprintf(str, size, 2244 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2245 xhci_trb_type_string(type), 2246 field1, field0, 2247 TRB_TO_VF_INTR_TARGET(field2), 2248 TRB_TO_VF_ID(field3), 2249 field3 & TRB_CYCLE ? 'C' : 'c'); 2250 break; 2251 case TRB_SET_LT: 2252 snprintf(str, size, 2253 "%s: belt %d flags %c", 2254 xhci_trb_type_string(type), 2255 TRB_TO_BELT(field3), 2256 field3 & TRB_CYCLE ? 'C' : 'c'); 2257 break; 2258 case TRB_GET_BW: 2259 snprintf(str, size, 2260 "%s: ctx %08x%08x slot %d speed %d flags %c", 2261 xhci_trb_type_string(type), 2262 field1, field0, 2263 TRB_TO_SLOT_ID(field3), 2264 TRB_TO_DEV_SPEED(field3), 2265 field3 & TRB_CYCLE ? 'C' : 'c'); 2266 break; 2267 case TRB_FORCE_HEADER: 2268 snprintf(str, size, 2269 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2270 xhci_trb_type_string(type), 2271 field2, field1, field0 & 0xffffffe0, 2272 TRB_TO_PACKET_TYPE(field0), 2273 TRB_TO_ROOTHUB_PORT(field3), 2274 field3 & TRB_CYCLE ? 'C' : 'c'); 2275 break; 2276 default: 2277 snprintf(str, size, 2278 "type '%s' -> raw %08x %08x %08x %08x", 2279 xhci_trb_type_string(type), 2280 field0, field1, field2, field3); 2281 } 2282 2283 return str; 2284 } 2285 2286 static inline const char *xhci_decode_ctrl_ctx(char *str, 2287 unsigned long drop, unsigned long add) 2288 { 2289 unsigned int bit; 2290 int ret = 0; 2291 2292 str[0] = '\0'; 2293 2294 if (drop) { 2295 ret = sprintf(str, "Drop:"); 2296 for_each_set_bit(bit, &drop, 32) 2297 ret += sprintf(str + ret, " %d%s", 2298 bit / 2, 2299 bit % 2 ? "in":"out"); 2300 ret += sprintf(str + ret, ", "); 2301 } 2302 2303 if (add) { 2304 ret += sprintf(str + ret, "Add:%s%s", 2305 (add & SLOT_FLAG) ? " slot":"", 2306 (add & EP0_FLAG) ? " ep0":""); 2307 add &= ~(SLOT_FLAG | EP0_FLAG); 2308 for_each_set_bit(bit, &add, 32) 2309 ret += sprintf(str + ret, " %d%s", 2310 bit / 2, 2311 bit % 2 ? "in":"out"); 2312 } 2313 return str; 2314 } 2315 2316 static inline const char *xhci_decode_slot_context(char *str, 2317 u32 info, u32 info2, u32 tt_info, u32 state) 2318 { 2319 u32 speed; 2320 u32 hub; 2321 u32 mtt; 2322 int ret = 0; 2323 2324 speed = info & DEV_SPEED; 2325 hub = info & DEV_HUB; 2326 mtt = info & DEV_MTT; 2327 2328 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2329 info & ROUTE_STRING_MASK, 2330 ({ char *s; 2331 switch (speed) { 2332 case SLOT_SPEED_FS: 2333 s = "full-speed"; 2334 break; 2335 case SLOT_SPEED_LS: 2336 s = "low-speed"; 2337 break; 2338 case SLOT_SPEED_HS: 2339 s = "high-speed"; 2340 break; 2341 case SLOT_SPEED_SS: 2342 s = "super-speed"; 2343 break; 2344 case SLOT_SPEED_SSP: 2345 s = "super-speed plus"; 2346 break; 2347 default: 2348 s = "UNKNOWN speed"; 2349 } s; }), 2350 mtt ? " multi-TT" : "", 2351 hub ? " Hub" : "", 2352 (info & LAST_CTX_MASK) >> 27, 2353 info2 & MAX_EXIT, 2354 DEVINFO_TO_ROOT_HUB_PORT(info2), 2355 DEVINFO_TO_MAX_PORTS(info2)); 2356 2357 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2358 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2359 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2360 state & DEV_ADDR_MASK, 2361 xhci_slot_state_string(GET_SLOT_STATE(state))); 2362 2363 return str; 2364 } 2365 2366 2367 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2368 { 2369 switch (portsc & PORT_PLS_MASK) { 2370 case XDEV_U0: 2371 return "U0"; 2372 case XDEV_U1: 2373 return "U1"; 2374 case XDEV_U2: 2375 return "U2"; 2376 case XDEV_U3: 2377 return "U3"; 2378 case XDEV_DISABLED: 2379 return "Disabled"; 2380 case XDEV_RXDETECT: 2381 return "RxDetect"; 2382 case XDEV_INACTIVE: 2383 return "Inactive"; 2384 case XDEV_POLLING: 2385 return "Polling"; 2386 case XDEV_RECOVERY: 2387 return "Recovery"; 2388 case XDEV_HOT_RESET: 2389 return "Hot Reset"; 2390 case XDEV_COMP_MODE: 2391 return "Compliance mode"; 2392 case XDEV_TEST_MODE: 2393 return "Test mode"; 2394 case XDEV_RESUME: 2395 return "Resume"; 2396 default: 2397 break; 2398 } 2399 return "Unknown"; 2400 } 2401 2402 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2403 { 2404 int ret; 2405 2406 ret = sprintf(str, "0x%08x ", portsc); 2407 2408 if (portsc == ~(u32)0) 2409 return str; 2410 2411 ret += sprintf(str + ret, "Speed=%d ", DEV_PORT_SPEED(portsc)); 2412 ret += sprintf(str + ret, "Link=%s ", xhci_portsc_link_state_string(portsc)); 2413 2414 /* RO/ROS: Read-only */ 2415 if (portsc & PORT_CONNECT) 2416 ret += sprintf(str + ret, "CCS "); 2417 if (portsc & PORT_OC) 2418 ret += sprintf(str + ret, "OCA "); /* No set for USB2 ports */ 2419 if (portsc & PORT_CAS) 2420 ret += sprintf(str + ret, "CAS "); 2421 if (portsc & PORT_DEV_REMOVE) 2422 ret += sprintf(str + ret, "DR "); 2423 2424 /* RWS; writing 1 sets the bit, writing 0 clears the bit. */ 2425 if (portsc & PORT_POWER) 2426 ret += sprintf(str + ret, "PP "); 2427 if (portsc & PORT_WKCONN_E) 2428 ret += sprintf(str + ret, "WCE "); 2429 if (portsc & PORT_WKDISC_E) 2430 ret += sprintf(str + ret, "WDE "); 2431 if (portsc & PORT_WKOC_E) 2432 ret += sprintf(str + ret, "WOE "); 2433 2434 /* RW; writing 1 sets the bit, writing 0 clears the bit */ 2435 if (portsc & PORT_LINK_STROBE) 2436 ret += sprintf(str + ret, "LWS "); /* LWS 0 write is ignored */ 2437 2438 /* RW1S; writing 1 sets the bit, writing 0 has no effect */ 2439 if (portsc & PORT_RESET) 2440 ret += sprintf(str + ret, "PR "); 2441 if (portsc & PORT_WR) 2442 ret += sprintf(str + ret, "WPR "); /* RsvdZ for USB2 ports */ 2443 2444 /* RW1CS; writing 1 clears the bit, writing 0 has no effect. */ 2445 if (portsc & PORT_PE) 2446 ret += sprintf(str + ret, "PED "); 2447 if (portsc & PORT_CSC) 2448 ret += sprintf(str + ret, "CSC "); 2449 if (portsc & PORT_PEC) 2450 ret += sprintf(str + ret, "PEC "); /* No set for USB3 ports */ 2451 if (portsc & PORT_WRC) 2452 ret += sprintf(str + ret, "WRC "); /* RsvdZ for USB2 ports */ 2453 if (portsc & PORT_OCC) 2454 ret += sprintf(str + ret, "OCC "); 2455 if (portsc & PORT_RC) 2456 ret += sprintf(str + ret, "PRC "); 2457 if (portsc & PORT_PLC) 2458 ret += sprintf(str + ret, "PLC "); 2459 if (portsc & PORT_CEC) 2460 ret += sprintf(str + ret, "CEC "); /* RsvdZ for USB2 ports */ 2461 2462 return str; 2463 } 2464 2465 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2466 { 2467 int ret = 0; 2468 2469 ret = sprintf(str, " 0x%08x", usbsts); 2470 2471 if (usbsts == ~(u32)0) 2472 return str; 2473 2474 if (usbsts & STS_HALT) 2475 ret += sprintf(str + ret, " HCHalted"); 2476 if (usbsts & STS_FATAL) 2477 ret += sprintf(str + ret, " HSE"); 2478 if (usbsts & STS_EINT) 2479 ret += sprintf(str + ret, " EINT"); 2480 if (usbsts & STS_PORT) 2481 ret += sprintf(str + ret, " PCD"); 2482 if (usbsts & STS_SAVE) 2483 ret += sprintf(str + ret, " SSS"); 2484 if (usbsts & STS_RESTORE) 2485 ret += sprintf(str + ret, " RSS"); 2486 if (usbsts & STS_SRE) 2487 ret += sprintf(str + ret, " SRE"); 2488 if (usbsts & STS_CNR) 2489 ret += sprintf(str + ret, " CNR"); 2490 if (usbsts & STS_HCE) 2491 ret += sprintf(str + ret, " HCE"); 2492 2493 return str; 2494 } 2495 2496 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2497 { 2498 u8 ep; 2499 u16 stream; 2500 int ret; 2501 2502 ep = (doorbell & 0xff); 2503 stream = doorbell >> 16; 2504 2505 if (slot == 0) { 2506 sprintf(str, "Command Ring %d", doorbell); 2507 return str; 2508 } 2509 ret = sprintf(str, "Slot %d ", slot); 2510 if (ep > 0 && ep < 32) 2511 ret = sprintf(str + ret, "ep%d%s", 2512 ep / 2, 2513 ep % 2 ? "in" : "out"); 2514 else if (ep == 0 || ep < 248) 2515 ret = sprintf(str + ret, "Reserved %d", ep); 2516 else 2517 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2518 if (stream) 2519 ret = sprintf(str + ret, " Stream %d", stream); 2520 2521 return str; 2522 } 2523 2524 static inline const char *xhci_ep_state_string(u8 state) 2525 { 2526 switch (state) { 2527 case EP_STATE_DISABLED: 2528 return "disabled"; 2529 case EP_STATE_RUNNING: 2530 return "running"; 2531 case EP_STATE_HALTED: 2532 return "halted"; 2533 case EP_STATE_STOPPED: 2534 return "stopped"; 2535 case EP_STATE_ERROR: 2536 return "error"; 2537 default: 2538 return "INVALID"; 2539 } 2540 } 2541 2542 static inline const char *xhci_ep_type_string(u8 type) 2543 { 2544 switch (type) { 2545 case ISOC_OUT_EP: 2546 return "Isoc OUT"; 2547 case BULK_OUT_EP: 2548 return "Bulk OUT"; 2549 case INT_OUT_EP: 2550 return "Int OUT"; 2551 case CTRL_EP: 2552 return "Ctrl"; 2553 case ISOC_IN_EP: 2554 return "Isoc IN"; 2555 case BULK_IN_EP: 2556 return "Bulk IN"; 2557 case INT_IN_EP: 2558 return "Int IN"; 2559 default: 2560 return "INVALID"; 2561 } 2562 } 2563 2564 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2565 u32 info2, u64 deq, u32 tx_info) 2566 { 2567 int ret; 2568 2569 u32 esit; 2570 u16 maxp; 2571 u16 avg; 2572 2573 u8 max_pstr; 2574 u8 ep_state; 2575 u8 interval; 2576 u8 ep_type; 2577 u8 burst; 2578 u8 cerr; 2579 u8 mult; 2580 2581 bool lsa; 2582 bool hid; 2583 2584 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2585 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2586 2587 ep_state = info & EP_STATE_MASK; 2588 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2589 interval = CTX_TO_EP_INTERVAL(info); 2590 mult = CTX_TO_EP_MULT(info) + 1; 2591 lsa = !!(info & EP_HAS_LSA); 2592 2593 cerr = (info2 & (3 << 1)) >> 1; 2594 ep_type = CTX_TO_EP_TYPE(info2); 2595 hid = !!(info2 & (1 << 7)); 2596 burst = CTX_TO_MAX_BURST(info2); 2597 maxp = MAX_PACKET_DECODED(info2); 2598 2599 avg = EP_AVG_TRB_LENGTH(tx_info); 2600 2601 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2602 xhci_ep_state_string(ep_state), mult, 2603 max_pstr, lsa ? "LSA " : ""); 2604 2605 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2606 (1 << interval) * 125, esit, cerr); 2607 2608 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2609 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2610 burst, maxp, deq); 2611 2612 ret += sprintf(str + ret, "avg trb len %d", avg); 2613 2614 return str; 2615 } 2616 2617 #endif /* __LINUX_XHCI_HCD_H */ 2618