1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 #include "xhci-port.h" 27 #include "xhci-caps.h" 28 29 /* max buffer size for trace and debug messages */ 30 #define XHCI_MSG_MAX 500 31 32 /* xHCI PCI Configuration Registers */ 33 #define XHCI_SBRN_OFFSET (0x60) 34 35 /* Max number of USB devices for any host controller - limit in section 6.1 */ 36 #define MAX_HC_SLOTS 256 37 /* Section 5.3.3 - MaxPorts */ 38 #define MAX_HC_PORTS 127 39 40 /* 41 * xHCI register interface. 42 * This corresponds to the eXtensible Host Controller Interface (xHCI) 43 * Revision 0.95 specification 44 */ 45 46 /** 47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 48 * @hc_capbase: length of the capabilities register and HC version number 49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 52 * @hcc_params: HCCPARAMS - Capability Parameters 53 * @db_off: DBOFF - Doorbell array offset 54 * @run_regs_off: RTSOFF - Runtime register space offset 55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 56 */ 57 struct xhci_cap_regs { 58 __le32 hc_capbase; 59 __le32 hcs_params1; 60 __le32 hcs_params2; 61 __le32 hcs_params3; 62 __le32 hcc_params; 63 __le32 db_off; 64 __le32 run_regs_off; 65 __le32 hcc_params2; /* xhci 1.1 */ 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* Number of registers per port */ 70 #define NUM_PORT_REGS 4 71 72 #define PORTSC 0 73 #define PORTPMSC 1 74 #define PORTLI 2 75 #define PORTHLPMC 3 76 77 /** 78 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 79 * @command: USBCMD - xHC command register 80 * @status: USBSTS - xHC status register 81 * @page_size: This indicates the page size that the host controller 82 * supports. If bit n is set, the HC supports a page size 83 * of 2^(n+12), up to a 128MB page size. 84 * 4K is the minimum page size. 85 * @cmd_ring: CRP - 64-bit Command Ring Pointer 86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 87 * @config_reg: CONFIG - Configure Register 88 * @port_status_base: PORTSCn - base address for Port Status and Control 89 * Each port has a Port Status and Control register, 90 * followed by a Port Power Management Status and Control 91 * register, a Port Link Info register, and a reserved 92 * register. 93 * @port_power_base: PORTPMSCn - base address for 94 * Port Power Management Status and Control 95 * @port_link_base: PORTLIn - base address for Port Link Info (current 96 * Link PM state and control) for USB 2.1 and USB 3.0 97 * devices. 98 */ 99 struct xhci_op_regs { 100 __le32 command; 101 __le32 status; 102 __le32 page_size; 103 __le32 reserved1; 104 __le32 reserved2; 105 __le32 dev_notification; 106 __le64 cmd_ring; 107 /* rsvd: offset 0x20-2F */ 108 __le32 reserved3[4]; 109 __le64 dcbaa_ptr; 110 __le32 config_reg; 111 /* rsvd: offset 0x3C-3FF */ 112 __le32 reserved4[241]; 113 /* port 1 registers, which serve as a base address for other ports */ 114 __le32 port_status_base; 115 __le32 port_power_base; 116 __le32 port_link_base; 117 __le32 reserved5; 118 /* registers for ports 2-255 */ 119 __le32 reserved6[NUM_PORT_REGS*254]; 120 }; 121 122 /* USBCMD - USB command - command bitmasks */ 123 /* start/stop HC execution - do not write unless HC is halted*/ 124 #define CMD_RUN XHCI_CMD_RUN 125 /* Reset HC - resets internal HC state machine and all registers (except 126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 127 * The xHCI driver must reinitialize the xHC after setting this bit. 128 */ 129 #define CMD_RESET (1 << 1) 130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 131 #define CMD_EIE XHCI_CMD_EIE 132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 133 #define CMD_HSEIE XHCI_CMD_HSEIE 134 /* bits 4:6 are reserved (and should be preserved on writes). */ 135 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 136 #define CMD_LRESET (1 << 7) 137 /* host controller save/restore state. */ 138 #define CMD_CSS (1 << 8) 139 #define CMD_CRS (1 << 9) 140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 141 #define CMD_EWE XHCI_CMD_EWE 142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 144 * '0' means the xHC can power it off if all ports are in the disconnect, 145 * disabled, or powered-off state. 146 */ 147 #define CMD_PM_INDEX (1 << 11) 148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 149 #define CMD_ETE (1 << 14) 150 /* bits 15:31 are reserved (and should be preserved on writes). */ 151 152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 153 #define XHCI_RESET_SHORT_USEC (250 * 1000) 154 155 /* USBSTS - USB status - status bitmasks */ 156 /* HC not running - set to 1 when run/stop bit is cleared. */ 157 #define STS_HALT XHCI_STS_HALT 158 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 159 #define STS_FATAL (1 << 2) 160 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 161 #define STS_EINT (1 << 3) 162 /* port change detect */ 163 #define STS_PORT (1 << 4) 164 /* bits 5:7 reserved and zeroed */ 165 /* save state status - '1' means xHC is saving state */ 166 #define STS_SAVE (1 << 8) 167 /* restore state status - '1' means xHC is restoring state */ 168 #define STS_RESTORE (1 << 9) 169 /* true: save or restore error */ 170 #define STS_SRE (1 << 10) 171 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 172 #define STS_CNR XHCI_STS_CNR 173 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 174 #define STS_HCE (1 << 12) 175 /* bits 13:31 reserved and should be preserved */ 176 177 /* 178 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 179 * Generate a device notification event when the HC sees a transaction with a 180 * notification type that matches a bit set in this bit field. 181 */ 182 #define DEV_NOTE_MASK (0xffff) 183 /* Most of the device notification types should only be used for debug. 184 * SW does need to pay attention to function wake notifications. 185 */ 186 #define DEV_NOTE_FWAKE (1 << 1) 187 188 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 189 /* bit 0 - Cycle bit indicates the ownership of the command ring */ 190 #define CMD_RING_CYCLE (1 << 0) 191 /* stop ring operation after completion of the currently executing command */ 192 #define CMD_RING_PAUSE (1 << 1) 193 /* stop ring immediately - abort the currently executing command */ 194 #define CMD_RING_ABORT (1 << 2) 195 /* true: command ring is running */ 196 #define CMD_RING_RUNNING (1 << 3) 197 /* bits 63:6 - Command Ring pointer */ 198 #define CMD_RING_PTR_MASK GENMASK_ULL(63, 6) 199 200 /* CONFIG - Configure Register - config_reg bitmasks */ 201 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 202 #define MAX_DEVS(p) ((p) & 0xff) 203 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 204 #define CONFIG_U3E (1 << 8) 205 /* bit 9: Configuration Information Enable, xhci 1.1 */ 206 #define CONFIG_CIE (1 << 9) 207 /* bits 10:31 - reserved and should be preserved */ 208 209 /* bits 15:0 - HCD page shift bit */ 210 #define XHCI_PAGE_SIZE_MASK 0xffff 211 212 /** 213 * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2. 214 * @iman: IMAN - Interrupt Management Register. Used to enable 215 * interrupts and check for pending interrupts. 216 * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts. 217 * @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST). 218 * @erst_base: ERSTBA - Event ring segment table base address. 219 * @erst_dequeue: ERDP - Event ring dequeue pointer. 220 * 221 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 222 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 223 * multiple segments of the same size. The HC places events on the ring and 224 * "updates the Cycle bit in the TRBs to indicate to software the current 225 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 226 * updates the dequeue pointer. 227 */ 228 struct xhci_intr_reg { 229 __le32 iman; 230 __le32 imod; 231 __le32 erst_size; 232 __le32 rsvd; 233 __le64 erst_base; 234 __le64 erst_dequeue; 235 }; 236 237 /* iman bitmasks */ 238 /* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */ 239 #define IMAN_IP (1 << 0) 240 /* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */ 241 #define IMAN_IE (1 << 1) 242 243 /* imod bitmasks */ 244 /* 245 * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts 246 * (in 250ns intervals). The interval between interrupts will be longer if there are no 247 * events on the event ring. Default is 4000 (1 ms). 248 */ 249 #define IMODI_MASK (0xffff) 250 /* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */ 251 #define IMODC_MASK (0xffff << 16) 252 253 /* erst_size bitmasks */ 254 /* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */ 255 #define ERST_SIZE_MASK (0xffff) 256 257 /* erst_base bitmasks */ 258 /* bits 63:6 - Event Ring Segment Table Base Address Register */ 259 #define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6) 260 261 /* erst_dequeue bitmasks */ 262 /* 263 * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the 264 * current dequeue pointer lies. This is an optional HW hint. 265 */ 266 #define ERST_DESI_MASK (0x7) 267 /* 268 * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by 269 * a work queue (or delayed service routine)? 270 */ 271 #define ERST_EHB (1 << 3) 272 /* bits 63:4 - Event Ring Dequeue Pointer */ 273 #define ERST_PTR_MASK GENMASK_ULL(63, 4) 274 275 /** 276 * struct xhci_run_regs 277 * @microframe_index: 278 * MFINDEX - current microframe number 279 * 280 * Section 5.5 Host Controller Runtime Registers: 281 * "Software should read and write these registers using only Dword (32 bit) 282 * or larger accesses" 283 */ 284 struct xhci_run_regs { 285 __le32 microframe_index; 286 __le32 rsvd[7]; 287 struct xhci_intr_reg ir_set[128]; 288 }; 289 290 /** 291 * struct doorbell_array 292 * 293 * Bits 0 - 7: Endpoint target 294 * Bits 8 - 15: RsvdZ 295 * Bits 16 - 31: Stream ID 296 * 297 * Section 5.6 298 */ 299 struct xhci_doorbell_array { 300 __le32 doorbell[256]; 301 }; 302 303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 304 #define DB_VALUE_HOST 0x00000000 305 306 #define PLT_MASK (0x03 << 6) 307 #define PLT_SYM (0x00 << 6) 308 #define PLT_ASYM_RX (0x02 << 6) 309 #define PLT_ASYM_TX (0x03 << 6) 310 311 /** 312 * struct xhci_container_ctx 313 * @type: Type of context. Used to calculated offsets to contained contexts. 314 * @size: Size of the context data 315 * @bytes: The raw context data given to HW 316 * @dma: dma address of the bytes 317 * 318 * Represents either a Device or Input context. Holds a pointer to the raw 319 * memory used for the context (bytes) and dma address of it (dma). 320 */ 321 struct xhci_container_ctx { 322 unsigned type; 323 #define XHCI_CTX_TYPE_DEVICE 0x1 324 #define XHCI_CTX_TYPE_INPUT 0x2 325 326 int size; 327 328 u8 *bytes; 329 dma_addr_t dma; 330 }; 331 332 /** 333 * struct xhci_slot_ctx 334 * @dev_info: Route string, device speed, hub info, and last valid endpoint 335 * @dev_info2: Max exit latency for device number, root hub port number 336 * @tt_info: tt_info is used to construct split transaction tokens 337 * @dev_state: slot state and device address 338 * 339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 341 * reserved at the end of the slot context for HC internal use. 342 */ 343 struct xhci_slot_ctx { 344 __le32 dev_info; 345 __le32 dev_info2; 346 __le32 tt_info; 347 __le32 dev_state; 348 /* offset 0x10 to 0x1f reserved for HC internal use */ 349 __le32 reserved[4]; 350 }; 351 352 /* dev_info bitmasks */ 353 /* Route String - 0:19 */ 354 #define ROUTE_STRING_MASK (0xfffff) 355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 356 #define DEV_SPEED (0xf << 20) 357 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 358 /* bit 24 reserved */ 359 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 360 #define DEV_MTT (0x1 << 25) 361 /* Set if the device is a hub - bit 26 */ 362 #define DEV_HUB (0x1 << 26) 363 /* Index of the last valid endpoint context in this device context - 27:31 */ 364 #define LAST_CTX_MASK (0x1f << 27) 365 #define LAST_CTX(p) ((p) << 27) 366 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 367 #define SLOT_FLAG (1 << 0) 368 #define EP0_FLAG (1 << 1) 369 370 /* dev_info2 bitmasks */ 371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 372 #define MAX_EXIT (0xffff) 373 /* Root hub port number that is needed to access the USB device */ 374 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 375 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 376 /* Maximum number of ports under a hub device */ 377 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 378 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 379 380 /* tt_info bitmasks */ 381 /* 382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 383 * The Slot ID of the hub that isolates the high speed signaling from 384 * this low or full-speed device. '0' if attached to root hub port. 385 */ 386 #define TT_SLOT (0xff) 387 /* 388 * The number of the downstream facing port of the high-speed hub 389 * '0' if the device is not low or full speed. 390 */ 391 #define TT_PORT (0xff << 8) 392 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 393 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 394 395 /* dev_state bitmasks */ 396 /* USB device address - assigned by the HC */ 397 #define DEV_ADDR_MASK (0xff) 398 /* bits 8:26 reserved */ 399 /* Slot state */ 400 #define SLOT_STATE (0x1f << 27) 401 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 402 403 #define SLOT_STATE_DISABLED 0 404 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 405 #define SLOT_STATE_DEFAULT 1 406 #define SLOT_STATE_ADDRESSED 2 407 #define SLOT_STATE_CONFIGURED 3 408 409 /** 410 * struct xhci_ep_ctx 411 * @ep_info: endpoint state, streams, mult, and interval information. 412 * @ep_info2: information on endpoint type, max packet size, max burst size, 413 * error count, and whether the HC will force an event for all 414 * transactions. 415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 416 * defines one stream, this points to the endpoint transfer ring. 417 * Otherwise, it points to a stream context array, which has a 418 * ring pointer for each flow. 419 * @tx_info: 420 * Average TRB lengths for the endpoint ring and 421 * max payload within an Endpoint Service Interval Time (ESIT). 422 * 423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 425 * reserved at the end of the endpoint context for HC internal use. 426 */ 427 struct xhci_ep_ctx { 428 __le32 ep_info; 429 __le32 ep_info2; 430 __le64 deq; 431 __le32 tx_info; 432 /* offset 0x14 - 0x1f reserved for HC internal use */ 433 __le32 reserved[3]; 434 }; 435 436 /* ep_info bitmasks */ 437 /* 438 * Endpoint State - bits 0:2 439 * 0 - disabled 440 * 1 - running 441 * 2 - halted due to halt condition - ok to manipulate endpoint ring 442 * 3 - stopped 443 * 4 - TRB error 444 * 5-7 - reserved 445 */ 446 #define EP_STATE_MASK (0x7) 447 #define EP_STATE_DISABLED 0 448 #define EP_STATE_RUNNING 1 449 #define EP_STATE_HALTED 2 450 #define EP_STATE_STOPPED 3 451 #define EP_STATE_ERROR 4 452 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 453 454 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 455 #define EP_MULT(p) (((p) & 0x3) << 8) 456 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 457 /* bits 10:14 are Max Primary Streams */ 458 /* bit 15 is Linear Stream Array */ 459 /* Interval - period between requests to an endpoint - 125u increments. */ 460 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 461 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 462 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 463 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 464 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 465 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 466 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 467 #define EP_HAS_LSA (1 << 15) 468 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 469 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 470 471 /* ep_info2 bitmasks */ 472 /* 473 * Force Event - generate transfer events for all TRBs for this endpoint 474 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 475 */ 476 #define FORCE_EVENT (0x1) 477 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 478 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 479 #define EP_TYPE(p) ((p) << 3) 480 #define ISOC_OUT_EP 1 481 #define BULK_OUT_EP 2 482 #define INT_OUT_EP 3 483 #define CTRL_EP 4 484 #define ISOC_IN_EP 5 485 #define BULK_IN_EP 6 486 #define INT_IN_EP 7 487 /* bit 6 reserved */ 488 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 489 #define MAX_BURST(p) (((p)&0xff) << 8) 490 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 491 #define MAX_PACKET(p) (((p)&0xffff) << 16) 492 #define MAX_PACKET_MASK (0xffff << 16) 493 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 494 495 /* tx_info bitmasks */ 496 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 497 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 498 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 499 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 500 501 /* deq bitmasks */ 502 #define EP_CTX_CYCLE_MASK (1 << 0) 503 /* bits 63:4 - TR Dequeue Pointer */ 504 #define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4) 505 506 507 /** 508 * struct xhci_input_control_context 509 * Input control context; see section 6.2.5. 510 * 511 * @drop_context: set the bit of the endpoint context you want to disable 512 * @add_context: set the bit of the endpoint context you want to enable 513 */ 514 struct xhci_input_control_ctx { 515 __le32 drop_flags; 516 __le32 add_flags; 517 __le32 rsvd2[6]; 518 }; 519 520 #define EP_IS_ADDED(ctrl_ctx, i) \ 521 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 522 #define EP_IS_DROPPED(ctrl_ctx, i) \ 523 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 524 525 /* Represents everything that is needed to issue a command on the command ring. 526 * It's useful to pre-allocate these for commands that cannot fail due to 527 * out-of-memory errors, like freeing streams. 528 */ 529 struct xhci_command { 530 /* Input context for changing device state */ 531 struct xhci_container_ctx *in_ctx; 532 u32 status; 533 u32 comp_param; 534 int slot_id; 535 /* If completion is null, no one is waiting on this command 536 * and the structure can be freed after the command completes. 537 */ 538 struct completion *completion; 539 union xhci_trb *command_trb; 540 struct list_head cmd_list; 541 /* xHCI command response timeout in milliseconds */ 542 unsigned int timeout_ms; 543 }; 544 545 /* drop context bitmasks */ 546 #define DROP_EP(x) (0x1 << x) 547 /* add context bitmasks */ 548 #define ADD_EP(x) (0x1 << x) 549 550 struct xhci_stream_ctx { 551 /* 64-bit stream ring address, cycle state, and stream type */ 552 __le64 stream_ring; 553 /* offset 0x14 - 0x1f reserved for HC internal use */ 554 __le32 reserved[2]; 555 }; 556 557 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 558 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 559 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 560 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 561 #define SCT_SEC_TR 0 562 /* Primary stream array type, dequeue pointer is to a transfer ring */ 563 #define SCT_PRI_TR 1 564 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 565 #define SCT_SSA_8 2 566 #define SCT_SSA_16 3 567 #define SCT_SSA_32 4 568 #define SCT_SSA_64 5 569 #define SCT_SSA_128 6 570 #define SCT_SSA_256 7 571 572 /* Assume no secondary streams for now */ 573 struct xhci_stream_info { 574 struct xhci_ring **stream_rings; 575 /* Number of streams, including stream 0 (which drivers can't use) */ 576 unsigned int num_streams; 577 /* The stream context array may be bigger than 578 * the number of streams the driver asked for 579 */ 580 struct xhci_stream_ctx *stream_ctx_array; 581 unsigned int num_stream_ctxs; 582 dma_addr_t ctx_array_dma; 583 /* For mapping physical TRB addresses to segments in stream rings */ 584 struct radix_tree_root trb_address_map; 585 struct xhci_command *free_streams_command; 586 }; 587 588 #define SMALL_STREAM_ARRAY_SIZE 256 589 #define MEDIUM_STREAM_ARRAY_SIZE 1024 590 #define GET_PORT_BW_ARRAY_SIZE 256 591 592 /* Some Intel xHCI host controllers need software to keep track of the bus 593 * bandwidth. Keep track of endpoint info here. Each root port is allocated 594 * the full bus bandwidth. We must also treat TTs (including each port under a 595 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 596 * (DMI) also limits the total bandwidth (across all domains) that can be used. 597 */ 598 struct xhci_bw_info { 599 /* ep_interval is zero-based */ 600 unsigned int ep_interval; 601 /* mult and num_packets are one-based */ 602 unsigned int mult; 603 unsigned int num_packets; 604 unsigned int max_packet_size; 605 unsigned int max_esit_payload; 606 unsigned int type; 607 }; 608 609 /* "Block" sizes in bytes the hardware uses for different device speeds. 610 * The logic in this part of the hardware limits the number of bits the hardware 611 * can use, so must represent bandwidth in a less precise manner to mimic what 612 * the scheduler hardware computes. 613 */ 614 #define FS_BLOCK 1 615 #define HS_BLOCK 4 616 #define SS_BLOCK 16 617 #define DMI_BLOCK 32 618 619 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 620 * with each byte transferred. SuperSpeed devices have an initial overhead to 621 * set up bursts. These are in blocks, see above. LS overhead has already been 622 * translated into FS blocks. 623 */ 624 #define DMI_OVERHEAD 8 625 #define DMI_OVERHEAD_BURST 4 626 #define SS_OVERHEAD 8 627 #define SS_OVERHEAD_BURST 32 628 #define HS_OVERHEAD 26 629 #define FS_OVERHEAD 20 630 #define LS_OVERHEAD 128 631 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 632 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 633 * of overhead associated with split transfers crossing microframe boundaries. 634 * 31 blocks is pure protocol overhead. 635 */ 636 #define TT_HS_OVERHEAD (31 + 94) 637 #define TT_DMI_OVERHEAD (25 + 12) 638 639 /* Bandwidth limits in blocks */ 640 #define FS_BW_LIMIT 1285 641 #define TT_BW_LIMIT 1320 642 #define HS_BW_LIMIT 1607 643 #define SS_BW_LIMIT_IN 3906 644 #define DMI_BW_LIMIT_IN 3906 645 #define SS_BW_LIMIT_OUT 3906 646 #define DMI_BW_LIMIT_OUT 3906 647 648 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 649 #define FS_BW_RESERVED 10 650 #define HS_BW_RESERVED 20 651 #define SS_BW_RESERVED 10 652 653 struct xhci_virt_ep { 654 struct xhci_virt_device *vdev; /* parent */ 655 unsigned int ep_index; 656 struct xhci_ring *ring; 657 /* Related to endpoints that are configured to use stream IDs only */ 658 struct xhci_stream_info *stream_info; 659 /* Temporary storage in case the configure endpoint command fails and we 660 * have to restore the device state to the previous state 661 */ 662 struct xhci_ring *new_ring; 663 unsigned int err_count; 664 unsigned int ep_state; 665 #define SET_DEQ_PENDING (1 << 0) 666 #define EP_HALTED (1 << 1) /* For stall handling */ 667 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 668 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 669 #define EP_GETTING_STREAMS (1 << 3) 670 #define EP_HAS_STREAMS (1 << 4) 671 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 672 #define EP_GETTING_NO_STREAMS (1 << 5) 673 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 674 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 675 /* usb_hub_clear_tt_buffer is in progress */ 676 #define EP_CLEARING_TT (1 << 8) 677 /* ---- Related to URB cancellation ---- */ 678 struct list_head cancelled_td_list; 679 struct xhci_hcd *xhci; 680 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 681 * command. We'll need to update the ring's dequeue segment and dequeue 682 * pointer after the command completes. 683 */ 684 struct xhci_segment *queued_deq_seg; 685 union xhci_trb *queued_deq_ptr; 686 /* 687 * Sometimes the xHC can not process isochronous endpoint ring quickly 688 * enough, and it will miss some isoc tds on the ring and generate 689 * a Missed Service Error Event. 690 * Set skip flag when receive a Missed Service Error Event and 691 * process the missed tds on the endpoint ring. 692 */ 693 bool skip; 694 /* Bandwidth checking storage */ 695 struct xhci_bw_info bw_info; 696 struct list_head bw_endpoint_list; 697 unsigned long stop_time; 698 /* Isoch Frame ID checking storage */ 699 int next_frame_id; 700 /* Use new Isoch TRB layout needed for extended TBC support */ 701 bool use_extended_tbc; 702 /* set if this endpoint is controlled via sideband access*/ 703 struct xhci_sideband *sideband; 704 }; 705 706 enum xhci_overhead_type { 707 LS_OVERHEAD_TYPE = 0, 708 FS_OVERHEAD_TYPE, 709 HS_OVERHEAD_TYPE, 710 }; 711 712 struct xhci_interval_bw { 713 unsigned int num_packets; 714 /* Sorted by max packet size. 715 * Head of the list is the greatest max packet size. 716 */ 717 struct list_head endpoints; 718 /* How many endpoints of each speed are present. */ 719 unsigned int overhead[3]; 720 }; 721 722 #define XHCI_MAX_INTERVAL 16 723 724 struct xhci_interval_bw_table { 725 unsigned int interval0_esit_payload; 726 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 727 /* Includes reserved bandwidth for async endpoints */ 728 unsigned int bw_used; 729 unsigned int ss_bw_in; 730 unsigned int ss_bw_out; 731 }; 732 733 #define EP_CTX_PER_DEV 31 734 735 struct xhci_virt_device { 736 int slot_id; 737 struct usb_device *udev; 738 /* 739 * Commands to the hardware are passed an "input context" that 740 * tells the hardware what to change in its data structures. 741 * The hardware will return changes in an "output context" that 742 * software must allocate for the hardware. We need to keep 743 * track of input and output contexts separately because 744 * these commands might fail and we don't trust the hardware. 745 */ 746 struct xhci_container_ctx *out_ctx; 747 /* Used for addressing devices and configuration changes */ 748 struct xhci_container_ctx *in_ctx; 749 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 750 struct xhci_port *rhub_port; 751 struct xhci_interval_bw_table *bw_table; 752 struct xhci_tt_bw_info *tt_info; 753 /* 754 * flags for state tracking based on events and issued commands. 755 * Software can not rely on states from output contexts because of 756 * latency between events and xHC updating output context values. 757 * See xhci 1.1 section 4.8.3 for more details 758 */ 759 unsigned long flags; 760 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 761 762 /* The current max exit latency for the enabled USB3 link states. */ 763 u16 current_mel; 764 /* Used for the debugfs interfaces. */ 765 void *debugfs_private; 766 /* set if this endpoint is controlled via sideband access*/ 767 struct xhci_sideband *sideband; 768 }; 769 770 /* 771 * For each roothub, keep track of the bandwidth information for each periodic 772 * interval. 773 * 774 * If a high speed hub is attached to the roothub, each TT associated with that 775 * hub is a separate bandwidth domain. The interval information for the 776 * endpoints on the devices under that TT will appear in the TT structure. 777 */ 778 struct xhci_root_port_bw_info { 779 struct list_head tts; 780 unsigned int num_active_tts; 781 struct xhci_interval_bw_table bw_table; 782 }; 783 784 struct xhci_tt_bw_info { 785 struct list_head tt_list; 786 int slot_id; 787 int ttport; 788 struct xhci_interval_bw_table bw_table; 789 int active_eps; 790 }; 791 792 793 /** 794 * struct xhci_device_context_array 795 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 796 */ 797 struct xhci_device_context_array { 798 /* 64-bit device addresses; we only write 32-bit addresses */ 799 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 800 /* private xHCD pointers */ 801 dma_addr_t dma; 802 }; 803 /* TODO: write function to set the 64-bit device DMA address */ 804 /* 805 * TODO: change this to be dynamically sized at HC mem init time since the HC 806 * might not be able to handle the maximum number of devices possible. 807 */ 808 809 810 struct xhci_transfer_event { 811 /* 64-bit buffer address, or immediate data */ 812 __le64 buffer; 813 __le32 transfer_len; 814 /* This field is interpreted differently based on the type of TRB */ 815 __le32 flags; 816 }; 817 818 /* Transfer event flags bitfield, also for select command completion events */ 819 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 820 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 821 822 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 823 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 824 825 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 826 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 827 828 /* Transfer event TRB length bit mask */ 829 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 830 831 /* Completion Code - only applicable for some types of TRBs */ 832 #define COMP_CODE_MASK (0xff << 24) 833 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 834 #define COMP_INVALID 0 835 #define COMP_SUCCESS 1 836 #define COMP_DATA_BUFFER_ERROR 2 837 #define COMP_BABBLE_DETECTED_ERROR 3 838 #define COMP_USB_TRANSACTION_ERROR 4 839 #define COMP_TRB_ERROR 5 840 #define COMP_STALL_ERROR 6 841 #define COMP_RESOURCE_ERROR 7 842 #define COMP_BANDWIDTH_ERROR 8 843 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 844 #define COMP_INVALID_STREAM_TYPE_ERROR 10 845 #define COMP_SLOT_NOT_ENABLED_ERROR 11 846 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 847 #define COMP_SHORT_PACKET 13 848 #define COMP_RING_UNDERRUN 14 849 #define COMP_RING_OVERRUN 15 850 #define COMP_VF_EVENT_RING_FULL_ERROR 16 851 #define COMP_PARAMETER_ERROR 17 852 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 853 #define COMP_CONTEXT_STATE_ERROR 19 854 #define COMP_NO_PING_RESPONSE_ERROR 20 855 #define COMP_EVENT_RING_FULL_ERROR 21 856 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 857 #define COMP_MISSED_SERVICE_ERROR 23 858 #define COMP_COMMAND_RING_STOPPED 24 859 #define COMP_COMMAND_ABORTED 25 860 #define COMP_STOPPED 26 861 #define COMP_STOPPED_LENGTH_INVALID 27 862 #define COMP_STOPPED_SHORT_PACKET 28 863 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 864 #define COMP_ISOCH_BUFFER_OVERRUN 31 865 #define COMP_EVENT_LOST_ERROR 32 866 #define COMP_UNDEFINED_ERROR 33 867 #define COMP_INVALID_STREAM_ID_ERROR 34 868 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 869 #define COMP_SPLIT_TRANSACTION_ERROR 36 870 871 static inline const char *xhci_trb_comp_code_string(u8 status) 872 { 873 switch (status) { 874 case COMP_INVALID: 875 return "Invalid"; 876 case COMP_SUCCESS: 877 return "Success"; 878 case COMP_DATA_BUFFER_ERROR: 879 return "Data Buffer Error"; 880 case COMP_BABBLE_DETECTED_ERROR: 881 return "Babble Detected"; 882 case COMP_USB_TRANSACTION_ERROR: 883 return "USB Transaction Error"; 884 case COMP_TRB_ERROR: 885 return "TRB Error"; 886 case COMP_STALL_ERROR: 887 return "Stall Error"; 888 case COMP_RESOURCE_ERROR: 889 return "Resource Error"; 890 case COMP_BANDWIDTH_ERROR: 891 return "Bandwidth Error"; 892 case COMP_NO_SLOTS_AVAILABLE_ERROR: 893 return "No Slots Available Error"; 894 case COMP_INVALID_STREAM_TYPE_ERROR: 895 return "Invalid Stream Type Error"; 896 case COMP_SLOT_NOT_ENABLED_ERROR: 897 return "Slot Not Enabled Error"; 898 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 899 return "Endpoint Not Enabled Error"; 900 case COMP_SHORT_PACKET: 901 return "Short Packet"; 902 case COMP_RING_UNDERRUN: 903 return "Ring Underrun"; 904 case COMP_RING_OVERRUN: 905 return "Ring Overrun"; 906 case COMP_VF_EVENT_RING_FULL_ERROR: 907 return "VF Event Ring Full Error"; 908 case COMP_PARAMETER_ERROR: 909 return "Parameter Error"; 910 case COMP_BANDWIDTH_OVERRUN_ERROR: 911 return "Bandwidth Overrun Error"; 912 case COMP_CONTEXT_STATE_ERROR: 913 return "Context State Error"; 914 case COMP_NO_PING_RESPONSE_ERROR: 915 return "No Ping Response Error"; 916 case COMP_EVENT_RING_FULL_ERROR: 917 return "Event Ring Full Error"; 918 case COMP_INCOMPATIBLE_DEVICE_ERROR: 919 return "Incompatible Device Error"; 920 case COMP_MISSED_SERVICE_ERROR: 921 return "Missed Service Error"; 922 case COMP_COMMAND_RING_STOPPED: 923 return "Command Ring Stopped"; 924 case COMP_COMMAND_ABORTED: 925 return "Command Aborted"; 926 case COMP_STOPPED: 927 return "Stopped"; 928 case COMP_STOPPED_LENGTH_INVALID: 929 return "Stopped - Length Invalid"; 930 case COMP_STOPPED_SHORT_PACKET: 931 return "Stopped - Short Packet"; 932 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 933 return "Max Exit Latency Too Large Error"; 934 case COMP_ISOCH_BUFFER_OVERRUN: 935 return "Isoch Buffer Overrun"; 936 case COMP_EVENT_LOST_ERROR: 937 return "Event Lost Error"; 938 case COMP_UNDEFINED_ERROR: 939 return "Undefined Error"; 940 case COMP_INVALID_STREAM_ID_ERROR: 941 return "Invalid Stream ID Error"; 942 case COMP_SECONDARY_BANDWIDTH_ERROR: 943 return "Secondary Bandwidth Error"; 944 case COMP_SPLIT_TRANSACTION_ERROR: 945 return "Split Transaction Error"; 946 default: 947 return "Unknown!!"; 948 } 949 } 950 951 struct xhci_link_trb { 952 /* 64-bit segment pointer*/ 953 __le64 segment_ptr; 954 __le32 intr_target; 955 __le32 control; 956 }; 957 958 /* control bitfields */ 959 #define LINK_TOGGLE (0x1<<1) 960 961 /* Command completion event TRB */ 962 struct xhci_event_cmd { 963 /* Pointer to command TRB, or the value passed by the event data trb */ 964 __le64 cmd_trb; 965 __le32 status; 966 __le32 flags; 967 }; 968 969 /* status bitmasks */ 970 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 971 972 /* Address device - disable SetAddress */ 973 #define TRB_BSR (1<<9) 974 975 /* Configure Endpoint - Deconfigure */ 976 #define TRB_DC (1<<9) 977 978 /* Stop Ring - Transfer State Preserve */ 979 #define TRB_TSP (1<<9) 980 981 enum xhci_ep_reset_type { 982 EP_HARD_RESET, 983 EP_SOFT_RESET, 984 }; 985 986 /* Force Event */ 987 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 988 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 989 990 /* Set Latency Tolerance Value */ 991 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 992 993 /* Get Port Bandwidth */ 994 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 995 996 /* Force Header */ 997 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 998 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 999 1000 enum xhci_setup_dev { 1001 SETUP_CONTEXT_ONLY, 1002 SETUP_CONTEXT_ADDRESS, 1003 }; 1004 1005 /* bits 16:23 are the virtual function ID */ 1006 /* bits 24:31 are the slot ID */ 1007 1008 /* bits 19:16 are the dev speed */ 1009 #define DEV_SPEED_FOR_TRB(p) ((p) << 16) 1010 1011 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1012 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1013 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1014 #define LAST_EP_INDEX 30 1015 1016 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1017 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1018 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1019 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1020 1021 /* Link TRB specific fields */ 1022 #define TRB_TC (1<<1) 1023 1024 /* Port Status Change Event TRB fields */ 1025 /* Port ID - bits 31:24 */ 1026 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1027 1028 #define EVENT_DATA (1 << 2) 1029 1030 /* Normal TRB fields */ 1031 /* transfer_len bitmasks - bits 0:16 */ 1032 #define TRB_LEN(p) ((p) & 0x1ffff) 1033 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1034 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1035 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1036 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1037 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1038 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1039 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1040 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1041 1042 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1043 #define TRB_CYCLE (1<<0) 1044 /* 1045 * Force next event data TRB to be evaluated before task switch. 1046 * Used to pass OS data back after a TD completes. 1047 */ 1048 #define TRB_ENT (1<<1) 1049 /* Interrupt on short packet */ 1050 #define TRB_ISP (1<<2) 1051 /* Set PCIe no snoop attribute */ 1052 #define TRB_NO_SNOOP (1<<3) 1053 /* Chain multiple TRBs into a TD */ 1054 #define TRB_CHAIN (1<<4) 1055 /* Interrupt on completion */ 1056 #define TRB_IOC (1<<5) 1057 /* The buffer pointer contains immediate data */ 1058 #define TRB_IDT (1<<6) 1059 /* TDs smaller than this might use IDT */ 1060 #define TRB_IDT_MAX_SIZE 8 1061 1062 /* Block Event Interrupt */ 1063 #define TRB_BEI (1<<9) 1064 1065 /* Control transfer TRB specific fields */ 1066 #define TRB_DIR_IN (1<<16) 1067 #define TRB_TX_TYPE(p) ((p) << 16) 1068 #define TRB_DATA_OUT 2 1069 #define TRB_DATA_IN 3 1070 1071 /* Isochronous TRB specific fields */ 1072 #define TRB_SIA (1<<31) 1073 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1074 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1075 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1076 #define TRB_TBC(p) (((p) & 0x3) << 7) 1077 #define GET_TBC(p) (((p) >> 7) & 0x3) 1078 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1079 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1080 1081 /* TRB cache size for xHC with TRB cache */ 1082 #define TRB_CACHE_SIZE_HS 8 1083 #define TRB_CACHE_SIZE_SS 16 1084 1085 struct xhci_generic_trb { 1086 __le32 field[4]; 1087 }; 1088 1089 union xhci_trb { 1090 struct xhci_link_trb link; 1091 struct xhci_transfer_event trans_event; 1092 struct xhci_event_cmd event_cmd; 1093 struct xhci_generic_trb generic; 1094 }; 1095 1096 /* TRB bit mask */ 1097 #define TRB_TYPE_BITMASK (0xfc00) 1098 #define TRB_TYPE(p) ((p) << 10) 1099 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1100 /* TRB type IDs */ 1101 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1102 #define TRB_NORMAL 1 1103 /* setup stage for control transfers */ 1104 #define TRB_SETUP 2 1105 /* data stage for control transfers */ 1106 #define TRB_DATA 3 1107 /* status stage for control transfers */ 1108 #define TRB_STATUS 4 1109 /* isoc transfers */ 1110 #define TRB_ISOC 5 1111 /* TRB for linking ring segments */ 1112 #define TRB_LINK 6 1113 #define TRB_EVENT_DATA 7 1114 /* Transfer Ring No-op (not for the command ring) */ 1115 #define TRB_TR_NOOP 8 1116 /* Command TRBs */ 1117 /* Enable Slot Command */ 1118 #define TRB_ENABLE_SLOT 9 1119 /* Disable Slot Command */ 1120 #define TRB_DISABLE_SLOT 10 1121 /* Address Device Command */ 1122 #define TRB_ADDR_DEV 11 1123 /* Configure Endpoint Command */ 1124 #define TRB_CONFIG_EP 12 1125 /* Evaluate Context Command */ 1126 #define TRB_EVAL_CONTEXT 13 1127 /* Reset Endpoint Command */ 1128 #define TRB_RESET_EP 14 1129 /* Stop Transfer Ring Command */ 1130 #define TRB_STOP_RING 15 1131 /* Set Transfer Ring Dequeue Pointer Command */ 1132 #define TRB_SET_DEQ 16 1133 /* Reset Device Command */ 1134 #define TRB_RESET_DEV 17 1135 /* Force Event Command (opt) */ 1136 #define TRB_FORCE_EVENT 18 1137 /* Negotiate Bandwidth Command (opt) */ 1138 #define TRB_NEG_BANDWIDTH 19 1139 /* Set Latency Tolerance Value Command (opt) */ 1140 #define TRB_SET_LT 20 1141 /* Get port bandwidth Command */ 1142 #define TRB_GET_BW 21 1143 /* Force Header Command - generate a transaction or link management packet */ 1144 #define TRB_FORCE_HEADER 22 1145 /* No-op Command - not for transfer rings */ 1146 #define TRB_CMD_NOOP 23 1147 /* TRB IDs 24-31 reserved */ 1148 /* Event TRBS */ 1149 /* Transfer Event */ 1150 #define TRB_TRANSFER 32 1151 /* Command Completion Event */ 1152 #define TRB_COMPLETION 33 1153 /* Port Status Change Event */ 1154 #define TRB_PORT_STATUS 34 1155 /* Bandwidth Request Event (opt) */ 1156 #define TRB_BANDWIDTH_EVENT 35 1157 /* Doorbell Event (opt) */ 1158 #define TRB_DOORBELL 36 1159 /* Host Controller Event */ 1160 #define TRB_HC_EVENT 37 1161 /* Device Notification Event - device sent function wake notification */ 1162 #define TRB_DEV_NOTE 38 1163 /* MFINDEX Wrap Event - microframe counter wrapped */ 1164 #define TRB_MFINDEX_WRAP 39 1165 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1166 #define TRB_VENDOR_DEFINED_LOW 48 1167 /* Nec vendor-specific command completion event. */ 1168 #define TRB_NEC_CMD_COMP 48 1169 /* Get NEC firmware revision. */ 1170 #define TRB_NEC_GET_FW 49 1171 1172 static inline const char *xhci_trb_type_string(u8 type) 1173 { 1174 switch (type) { 1175 case TRB_NORMAL: 1176 return "Normal"; 1177 case TRB_SETUP: 1178 return "Setup Stage"; 1179 case TRB_DATA: 1180 return "Data Stage"; 1181 case TRB_STATUS: 1182 return "Status Stage"; 1183 case TRB_ISOC: 1184 return "Isoch"; 1185 case TRB_LINK: 1186 return "Link"; 1187 case TRB_EVENT_DATA: 1188 return "Event Data"; 1189 case TRB_TR_NOOP: 1190 return "No-Op"; 1191 case TRB_ENABLE_SLOT: 1192 return "Enable Slot Command"; 1193 case TRB_DISABLE_SLOT: 1194 return "Disable Slot Command"; 1195 case TRB_ADDR_DEV: 1196 return "Address Device Command"; 1197 case TRB_CONFIG_EP: 1198 return "Configure Endpoint Command"; 1199 case TRB_EVAL_CONTEXT: 1200 return "Evaluate Context Command"; 1201 case TRB_RESET_EP: 1202 return "Reset Endpoint Command"; 1203 case TRB_STOP_RING: 1204 return "Stop Ring Command"; 1205 case TRB_SET_DEQ: 1206 return "Set TR Dequeue Pointer Command"; 1207 case TRB_RESET_DEV: 1208 return "Reset Device Command"; 1209 case TRB_FORCE_EVENT: 1210 return "Force Event Command"; 1211 case TRB_NEG_BANDWIDTH: 1212 return "Negotiate Bandwidth Command"; 1213 case TRB_SET_LT: 1214 return "Set Latency Tolerance Value Command"; 1215 case TRB_GET_BW: 1216 return "Get Port Bandwidth Command"; 1217 case TRB_FORCE_HEADER: 1218 return "Force Header Command"; 1219 case TRB_CMD_NOOP: 1220 return "No-Op Command"; 1221 case TRB_TRANSFER: 1222 return "Transfer Event"; 1223 case TRB_COMPLETION: 1224 return "Command Completion Event"; 1225 case TRB_PORT_STATUS: 1226 return "Port Status Change Event"; 1227 case TRB_BANDWIDTH_EVENT: 1228 return "Bandwidth Request Event"; 1229 case TRB_DOORBELL: 1230 return "Doorbell Event"; 1231 case TRB_HC_EVENT: 1232 return "Host Controller Event"; 1233 case TRB_DEV_NOTE: 1234 return "Device Notification Event"; 1235 case TRB_MFINDEX_WRAP: 1236 return "MFINDEX Wrap Event"; 1237 case TRB_NEC_CMD_COMP: 1238 return "NEC Command Completion Event"; 1239 case TRB_NEC_GET_FW: 1240 return "NET Get Firmware Revision Command"; 1241 default: 1242 return "UNKNOWN"; 1243 } 1244 } 1245 1246 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1247 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1248 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1249 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1250 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1251 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1252 1253 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1254 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1255 1256 /* 1257 * TRBS_PER_SEGMENT must be a multiple of 4, 1258 * since the command ring is 64-byte aligned. 1259 * It must also be greater than 16. 1260 */ 1261 #define TRBS_PER_SEGMENT 256 1262 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1263 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1264 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1265 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1266 /* TRB buffer pointers can't cross 64KB boundaries */ 1267 #define TRB_MAX_BUFF_SHIFT 16 1268 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1269 /* How much data is left before the 64KB boundary? */ 1270 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1271 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1272 #define MAX_SOFT_RETRY 3 1273 /* 1274 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1275 * XHCI_AVOID_BEI quirk is in use. 1276 */ 1277 #define AVOID_BEI_INTERVAL_MIN 8 1278 #define AVOID_BEI_INTERVAL_MAX 32 1279 1280 #define xhci_for_each_ring_seg(head, seg) \ 1281 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1282 1283 struct xhci_segment { 1284 union xhci_trb *trbs; 1285 /* private to HCD */ 1286 struct xhci_segment *next; 1287 unsigned int num; 1288 dma_addr_t dma; 1289 /* Max packet sized bounce buffer for td-fragmant alignment */ 1290 dma_addr_t bounce_dma; 1291 void *bounce_buf; 1292 unsigned int bounce_offs; 1293 unsigned int bounce_len; 1294 }; 1295 1296 enum xhci_cancelled_td_status { 1297 TD_DIRTY = 0, 1298 TD_HALTED, 1299 TD_CLEARING_CACHE, 1300 TD_CLEARING_CACHE_DEFERRED, 1301 TD_CLEARED, 1302 }; 1303 1304 struct xhci_td { 1305 struct list_head td_list; 1306 struct list_head cancelled_td_list; 1307 int status; 1308 enum xhci_cancelled_td_status cancel_status; 1309 struct urb *urb; 1310 struct xhci_segment *start_seg; 1311 union xhci_trb *start_trb; 1312 struct xhci_segment *end_seg; 1313 union xhci_trb *end_trb; 1314 struct xhci_segment *bounce_seg; 1315 /* actual_length of the URB has already been set */ 1316 bool urb_length_set; 1317 bool error_mid_td; 1318 }; 1319 1320 /* 1321 * xHCI command default timeout value in milliseconds. 1322 * USB 3.2 spec, section 9.2.6.1 1323 */ 1324 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1325 1326 /* command descriptor */ 1327 struct xhci_cd { 1328 struct xhci_command *command; 1329 union xhci_trb *cmd_trb; 1330 }; 1331 1332 enum xhci_ring_type { 1333 TYPE_CTRL = 0, 1334 TYPE_ISOC, 1335 TYPE_BULK, 1336 TYPE_INTR, 1337 TYPE_STREAM, 1338 TYPE_COMMAND, 1339 TYPE_EVENT, 1340 }; 1341 1342 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1343 { 1344 switch (type) { 1345 case TYPE_CTRL: 1346 return "CTRL"; 1347 case TYPE_ISOC: 1348 return "ISOC"; 1349 case TYPE_BULK: 1350 return "BULK"; 1351 case TYPE_INTR: 1352 return "INTR"; 1353 case TYPE_STREAM: 1354 return "STREAM"; 1355 case TYPE_COMMAND: 1356 return "CMD"; 1357 case TYPE_EVENT: 1358 return "EVENT"; 1359 } 1360 1361 return "UNKNOWN"; 1362 } 1363 1364 struct xhci_ring { 1365 struct xhci_segment *first_seg; 1366 struct xhci_segment *last_seg; 1367 union xhci_trb *enqueue; 1368 struct xhci_segment *enq_seg; 1369 union xhci_trb *dequeue; 1370 struct xhci_segment *deq_seg; 1371 struct list_head td_list; 1372 /* 1373 * Write the cycle state into the TRB cycle field to give ownership of 1374 * the TRB to the host controller (if we are the producer), or to check 1375 * if we own the TRB (if we are the consumer). See section 4.9.1. 1376 */ 1377 u32 cycle_state; 1378 unsigned int stream_id; 1379 unsigned int num_segs; 1380 unsigned int num_trbs_free; /* used only by xhci DbC */ 1381 unsigned int bounce_buf_len; 1382 enum xhci_ring_type type; 1383 u32 old_trb_comp_code; 1384 struct radix_tree_root *trb_address_map; 1385 }; 1386 1387 struct xhci_erst_entry { 1388 /* 64-bit event ring segment address */ 1389 __le64 seg_addr; 1390 __le32 seg_size; 1391 /* Set to zero */ 1392 __le32 rsvd; 1393 }; 1394 1395 struct xhci_erst { 1396 struct xhci_erst_entry *entries; 1397 unsigned int num_entries; 1398 /* xhci->event_ring keeps track of segment dma addresses */ 1399 dma_addr_t erst_dma_addr; 1400 }; 1401 1402 struct xhci_scratchpad { 1403 u64 *sp_array; 1404 dma_addr_t sp_dma; 1405 void **sp_buffers; 1406 }; 1407 1408 struct urb_priv { 1409 int num_tds; 1410 int num_tds_done; 1411 struct xhci_td td[] __counted_by(num_tds); 1412 }; 1413 1414 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1415 #define ERST_DEFAULT_SEGS 2 1416 /* Poll every 60 seconds */ 1417 #define POLL_TIMEOUT 60 1418 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1419 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1420 /* XXX: Make these module parameters */ 1421 1422 struct s3_save { 1423 u32 command; 1424 u32 dev_nt; 1425 u64 dcbaa_ptr; 1426 u32 config_reg; 1427 }; 1428 1429 /* Use for lpm */ 1430 struct dev_info { 1431 u32 dev_id; 1432 struct list_head list; 1433 }; 1434 1435 struct xhci_bus_state { 1436 unsigned long bus_suspended; 1437 unsigned long next_statechange; 1438 1439 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1440 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1441 u32 port_c_suspend; 1442 u32 suspended_ports; 1443 u32 port_remote_wakeup; 1444 /* which ports have started to resume */ 1445 unsigned long resuming_ports; 1446 }; 1447 1448 struct xhci_interrupter { 1449 struct xhci_ring *event_ring; 1450 struct xhci_erst erst; 1451 struct xhci_intr_reg __iomem *ir_set; 1452 unsigned int intr_num; 1453 bool ip_autoclear; 1454 u32 isoc_bei_interval; 1455 /* For interrupter registers save and restore over suspend/resume */ 1456 u32 s3_iman; 1457 u32 s3_imod; 1458 u32 s3_erst_size; 1459 u64 s3_erst_base; 1460 u64 s3_erst_dequeue; 1461 }; 1462 /* 1463 * It can take up to 20 ms to transition from RExit to U0 on the 1464 * Intel Lynx Point LP xHCI host. 1465 */ 1466 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1467 struct xhci_port_cap { 1468 u32 *psi; /* array of protocol speed ID entries */ 1469 u8 psi_count; 1470 u8 psi_uid_count; 1471 u8 maj_rev; 1472 u8 min_rev; 1473 u32 protocol_caps; 1474 }; 1475 1476 struct xhci_port { 1477 __le32 __iomem *addr; 1478 int hw_portnum; 1479 int hcd_portnum; 1480 struct xhci_hub *rhub; 1481 struct xhci_port_cap *port_cap; 1482 unsigned int lpm_incapable:1; 1483 unsigned long resume_timestamp; 1484 bool rexit_active; 1485 /* Slot ID is the index of the device directly connected to the port */ 1486 int slot_id; 1487 struct completion rexit_done; 1488 struct completion u3exit_done; 1489 }; 1490 1491 struct xhci_hub { 1492 struct xhci_port **ports; 1493 unsigned int num_ports; 1494 struct usb_hcd *hcd; 1495 /* keep track of bus suspend info */ 1496 struct xhci_bus_state bus_state; 1497 /* supported prococol extended capabiliy values */ 1498 u8 maj_rev; 1499 u8 min_rev; 1500 }; 1501 1502 /* There is one xhci_hcd structure per controller */ 1503 struct xhci_hcd { 1504 struct usb_hcd *main_hcd; 1505 struct usb_hcd *shared_hcd; 1506 /* glue to PCI and HCD framework */ 1507 struct xhci_cap_regs __iomem *cap_regs; 1508 struct xhci_op_regs __iomem *op_regs; 1509 struct xhci_run_regs __iomem *run_regs; 1510 struct xhci_doorbell_array __iomem *dba; 1511 1512 /* Cached register copies of read-only HC data */ 1513 __u32 hcs_params1; 1514 __u32 hcs_params2; 1515 __u32 hcs_params3; 1516 __u32 hcc_params; 1517 __u32 hcc_params2; 1518 1519 spinlock_t lock; 1520 1521 /* packed release number */ 1522 u16 hci_version; 1523 u16 max_interrupters; 1524 /* imod_interval in ns (I * 250ns) */ 1525 u32 imod_interval; 1526 u32 page_size; 1527 /* MSI-X/MSI vectors */ 1528 int nvecs; 1529 /* optional clocks */ 1530 struct clk *clk; 1531 struct clk *reg_clk; 1532 /* optional reset controller */ 1533 struct reset_control *reset; 1534 /* data structures */ 1535 struct xhci_device_context_array *dcbaa; 1536 struct xhci_interrupter **interrupters; 1537 struct xhci_ring *cmd_ring; 1538 unsigned int cmd_ring_state; 1539 #define CMD_RING_STATE_RUNNING (1 << 0) 1540 #define CMD_RING_STATE_ABORTED (1 << 1) 1541 #define CMD_RING_STATE_STOPPED (1 << 2) 1542 struct list_head cmd_list; 1543 unsigned int cmd_ring_reserved_trbs; 1544 struct delayed_work cmd_timer; 1545 struct completion cmd_ring_stop_completion; 1546 struct xhci_command *current_cmd; 1547 1548 /* Scratchpad */ 1549 struct xhci_scratchpad *scratchpad; 1550 1551 /* slot enabling and address device helpers */ 1552 /* these are not thread safe so use mutex */ 1553 struct mutex mutex; 1554 /* Internal mirror of the HW's dcbaa */ 1555 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1556 /* For keeping track of bandwidth domains per roothub. */ 1557 struct xhci_root_port_bw_info *rh_bw; 1558 1559 /* DMA pools */ 1560 struct dma_pool *device_pool; 1561 struct dma_pool *segment_pool; 1562 struct dma_pool *small_streams_pool; 1563 struct dma_pool *port_bw_pool; 1564 struct dma_pool *medium_streams_pool; 1565 1566 /* Host controller watchdog timer structures */ 1567 unsigned int xhc_state; 1568 unsigned long run_graceperiod; 1569 struct s3_save s3; 1570 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1571 * 1572 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1573 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1574 * that sees this status (other than the timer that set it) should stop touching 1575 * hardware immediately. Interrupt handlers should return immediately when 1576 * they see this status (any time they drop and re-acquire xhci->lock). 1577 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1578 * putting the TD on the canceled list, etc. 1579 * 1580 * There are no reports of xHCI host controllers that display this issue. 1581 */ 1582 #define XHCI_STATE_DYING (1 << 0) 1583 #define XHCI_STATE_HALTED (1 << 1) 1584 #define XHCI_STATE_REMOVING (1 << 2) 1585 unsigned long long quirks; 1586 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1587 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1588 #define XHCI_NEC_HOST BIT_ULL(2) 1589 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1590 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1591 /* 1592 * Certain Intel host controllers have a limit to the number of endpoint 1593 * contexts they can handle. Ideally, they would signal that they can't handle 1594 * anymore endpoint contexts by returning a Resource Error for the Configure 1595 * Endpoint command, but they don't. Instead they expect software to keep track 1596 * of the number of active endpoints for them, across configure endpoint 1597 * commands, reset device commands, disable slot commands, and address device 1598 * commands. 1599 */ 1600 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1601 #define XHCI_BROKEN_MSI BIT_ULL(6) 1602 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1603 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1604 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1605 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1606 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1607 #define XHCI_INTEL_HOST BIT_ULL(12) 1608 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1609 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1610 #define XHCI_AVOID_BEI BIT_ULL(15) 1611 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1612 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1613 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1614 /* For controllers with a broken beyond repair streams implementation */ 1615 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1616 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1617 #define XHCI_MTK_HOST BIT_ULL(21) 1618 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1619 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1620 #define XHCI_MISSING_CAS BIT_ULL(24) 1621 /* For controller with a broken Port Disable implementation */ 1622 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1623 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1624 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1625 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1626 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1627 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1628 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1629 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1630 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1631 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1632 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1633 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1634 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1635 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1636 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1637 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1638 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1639 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1640 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1641 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1642 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1643 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1644 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1645 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1646 #define XHCI_ETRON_HOST BIT_ULL(49) 1647 #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50) 1648 1649 unsigned int num_active_eps; 1650 unsigned int limit_active_eps; 1651 struct xhci_port *hw_ports; 1652 struct xhci_hub usb2_rhub; 1653 struct xhci_hub usb3_rhub; 1654 /* support xHCI 1.0 spec USB2 hardware LPM */ 1655 unsigned hw_lpm_support:1; 1656 /* Broken Suspend flag for SNPS Suspend resume issue */ 1657 unsigned broken_suspend:1; 1658 /* Indicates that omitting hcd is supported if root hub has no ports */ 1659 unsigned allow_single_roothub:1; 1660 /* cached extended protocol port capabilities */ 1661 struct xhci_port_cap *port_caps; 1662 unsigned int num_port_caps; 1663 /* Compliance Mode Recovery Data */ 1664 struct timer_list comp_mode_recovery_timer; 1665 u32 port_status_u0; 1666 u16 test_mode; 1667 /* Compliance Mode Timer Triggered every 2 seconds */ 1668 #define COMP_MODE_RCVRY_MSECS 2000 1669 1670 struct dentry *debugfs_root; 1671 struct dentry *debugfs_slots; 1672 struct list_head regset_list; 1673 1674 void *dbc; 1675 /* platform-specific data -- must come last */ 1676 unsigned long priv[] __aligned(sizeof(s64)); 1677 }; 1678 1679 /* Platform specific overrides to generic XHCI hc_driver ops */ 1680 struct xhci_driver_overrides { 1681 size_t extra_priv_size; 1682 int (*reset)(struct usb_hcd *hcd); 1683 int (*start)(struct usb_hcd *hcd); 1684 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1685 struct usb_host_endpoint *ep); 1686 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1687 struct usb_host_endpoint *ep); 1688 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1689 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1690 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1691 struct usb_tt *tt, gfp_t mem_flags); 1692 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1693 u16 wIndex, char *buf, u16 wLength); 1694 }; 1695 1696 #define XHCI_CFC_DELAY 10 1697 1698 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1699 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1700 { 1701 struct usb_hcd *primary_hcd; 1702 1703 if (usb_hcd_is_primary_hcd(hcd)) 1704 primary_hcd = hcd; 1705 else 1706 primary_hcd = hcd->primary_hcd; 1707 1708 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1709 } 1710 1711 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1712 { 1713 return xhci->main_hcd; 1714 } 1715 1716 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1717 { 1718 if (xhci->shared_hcd) 1719 return xhci->shared_hcd; 1720 1721 if (!xhci->usb2_rhub.num_ports) 1722 return xhci->main_hcd; 1723 1724 return NULL; 1725 } 1726 1727 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1728 { 1729 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1730 1731 return hcd == xhci_get_usb3_hcd(xhci); 1732 } 1733 1734 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1735 { 1736 return xhci->allow_single_roothub && 1737 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1738 } 1739 1740 #define xhci_dbg(xhci, fmt, args...) \ 1741 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1742 #define xhci_err(xhci, fmt, args...) \ 1743 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1744 #define xhci_warn(xhci, fmt, args...) \ 1745 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1746 #define xhci_info(xhci, fmt, args...) \ 1747 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1748 1749 /* 1750 * Registers should always be accessed with double word or quad word accesses. 1751 * 1752 * Some xHCI implementations may support 64-bit address pointers. Registers 1753 * with 64-bit address pointers should be written to with dword accesses by 1754 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1755 * xHCI implementations that do not support 64-bit address pointers will ignore 1756 * the high dword, and write order is irrelevant. 1757 */ 1758 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1759 __le64 __iomem *regs) 1760 { 1761 return lo_hi_readq(regs); 1762 } 1763 static inline void xhci_write_64(struct xhci_hcd *xhci, 1764 const u64 val, __le64 __iomem *regs) 1765 { 1766 lo_hi_writeq(val, regs); 1767 } 1768 1769 1770 /* 1771 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1772 * Other chapters and later specs say that it should only be set if the link is inside a TD 1773 * which continues from the end of one segment to the next segment. 1774 * 1775 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1776 * 1777 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1778 * "resynchronizing the pipe" after a Missed Service Error. 1779 */ 1780 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1781 { 1782 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1783 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1784 } 1785 1786 /* xHCI debugging */ 1787 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1788 struct xhci_container_ctx *ctx); 1789 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1790 const char *fmt, ...); 1791 1792 /* xHCI memory management */ 1793 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1794 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1795 void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev, int slot_id); 1796 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1797 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1798 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1799 struct usb_device *udev); 1800 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1801 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1802 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1803 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1804 struct xhci_virt_device *virt_dev, 1805 int old_active_eps); 1806 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1807 void xhci_update_bw_info(struct xhci_hcd *xhci, 1808 struct xhci_container_ctx *in_ctx, 1809 struct xhci_input_control_ctx *ctrl_ctx, 1810 struct xhci_virt_device *virt_dev); 1811 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1812 struct xhci_container_ctx *in_ctx, 1813 struct xhci_container_ctx *out_ctx, 1814 unsigned int ep_index); 1815 void xhci_slot_copy(struct xhci_hcd *xhci, 1816 struct xhci_container_ctx *in_ctx, 1817 struct xhci_container_ctx *out_ctx); 1818 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1819 struct usb_device *udev, struct usb_host_endpoint *ep, 1820 gfp_t mem_flags); 1821 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1822 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1823 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1824 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1825 unsigned int num_trbs, gfp_t flags); 1826 void xhci_initialize_ring_info(struct xhci_ring *ring); 1827 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1828 struct xhci_virt_device *virt_dev, 1829 unsigned int ep_index); 1830 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1831 unsigned int num_stream_ctxs, 1832 unsigned int num_streams, 1833 unsigned int max_packet, gfp_t flags); 1834 void xhci_free_stream_info(struct xhci_hcd *xhci, 1835 struct xhci_stream_info *stream_info); 1836 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1837 struct xhci_ep_ctx *ep_ctx, 1838 struct xhci_stream_info *stream_info); 1839 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1840 struct xhci_virt_ep *ep); 1841 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1842 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1843 struct xhci_ring *xhci_dma_to_transfer_ring( 1844 struct xhci_virt_ep *ep, 1845 u64 address); 1846 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1847 bool allocate_completion, gfp_t mem_flags); 1848 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1849 bool allocate_completion, gfp_t mem_flags); 1850 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1851 void xhci_free_command(struct xhci_hcd *xhci, 1852 struct xhci_command *command); 1853 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1854 int type, gfp_t flags); 1855 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1856 struct xhci_container_ctx *ctx); 1857 struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci, 1858 gfp_t flags); 1859 void xhci_free_port_bw_ctx(struct xhci_hcd *xhci, 1860 struct xhci_container_ctx *ctx); 1861 struct xhci_interrupter * 1862 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1863 u32 imod_interval, unsigned int intr_num); 1864 void xhci_remove_secondary_interrupter(struct usb_hcd 1865 *hcd, struct xhci_interrupter *ir); 1866 void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, 1867 struct xhci_ring *ring, 1868 struct xhci_interrupter *ir); 1869 1870 /* xHCI host controller glue */ 1871 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1872 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1873 void xhci_quiesce(struct xhci_hcd *xhci); 1874 int xhci_halt(struct xhci_hcd *xhci); 1875 int xhci_start(struct xhci_hcd *xhci); 1876 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1877 int xhci_run(struct usb_hcd *hcd); 1878 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1879 void xhci_shutdown(struct usb_hcd *hcd); 1880 void xhci_stop(struct usb_hcd *hcd); 1881 void xhci_init_driver(struct hc_driver *drv, 1882 const struct xhci_driver_overrides *over); 1883 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1884 struct usb_host_endpoint *ep); 1885 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1886 struct usb_host_endpoint *ep); 1887 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1888 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1889 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1890 struct usb_tt *tt, gfp_t mem_flags); 1891 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1892 int xhci_disable_and_free_slot(struct xhci_hcd *xhci, u32 slot_id); 1893 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1894 1895 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1896 int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1897 1898 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1899 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1900 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1901 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1902 struct xhci_virt_device *virt_dev, 1903 struct usb_device *hdev, 1904 struct usb_tt *tt, gfp_t mem_flags); 1905 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1906 u32 imod_interval); 1907 int xhci_enable_interrupter(struct xhci_interrupter *ir); 1908 int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir); 1909 1910 /* xHCI ring, segment, TRB, and TD functions */ 1911 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1912 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1913 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1914 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1915 u32 trb_type, u32 slot_id); 1916 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1917 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1918 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1919 u32 field1, u32 field2, u32 field3, u32 field4); 1920 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1921 int slot_id, unsigned int ep_index, int suspend); 1922 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1923 int slot_id, unsigned int ep_index); 1924 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1925 int slot_id, unsigned int ep_index); 1926 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1927 int slot_id, unsigned int ep_index); 1928 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1929 struct urb *urb, int slot_id, unsigned int ep_index); 1930 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1931 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1932 bool command_must_succeed); 1933 int xhci_queue_get_port_bw(struct xhci_hcd *xhci, 1934 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 1935 u8 dev_speed, bool command_must_succeed); 1936 int xhci_get_port_bandwidth(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, 1937 u8 dev_speed); 1938 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1939 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1940 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1941 int slot_id, unsigned int ep_index, 1942 enum xhci_ep_reset_type reset_type); 1943 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1944 u32 slot_id); 1945 void xhci_handle_command_timeout(struct work_struct *work); 1946 1947 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1948 unsigned int ep_index, unsigned int stream_id); 1949 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1950 unsigned int slot_id, 1951 unsigned int ep_index); 1952 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1953 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1954 unsigned int count_trbs(u64 addr, u64 len); 1955 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1956 int suspend, gfp_t gfp_flags); 1957 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1958 void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 1959 struct xhci_interrupter *ir, 1960 bool clear_ehb); 1961 void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num); 1962 int xhci_usb_endpoint_maxp(struct usb_device *udev, 1963 struct usb_host_endpoint *host_ep); 1964 1965 /* xHCI roothub code */ 1966 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1967 u32 link_state); 1968 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1969 u32 port_bit); 1970 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1971 char *buf, u16 wLength); 1972 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1973 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1974 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1975 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1976 struct xhci_port *port); 1977 void xhci_hc_died(struct xhci_hcd *xhci); 1978 1979 #ifdef CONFIG_PM 1980 int xhci_bus_suspend(struct usb_hcd *hcd); 1981 int xhci_bus_resume(struct usb_hcd *hcd); 1982 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1983 #else 1984 #define xhci_bus_suspend NULL 1985 #define xhci_bus_resume NULL 1986 #define xhci_get_resuming_ports NULL 1987 #endif /* CONFIG_PM */ 1988 1989 u32 xhci_port_state_to_neutral(u32 state); 1990 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1991 1992 /* xHCI contexts */ 1993 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1994 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1995 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1996 1997 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1998 unsigned int slot_id, unsigned int ep_index, 1999 unsigned int stream_id); 2000 2001 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2002 struct urb *urb) 2003 { 2004 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2005 xhci_get_endpoint_index(&urb->ep->desc), 2006 urb->stream_id); 2007 } 2008 2009 /* 2010 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2011 * them anyways as we where unable to find a device that matches the 2012 * constraints. 2013 */ 2014 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2015 { 2016 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2017 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2018 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2019 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2020 !urb->num_sgs) 2021 return true; 2022 2023 return false; 2024 } 2025 2026 static inline char *xhci_slot_state_string(u32 state) 2027 { 2028 switch (state) { 2029 case SLOT_STATE_ENABLED: 2030 return "enabled/disabled"; 2031 case SLOT_STATE_DEFAULT: 2032 return "default"; 2033 case SLOT_STATE_ADDRESSED: 2034 return "addressed"; 2035 case SLOT_STATE_CONFIGURED: 2036 return "configured"; 2037 default: 2038 return "reserved"; 2039 } 2040 } 2041 2042 static inline const char *xhci_decode_trb(char *str, size_t size, 2043 u32 field0, u32 field1, u32 field2, u32 field3) 2044 { 2045 int type = TRB_FIELD_TO_TYPE(field3); 2046 2047 switch (type) { 2048 case TRB_LINK: 2049 snprintf(str, size, 2050 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2051 field1, field0, GET_INTR_TARGET(field2), 2052 xhci_trb_type_string(type), 2053 field3 & TRB_IOC ? 'I' : 'i', 2054 field3 & TRB_CHAIN ? 'C' : 'c', 2055 field3 & TRB_TC ? 'T' : 't', 2056 field3 & TRB_CYCLE ? 'C' : 'c'); 2057 break; 2058 case TRB_TRANSFER: 2059 case TRB_COMPLETION: 2060 case TRB_PORT_STATUS: 2061 case TRB_BANDWIDTH_EVENT: 2062 case TRB_DOORBELL: 2063 case TRB_HC_EVENT: 2064 case TRB_DEV_NOTE: 2065 case TRB_MFINDEX_WRAP: 2066 snprintf(str, size, 2067 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2068 field1, field0, 2069 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2070 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2071 TRB_TO_EP_ID(field3), 2072 xhci_trb_type_string(type), 2073 field3 & EVENT_DATA ? 'E' : 'e', 2074 field3 & TRB_CYCLE ? 'C' : 'c'); 2075 2076 break; 2077 case TRB_SETUP: 2078 snprintf(str, size, 2079 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2080 field0 & 0xff, 2081 (field0 & 0xff00) >> 8, 2082 (field0 & 0xff000000) >> 24, 2083 (field0 & 0xff0000) >> 16, 2084 (field1 & 0xff00) >> 8, 2085 field1 & 0xff, 2086 (field1 & 0xff000000) >> 16 | 2087 (field1 & 0xff0000) >> 16, 2088 TRB_LEN(field2), GET_TD_SIZE(field2), 2089 GET_INTR_TARGET(field2), 2090 xhci_trb_type_string(type), 2091 field3 & TRB_IDT ? 'I' : 'i', 2092 field3 & TRB_IOC ? 'I' : 'i', 2093 field3 & TRB_CYCLE ? 'C' : 'c'); 2094 break; 2095 case TRB_DATA: 2096 snprintf(str, size, 2097 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2098 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2099 GET_INTR_TARGET(field2), 2100 xhci_trb_type_string(type), 2101 field3 & TRB_IDT ? 'I' : 'i', 2102 field3 & TRB_IOC ? 'I' : 'i', 2103 field3 & TRB_CHAIN ? 'C' : 'c', 2104 field3 & TRB_NO_SNOOP ? 'S' : 's', 2105 field3 & TRB_ISP ? 'I' : 'i', 2106 field3 & TRB_ENT ? 'E' : 'e', 2107 field3 & TRB_CYCLE ? 'C' : 'c'); 2108 break; 2109 case TRB_STATUS: 2110 snprintf(str, size, 2111 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2112 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2113 GET_INTR_TARGET(field2), 2114 xhci_trb_type_string(type), 2115 field3 & TRB_IOC ? 'I' : 'i', 2116 field3 & TRB_CHAIN ? 'C' : 'c', 2117 field3 & TRB_ENT ? 'E' : 'e', 2118 field3 & TRB_CYCLE ? 'C' : 'c'); 2119 break; 2120 case TRB_NORMAL: 2121 case TRB_EVENT_DATA: 2122 case TRB_TR_NOOP: 2123 snprintf(str, size, 2124 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2125 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2126 GET_INTR_TARGET(field2), 2127 xhci_trb_type_string(type), 2128 field3 & TRB_BEI ? 'B' : 'b', 2129 field3 & TRB_IDT ? 'I' : 'i', 2130 field3 & TRB_IOC ? 'I' : 'i', 2131 field3 & TRB_CHAIN ? 'C' : 'c', 2132 field3 & TRB_NO_SNOOP ? 'S' : 's', 2133 field3 & TRB_ISP ? 'I' : 'i', 2134 field3 & TRB_ENT ? 'E' : 'e', 2135 field3 & TRB_CYCLE ? 'C' : 'c'); 2136 break; 2137 case TRB_ISOC: 2138 snprintf(str, size, 2139 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2140 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2141 GET_INTR_TARGET(field2), 2142 xhci_trb_type_string(type), 2143 GET_TBC(field3), 2144 GET_TLBPC(field3), 2145 GET_FRAME_ID(field3), 2146 field3 & TRB_SIA ? 'S' : 's', 2147 field3 & TRB_BEI ? 'B' : 'b', 2148 field3 & TRB_IDT ? 'I' : 'i', 2149 field3 & TRB_IOC ? 'I' : 'i', 2150 field3 & TRB_CHAIN ? 'C' : 'c', 2151 field3 & TRB_NO_SNOOP ? 'S' : 's', 2152 field3 & TRB_ISP ? 'I' : 'i', 2153 field3 & TRB_ENT ? 'E' : 'e', 2154 field3 & TRB_CYCLE ? 'C' : 'c'); 2155 break; 2156 case TRB_CMD_NOOP: 2157 case TRB_ENABLE_SLOT: 2158 snprintf(str, size, 2159 "%s: flags %c", 2160 xhci_trb_type_string(type), 2161 field3 & TRB_CYCLE ? 'C' : 'c'); 2162 break; 2163 case TRB_DISABLE_SLOT: 2164 case TRB_NEG_BANDWIDTH: 2165 snprintf(str, size, 2166 "%s: slot %d flags %c", 2167 xhci_trb_type_string(type), 2168 TRB_TO_SLOT_ID(field3), 2169 field3 & TRB_CYCLE ? 'C' : 'c'); 2170 break; 2171 case TRB_ADDR_DEV: 2172 snprintf(str, size, 2173 "%s: ctx %08x%08x slot %d flags %c:%c", 2174 xhci_trb_type_string(type), 2175 field1, field0, 2176 TRB_TO_SLOT_ID(field3), 2177 field3 & TRB_BSR ? 'B' : 'b', 2178 field3 & TRB_CYCLE ? 'C' : 'c'); 2179 break; 2180 case TRB_CONFIG_EP: 2181 snprintf(str, size, 2182 "%s: ctx %08x%08x slot %d flags %c:%c", 2183 xhci_trb_type_string(type), 2184 field1, field0, 2185 TRB_TO_SLOT_ID(field3), 2186 field3 & TRB_DC ? 'D' : 'd', 2187 field3 & TRB_CYCLE ? 'C' : 'c'); 2188 break; 2189 case TRB_EVAL_CONTEXT: 2190 snprintf(str, size, 2191 "%s: ctx %08x%08x slot %d flags %c", 2192 xhci_trb_type_string(type), 2193 field1, field0, 2194 TRB_TO_SLOT_ID(field3), 2195 field3 & TRB_CYCLE ? 'C' : 'c'); 2196 break; 2197 case TRB_RESET_EP: 2198 snprintf(str, size, 2199 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2200 xhci_trb_type_string(type), 2201 field1, field0, 2202 TRB_TO_SLOT_ID(field3), 2203 TRB_TO_EP_ID(field3), 2204 field3 & TRB_TSP ? 'T' : 't', 2205 field3 & TRB_CYCLE ? 'C' : 'c'); 2206 break; 2207 case TRB_STOP_RING: 2208 snprintf(str, size, 2209 "%s: slot %d sp %d ep %d flags %c", 2210 xhci_trb_type_string(type), 2211 TRB_TO_SLOT_ID(field3), 2212 TRB_TO_SUSPEND_PORT(field3), 2213 TRB_TO_EP_ID(field3), 2214 field3 & TRB_CYCLE ? 'C' : 'c'); 2215 break; 2216 case TRB_SET_DEQ: 2217 snprintf(str, size, 2218 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2219 xhci_trb_type_string(type), 2220 field1, field0, 2221 TRB_TO_STREAM_ID(field2), 2222 TRB_TO_SLOT_ID(field3), 2223 TRB_TO_EP_ID(field3), 2224 field3 & TRB_CYCLE ? 'C' : 'c'); 2225 break; 2226 case TRB_RESET_DEV: 2227 snprintf(str, size, 2228 "%s: slot %d flags %c", 2229 xhci_trb_type_string(type), 2230 TRB_TO_SLOT_ID(field3), 2231 field3 & TRB_CYCLE ? 'C' : 'c'); 2232 break; 2233 case TRB_FORCE_EVENT: 2234 snprintf(str, size, 2235 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2236 xhci_trb_type_string(type), 2237 field1, field0, 2238 TRB_TO_VF_INTR_TARGET(field2), 2239 TRB_TO_VF_ID(field3), 2240 field3 & TRB_CYCLE ? 'C' : 'c'); 2241 break; 2242 case TRB_SET_LT: 2243 snprintf(str, size, 2244 "%s: belt %d flags %c", 2245 xhci_trb_type_string(type), 2246 TRB_TO_BELT(field3), 2247 field3 & TRB_CYCLE ? 'C' : 'c'); 2248 break; 2249 case TRB_GET_BW: 2250 snprintf(str, size, 2251 "%s: ctx %08x%08x slot %d speed %d flags %c", 2252 xhci_trb_type_string(type), 2253 field1, field0, 2254 TRB_TO_SLOT_ID(field3), 2255 TRB_TO_DEV_SPEED(field3), 2256 field3 & TRB_CYCLE ? 'C' : 'c'); 2257 break; 2258 case TRB_FORCE_HEADER: 2259 snprintf(str, size, 2260 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2261 xhci_trb_type_string(type), 2262 field2, field1, field0 & 0xffffffe0, 2263 TRB_TO_PACKET_TYPE(field0), 2264 TRB_TO_ROOTHUB_PORT(field3), 2265 field3 & TRB_CYCLE ? 'C' : 'c'); 2266 break; 2267 default: 2268 snprintf(str, size, 2269 "type '%s' -> raw %08x %08x %08x %08x", 2270 xhci_trb_type_string(type), 2271 field0, field1, field2, field3); 2272 } 2273 2274 return str; 2275 } 2276 2277 static inline const char *xhci_decode_ctrl_ctx(char *str, 2278 unsigned long drop, unsigned long add) 2279 { 2280 unsigned int bit; 2281 int ret = 0; 2282 2283 str[0] = '\0'; 2284 2285 if (drop) { 2286 ret = sprintf(str, "Drop:"); 2287 for_each_set_bit(bit, &drop, 32) 2288 ret += sprintf(str + ret, " %d%s", 2289 bit / 2, 2290 bit % 2 ? "in":"out"); 2291 ret += sprintf(str + ret, ", "); 2292 } 2293 2294 if (add) { 2295 ret += sprintf(str + ret, "Add:%s%s", 2296 (add & SLOT_FLAG) ? " slot":"", 2297 (add & EP0_FLAG) ? " ep0":""); 2298 add &= ~(SLOT_FLAG | EP0_FLAG); 2299 for_each_set_bit(bit, &add, 32) 2300 ret += sprintf(str + ret, " %d%s", 2301 bit / 2, 2302 bit % 2 ? "in":"out"); 2303 } 2304 return str; 2305 } 2306 2307 static inline const char *xhci_decode_slot_context(char *str, 2308 u32 info, u32 info2, u32 tt_info, u32 state) 2309 { 2310 u32 speed; 2311 u32 hub; 2312 u32 mtt; 2313 int ret = 0; 2314 2315 speed = info & DEV_SPEED; 2316 hub = info & DEV_HUB; 2317 mtt = info & DEV_MTT; 2318 2319 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2320 info & ROUTE_STRING_MASK, 2321 ({ char *s; 2322 switch (speed) { 2323 case SLOT_SPEED_FS: 2324 s = "full-speed"; 2325 break; 2326 case SLOT_SPEED_LS: 2327 s = "low-speed"; 2328 break; 2329 case SLOT_SPEED_HS: 2330 s = "high-speed"; 2331 break; 2332 case SLOT_SPEED_SS: 2333 s = "super-speed"; 2334 break; 2335 case SLOT_SPEED_SSP: 2336 s = "super-speed plus"; 2337 break; 2338 default: 2339 s = "UNKNOWN speed"; 2340 } s; }), 2341 mtt ? " multi-TT" : "", 2342 hub ? " Hub" : "", 2343 (info & LAST_CTX_MASK) >> 27, 2344 info2 & MAX_EXIT, 2345 DEVINFO_TO_ROOT_HUB_PORT(info2), 2346 DEVINFO_TO_MAX_PORTS(info2)); 2347 2348 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2349 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2350 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2351 state & DEV_ADDR_MASK, 2352 xhci_slot_state_string(GET_SLOT_STATE(state))); 2353 2354 return str; 2355 } 2356 2357 2358 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2359 { 2360 switch (portsc & PORT_PLS_MASK) { 2361 case XDEV_U0: 2362 return "U0"; 2363 case XDEV_U1: 2364 return "U1"; 2365 case XDEV_U2: 2366 return "U2"; 2367 case XDEV_U3: 2368 return "U3"; 2369 case XDEV_DISABLED: 2370 return "Disabled"; 2371 case XDEV_RXDETECT: 2372 return "RxDetect"; 2373 case XDEV_INACTIVE: 2374 return "Inactive"; 2375 case XDEV_POLLING: 2376 return "Polling"; 2377 case XDEV_RECOVERY: 2378 return "Recovery"; 2379 case XDEV_HOT_RESET: 2380 return "Hot Reset"; 2381 case XDEV_COMP_MODE: 2382 return "Compliance mode"; 2383 case XDEV_TEST_MODE: 2384 return "Test mode"; 2385 case XDEV_RESUME: 2386 return "Resume"; 2387 default: 2388 break; 2389 } 2390 return "Unknown"; 2391 } 2392 2393 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2394 { 2395 int ret; 2396 2397 ret = sprintf(str, "0x%08x ", portsc); 2398 2399 if (portsc == ~(u32)0) 2400 return str; 2401 2402 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ", 2403 portsc & PORT_POWER ? "Powered" : "Powered-off", 2404 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2405 portsc & PORT_PE ? "Enabled" : "Disabled", 2406 xhci_portsc_link_state_string(portsc), 2407 DEV_PORT_SPEED(portsc)); 2408 2409 if (portsc & PORT_OC) 2410 ret += sprintf(str + ret, "OverCurrent "); 2411 if (portsc & PORT_RESET) 2412 ret += sprintf(str + ret, "In-Reset "); 2413 2414 ret += sprintf(str + ret, "Change: "); 2415 if (portsc & PORT_CSC) 2416 ret += sprintf(str + ret, "CSC "); 2417 if (portsc & PORT_PEC) 2418 ret += sprintf(str + ret, "PEC "); 2419 if (portsc & PORT_WRC) 2420 ret += sprintf(str + ret, "WRC "); 2421 if (portsc & PORT_OCC) 2422 ret += sprintf(str + ret, "OCC "); 2423 if (portsc & PORT_RC) 2424 ret += sprintf(str + ret, "PRC "); 2425 if (portsc & PORT_PLC) 2426 ret += sprintf(str + ret, "PLC "); 2427 if (portsc & PORT_CEC) 2428 ret += sprintf(str + ret, "CEC "); 2429 if (portsc & PORT_CAS) 2430 ret += sprintf(str + ret, "CAS "); 2431 2432 ret += sprintf(str + ret, "Wake: "); 2433 if (portsc & PORT_WKCONN_E) 2434 ret += sprintf(str + ret, "WCE "); 2435 if (portsc & PORT_WKDISC_E) 2436 ret += sprintf(str + ret, "WDE "); 2437 if (portsc & PORT_WKOC_E) 2438 ret += sprintf(str + ret, "WOE "); 2439 2440 return str; 2441 } 2442 2443 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2444 { 2445 int ret = 0; 2446 2447 ret = sprintf(str, " 0x%08x", usbsts); 2448 2449 if (usbsts == ~(u32)0) 2450 return str; 2451 2452 if (usbsts & STS_HALT) 2453 ret += sprintf(str + ret, " HCHalted"); 2454 if (usbsts & STS_FATAL) 2455 ret += sprintf(str + ret, " HSE"); 2456 if (usbsts & STS_EINT) 2457 ret += sprintf(str + ret, " EINT"); 2458 if (usbsts & STS_PORT) 2459 ret += sprintf(str + ret, " PCD"); 2460 if (usbsts & STS_SAVE) 2461 ret += sprintf(str + ret, " SSS"); 2462 if (usbsts & STS_RESTORE) 2463 ret += sprintf(str + ret, " RSS"); 2464 if (usbsts & STS_SRE) 2465 ret += sprintf(str + ret, " SRE"); 2466 if (usbsts & STS_CNR) 2467 ret += sprintf(str + ret, " CNR"); 2468 if (usbsts & STS_HCE) 2469 ret += sprintf(str + ret, " HCE"); 2470 2471 return str; 2472 } 2473 2474 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2475 { 2476 u8 ep; 2477 u16 stream; 2478 int ret; 2479 2480 ep = (doorbell & 0xff); 2481 stream = doorbell >> 16; 2482 2483 if (slot == 0) { 2484 sprintf(str, "Command Ring %d", doorbell); 2485 return str; 2486 } 2487 ret = sprintf(str, "Slot %d ", slot); 2488 if (ep > 0 && ep < 32) 2489 ret = sprintf(str + ret, "ep%d%s", 2490 ep / 2, 2491 ep % 2 ? "in" : "out"); 2492 else if (ep == 0 || ep < 248) 2493 ret = sprintf(str + ret, "Reserved %d", ep); 2494 else 2495 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2496 if (stream) 2497 ret = sprintf(str + ret, " Stream %d", stream); 2498 2499 return str; 2500 } 2501 2502 static inline const char *xhci_ep_state_string(u8 state) 2503 { 2504 switch (state) { 2505 case EP_STATE_DISABLED: 2506 return "disabled"; 2507 case EP_STATE_RUNNING: 2508 return "running"; 2509 case EP_STATE_HALTED: 2510 return "halted"; 2511 case EP_STATE_STOPPED: 2512 return "stopped"; 2513 case EP_STATE_ERROR: 2514 return "error"; 2515 default: 2516 return "INVALID"; 2517 } 2518 } 2519 2520 static inline const char *xhci_ep_type_string(u8 type) 2521 { 2522 switch (type) { 2523 case ISOC_OUT_EP: 2524 return "Isoc OUT"; 2525 case BULK_OUT_EP: 2526 return "Bulk OUT"; 2527 case INT_OUT_EP: 2528 return "Int OUT"; 2529 case CTRL_EP: 2530 return "Ctrl"; 2531 case ISOC_IN_EP: 2532 return "Isoc IN"; 2533 case BULK_IN_EP: 2534 return "Bulk IN"; 2535 case INT_IN_EP: 2536 return "Int IN"; 2537 default: 2538 return "INVALID"; 2539 } 2540 } 2541 2542 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2543 u32 info2, u64 deq, u32 tx_info) 2544 { 2545 int ret; 2546 2547 u32 esit; 2548 u16 maxp; 2549 u16 avg; 2550 2551 u8 max_pstr; 2552 u8 ep_state; 2553 u8 interval; 2554 u8 ep_type; 2555 u8 burst; 2556 u8 cerr; 2557 u8 mult; 2558 2559 bool lsa; 2560 bool hid; 2561 2562 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2563 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2564 2565 ep_state = info & EP_STATE_MASK; 2566 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2567 interval = CTX_TO_EP_INTERVAL(info); 2568 mult = CTX_TO_EP_MULT(info) + 1; 2569 lsa = !!(info & EP_HAS_LSA); 2570 2571 cerr = (info2 & (3 << 1)) >> 1; 2572 ep_type = CTX_TO_EP_TYPE(info2); 2573 hid = !!(info2 & (1 << 7)); 2574 burst = CTX_TO_MAX_BURST(info2); 2575 maxp = MAX_PACKET_DECODED(info2); 2576 2577 avg = EP_AVG_TRB_LENGTH(tx_info); 2578 2579 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2580 xhci_ep_state_string(ep_state), mult, 2581 max_pstr, lsa ? "LSA " : ""); 2582 2583 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2584 (1 << interval) * 125, esit, cerr); 2585 2586 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2587 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2588 burst, maxp, deq); 2589 2590 ret += sprintf(str + ret, "avg trb len %d", avg); 2591 2592 return str; 2593 } 2594 2595 #endif /* __LINUX_XHCI_HCD_H */ 2596