1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 #include "xhci-port.h" 27 #include "xhci-caps.h" 28 29 /* max buffer size for trace and debug messages */ 30 #define XHCI_MSG_MAX 500 31 32 /* xHCI PCI Configuration Registers */ 33 #define XHCI_SBRN_OFFSET (0x60) 34 35 /* Max number of USB devices for any host controller - limit in section 6.1 */ 36 #define MAX_HC_SLOTS 256 37 /* Section 5.3.3 - MaxPorts */ 38 #define MAX_HC_PORTS 127 39 40 /* 41 * xHCI register interface. 42 * This corresponds to the eXtensible Host Controller Interface (xHCI) 43 * Revision 0.95 specification 44 */ 45 46 /** 47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 48 * @hc_capbase: length of the capabilities register and HC version number 49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 52 * @hcc_params: HCCPARAMS - Capability Parameters 53 * @db_off: DBOFF - Doorbell array offset 54 * @run_regs_off: RTSOFF - Runtime register space offset 55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 56 */ 57 struct xhci_cap_regs { 58 __le32 hc_capbase; 59 __le32 hcs_params1; 60 __le32 hcs_params2; 61 __le32 hcs_params3; 62 __le32 hcc_params; 63 __le32 db_off; 64 __le32 run_regs_off; 65 __le32 hcc_params2; /* xhci 1.1 */ 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* Number of registers per port */ 70 #define NUM_PORT_REGS 4 71 72 #define PORTSC 0 73 #define PORTPMSC 1 74 #define PORTLI 2 75 #define PORTHLPMC 3 76 77 /** 78 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 79 * @command: USBCMD - xHC command register 80 * @status: USBSTS - xHC status register 81 * @page_size: This indicates the page size that the host controller 82 * supports. If bit n is set, the HC supports a page size 83 * of 2^(n+12), up to a 128MB page size. 84 * 4K is the minimum page size. 85 * @cmd_ring: CRP - 64-bit Command Ring Pointer 86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 87 * @config_reg: CONFIG - Configure Register 88 * @port_status_base: PORTSCn - base address for Port Status and Control 89 * Each port has a Port Status and Control register, 90 * followed by a Port Power Management Status and Control 91 * register, a Port Link Info register, and a reserved 92 * register. 93 * @port_power_base: PORTPMSCn - base address for 94 * Port Power Management Status and Control 95 * @port_link_base: PORTLIn - base address for Port Link Info (current 96 * Link PM state and control) for USB 2.1 and USB 3.0 97 * devices. 98 */ 99 struct xhci_op_regs { 100 __le32 command; 101 __le32 status; 102 __le32 page_size; 103 __le32 reserved1; 104 __le32 reserved2; 105 __le32 dev_notification; 106 __le64 cmd_ring; 107 /* rsvd: offset 0x20-2F */ 108 __le32 reserved3[4]; 109 __le64 dcbaa_ptr; 110 __le32 config_reg; 111 /* rsvd: offset 0x3C-3FF */ 112 __le32 reserved4[241]; 113 /* port 1 registers, which serve as a base address for other ports */ 114 __le32 port_status_base; 115 __le32 port_power_base; 116 __le32 port_link_base; 117 __le32 reserved5; 118 /* registers for ports 2-255 */ 119 __le32 reserved6[NUM_PORT_REGS*254]; 120 }; 121 122 /* USBCMD - USB command - command bitmasks */ 123 /* start/stop HC execution - do not write unless HC is halted*/ 124 #define CMD_RUN XHCI_CMD_RUN 125 /* Reset HC - resets internal HC state machine and all registers (except 126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 127 * The xHCI driver must reinitialize the xHC after setting this bit. 128 */ 129 #define CMD_RESET (1 << 1) 130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 131 #define CMD_EIE XHCI_CMD_EIE 132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 133 #define CMD_HSEIE XHCI_CMD_HSEIE 134 /* bits 4:6 are reserved (and should be preserved on writes). */ 135 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 136 #define CMD_LRESET (1 << 7) 137 /* host controller save/restore state. */ 138 #define CMD_CSS (1 << 8) 139 #define CMD_CRS (1 << 9) 140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 141 #define CMD_EWE XHCI_CMD_EWE 142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 144 * '0' means the xHC can power it off if all ports are in the disconnect, 145 * disabled, or powered-off state. 146 */ 147 #define CMD_PM_INDEX (1 << 11) 148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 149 #define CMD_ETE (1 << 14) 150 /* bits 15:31 are reserved (and should be preserved on writes). */ 151 152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 153 #define XHCI_RESET_SHORT_USEC (250 * 1000) 154 155 /* IMAN - Interrupt Management Register */ 156 #define IMAN_IE (1 << 1) 157 #define IMAN_IP (1 << 0) 158 159 /* USBSTS - USB status - status bitmasks */ 160 /* HC not running - set to 1 when run/stop bit is cleared. */ 161 #define STS_HALT XHCI_STS_HALT 162 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 163 #define STS_FATAL (1 << 2) 164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 165 #define STS_EINT (1 << 3) 166 /* port change detect */ 167 #define STS_PORT (1 << 4) 168 /* bits 5:7 reserved and zeroed */ 169 /* save state status - '1' means xHC is saving state */ 170 #define STS_SAVE (1 << 8) 171 /* restore state status - '1' means xHC is restoring state */ 172 #define STS_RESTORE (1 << 9) 173 /* true: save or restore error */ 174 #define STS_SRE (1 << 10) 175 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 176 #define STS_CNR XHCI_STS_CNR 177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 178 #define STS_HCE (1 << 12) 179 /* bits 13:31 reserved and should be preserved */ 180 181 /* 182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 183 * Generate a device notification event when the HC sees a transaction with a 184 * notification type that matches a bit set in this bit field. 185 */ 186 #define DEV_NOTE_MASK (0xffff) 187 #define ENABLE_DEV_NOTE(x) (1 << (x)) 188 /* Most of the device notification types should only be used for debug. 189 * SW does need to pay attention to function wake notifications. 190 */ 191 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 192 193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 194 /* bit 0 is the command ring cycle state */ 195 /* stop ring operation after completion of the currently executing command */ 196 #define CMD_RING_PAUSE (1 << 1) 197 /* stop ring immediately - abort the currently executing command */ 198 #define CMD_RING_ABORT (1 << 2) 199 /* true: command ring is running */ 200 #define CMD_RING_RUNNING (1 << 3) 201 /* bits 4:5 reserved and should be preserved */ 202 /* Command Ring pointer - bit mask for the lower 32 bits. */ 203 #define CMD_RING_RSVD_BITS (0x3f) 204 205 /* CONFIG - Configure Register - config_reg bitmasks */ 206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 207 #define MAX_DEVS(p) ((p) & 0xff) 208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 209 #define CONFIG_U3E (1 << 8) 210 /* bit 9: Configuration Information Enable, xhci 1.1 */ 211 #define CONFIG_CIE (1 << 9) 212 /* bits 10:31 - reserved and should be preserved */ 213 214 /* bits 15:0 - HCD page shift bit */ 215 #define XHCI_PAGE_SIZE_MASK 0xffff 216 217 /** 218 * struct xhci_intr_reg - Interrupt Register Set 219 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 220 * interrupts and check for pending interrupts. 221 * @irq_control: IMOD - Interrupt Moderation Register. 222 * Used to throttle interrupts. 223 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 224 * @erst_base: ERST base address. 225 * @erst_dequeue: Event ring dequeue pointer. 226 * 227 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 228 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 229 * multiple segments of the same size. The HC places events on the ring and 230 * "updates the Cycle bit in the TRBs to indicate to software the current 231 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 232 * updates the dequeue pointer. 233 */ 234 struct xhci_intr_reg { 235 __le32 irq_pending; 236 __le32 irq_control; 237 __le32 erst_size; 238 __le32 rsvd; 239 __le64 erst_base; 240 __le64 erst_dequeue; 241 }; 242 243 /* irq_pending bitmasks */ 244 #define ER_IRQ_PENDING(p) ((p) & 0x1) 245 /* bits 2:31 need to be preserved */ 246 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 247 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 248 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 249 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 250 251 /* irq_control bitmasks */ 252 /* Minimum interval between interrupts (in 250ns intervals). The interval 253 * between interrupts will be longer if there are no events on the event ring. 254 * Default is 4000 (1 ms). 255 */ 256 #define ER_IRQ_INTERVAL_MASK (0xffff) 257 /* Counter used to count down the time to the next interrupt - HW use only */ 258 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 259 260 /* erst_size bitmasks */ 261 /* Preserve bits 16:31 of erst_size */ 262 #define ERST_SIZE_MASK (0xffff << 16) 263 264 /* erst_base bitmasks */ 265 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) 266 267 /* erst_dequeue bitmasks */ 268 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 269 * where the current dequeue pointer lies. This is an optional HW hint. 270 */ 271 #define ERST_DESI_MASK (0x7) 272 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 273 * a work queue (or delayed service routine)? 274 */ 275 #define ERST_EHB (1 << 3) 276 #define ERST_PTR_MASK (GENMASK_ULL(63, 4)) 277 278 /** 279 * struct xhci_run_regs 280 * @microframe_index: 281 * MFINDEX - current microframe number 282 * 283 * Section 5.5 Host Controller Runtime Registers: 284 * "Software should read and write these registers using only Dword (32 bit) 285 * or larger accesses" 286 */ 287 struct xhci_run_regs { 288 __le32 microframe_index; 289 __le32 rsvd[7]; 290 struct xhci_intr_reg ir_set[128]; 291 }; 292 293 /** 294 * struct doorbell_array 295 * 296 * Bits 0 - 7: Endpoint target 297 * Bits 8 - 15: RsvdZ 298 * Bits 16 - 31: Stream ID 299 * 300 * Section 5.6 301 */ 302 struct xhci_doorbell_array { 303 __le32 doorbell[256]; 304 }; 305 306 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 307 #define DB_VALUE_HOST 0x00000000 308 309 #define PLT_MASK (0x03 << 6) 310 #define PLT_SYM (0x00 << 6) 311 #define PLT_ASYM_RX (0x02 << 6) 312 #define PLT_ASYM_TX (0x03 << 6) 313 314 /** 315 * struct xhci_container_ctx 316 * @type: Type of context. Used to calculated offsets to contained contexts. 317 * @size: Size of the context data 318 * @bytes: The raw context data given to HW 319 * @dma: dma address of the bytes 320 * 321 * Represents either a Device or Input context. Holds a pointer to the raw 322 * memory used for the context (bytes) and dma address of it (dma). 323 */ 324 struct xhci_container_ctx { 325 unsigned type; 326 #define XHCI_CTX_TYPE_DEVICE 0x1 327 #define XHCI_CTX_TYPE_INPUT 0x2 328 329 int size; 330 331 u8 *bytes; 332 dma_addr_t dma; 333 }; 334 335 /** 336 * struct xhci_slot_ctx 337 * @dev_info: Route string, device speed, hub info, and last valid endpoint 338 * @dev_info2: Max exit latency for device number, root hub port number 339 * @tt_info: tt_info is used to construct split transaction tokens 340 * @dev_state: slot state and device address 341 * 342 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 343 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 344 * reserved at the end of the slot context for HC internal use. 345 */ 346 struct xhci_slot_ctx { 347 __le32 dev_info; 348 __le32 dev_info2; 349 __le32 tt_info; 350 __le32 dev_state; 351 /* offset 0x10 to 0x1f reserved for HC internal use */ 352 __le32 reserved[4]; 353 }; 354 355 /* dev_info bitmasks */ 356 /* Route String - 0:19 */ 357 #define ROUTE_STRING_MASK (0xfffff) 358 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 359 #define DEV_SPEED (0xf << 20) 360 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 361 /* bit 24 reserved */ 362 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 363 #define DEV_MTT (0x1 << 25) 364 /* Set if the device is a hub - bit 26 */ 365 #define DEV_HUB (0x1 << 26) 366 /* Index of the last valid endpoint context in this device context - 27:31 */ 367 #define LAST_CTX_MASK (0x1f << 27) 368 #define LAST_CTX(p) ((p) << 27) 369 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 370 #define SLOT_FLAG (1 << 0) 371 #define EP0_FLAG (1 << 1) 372 373 /* dev_info2 bitmasks */ 374 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 375 #define MAX_EXIT (0xffff) 376 /* Root hub port number that is needed to access the USB device */ 377 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 378 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 379 /* Maximum number of ports under a hub device */ 380 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 381 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 382 383 /* tt_info bitmasks */ 384 /* 385 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 386 * The Slot ID of the hub that isolates the high speed signaling from 387 * this low or full-speed device. '0' if attached to root hub port. 388 */ 389 #define TT_SLOT (0xff) 390 /* 391 * The number of the downstream facing port of the high-speed hub 392 * '0' if the device is not low or full speed. 393 */ 394 #define TT_PORT (0xff << 8) 395 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 396 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 397 398 /* dev_state bitmasks */ 399 /* USB device address - assigned by the HC */ 400 #define DEV_ADDR_MASK (0xff) 401 /* bits 8:26 reserved */ 402 /* Slot state */ 403 #define SLOT_STATE (0x1f << 27) 404 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 405 406 #define SLOT_STATE_DISABLED 0 407 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 408 #define SLOT_STATE_DEFAULT 1 409 #define SLOT_STATE_ADDRESSED 2 410 #define SLOT_STATE_CONFIGURED 3 411 412 /** 413 * struct xhci_ep_ctx 414 * @ep_info: endpoint state, streams, mult, and interval information. 415 * @ep_info2: information on endpoint type, max packet size, max burst size, 416 * error count, and whether the HC will force an event for all 417 * transactions. 418 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 419 * defines one stream, this points to the endpoint transfer ring. 420 * Otherwise, it points to a stream context array, which has a 421 * ring pointer for each flow. 422 * @tx_info: 423 * Average TRB lengths for the endpoint ring and 424 * max payload within an Endpoint Service Interval Time (ESIT). 425 * 426 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 427 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 428 * reserved at the end of the endpoint context for HC internal use. 429 */ 430 struct xhci_ep_ctx { 431 __le32 ep_info; 432 __le32 ep_info2; 433 __le64 deq; 434 __le32 tx_info; 435 /* offset 0x14 - 0x1f reserved for HC internal use */ 436 __le32 reserved[3]; 437 }; 438 439 /* ep_info bitmasks */ 440 /* 441 * Endpoint State - bits 0:2 442 * 0 - disabled 443 * 1 - running 444 * 2 - halted due to halt condition - ok to manipulate endpoint ring 445 * 3 - stopped 446 * 4 - TRB error 447 * 5-7 - reserved 448 */ 449 #define EP_STATE_MASK (0x7) 450 #define EP_STATE_DISABLED 0 451 #define EP_STATE_RUNNING 1 452 #define EP_STATE_HALTED 2 453 #define EP_STATE_STOPPED 3 454 #define EP_STATE_ERROR 4 455 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 456 457 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 458 #define EP_MULT(p) (((p) & 0x3) << 8) 459 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 460 /* bits 10:14 are Max Primary Streams */ 461 /* bit 15 is Linear Stream Array */ 462 /* Interval - period between requests to an endpoint - 125u increments. */ 463 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 464 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 465 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 466 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 467 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 468 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 469 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 470 #define EP_HAS_LSA (1 << 15) 471 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 472 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 473 474 /* ep_info2 bitmasks */ 475 /* 476 * Force Event - generate transfer events for all TRBs for this endpoint 477 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 478 */ 479 #define FORCE_EVENT (0x1) 480 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 481 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 482 #define EP_TYPE(p) ((p) << 3) 483 #define ISOC_OUT_EP 1 484 #define BULK_OUT_EP 2 485 #define INT_OUT_EP 3 486 #define CTRL_EP 4 487 #define ISOC_IN_EP 5 488 #define BULK_IN_EP 6 489 #define INT_IN_EP 7 490 /* bit 6 reserved */ 491 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 492 #define MAX_BURST(p) (((p)&0xff) << 8) 493 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 494 #define MAX_PACKET(p) (((p)&0xffff) << 16) 495 #define MAX_PACKET_MASK (0xffff << 16) 496 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 497 498 /* tx_info bitmasks */ 499 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 500 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 501 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 502 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 503 504 /* deq bitmasks */ 505 #define EP_CTX_CYCLE_MASK (1 << 0) 506 #define SCTX_DEQ_MASK (~0xfL) 507 508 509 /** 510 * struct xhci_input_control_context 511 * Input control context; see section 6.2.5. 512 * 513 * @drop_context: set the bit of the endpoint context you want to disable 514 * @add_context: set the bit of the endpoint context you want to enable 515 */ 516 struct xhci_input_control_ctx { 517 __le32 drop_flags; 518 __le32 add_flags; 519 __le32 rsvd2[6]; 520 }; 521 522 #define EP_IS_ADDED(ctrl_ctx, i) \ 523 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 524 #define EP_IS_DROPPED(ctrl_ctx, i) \ 525 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 526 527 /* Represents everything that is needed to issue a command on the command ring. 528 * It's useful to pre-allocate these for commands that cannot fail due to 529 * out-of-memory errors, like freeing streams. 530 */ 531 struct xhci_command { 532 /* Input context for changing device state */ 533 struct xhci_container_ctx *in_ctx; 534 u32 status; 535 u32 comp_param; 536 int slot_id; 537 /* If completion is null, no one is waiting on this command 538 * and the structure can be freed after the command completes. 539 */ 540 struct completion *completion; 541 union xhci_trb *command_trb; 542 struct list_head cmd_list; 543 /* xHCI command response timeout in milliseconds */ 544 unsigned int timeout_ms; 545 }; 546 547 /* drop context bitmasks */ 548 #define DROP_EP(x) (0x1 << x) 549 /* add context bitmasks */ 550 #define ADD_EP(x) (0x1 << x) 551 552 struct xhci_stream_ctx { 553 /* 64-bit stream ring address, cycle state, and stream type */ 554 __le64 stream_ring; 555 /* offset 0x14 - 0x1f reserved for HC internal use */ 556 __le32 reserved[2]; 557 }; 558 559 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 560 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 561 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 562 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 563 #define SCT_SEC_TR 0 564 /* Primary stream array type, dequeue pointer is to a transfer ring */ 565 #define SCT_PRI_TR 1 566 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 567 #define SCT_SSA_8 2 568 #define SCT_SSA_16 3 569 #define SCT_SSA_32 4 570 #define SCT_SSA_64 5 571 #define SCT_SSA_128 6 572 #define SCT_SSA_256 7 573 574 /* Assume no secondary streams for now */ 575 struct xhci_stream_info { 576 struct xhci_ring **stream_rings; 577 /* Number of streams, including stream 0 (which drivers can't use) */ 578 unsigned int num_streams; 579 /* The stream context array may be bigger than 580 * the number of streams the driver asked for 581 */ 582 struct xhci_stream_ctx *stream_ctx_array; 583 unsigned int num_stream_ctxs; 584 dma_addr_t ctx_array_dma; 585 /* For mapping physical TRB addresses to segments in stream rings */ 586 struct radix_tree_root trb_address_map; 587 struct xhci_command *free_streams_command; 588 }; 589 590 #define SMALL_STREAM_ARRAY_SIZE 256 591 #define MEDIUM_STREAM_ARRAY_SIZE 1024 592 593 /* Some Intel xHCI host controllers need software to keep track of the bus 594 * bandwidth. Keep track of endpoint info here. Each root port is allocated 595 * the full bus bandwidth. We must also treat TTs (including each port under a 596 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 597 * (DMI) also limits the total bandwidth (across all domains) that can be used. 598 */ 599 struct xhci_bw_info { 600 /* ep_interval is zero-based */ 601 unsigned int ep_interval; 602 /* mult and num_packets are one-based */ 603 unsigned int mult; 604 unsigned int num_packets; 605 unsigned int max_packet_size; 606 unsigned int max_esit_payload; 607 unsigned int type; 608 }; 609 610 /* "Block" sizes in bytes the hardware uses for different device speeds. 611 * The logic in this part of the hardware limits the number of bits the hardware 612 * can use, so must represent bandwidth in a less precise manner to mimic what 613 * the scheduler hardware computes. 614 */ 615 #define FS_BLOCK 1 616 #define HS_BLOCK 4 617 #define SS_BLOCK 16 618 #define DMI_BLOCK 32 619 620 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 621 * with each byte transferred. SuperSpeed devices have an initial overhead to 622 * set up bursts. These are in blocks, see above. LS overhead has already been 623 * translated into FS blocks. 624 */ 625 #define DMI_OVERHEAD 8 626 #define DMI_OVERHEAD_BURST 4 627 #define SS_OVERHEAD 8 628 #define SS_OVERHEAD_BURST 32 629 #define HS_OVERHEAD 26 630 #define FS_OVERHEAD 20 631 #define LS_OVERHEAD 128 632 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 633 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 634 * of overhead associated with split transfers crossing microframe boundaries. 635 * 31 blocks is pure protocol overhead. 636 */ 637 #define TT_HS_OVERHEAD (31 + 94) 638 #define TT_DMI_OVERHEAD (25 + 12) 639 640 /* Bandwidth limits in blocks */ 641 #define FS_BW_LIMIT 1285 642 #define TT_BW_LIMIT 1320 643 #define HS_BW_LIMIT 1607 644 #define SS_BW_LIMIT_IN 3906 645 #define DMI_BW_LIMIT_IN 3906 646 #define SS_BW_LIMIT_OUT 3906 647 #define DMI_BW_LIMIT_OUT 3906 648 649 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 650 #define FS_BW_RESERVED 10 651 #define HS_BW_RESERVED 20 652 #define SS_BW_RESERVED 10 653 654 struct xhci_virt_ep { 655 struct xhci_virt_device *vdev; /* parent */ 656 unsigned int ep_index; 657 struct xhci_ring *ring; 658 /* Related to endpoints that are configured to use stream IDs only */ 659 struct xhci_stream_info *stream_info; 660 /* Temporary storage in case the configure endpoint command fails and we 661 * have to restore the device state to the previous state 662 */ 663 struct xhci_ring *new_ring; 664 unsigned int err_count; 665 unsigned int ep_state; 666 #define SET_DEQ_PENDING (1 << 0) 667 #define EP_HALTED (1 << 1) /* For stall handling */ 668 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 669 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 670 #define EP_GETTING_STREAMS (1 << 3) 671 #define EP_HAS_STREAMS (1 << 4) 672 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 673 #define EP_GETTING_NO_STREAMS (1 << 5) 674 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 675 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 676 /* usb_hub_clear_tt_buffer is in progress */ 677 #define EP_CLEARING_TT (1 << 8) 678 /* ---- Related to URB cancellation ---- */ 679 struct list_head cancelled_td_list; 680 struct xhci_hcd *xhci; 681 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 682 * command. We'll need to update the ring's dequeue segment and dequeue 683 * pointer after the command completes. 684 */ 685 struct xhci_segment *queued_deq_seg; 686 union xhci_trb *queued_deq_ptr; 687 /* 688 * Sometimes the xHC can not process isochronous endpoint ring quickly 689 * enough, and it will miss some isoc tds on the ring and generate 690 * a Missed Service Error Event. 691 * Set skip flag when receive a Missed Service Error Event and 692 * process the missed tds on the endpoint ring. 693 */ 694 bool skip; 695 /* Bandwidth checking storage */ 696 struct xhci_bw_info bw_info; 697 struct list_head bw_endpoint_list; 698 unsigned long stop_time; 699 /* Isoch Frame ID checking storage */ 700 int next_frame_id; 701 /* Use new Isoch TRB layout needed for extended TBC support */ 702 bool use_extended_tbc; 703 }; 704 705 enum xhci_overhead_type { 706 LS_OVERHEAD_TYPE = 0, 707 FS_OVERHEAD_TYPE, 708 HS_OVERHEAD_TYPE, 709 }; 710 711 struct xhci_interval_bw { 712 unsigned int num_packets; 713 /* Sorted by max packet size. 714 * Head of the list is the greatest max packet size. 715 */ 716 struct list_head endpoints; 717 /* How many endpoints of each speed are present. */ 718 unsigned int overhead[3]; 719 }; 720 721 #define XHCI_MAX_INTERVAL 16 722 723 struct xhci_interval_bw_table { 724 unsigned int interval0_esit_payload; 725 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 726 /* Includes reserved bandwidth for async endpoints */ 727 unsigned int bw_used; 728 unsigned int ss_bw_in; 729 unsigned int ss_bw_out; 730 }; 731 732 #define EP_CTX_PER_DEV 31 733 734 struct xhci_virt_device { 735 int slot_id; 736 struct usb_device *udev; 737 /* 738 * Commands to the hardware are passed an "input context" that 739 * tells the hardware what to change in its data structures. 740 * The hardware will return changes in an "output context" that 741 * software must allocate for the hardware. We need to keep 742 * track of input and output contexts separately because 743 * these commands might fail and we don't trust the hardware. 744 */ 745 struct xhci_container_ctx *out_ctx; 746 /* Used for addressing devices and configuration changes */ 747 struct xhci_container_ctx *in_ctx; 748 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 749 struct xhci_port *rhub_port; 750 struct xhci_interval_bw_table *bw_table; 751 struct xhci_tt_bw_info *tt_info; 752 /* 753 * flags for state tracking based on events and issued commands. 754 * Software can not rely on states from output contexts because of 755 * latency between events and xHC updating output context values. 756 * See xhci 1.1 section 4.8.3 for more details 757 */ 758 unsigned long flags; 759 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 760 761 /* The current max exit latency for the enabled USB3 link states. */ 762 u16 current_mel; 763 /* Used for the debugfs interfaces. */ 764 void *debugfs_private; 765 }; 766 767 /* 768 * For each roothub, keep track of the bandwidth information for each periodic 769 * interval. 770 * 771 * If a high speed hub is attached to the roothub, each TT associated with that 772 * hub is a separate bandwidth domain. The interval information for the 773 * endpoints on the devices under that TT will appear in the TT structure. 774 */ 775 struct xhci_root_port_bw_info { 776 struct list_head tts; 777 unsigned int num_active_tts; 778 struct xhci_interval_bw_table bw_table; 779 }; 780 781 struct xhci_tt_bw_info { 782 struct list_head tt_list; 783 int slot_id; 784 int ttport; 785 struct xhci_interval_bw_table bw_table; 786 int active_eps; 787 }; 788 789 790 /** 791 * struct xhci_device_context_array 792 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 793 */ 794 struct xhci_device_context_array { 795 /* 64-bit device addresses; we only write 32-bit addresses */ 796 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 797 /* private xHCD pointers */ 798 dma_addr_t dma; 799 }; 800 /* TODO: write function to set the 64-bit device DMA address */ 801 /* 802 * TODO: change this to be dynamically sized at HC mem init time since the HC 803 * might not be able to handle the maximum number of devices possible. 804 */ 805 806 807 struct xhci_transfer_event { 808 /* 64-bit buffer address, or immediate data */ 809 __le64 buffer; 810 __le32 transfer_len; 811 /* This field is interpreted differently based on the type of TRB */ 812 __le32 flags; 813 }; 814 815 /* Transfer event flags bitfield, also for select command completion events */ 816 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 817 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 818 819 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 820 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 821 822 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 823 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 824 825 /* Transfer event TRB length bit mask */ 826 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 827 828 /* Completion Code - only applicable for some types of TRBs */ 829 #define COMP_CODE_MASK (0xff << 24) 830 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 831 #define COMP_INVALID 0 832 #define COMP_SUCCESS 1 833 #define COMP_DATA_BUFFER_ERROR 2 834 #define COMP_BABBLE_DETECTED_ERROR 3 835 #define COMP_USB_TRANSACTION_ERROR 4 836 #define COMP_TRB_ERROR 5 837 #define COMP_STALL_ERROR 6 838 #define COMP_RESOURCE_ERROR 7 839 #define COMP_BANDWIDTH_ERROR 8 840 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 841 #define COMP_INVALID_STREAM_TYPE_ERROR 10 842 #define COMP_SLOT_NOT_ENABLED_ERROR 11 843 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 844 #define COMP_SHORT_PACKET 13 845 #define COMP_RING_UNDERRUN 14 846 #define COMP_RING_OVERRUN 15 847 #define COMP_VF_EVENT_RING_FULL_ERROR 16 848 #define COMP_PARAMETER_ERROR 17 849 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 850 #define COMP_CONTEXT_STATE_ERROR 19 851 #define COMP_NO_PING_RESPONSE_ERROR 20 852 #define COMP_EVENT_RING_FULL_ERROR 21 853 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 854 #define COMP_MISSED_SERVICE_ERROR 23 855 #define COMP_COMMAND_RING_STOPPED 24 856 #define COMP_COMMAND_ABORTED 25 857 #define COMP_STOPPED 26 858 #define COMP_STOPPED_LENGTH_INVALID 27 859 #define COMP_STOPPED_SHORT_PACKET 28 860 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 861 #define COMP_ISOCH_BUFFER_OVERRUN 31 862 #define COMP_EVENT_LOST_ERROR 32 863 #define COMP_UNDEFINED_ERROR 33 864 #define COMP_INVALID_STREAM_ID_ERROR 34 865 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 866 #define COMP_SPLIT_TRANSACTION_ERROR 36 867 868 static inline const char *xhci_trb_comp_code_string(u8 status) 869 { 870 switch (status) { 871 case COMP_INVALID: 872 return "Invalid"; 873 case COMP_SUCCESS: 874 return "Success"; 875 case COMP_DATA_BUFFER_ERROR: 876 return "Data Buffer Error"; 877 case COMP_BABBLE_DETECTED_ERROR: 878 return "Babble Detected"; 879 case COMP_USB_TRANSACTION_ERROR: 880 return "USB Transaction Error"; 881 case COMP_TRB_ERROR: 882 return "TRB Error"; 883 case COMP_STALL_ERROR: 884 return "Stall Error"; 885 case COMP_RESOURCE_ERROR: 886 return "Resource Error"; 887 case COMP_BANDWIDTH_ERROR: 888 return "Bandwidth Error"; 889 case COMP_NO_SLOTS_AVAILABLE_ERROR: 890 return "No Slots Available Error"; 891 case COMP_INVALID_STREAM_TYPE_ERROR: 892 return "Invalid Stream Type Error"; 893 case COMP_SLOT_NOT_ENABLED_ERROR: 894 return "Slot Not Enabled Error"; 895 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 896 return "Endpoint Not Enabled Error"; 897 case COMP_SHORT_PACKET: 898 return "Short Packet"; 899 case COMP_RING_UNDERRUN: 900 return "Ring Underrun"; 901 case COMP_RING_OVERRUN: 902 return "Ring Overrun"; 903 case COMP_VF_EVENT_RING_FULL_ERROR: 904 return "VF Event Ring Full Error"; 905 case COMP_PARAMETER_ERROR: 906 return "Parameter Error"; 907 case COMP_BANDWIDTH_OVERRUN_ERROR: 908 return "Bandwidth Overrun Error"; 909 case COMP_CONTEXT_STATE_ERROR: 910 return "Context State Error"; 911 case COMP_NO_PING_RESPONSE_ERROR: 912 return "No Ping Response Error"; 913 case COMP_EVENT_RING_FULL_ERROR: 914 return "Event Ring Full Error"; 915 case COMP_INCOMPATIBLE_DEVICE_ERROR: 916 return "Incompatible Device Error"; 917 case COMP_MISSED_SERVICE_ERROR: 918 return "Missed Service Error"; 919 case COMP_COMMAND_RING_STOPPED: 920 return "Command Ring Stopped"; 921 case COMP_COMMAND_ABORTED: 922 return "Command Aborted"; 923 case COMP_STOPPED: 924 return "Stopped"; 925 case COMP_STOPPED_LENGTH_INVALID: 926 return "Stopped - Length Invalid"; 927 case COMP_STOPPED_SHORT_PACKET: 928 return "Stopped - Short Packet"; 929 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 930 return "Max Exit Latency Too Large Error"; 931 case COMP_ISOCH_BUFFER_OVERRUN: 932 return "Isoch Buffer Overrun"; 933 case COMP_EVENT_LOST_ERROR: 934 return "Event Lost Error"; 935 case COMP_UNDEFINED_ERROR: 936 return "Undefined Error"; 937 case COMP_INVALID_STREAM_ID_ERROR: 938 return "Invalid Stream ID Error"; 939 case COMP_SECONDARY_BANDWIDTH_ERROR: 940 return "Secondary Bandwidth Error"; 941 case COMP_SPLIT_TRANSACTION_ERROR: 942 return "Split Transaction Error"; 943 default: 944 return "Unknown!!"; 945 } 946 } 947 948 struct xhci_link_trb { 949 /* 64-bit segment pointer*/ 950 __le64 segment_ptr; 951 __le32 intr_target; 952 __le32 control; 953 }; 954 955 /* control bitfields */ 956 #define LINK_TOGGLE (0x1<<1) 957 958 /* Command completion event TRB */ 959 struct xhci_event_cmd { 960 /* Pointer to command TRB, or the value passed by the event data trb */ 961 __le64 cmd_trb; 962 __le32 status; 963 __le32 flags; 964 }; 965 966 /* status bitmasks */ 967 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 968 969 /* Address device - disable SetAddress */ 970 #define TRB_BSR (1<<9) 971 972 /* Configure Endpoint - Deconfigure */ 973 #define TRB_DC (1<<9) 974 975 /* Stop Ring - Transfer State Preserve */ 976 #define TRB_TSP (1<<9) 977 978 enum xhci_ep_reset_type { 979 EP_HARD_RESET, 980 EP_SOFT_RESET, 981 }; 982 983 /* Force Event */ 984 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 985 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 986 987 /* Set Latency Tolerance Value */ 988 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 989 990 /* Get Port Bandwidth */ 991 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 992 993 /* Force Header */ 994 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 995 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 996 997 enum xhci_setup_dev { 998 SETUP_CONTEXT_ONLY, 999 SETUP_CONTEXT_ADDRESS, 1000 }; 1001 1002 /* bits 16:23 are the virtual function ID */ 1003 /* bits 24:31 are the slot ID */ 1004 1005 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1006 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1007 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1008 #define LAST_EP_INDEX 30 1009 1010 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1011 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1012 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1013 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1014 1015 /* Link TRB specific fields */ 1016 #define TRB_TC (1<<1) 1017 1018 /* Port Status Change Event TRB fields */ 1019 /* Port ID - bits 31:24 */ 1020 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1021 1022 #define EVENT_DATA (1 << 2) 1023 1024 /* Normal TRB fields */ 1025 /* transfer_len bitmasks - bits 0:16 */ 1026 #define TRB_LEN(p) ((p) & 0x1ffff) 1027 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1028 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1029 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1030 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1031 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1032 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1033 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1034 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1035 1036 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1037 #define TRB_CYCLE (1<<0) 1038 /* 1039 * Force next event data TRB to be evaluated before task switch. 1040 * Used to pass OS data back after a TD completes. 1041 */ 1042 #define TRB_ENT (1<<1) 1043 /* Interrupt on short packet */ 1044 #define TRB_ISP (1<<2) 1045 /* Set PCIe no snoop attribute */ 1046 #define TRB_NO_SNOOP (1<<3) 1047 /* Chain multiple TRBs into a TD */ 1048 #define TRB_CHAIN (1<<4) 1049 /* Interrupt on completion */ 1050 #define TRB_IOC (1<<5) 1051 /* The buffer pointer contains immediate data */ 1052 #define TRB_IDT (1<<6) 1053 /* TDs smaller than this might use IDT */ 1054 #define TRB_IDT_MAX_SIZE 8 1055 1056 /* Block Event Interrupt */ 1057 #define TRB_BEI (1<<9) 1058 1059 /* Control transfer TRB specific fields */ 1060 #define TRB_DIR_IN (1<<16) 1061 #define TRB_TX_TYPE(p) ((p) << 16) 1062 #define TRB_DATA_OUT 2 1063 #define TRB_DATA_IN 3 1064 1065 /* Isochronous TRB specific fields */ 1066 #define TRB_SIA (1<<31) 1067 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1068 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1069 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1070 #define TRB_TBC(p) (((p) & 0x3) << 7) 1071 #define GET_TBC(p) (((p) >> 7) & 0x3) 1072 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1073 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1074 1075 /* TRB cache size for xHC with TRB cache */ 1076 #define TRB_CACHE_SIZE_HS 8 1077 #define TRB_CACHE_SIZE_SS 16 1078 1079 struct xhci_generic_trb { 1080 __le32 field[4]; 1081 }; 1082 1083 union xhci_trb { 1084 struct xhci_link_trb link; 1085 struct xhci_transfer_event trans_event; 1086 struct xhci_event_cmd event_cmd; 1087 struct xhci_generic_trb generic; 1088 }; 1089 1090 /* TRB bit mask */ 1091 #define TRB_TYPE_BITMASK (0xfc00) 1092 #define TRB_TYPE(p) ((p) << 10) 1093 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1094 /* TRB type IDs */ 1095 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1096 #define TRB_NORMAL 1 1097 /* setup stage for control transfers */ 1098 #define TRB_SETUP 2 1099 /* data stage for control transfers */ 1100 #define TRB_DATA 3 1101 /* status stage for control transfers */ 1102 #define TRB_STATUS 4 1103 /* isoc transfers */ 1104 #define TRB_ISOC 5 1105 /* TRB for linking ring segments */ 1106 #define TRB_LINK 6 1107 #define TRB_EVENT_DATA 7 1108 /* Transfer Ring No-op (not for the command ring) */ 1109 #define TRB_TR_NOOP 8 1110 /* Command TRBs */ 1111 /* Enable Slot Command */ 1112 #define TRB_ENABLE_SLOT 9 1113 /* Disable Slot Command */ 1114 #define TRB_DISABLE_SLOT 10 1115 /* Address Device Command */ 1116 #define TRB_ADDR_DEV 11 1117 /* Configure Endpoint Command */ 1118 #define TRB_CONFIG_EP 12 1119 /* Evaluate Context Command */ 1120 #define TRB_EVAL_CONTEXT 13 1121 /* Reset Endpoint Command */ 1122 #define TRB_RESET_EP 14 1123 /* Stop Transfer Ring Command */ 1124 #define TRB_STOP_RING 15 1125 /* Set Transfer Ring Dequeue Pointer Command */ 1126 #define TRB_SET_DEQ 16 1127 /* Reset Device Command */ 1128 #define TRB_RESET_DEV 17 1129 /* Force Event Command (opt) */ 1130 #define TRB_FORCE_EVENT 18 1131 /* Negotiate Bandwidth Command (opt) */ 1132 #define TRB_NEG_BANDWIDTH 19 1133 /* Set Latency Tolerance Value Command (opt) */ 1134 #define TRB_SET_LT 20 1135 /* Get port bandwidth Command */ 1136 #define TRB_GET_BW 21 1137 /* Force Header Command - generate a transaction or link management packet */ 1138 #define TRB_FORCE_HEADER 22 1139 /* No-op Command - not for transfer rings */ 1140 #define TRB_CMD_NOOP 23 1141 /* TRB IDs 24-31 reserved */ 1142 /* Event TRBS */ 1143 /* Transfer Event */ 1144 #define TRB_TRANSFER 32 1145 /* Command Completion Event */ 1146 #define TRB_COMPLETION 33 1147 /* Port Status Change Event */ 1148 #define TRB_PORT_STATUS 34 1149 /* Bandwidth Request Event (opt) */ 1150 #define TRB_BANDWIDTH_EVENT 35 1151 /* Doorbell Event (opt) */ 1152 #define TRB_DOORBELL 36 1153 /* Host Controller Event */ 1154 #define TRB_HC_EVENT 37 1155 /* Device Notification Event - device sent function wake notification */ 1156 #define TRB_DEV_NOTE 38 1157 /* MFINDEX Wrap Event - microframe counter wrapped */ 1158 #define TRB_MFINDEX_WRAP 39 1159 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1160 #define TRB_VENDOR_DEFINED_LOW 48 1161 /* Nec vendor-specific command completion event. */ 1162 #define TRB_NEC_CMD_COMP 48 1163 /* Get NEC firmware revision. */ 1164 #define TRB_NEC_GET_FW 49 1165 1166 static inline const char *xhci_trb_type_string(u8 type) 1167 { 1168 switch (type) { 1169 case TRB_NORMAL: 1170 return "Normal"; 1171 case TRB_SETUP: 1172 return "Setup Stage"; 1173 case TRB_DATA: 1174 return "Data Stage"; 1175 case TRB_STATUS: 1176 return "Status Stage"; 1177 case TRB_ISOC: 1178 return "Isoch"; 1179 case TRB_LINK: 1180 return "Link"; 1181 case TRB_EVENT_DATA: 1182 return "Event Data"; 1183 case TRB_TR_NOOP: 1184 return "No-Op"; 1185 case TRB_ENABLE_SLOT: 1186 return "Enable Slot Command"; 1187 case TRB_DISABLE_SLOT: 1188 return "Disable Slot Command"; 1189 case TRB_ADDR_DEV: 1190 return "Address Device Command"; 1191 case TRB_CONFIG_EP: 1192 return "Configure Endpoint Command"; 1193 case TRB_EVAL_CONTEXT: 1194 return "Evaluate Context Command"; 1195 case TRB_RESET_EP: 1196 return "Reset Endpoint Command"; 1197 case TRB_STOP_RING: 1198 return "Stop Ring Command"; 1199 case TRB_SET_DEQ: 1200 return "Set TR Dequeue Pointer Command"; 1201 case TRB_RESET_DEV: 1202 return "Reset Device Command"; 1203 case TRB_FORCE_EVENT: 1204 return "Force Event Command"; 1205 case TRB_NEG_BANDWIDTH: 1206 return "Negotiate Bandwidth Command"; 1207 case TRB_SET_LT: 1208 return "Set Latency Tolerance Value Command"; 1209 case TRB_GET_BW: 1210 return "Get Port Bandwidth Command"; 1211 case TRB_FORCE_HEADER: 1212 return "Force Header Command"; 1213 case TRB_CMD_NOOP: 1214 return "No-Op Command"; 1215 case TRB_TRANSFER: 1216 return "Transfer Event"; 1217 case TRB_COMPLETION: 1218 return "Command Completion Event"; 1219 case TRB_PORT_STATUS: 1220 return "Port Status Change Event"; 1221 case TRB_BANDWIDTH_EVENT: 1222 return "Bandwidth Request Event"; 1223 case TRB_DOORBELL: 1224 return "Doorbell Event"; 1225 case TRB_HC_EVENT: 1226 return "Host Controller Event"; 1227 case TRB_DEV_NOTE: 1228 return "Device Notification Event"; 1229 case TRB_MFINDEX_WRAP: 1230 return "MFINDEX Wrap Event"; 1231 case TRB_NEC_CMD_COMP: 1232 return "NEC Command Completion Event"; 1233 case TRB_NEC_GET_FW: 1234 return "NET Get Firmware Revision Command"; 1235 default: 1236 return "UNKNOWN"; 1237 } 1238 } 1239 1240 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1241 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1242 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1243 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1244 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1245 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1246 1247 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1248 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1249 1250 /* 1251 * TRBS_PER_SEGMENT must be a multiple of 4, 1252 * since the command ring is 64-byte aligned. 1253 * It must also be greater than 16. 1254 */ 1255 #define TRBS_PER_SEGMENT 256 1256 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1257 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1258 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1259 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1260 /* TRB buffer pointers can't cross 64KB boundaries */ 1261 #define TRB_MAX_BUFF_SHIFT 16 1262 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1263 /* How much data is left before the 64KB boundary? */ 1264 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1265 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1266 #define MAX_SOFT_RETRY 3 1267 /* 1268 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1269 * XHCI_AVOID_BEI quirk is in use. 1270 */ 1271 #define AVOID_BEI_INTERVAL_MIN 8 1272 #define AVOID_BEI_INTERVAL_MAX 32 1273 1274 #define xhci_for_each_ring_seg(head, seg) \ 1275 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1276 1277 struct xhci_segment { 1278 union xhci_trb *trbs; 1279 /* private to HCD */ 1280 struct xhci_segment *next; 1281 unsigned int num; 1282 dma_addr_t dma; 1283 /* Max packet sized bounce buffer for td-fragmant alignment */ 1284 dma_addr_t bounce_dma; 1285 void *bounce_buf; 1286 unsigned int bounce_offs; 1287 unsigned int bounce_len; 1288 }; 1289 1290 enum xhci_cancelled_td_status { 1291 TD_DIRTY = 0, 1292 TD_HALTED, 1293 TD_CLEARING_CACHE, 1294 TD_CLEARING_CACHE_DEFERRED, 1295 TD_CLEARED, 1296 }; 1297 1298 struct xhci_td { 1299 struct list_head td_list; 1300 struct list_head cancelled_td_list; 1301 int status; 1302 enum xhci_cancelled_td_status cancel_status; 1303 struct urb *urb; 1304 struct xhci_segment *start_seg; 1305 union xhci_trb *start_trb; 1306 struct xhci_segment *end_seg; 1307 union xhci_trb *end_trb; 1308 struct xhci_segment *bounce_seg; 1309 /* actual_length of the URB has already been set */ 1310 bool urb_length_set; 1311 bool error_mid_td; 1312 }; 1313 1314 /* 1315 * xHCI command default timeout value in milliseconds. 1316 * USB 3.2 spec, section 9.2.6.1 1317 */ 1318 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1319 1320 /* command descriptor */ 1321 struct xhci_cd { 1322 struct xhci_command *command; 1323 union xhci_trb *cmd_trb; 1324 }; 1325 1326 enum xhci_ring_type { 1327 TYPE_CTRL = 0, 1328 TYPE_ISOC, 1329 TYPE_BULK, 1330 TYPE_INTR, 1331 TYPE_STREAM, 1332 TYPE_COMMAND, 1333 TYPE_EVENT, 1334 }; 1335 1336 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1337 { 1338 switch (type) { 1339 case TYPE_CTRL: 1340 return "CTRL"; 1341 case TYPE_ISOC: 1342 return "ISOC"; 1343 case TYPE_BULK: 1344 return "BULK"; 1345 case TYPE_INTR: 1346 return "INTR"; 1347 case TYPE_STREAM: 1348 return "STREAM"; 1349 case TYPE_COMMAND: 1350 return "CMD"; 1351 case TYPE_EVENT: 1352 return "EVENT"; 1353 } 1354 1355 return "UNKNOWN"; 1356 } 1357 1358 struct xhci_ring { 1359 struct xhci_segment *first_seg; 1360 struct xhci_segment *last_seg; 1361 union xhci_trb *enqueue; 1362 struct xhci_segment *enq_seg; 1363 union xhci_trb *dequeue; 1364 struct xhci_segment *deq_seg; 1365 struct list_head td_list; 1366 /* 1367 * Write the cycle state into the TRB cycle field to give ownership of 1368 * the TRB to the host controller (if we are the producer), or to check 1369 * if we own the TRB (if we are the consumer). See section 4.9.1. 1370 */ 1371 u32 cycle_state; 1372 unsigned int stream_id; 1373 unsigned int num_segs; 1374 unsigned int num_trbs_free; /* used only by xhci DbC */ 1375 unsigned int bounce_buf_len; 1376 enum xhci_ring_type type; 1377 u32 old_trb_comp_code; 1378 struct radix_tree_root *trb_address_map; 1379 }; 1380 1381 struct xhci_erst_entry { 1382 /* 64-bit event ring segment address */ 1383 __le64 seg_addr; 1384 __le32 seg_size; 1385 /* Set to zero */ 1386 __le32 rsvd; 1387 }; 1388 1389 struct xhci_erst { 1390 struct xhci_erst_entry *entries; 1391 unsigned int num_entries; 1392 /* xhci->event_ring keeps track of segment dma addresses */ 1393 dma_addr_t erst_dma_addr; 1394 }; 1395 1396 struct xhci_scratchpad { 1397 u64 *sp_array; 1398 dma_addr_t sp_dma; 1399 void **sp_buffers; 1400 }; 1401 1402 struct urb_priv { 1403 int num_tds; 1404 int num_tds_done; 1405 struct xhci_td td[] __counted_by(num_tds); 1406 }; 1407 1408 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1409 #define ERST_DEFAULT_SEGS 2 1410 /* Poll every 60 seconds */ 1411 #define POLL_TIMEOUT 60 1412 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1413 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1414 /* XXX: Make these module parameters */ 1415 1416 struct s3_save { 1417 u32 command; 1418 u32 dev_nt; 1419 u64 dcbaa_ptr; 1420 u32 config_reg; 1421 }; 1422 1423 /* Use for lpm */ 1424 struct dev_info { 1425 u32 dev_id; 1426 struct list_head list; 1427 }; 1428 1429 struct xhci_bus_state { 1430 unsigned long bus_suspended; 1431 unsigned long next_statechange; 1432 1433 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1434 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1435 u32 port_c_suspend; 1436 u32 suspended_ports; 1437 u32 port_remote_wakeup; 1438 /* which ports have started to resume */ 1439 unsigned long resuming_ports; 1440 }; 1441 1442 struct xhci_interrupter { 1443 struct xhci_ring *event_ring; 1444 struct xhci_erst erst; 1445 struct xhci_intr_reg __iomem *ir_set; 1446 unsigned int intr_num; 1447 bool ip_autoclear; 1448 u32 isoc_bei_interval; 1449 /* For interrupter registers save and restore over suspend/resume */ 1450 u32 s3_irq_pending; 1451 u32 s3_irq_control; 1452 u32 s3_erst_size; 1453 u64 s3_erst_base; 1454 u64 s3_erst_dequeue; 1455 }; 1456 /* 1457 * It can take up to 20 ms to transition from RExit to U0 on the 1458 * Intel Lynx Point LP xHCI host. 1459 */ 1460 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1461 struct xhci_port_cap { 1462 u32 *psi; /* array of protocol speed ID entries */ 1463 u8 psi_count; 1464 u8 psi_uid_count; 1465 u8 maj_rev; 1466 u8 min_rev; 1467 u32 protocol_caps; 1468 }; 1469 1470 struct xhci_port { 1471 __le32 __iomem *addr; 1472 int hw_portnum; 1473 int hcd_portnum; 1474 struct xhci_hub *rhub; 1475 struct xhci_port_cap *port_cap; 1476 unsigned int lpm_incapable:1; 1477 unsigned long resume_timestamp; 1478 bool rexit_active; 1479 /* Slot ID is the index of the device directly connected to the port */ 1480 int slot_id; 1481 struct completion rexit_done; 1482 struct completion u3exit_done; 1483 }; 1484 1485 struct xhci_hub { 1486 struct xhci_port **ports; 1487 unsigned int num_ports; 1488 struct usb_hcd *hcd; 1489 /* keep track of bus suspend info */ 1490 struct xhci_bus_state bus_state; 1491 /* supported prococol extended capabiliy values */ 1492 u8 maj_rev; 1493 u8 min_rev; 1494 }; 1495 1496 /* There is one xhci_hcd structure per controller */ 1497 struct xhci_hcd { 1498 struct usb_hcd *main_hcd; 1499 struct usb_hcd *shared_hcd; 1500 /* glue to PCI and HCD framework */ 1501 struct xhci_cap_regs __iomem *cap_regs; 1502 struct xhci_op_regs __iomem *op_regs; 1503 struct xhci_run_regs __iomem *run_regs; 1504 struct xhci_doorbell_array __iomem *dba; 1505 1506 /* Cached register copies of read-only HC data */ 1507 __u32 hcs_params1; 1508 __u32 hcs_params2; 1509 __u32 hcs_params3; 1510 __u32 hcc_params; 1511 __u32 hcc_params2; 1512 1513 spinlock_t lock; 1514 1515 /* packed release number */ 1516 u16 hci_version; 1517 u16 max_interrupters; 1518 /* imod_interval in ns (I * 250ns) */ 1519 u32 imod_interval; 1520 u32 page_size; 1521 /* MSI-X/MSI vectors */ 1522 int nvecs; 1523 /* optional clocks */ 1524 struct clk *clk; 1525 struct clk *reg_clk; 1526 /* optional reset controller */ 1527 struct reset_control *reset; 1528 /* data structures */ 1529 struct xhci_device_context_array *dcbaa; 1530 struct xhci_interrupter **interrupters; 1531 struct xhci_ring *cmd_ring; 1532 unsigned int cmd_ring_state; 1533 #define CMD_RING_STATE_RUNNING (1 << 0) 1534 #define CMD_RING_STATE_ABORTED (1 << 1) 1535 #define CMD_RING_STATE_STOPPED (1 << 2) 1536 struct list_head cmd_list; 1537 unsigned int cmd_ring_reserved_trbs; 1538 struct delayed_work cmd_timer; 1539 struct completion cmd_ring_stop_completion; 1540 struct xhci_command *current_cmd; 1541 1542 /* Scratchpad */ 1543 struct xhci_scratchpad *scratchpad; 1544 1545 /* slot enabling and address device helpers */ 1546 /* these are not thread safe so use mutex */ 1547 struct mutex mutex; 1548 /* Internal mirror of the HW's dcbaa */ 1549 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1550 /* For keeping track of bandwidth domains per roothub. */ 1551 struct xhci_root_port_bw_info *rh_bw; 1552 1553 /* DMA pools */ 1554 struct dma_pool *device_pool; 1555 struct dma_pool *segment_pool; 1556 struct dma_pool *small_streams_pool; 1557 struct dma_pool *medium_streams_pool; 1558 1559 /* Host controller watchdog timer structures */ 1560 unsigned int xhc_state; 1561 unsigned long run_graceperiod; 1562 struct s3_save s3; 1563 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1564 * 1565 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1566 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1567 * that sees this status (other than the timer that set it) should stop touching 1568 * hardware immediately. Interrupt handlers should return immediately when 1569 * they see this status (any time they drop and re-acquire xhci->lock). 1570 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1571 * putting the TD on the canceled list, etc. 1572 * 1573 * There are no reports of xHCI host controllers that display this issue. 1574 */ 1575 #define XHCI_STATE_DYING (1 << 0) 1576 #define XHCI_STATE_HALTED (1 << 1) 1577 #define XHCI_STATE_REMOVING (1 << 2) 1578 unsigned long long quirks; 1579 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1580 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1581 #define XHCI_NEC_HOST BIT_ULL(2) 1582 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1583 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1584 /* 1585 * Certain Intel host controllers have a limit to the number of endpoint 1586 * contexts they can handle. Ideally, they would signal that they can't handle 1587 * anymore endpoint contexts by returning a Resource Error for the Configure 1588 * Endpoint command, but they don't. Instead they expect software to keep track 1589 * of the number of active endpoints for them, across configure endpoint 1590 * commands, reset device commands, disable slot commands, and address device 1591 * commands. 1592 */ 1593 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1594 #define XHCI_BROKEN_MSI BIT_ULL(6) 1595 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1596 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1597 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1598 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1599 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1600 #define XHCI_INTEL_HOST BIT_ULL(12) 1601 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1602 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1603 #define XHCI_AVOID_BEI BIT_ULL(15) 1604 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1605 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1606 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1607 /* For controllers with a broken beyond repair streams implementation */ 1608 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1609 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1610 #define XHCI_MTK_HOST BIT_ULL(21) 1611 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1612 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1613 #define XHCI_MISSING_CAS BIT_ULL(24) 1614 /* For controller with a broken Port Disable implementation */ 1615 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1616 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1617 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1618 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1619 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1620 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1621 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1622 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1623 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1624 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1625 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1626 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1627 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1628 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1629 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1630 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1631 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1632 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1633 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1634 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1635 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1636 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1637 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1638 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1639 #define XHCI_ETRON_HOST BIT_ULL(49) 1640 1641 unsigned int num_active_eps; 1642 unsigned int limit_active_eps; 1643 struct xhci_port *hw_ports; 1644 struct xhci_hub usb2_rhub; 1645 struct xhci_hub usb3_rhub; 1646 /* support xHCI 1.0 spec USB2 hardware LPM */ 1647 unsigned hw_lpm_support:1; 1648 /* Broken Suspend flag for SNPS Suspend resume issue */ 1649 unsigned broken_suspend:1; 1650 /* Indicates that omitting hcd is supported if root hub has no ports */ 1651 unsigned allow_single_roothub:1; 1652 /* cached extended protocol port capabilities */ 1653 struct xhci_port_cap *port_caps; 1654 unsigned int num_port_caps; 1655 /* Compliance Mode Recovery Data */ 1656 struct timer_list comp_mode_recovery_timer; 1657 u32 port_status_u0; 1658 u16 test_mode; 1659 /* Compliance Mode Timer Triggered every 2 seconds */ 1660 #define COMP_MODE_RCVRY_MSECS 2000 1661 1662 struct dentry *debugfs_root; 1663 struct dentry *debugfs_slots; 1664 struct list_head regset_list; 1665 1666 void *dbc; 1667 /* platform-specific data -- must come last */ 1668 unsigned long priv[] __aligned(sizeof(s64)); 1669 }; 1670 1671 /* Platform specific overrides to generic XHCI hc_driver ops */ 1672 struct xhci_driver_overrides { 1673 size_t extra_priv_size; 1674 int (*reset)(struct usb_hcd *hcd); 1675 int (*start)(struct usb_hcd *hcd); 1676 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1677 struct usb_host_endpoint *ep); 1678 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1679 struct usb_host_endpoint *ep); 1680 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1681 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1682 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1683 struct usb_tt *tt, gfp_t mem_flags); 1684 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1685 u16 wIndex, char *buf, u16 wLength); 1686 }; 1687 1688 #define XHCI_CFC_DELAY 10 1689 1690 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1691 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1692 { 1693 struct usb_hcd *primary_hcd; 1694 1695 if (usb_hcd_is_primary_hcd(hcd)) 1696 primary_hcd = hcd; 1697 else 1698 primary_hcd = hcd->primary_hcd; 1699 1700 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1701 } 1702 1703 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1704 { 1705 return xhci->main_hcd; 1706 } 1707 1708 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1709 { 1710 if (xhci->shared_hcd) 1711 return xhci->shared_hcd; 1712 1713 if (!xhci->usb2_rhub.num_ports) 1714 return xhci->main_hcd; 1715 1716 return NULL; 1717 } 1718 1719 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1720 { 1721 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1722 1723 return hcd == xhci_get_usb3_hcd(xhci); 1724 } 1725 1726 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1727 { 1728 return xhci->allow_single_roothub && 1729 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1730 } 1731 1732 #define xhci_dbg(xhci, fmt, args...) \ 1733 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1734 #define xhci_err(xhci, fmt, args...) \ 1735 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1736 #define xhci_warn(xhci, fmt, args...) \ 1737 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1738 #define xhci_info(xhci, fmt, args...) \ 1739 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1740 1741 /* 1742 * Registers should always be accessed with double word or quad word accesses. 1743 * 1744 * Some xHCI implementations may support 64-bit address pointers. Registers 1745 * with 64-bit address pointers should be written to with dword accesses by 1746 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1747 * xHCI implementations that do not support 64-bit address pointers will ignore 1748 * the high dword, and write order is irrelevant. 1749 */ 1750 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1751 __le64 __iomem *regs) 1752 { 1753 return lo_hi_readq(regs); 1754 } 1755 static inline void xhci_write_64(struct xhci_hcd *xhci, 1756 const u64 val, __le64 __iomem *regs) 1757 { 1758 lo_hi_writeq(val, regs); 1759 } 1760 1761 1762 /* 1763 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1764 * Other chapters and later specs say that it should only be set if the link is inside a TD 1765 * which continues from the end of one segment to the next segment. 1766 * 1767 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1768 * 1769 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1770 * "resynchronizing the pipe" after a Missed Service Error. 1771 */ 1772 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1773 { 1774 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1775 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1776 } 1777 1778 /* xHCI debugging */ 1779 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1780 struct xhci_container_ctx *ctx); 1781 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1782 const char *fmt, ...); 1783 1784 /* xHCI memory management */ 1785 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1786 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1787 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1788 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1789 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1790 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1791 struct usb_device *udev); 1792 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1793 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1794 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1795 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1796 struct xhci_virt_device *virt_dev, 1797 int old_active_eps); 1798 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1799 void xhci_update_bw_info(struct xhci_hcd *xhci, 1800 struct xhci_container_ctx *in_ctx, 1801 struct xhci_input_control_ctx *ctrl_ctx, 1802 struct xhci_virt_device *virt_dev); 1803 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1804 struct xhci_container_ctx *in_ctx, 1805 struct xhci_container_ctx *out_ctx, 1806 unsigned int ep_index); 1807 void xhci_slot_copy(struct xhci_hcd *xhci, 1808 struct xhci_container_ctx *in_ctx, 1809 struct xhci_container_ctx *out_ctx); 1810 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1811 struct usb_device *udev, struct usb_host_endpoint *ep, 1812 gfp_t mem_flags); 1813 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1814 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1815 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1816 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1817 unsigned int num_trbs, gfp_t flags); 1818 void xhci_initialize_ring_info(struct xhci_ring *ring); 1819 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1820 struct xhci_virt_device *virt_dev, 1821 unsigned int ep_index); 1822 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1823 unsigned int num_stream_ctxs, 1824 unsigned int num_streams, 1825 unsigned int max_packet, gfp_t flags); 1826 void xhci_free_stream_info(struct xhci_hcd *xhci, 1827 struct xhci_stream_info *stream_info); 1828 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1829 struct xhci_ep_ctx *ep_ctx, 1830 struct xhci_stream_info *stream_info); 1831 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1832 struct xhci_virt_ep *ep); 1833 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1834 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1835 struct xhci_ring *xhci_dma_to_transfer_ring( 1836 struct xhci_virt_ep *ep, 1837 u64 address); 1838 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1839 bool allocate_completion, gfp_t mem_flags); 1840 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1841 bool allocate_completion, gfp_t mem_flags); 1842 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1843 void xhci_free_command(struct xhci_hcd *xhci, 1844 struct xhci_command *command); 1845 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1846 int type, gfp_t flags); 1847 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1848 struct xhci_container_ctx *ctx); 1849 struct xhci_interrupter * 1850 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1851 u32 imod_interval); 1852 void xhci_remove_secondary_interrupter(struct usb_hcd 1853 *hcd, struct xhci_interrupter *ir); 1854 1855 /* xHCI host controller glue */ 1856 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1857 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1858 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, 1859 u32 mask, u32 done, int usec, unsigned int exit_state); 1860 void xhci_quiesce(struct xhci_hcd *xhci); 1861 int xhci_halt(struct xhci_hcd *xhci); 1862 int xhci_start(struct xhci_hcd *xhci); 1863 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1864 int xhci_run(struct usb_hcd *hcd); 1865 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1866 void xhci_shutdown(struct usb_hcd *hcd); 1867 void xhci_stop(struct usb_hcd *hcd); 1868 void xhci_init_driver(struct hc_driver *drv, 1869 const struct xhci_driver_overrides *over); 1870 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1871 struct usb_host_endpoint *ep); 1872 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1873 struct usb_host_endpoint *ep); 1874 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1875 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1876 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1877 struct usb_tt *tt, gfp_t mem_flags); 1878 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1879 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1880 1881 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1882 int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1883 1884 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1885 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1886 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1887 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1888 struct xhci_virt_device *virt_dev, 1889 struct usb_device *hdev, 1890 struct usb_tt *tt, gfp_t mem_flags); 1891 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1892 u32 imod_interval); 1893 int xhci_enable_interrupter(struct xhci_interrupter *ir); 1894 int xhci_disable_interrupter(struct xhci_interrupter *ir); 1895 1896 /* xHCI ring, segment, TRB, and TD functions */ 1897 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1898 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1899 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1900 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1901 u32 trb_type, u32 slot_id); 1902 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1903 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1904 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1905 u32 field1, u32 field2, u32 field3, u32 field4); 1906 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1907 int slot_id, unsigned int ep_index, int suspend); 1908 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1909 int slot_id, unsigned int ep_index); 1910 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1911 int slot_id, unsigned int ep_index); 1912 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1913 int slot_id, unsigned int ep_index); 1914 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1915 struct urb *urb, int slot_id, unsigned int ep_index); 1916 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1917 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1918 bool command_must_succeed); 1919 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1920 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1921 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1922 int slot_id, unsigned int ep_index, 1923 enum xhci_ep_reset_type reset_type); 1924 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1925 u32 slot_id); 1926 void xhci_handle_command_timeout(struct work_struct *work); 1927 1928 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1929 unsigned int ep_index, unsigned int stream_id); 1930 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1931 unsigned int slot_id, 1932 unsigned int ep_index); 1933 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1934 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1935 unsigned int count_trbs(u64 addr, u64 len); 1936 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1937 int suspend, gfp_t gfp_flags); 1938 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1939 1940 /* xHCI roothub code */ 1941 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1942 u32 link_state); 1943 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1944 u32 port_bit); 1945 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1946 char *buf, u16 wLength); 1947 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1948 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1949 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1950 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1951 struct xhci_port *port); 1952 void xhci_hc_died(struct xhci_hcd *xhci); 1953 1954 #ifdef CONFIG_PM 1955 int xhci_bus_suspend(struct usb_hcd *hcd); 1956 int xhci_bus_resume(struct usb_hcd *hcd); 1957 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1958 #else 1959 #define xhci_bus_suspend NULL 1960 #define xhci_bus_resume NULL 1961 #define xhci_get_resuming_ports NULL 1962 #endif /* CONFIG_PM */ 1963 1964 u32 xhci_port_state_to_neutral(u32 state); 1965 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1966 1967 /* xHCI contexts */ 1968 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1969 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1970 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1971 1972 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1973 unsigned int slot_id, unsigned int ep_index, 1974 unsigned int stream_id); 1975 1976 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 1977 struct urb *urb) 1978 { 1979 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 1980 xhci_get_endpoint_index(&urb->ep->desc), 1981 urb->stream_id); 1982 } 1983 1984 /* 1985 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 1986 * them anyways as we where unable to find a device that matches the 1987 * constraints. 1988 */ 1989 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 1990 { 1991 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 1992 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 1993 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 1994 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 1995 !urb->num_sgs) 1996 return true; 1997 1998 return false; 1999 } 2000 2001 static inline char *xhci_slot_state_string(u32 state) 2002 { 2003 switch (state) { 2004 case SLOT_STATE_ENABLED: 2005 return "enabled/disabled"; 2006 case SLOT_STATE_DEFAULT: 2007 return "default"; 2008 case SLOT_STATE_ADDRESSED: 2009 return "addressed"; 2010 case SLOT_STATE_CONFIGURED: 2011 return "configured"; 2012 default: 2013 return "reserved"; 2014 } 2015 } 2016 2017 static inline const char *xhci_decode_trb(char *str, size_t size, 2018 u32 field0, u32 field1, u32 field2, u32 field3) 2019 { 2020 int type = TRB_FIELD_TO_TYPE(field3); 2021 2022 switch (type) { 2023 case TRB_LINK: 2024 snprintf(str, size, 2025 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2026 field1, field0, GET_INTR_TARGET(field2), 2027 xhci_trb_type_string(type), 2028 field3 & TRB_IOC ? 'I' : 'i', 2029 field3 & TRB_CHAIN ? 'C' : 'c', 2030 field3 & TRB_TC ? 'T' : 't', 2031 field3 & TRB_CYCLE ? 'C' : 'c'); 2032 break; 2033 case TRB_TRANSFER: 2034 case TRB_COMPLETION: 2035 case TRB_PORT_STATUS: 2036 case TRB_BANDWIDTH_EVENT: 2037 case TRB_DOORBELL: 2038 case TRB_HC_EVENT: 2039 case TRB_DEV_NOTE: 2040 case TRB_MFINDEX_WRAP: 2041 snprintf(str, size, 2042 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2043 field1, field0, 2044 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2045 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2046 TRB_TO_EP_ID(field3), 2047 xhci_trb_type_string(type), 2048 field3 & EVENT_DATA ? 'E' : 'e', 2049 field3 & TRB_CYCLE ? 'C' : 'c'); 2050 2051 break; 2052 case TRB_SETUP: 2053 snprintf(str, size, 2054 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2055 field0 & 0xff, 2056 (field0 & 0xff00) >> 8, 2057 (field0 & 0xff000000) >> 24, 2058 (field0 & 0xff0000) >> 16, 2059 (field1 & 0xff00) >> 8, 2060 field1 & 0xff, 2061 (field1 & 0xff000000) >> 16 | 2062 (field1 & 0xff0000) >> 16, 2063 TRB_LEN(field2), GET_TD_SIZE(field2), 2064 GET_INTR_TARGET(field2), 2065 xhci_trb_type_string(type), 2066 field3 & TRB_IDT ? 'I' : 'i', 2067 field3 & TRB_IOC ? 'I' : 'i', 2068 field3 & TRB_CYCLE ? 'C' : 'c'); 2069 break; 2070 case TRB_DATA: 2071 snprintf(str, size, 2072 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2073 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2074 GET_INTR_TARGET(field2), 2075 xhci_trb_type_string(type), 2076 field3 & TRB_IDT ? 'I' : 'i', 2077 field3 & TRB_IOC ? 'I' : 'i', 2078 field3 & TRB_CHAIN ? 'C' : 'c', 2079 field3 & TRB_NO_SNOOP ? 'S' : 's', 2080 field3 & TRB_ISP ? 'I' : 'i', 2081 field3 & TRB_ENT ? 'E' : 'e', 2082 field3 & TRB_CYCLE ? 'C' : 'c'); 2083 break; 2084 case TRB_STATUS: 2085 snprintf(str, size, 2086 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2087 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2088 GET_INTR_TARGET(field2), 2089 xhci_trb_type_string(type), 2090 field3 & TRB_IOC ? 'I' : 'i', 2091 field3 & TRB_CHAIN ? 'C' : 'c', 2092 field3 & TRB_ENT ? 'E' : 'e', 2093 field3 & TRB_CYCLE ? 'C' : 'c'); 2094 break; 2095 case TRB_NORMAL: 2096 case TRB_EVENT_DATA: 2097 case TRB_TR_NOOP: 2098 snprintf(str, size, 2099 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2100 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2101 GET_INTR_TARGET(field2), 2102 xhci_trb_type_string(type), 2103 field3 & TRB_BEI ? 'B' : 'b', 2104 field3 & TRB_IDT ? 'I' : 'i', 2105 field3 & TRB_IOC ? 'I' : 'i', 2106 field3 & TRB_CHAIN ? 'C' : 'c', 2107 field3 & TRB_NO_SNOOP ? 'S' : 's', 2108 field3 & TRB_ISP ? 'I' : 'i', 2109 field3 & TRB_ENT ? 'E' : 'e', 2110 field3 & TRB_CYCLE ? 'C' : 'c'); 2111 break; 2112 case TRB_ISOC: 2113 snprintf(str, size, 2114 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2115 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2116 GET_INTR_TARGET(field2), 2117 xhci_trb_type_string(type), 2118 GET_TBC(field3), 2119 GET_TLBPC(field3), 2120 GET_FRAME_ID(field3), 2121 field3 & TRB_SIA ? 'S' : 's', 2122 field3 & TRB_BEI ? 'B' : 'b', 2123 field3 & TRB_IDT ? 'I' : 'i', 2124 field3 & TRB_IOC ? 'I' : 'i', 2125 field3 & TRB_CHAIN ? 'C' : 'c', 2126 field3 & TRB_NO_SNOOP ? 'S' : 's', 2127 field3 & TRB_ISP ? 'I' : 'i', 2128 field3 & TRB_ENT ? 'E' : 'e', 2129 field3 & TRB_CYCLE ? 'C' : 'c'); 2130 break; 2131 case TRB_CMD_NOOP: 2132 case TRB_ENABLE_SLOT: 2133 snprintf(str, size, 2134 "%s: flags %c", 2135 xhci_trb_type_string(type), 2136 field3 & TRB_CYCLE ? 'C' : 'c'); 2137 break; 2138 case TRB_DISABLE_SLOT: 2139 case TRB_NEG_BANDWIDTH: 2140 snprintf(str, size, 2141 "%s: slot %d flags %c", 2142 xhci_trb_type_string(type), 2143 TRB_TO_SLOT_ID(field3), 2144 field3 & TRB_CYCLE ? 'C' : 'c'); 2145 break; 2146 case TRB_ADDR_DEV: 2147 snprintf(str, size, 2148 "%s: ctx %08x%08x slot %d flags %c:%c", 2149 xhci_trb_type_string(type), 2150 field1, field0, 2151 TRB_TO_SLOT_ID(field3), 2152 field3 & TRB_BSR ? 'B' : 'b', 2153 field3 & TRB_CYCLE ? 'C' : 'c'); 2154 break; 2155 case TRB_CONFIG_EP: 2156 snprintf(str, size, 2157 "%s: ctx %08x%08x slot %d flags %c:%c", 2158 xhci_trb_type_string(type), 2159 field1, field0, 2160 TRB_TO_SLOT_ID(field3), 2161 field3 & TRB_DC ? 'D' : 'd', 2162 field3 & TRB_CYCLE ? 'C' : 'c'); 2163 break; 2164 case TRB_EVAL_CONTEXT: 2165 snprintf(str, size, 2166 "%s: ctx %08x%08x slot %d flags %c", 2167 xhci_trb_type_string(type), 2168 field1, field0, 2169 TRB_TO_SLOT_ID(field3), 2170 field3 & TRB_CYCLE ? 'C' : 'c'); 2171 break; 2172 case TRB_RESET_EP: 2173 snprintf(str, size, 2174 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2175 xhci_trb_type_string(type), 2176 field1, field0, 2177 TRB_TO_SLOT_ID(field3), 2178 TRB_TO_EP_ID(field3), 2179 field3 & TRB_TSP ? 'T' : 't', 2180 field3 & TRB_CYCLE ? 'C' : 'c'); 2181 break; 2182 case TRB_STOP_RING: 2183 snprintf(str, size, 2184 "%s: slot %d sp %d ep %d flags %c", 2185 xhci_trb_type_string(type), 2186 TRB_TO_SLOT_ID(field3), 2187 TRB_TO_SUSPEND_PORT(field3), 2188 TRB_TO_EP_ID(field3), 2189 field3 & TRB_CYCLE ? 'C' : 'c'); 2190 break; 2191 case TRB_SET_DEQ: 2192 snprintf(str, size, 2193 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2194 xhci_trb_type_string(type), 2195 field1, field0, 2196 TRB_TO_STREAM_ID(field2), 2197 TRB_TO_SLOT_ID(field3), 2198 TRB_TO_EP_ID(field3), 2199 field3 & TRB_CYCLE ? 'C' : 'c'); 2200 break; 2201 case TRB_RESET_DEV: 2202 snprintf(str, size, 2203 "%s: slot %d flags %c", 2204 xhci_trb_type_string(type), 2205 TRB_TO_SLOT_ID(field3), 2206 field3 & TRB_CYCLE ? 'C' : 'c'); 2207 break; 2208 case TRB_FORCE_EVENT: 2209 snprintf(str, size, 2210 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2211 xhci_trb_type_string(type), 2212 field1, field0, 2213 TRB_TO_VF_INTR_TARGET(field2), 2214 TRB_TO_VF_ID(field3), 2215 field3 & TRB_CYCLE ? 'C' : 'c'); 2216 break; 2217 case TRB_SET_LT: 2218 snprintf(str, size, 2219 "%s: belt %d flags %c", 2220 xhci_trb_type_string(type), 2221 TRB_TO_BELT(field3), 2222 field3 & TRB_CYCLE ? 'C' : 'c'); 2223 break; 2224 case TRB_GET_BW: 2225 snprintf(str, size, 2226 "%s: ctx %08x%08x slot %d speed %d flags %c", 2227 xhci_trb_type_string(type), 2228 field1, field0, 2229 TRB_TO_SLOT_ID(field3), 2230 TRB_TO_DEV_SPEED(field3), 2231 field3 & TRB_CYCLE ? 'C' : 'c'); 2232 break; 2233 case TRB_FORCE_HEADER: 2234 snprintf(str, size, 2235 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2236 xhci_trb_type_string(type), 2237 field2, field1, field0 & 0xffffffe0, 2238 TRB_TO_PACKET_TYPE(field0), 2239 TRB_TO_ROOTHUB_PORT(field3), 2240 field3 & TRB_CYCLE ? 'C' : 'c'); 2241 break; 2242 default: 2243 snprintf(str, size, 2244 "type '%s' -> raw %08x %08x %08x %08x", 2245 xhci_trb_type_string(type), 2246 field0, field1, field2, field3); 2247 } 2248 2249 return str; 2250 } 2251 2252 static inline const char *xhci_decode_ctrl_ctx(char *str, 2253 unsigned long drop, unsigned long add) 2254 { 2255 unsigned int bit; 2256 int ret = 0; 2257 2258 str[0] = '\0'; 2259 2260 if (drop) { 2261 ret = sprintf(str, "Drop:"); 2262 for_each_set_bit(bit, &drop, 32) 2263 ret += sprintf(str + ret, " %d%s", 2264 bit / 2, 2265 bit % 2 ? "in":"out"); 2266 ret += sprintf(str + ret, ", "); 2267 } 2268 2269 if (add) { 2270 ret += sprintf(str + ret, "Add:%s%s", 2271 (add & SLOT_FLAG) ? " slot":"", 2272 (add & EP0_FLAG) ? " ep0":""); 2273 add &= ~(SLOT_FLAG | EP0_FLAG); 2274 for_each_set_bit(bit, &add, 32) 2275 ret += sprintf(str + ret, " %d%s", 2276 bit / 2, 2277 bit % 2 ? "in":"out"); 2278 } 2279 return str; 2280 } 2281 2282 static inline const char *xhci_decode_slot_context(char *str, 2283 u32 info, u32 info2, u32 tt_info, u32 state) 2284 { 2285 u32 speed; 2286 u32 hub; 2287 u32 mtt; 2288 int ret = 0; 2289 2290 speed = info & DEV_SPEED; 2291 hub = info & DEV_HUB; 2292 mtt = info & DEV_MTT; 2293 2294 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2295 info & ROUTE_STRING_MASK, 2296 ({ char *s; 2297 switch (speed) { 2298 case SLOT_SPEED_FS: 2299 s = "full-speed"; 2300 break; 2301 case SLOT_SPEED_LS: 2302 s = "low-speed"; 2303 break; 2304 case SLOT_SPEED_HS: 2305 s = "high-speed"; 2306 break; 2307 case SLOT_SPEED_SS: 2308 s = "super-speed"; 2309 break; 2310 case SLOT_SPEED_SSP: 2311 s = "super-speed plus"; 2312 break; 2313 default: 2314 s = "UNKNOWN speed"; 2315 } s; }), 2316 mtt ? " multi-TT" : "", 2317 hub ? " Hub" : "", 2318 (info & LAST_CTX_MASK) >> 27, 2319 info2 & MAX_EXIT, 2320 DEVINFO_TO_ROOT_HUB_PORT(info2), 2321 DEVINFO_TO_MAX_PORTS(info2)); 2322 2323 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2324 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2325 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2326 state & DEV_ADDR_MASK, 2327 xhci_slot_state_string(GET_SLOT_STATE(state))); 2328 2329 return str; 2330 } 2331 2332 2333 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2334 { 2335 switch (portsc & PORT_PLS_MASK) { 2336 case XDEV_U0: 2337 return "U0"; 2338 case XDEV_U1: 2339 return "U1"; 2340 case XDEV_U2: 2341 return "U2"; 2342 case XDEV_U3: 2343 return "U3"; 2344 case XDEV_DISABLED: 2345 return "Disabled"; 2346 case XDEV_RXDETECT: 2347 return "RxDetect"; 2348 case XDEV_INACTIVE: 2349 return "Inactive"; 2350 case XDEV_POLLING: 2351 return "Polling"; 2352 case XDEV_RECOVERY: 2353 return "Recovery"; 2354 case XDEV_HOT_RESET: 2355 return "Hot Reset"; 2356 case XDEV_COMP_MODE: 2357 return "Compliance mode"; 2358 case XDEV_TEST_MODE: 2359 return "Test mode"; 2360 case XDEV_RESUME: 2361 return "Resume"; 2362 default: 2363 break; 2364 } 2365 return "Unknown"; 2366 } 2367 2368 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2369 { 2370 int ret; 2371 2372 ret = sprintf(str, "0x%08x ", portsc); 2373 2374 if (portsc == ~(u32)0) 2375 return str; 2376 2377 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ", 2378 portsc & PORT_POWER ? "Powered" : "Powered-off", 2379 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2380 portsc & PORT_PE ? "Enabled" : "Disabled", 2381 xhci_portsc_link_state_string(portsc), 2382 DEV_PORT_SPEED(portsc)); 2383 2384 if (portsc & PORT_OC) 2385 ret += sprintf(str + ret, "OverCurrent "); 2386 if (portsc & PORT_RESET) 2387 ret += sprintf(str + ret, "In-Reset "); 2388 2389 ret += sprintf(str + ret, "Change: "); 2390 if (portsc & PORT_CSC) 2391 ret += sprintf(str + ret, "CSC "); 2392 if (portsc & PORT_PEC) 2393 ret += sprintf(str + ret, "PEC "); 2394 if (portsc & PORT_WRC) 2395 ret += sprintf(str + ret, "WRC "); 2396 if (portsc & PORT_OCC) 2397 ret += sprintf(str + ret, "OCC "); 2398 if (portsc & PORT_RC) 2399 ret += sprintf(str + ret, "PRC "); 2400 if (portsc & PORT_PLC) 2401 ret += sprintf(str + ret, "PLC "); 2402 if (portsc & PORT_CEC) 2403 ret += sprintf(str + ret, "CEC "); 2404 if (portsc & PORT_CAS) 2405 ret += sprintf(str + ret, "CAS "); 2406 2407 ret += sprintf(str + ret, "Wake: "); 2408 if (portsc & PORT_WKCONN_E) 2409 ret += sprintf(str + ret, "WCE "); 2410 if (portsc & PORT_WKDISC_E) 2411 ret += sprintf(str + ret, "WDE "); 2412 if (portsc & PORT_WKOC_E) 2413 ret += sprintf(str + ret, "WOE "); 2414 2415 return str; 2416 } 2417 2418 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2419 { 2420 int ret = 0; 2421 2422 ret = sprintf(str, " 0x%08x", usbsts); 2423 2424 if (usbsts == ~(u32)0) 2425 return str; 2426 2427 if (usbsts & STS_HALT) 2428 ret += sprintf(str + ret, " HCHalted"); 2429 if (usbsts & STS_FATAL) 2430 ret += sprintf(str + ret, " HSE"); 2431 if (usbsts & STS_EINT) 2432 ret += sprintf(str + ret, " EINT"); 2433 if (usbsts & STS_PORT) 2434 ret += sprintf(str + ret, " PCD"); 2435 if (usbsts & STS_SAVE) 2436 ret += sprintf(str + ret, " SSS"); 2437 if (usbsts & STS_RESTORE) 2438 ret += sprintf(str + ret, " RSS"); 2439 if (usbsts & STS_SRE) 2440 ret += sprintf(str + ret, " SRE"); 2441 if (usbsts & STS_CNR) 2442 ret += sprintf(str + ret, " CNR"); 2443 if (usbsts & STS_HCE) 2444 ret += sprintf(str + ret, " HCE"); 2445 2446 return str; 2447 } 2448 2449 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2450 { 2451 u8 ep; 2452 u16 stream; 2453 int ret; 2454 2455 ep = (doorbell & 0xff); 2456 stream = doorbell >> 16; 2457 2458 if (slot == 0) { 2459 sprintf(str, "Command Ring %d", doorbell); 2460 return str; 2461 } 2462 ret = sprintf(str, "Slot %d ", slot); 2463 if (ep > 0 && ep < 32) 2464 ret = sprintf(str + ret, "ep%d%s", 2465 ep / 2, 2466 ep % 2 ? "in" : "out"); 2467 else if (ep == 0 || ep < 248) 2468 ret = sprintf(str + ret, "Reserved %d", ep); 2469 else 2470 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2471 if (stream) 2472 ret = sprintf(str + ret, " Stream %d", stream); 2473 2474 return str; 2475 } 2476 2477 static inline const char *xhci_ep_state_string(u8 state) 2478 { 2479 switch (state) { 2480 case EP_STATE_DISABLED: 2481 return "disabled"; 2482 case EP_STATE_RUNNING: 2483 return "running"; 2484 case EP_STATE_HALTED: 2485 return "halted"; 2486 case EP_STATE_STOPPED: 2487 return "stopped"; 2488 case EP_STATE_ERROR: 2489 return "error"; 2490 default: 2491 return "INVALID"; 2492 } 2493 } 2494 2495 static inline const char *xhci_ep_type_string(u8 type) 2496 { 2497 switch (type) { 2498 case ISOC_OUT_EP: 2499 return "Isoc OUT"; 2500 case BULK_OUT_EP: 2501 return "Bulk OUT"; 2502 case INT_OUT_EP: 2503 return "Int OUT"; 2504 case CTRL_EP: 2505 return "Ctrl"; 2506 case ISOC_IN_EP: 2507 return "Isoc IN"; 2508 case BULK_IN_EP: 2509 return "Bulk IN"; 2510 case INT_IN_EP: 2511 return "Int IN"; 2512 default: 2513 return "INVALID"; 2514 } 2515 } 2516 2517 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2518 u32 info2, u64 deq, u32 tx_info) 2519 { 2520 int ret; 2521 2522 u32 esit; 2523 u16 maxp; 2524 u16 avg; 2525 2526 u8 max_pstr; 2527 u8 ep_state; 2528 u8 interval; 2529 u8 ep_type; 2530 u8 burst; 2531 u8 cerr; 2532 u8 mult; 2533 2534 bool lsa; 2535 bool hid; 2536 2537 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2538 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2539 2540 ep_state = info & EP_STATE_MASK; 2541 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2542 interval = CTX_TO_EP_INTERVAL(info); 2543 mult = CTX_TO_EP_MULT(info) + 1; 2544 lsa = !!(info & EP_HAS_LSA); 2545 2546 cerr = (info2 & (3 << 1)) >> 1; 2547 ep_type = CTX_TO_EP_TYPE(info2); 2548 hid = !!(info2 & (1 << 7)); 2549 burst = CTX_TO_MAX_BURST(info2); 2550 maxp = MAX_PACKET_DECODED(info2); 2551 2552 avg = EP_AVG_TRB_LENGTH(tx_info); 2553 2554 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2555 xhci_ep_state_string(ep_state), mult, 2556 max_pstr, lsa ? "LSA " : ""); 2557 2558 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2559 (1 << interval) * 125, esit, cerr); 2560 2561 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2562 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2563 burst, maxp, deq); 2564 2565 ret += sprintf(str + ret, "avg trb len %d", avg); 2566 2567 return str; 2568 } 2569 2570 #endif /* __LINUX_XHCI_HCD_H */ 2571