1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 #include "pci-quirks.h" 34 35 /* xHCI PCI Configuration Registers */ 36 #define XHCI_SBRN_OFFSET (0x60) 37 38 /* Max number of USB devices for any host controller - limit in section 6.1 */ 39 #define MAX_HC_SLOTS 256 40 /* Section 5.3.3 - MaxPorts */ 41 #define MAX_HC_PORTS 127 42 43 /* 44 * xHCI register interface. 45 * This corresponds to the eXtensible Host Controller Interface (xHCI) 46 * Revision 0.95 specification 47 */ 48 49 /** 50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 51 * @hc_capbase: length of the capabilities register and HC version number 52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 55 * @hcc_params: HCCPARAMS - Capability Parameters 56 * @db_off: DBOFF - Doorbell array offset 57 * @run_regs_off: RTSOFF - Runtime register space offset 58 */ 59 struct xhci_cap_regs { 60 __le32 hc_capbase; 61 __le32 hcs_params1; 62 __le32 hcs_params2; 63 __le32 hcs_params3; 64 __le32 hcc_params; 65 __le32 db_off; 66 __le32 run_regs_off; 67 /* Reserved up to (CAPLENGTH - 0x1C) */ 68 }; 69 70 /* hc_capbase bitmasks */ 71 /* bits 7:0 - how long is the Capabilities register */ 72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 73 /* bits 31:16 */ 74 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 75 76 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 77 /* bits 0:7, Max Device Slots */ 78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 79 #define HCS_SLOTS_MASK 0xff 80 /* bits 8:18, Max Interrupters */ 81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 84 85 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 86 /* bits 0:3, frames or uframes that SW needs to queue transactions 87 * ahead of the HW to meet periodic deadlines */ 88 #define HCS_IST(p) (((p) >> 0) & 0xf) 89 /* bits 4:7, max number of Event Ring segments */ 90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 94 95 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 100 101 /* HCCPARAMS - hcc_params - bitmasks */ 102 /* true: HC can use 64-bit address pointers */ 103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 104 /* true: HC can do bandwidth negotiation */ 105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 106 /* true: HC uses 64-byte Device Context structures 107 * FIXME 64-byte context structures aren't supported yet. 108 */ 109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 110 /* true: HC has port power switches */ 111 #define HCC_PPC(p) ((p) & (1 << 3)) 112 /* true: HC has port indicators */ 113 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 114 /* true: HC has Light HC Reset Capability */ 115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 116 /* true: HC supports latency tolerance messaging */ 117 #define HCC_LTC(p) ((p) & (1 << 6)) 118 /* true: no secondary Stream ID Support */ 119 #define HCC_NSS(p) ((p) & (1 << 7)) 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 124 125 /* db_off bitmask - bits 0:1 reserved */ 126 #define DBOFF_MASK (~0x3) 127 128 /* run_regs_off bitmask - bits 0:4 reserved */ 129 #define RTSOFF_MASK (~0x1f) 130 131 132 /* Number of registers per port */ 133 #define NUM_PORT_REGS 4 134 135 /** 136 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 137 * @command: USBCMD - xHC command register 138 * @status: USBSTS - xHC status register 139 * @page_size: This indicates the page size that the host controller 140 * supports. If bit n is set, the HC supports a page size 141 * of 2^(n+12), up to a 128MB page size. 142 * 4K is the minimum page size. 143 * @cmd_ring: CRP - 64-bit Command Ring Pointer 144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 145 * @config_reg: CONFIG - Configure Register 146 * @port_status_base: PORTSCn - base address for Port Status and Control 147 * Each port has a Port Status and Control register, 148 * followed by a Port Power Management Status and Control 149 * register, a Port Link Info register, and a reserved 150 * register. 151 * @port_power_base: PORTPMSCn - base address for 152 * Port Power Management Status and Control 153 * @port_link_base: PORTLIn - base address for Port Link Info (current 154 * Link PM state and control) for USB 2.1 and USB 3.0 155 * devices. 156 */ 157 struct xhci_op_regs { 158 __le32 command; 159 __le32 status; 160 __le32 page_size; 161 __le32 reserved1; 162 __le32 reserved2; 163 __le32 dev_notification; 164 __le64 cmd_ring; 165 /* rsvd: offset 0x20-2F */ 166 __le32 reserved3[4]; 167 __le64 dcbaa_ptr; 168 __le32 config_reg; 169 /* rsvd: offset 0x3C-3FF */ 170 __le32 reserved4[241]; 171 /* port 1 registers, which serve as a base address for other ports */ 172 __le32 port_status_base; 173 __le32 port_power_base; 174 __le32 port_link_base; 175 __le32 reserved5; 176 /* registers for ports 2-255 */ 177 __le32 reserved6[NUM_PORT_REGS*254]; 178 }; 179 180 /* USBCMD - USB command - command bitmasks */ 181 /* start/stop HC execution - do not write unless HC is halted*/ 182 #define CMD_RUN XHCI_CMD_RUN 183 /* Reset HC - resets internal HC state machine and all registers (except 184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 185 * The xHCI driver must reinitialize the xHC after setting this bit. 186 */ 187 #define CMD_RESET (1 << 1) 188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 189 #define CMD_EIE XHCI_CMD_EIE 190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 191 #define CMD_HSEIE XHCI_CMD_HSEIE 192 /* bits 4:6 are reserved (and should be preserved on writes). */ 193 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 194 #define CMD_LRESET (1 << 7) 195 /* host controller save/restore state. */ 196 #define CMD_CSS (1 << 8) 197 #define CMD_CRS (1 << 9) 198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 199 #define CMD_EWE XHCI_CMD_EWE 200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 202 * '0' means the xHC can power it off if all ports are in the disconnect, 203 * disabled, or powered-off state. 204 */ 205 #define CMD_PM_INDEX (1 << 11) 206 /* bits 12:31 are reserved (and should be preserved on writes). */ 207 208 /* IMAN - Interrupt Management Register */ 209 #define IMAN_IP (1 << 1) 210 #define IMAN_IE (1 << 0) 211 212 /* USBSTS - USB status - status bitmasks */ 213 /* HC not running - set to 1 when run/stop bit is cleared. */ 214 #define STS_HALT XHCI_STS_HALT 215 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 216 #define STS_FATAL (1 << 2) 217 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 218 #define STS_EINT (1 << 3) 219 /* port change detect */ 220 #define STS_PORT (1 << 4) 221 /* bits 5:7 reserved and zeroed */ 222 /* save state status - '1' means xHC is saving state */ 223 #define STS_SAVE (1 << 8) 224 /* restore state status - '1' means xHC is restoring state */ 225 #define STS_RESTORE (1 << 9) 226 /* true: save or restore error */ 227 #define STS_SRE (1 << 10) 228 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 229 #define STS_CNR XHCI_STS_CNR 230 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 231 #define STS_HCE (1 << 12) 232 /* bits 13:31 reserved and should be preserved */ 233 234 /* 235 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 236 * Generate a device notification event when the HC sees a transaction with a 237 * notification type that matches a bit set in this bit field. 238 */ 239 #define DEV_NOTE_MASK (0xffff) 240 #define ENABLE_DEV_NOTE(x) (1 << (x)) 241 /* Most of the device notification types should only be used for debug. 242 * SW does need to pay attention to function wake notifications. 243 */ 244 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 245 246 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 247 /* bit 0 is the command ring cycle state */ 248 /* stop ring operation after completion of the currently executing command */ 249 #define CMD_RING_PAUSE (1 << 1) 250 /* stop ring immediately - abort the currently executing command */ 251 #define CMD_RING_ABORT (1 << 2) 252 /* true: command ring is running */ 253 #define CMD_RING_RUNNING (1 << 3) 254 /* bits 4:5 reserved and should be preserved */ 255 /* Command Ring pointer - bit mask for the lower 32 bits. */ 256 #define CMD_RING_RSVD_BITS (0x3f) 257 258 /* CONFIG - Configure Register - config_reg bitmasks */ 259 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 260 #define MAX_DEVS(p) ((p) & 0xff) 261 /* bits 8:31 - reserved and should be preserved */ 262 263 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 264 /* true: device connected */ 265 #define PORT_CONNECT (1 << 0) 266 /* true: port enabled */ 267 #define PORT_PE (1 << 1) 268 /* bit 2 reserved and zeroed */ 269 /* true: port has an over-current condition */ 270 #define PORT_OC (1 << 3) 271 /* true: port reset signaling asserted */ 272 #define PORT_RESET (1 << 4) 273 /* Port Link State - bits 5:8 274 * A read gives the current link PM state of the port, 275 * a write with Link State Write Strobe set sets the link state. 276 */ 277 #define PORT_PLS_MASK (0xf << 5) 278 #define XDEV_U0 (0x0 << 5) 279 #define XDEV_U2 (0x2 << 5) 280 #define XDEV_U3 (0x3 << 5) 281 #define XDEV_RESUME (0xf << 5) 282 /* true: port has power (see HCC_PPC) */ 283 #define PORT_POWER (1 << 9) 284 /* bits 10:13 indicate device speed: 285 * 0 - undefined speed - port hasn't be initialized by a reset yet 286 * 1 - full speed 287 * 2 - low speed 288 * 3 - high speed 289 * 4 - super speed 290 * 5-15 reserved 291 */ 292 #define DEV_SPEED_MASK (0xf << 10) 293 #define XDEV_FS (0x1 << 10) 294 #define XDEV_LS (0x2 << 10) 295 #define XDEV_HS (0x3 << 10) 296 #define XDEV_SS (0x4 << 10) 297 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 298 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 299 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 300 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 301 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 302 /* Bits 20:23 in the Slot Context are the speed for the device */ 303 #define SLOT_SPEED_FS (XDEV_FS << 10) 304 #define SLOT_SPEED_LS (XDEV_LS << 10) 305 #define SLOT_SPEED_HS (XDEV_HS << 10) 306 #define SLOT_SPEED_SS (XDEV_SS << 10) 307 /* Port Indicator Control */ 308 #define PORT_LED_OFF (0 << 14) 309 #define PORT_LED_AMBER (1 << 14) 310 #define PORT_LED_GREEN (2 << 14) 311 #define PORT_LED_MASK (3 << 14) 312 /* Port Link State Write Strobe - set this when changing link state */ 313 #define PORT_LINK_STROBE (1 << 16) 314 /* true: connect status change */ 315 #define PORT_CSC (1 << 17) 316 /* true: port enable change */ 317 #define PORT_PEC (1 << 18) 318 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 319 * into an enabled state, and the device into the default state. A "warm" reset 320 * also resets the link, forcing the device through the link training sequence. 321 * SW can also look at the Port Reset register to see when warm reset is done. 322 */ 323 #define PORT_WRC (1 << 19) 324 /* true: over-current change */ 325 #define PORT_OCC (1 << 20) 326 /* true: reset change - 1 to 0 transition of PORT_RESET */ 327 #define PORT_RC (1 << 21) 328 /* port link status change - set on some port link state transitions: 329 * Transition Reason 330 * ------------------------------------------------------------------------------ 331 * - U3 to Resume Wakeup signaling from a device 332 * - Resume to Recovery to U0 USB 3.0 device resume 333 * - Resume to U0 USB 2.0 device resume 334 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 335 * - U3 to U0 Software resume of USB 2.0 device complete 336 * - U2 to U0 L1 resume of USB 2.1 device complete 337 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 338 * - U0 to disabled L1 entry error with USB 2.1 device 339 * - Any state to inactive Error on USB 3.0 port 340 */ 341 #define PORT_PLC (1 << 22) 342 /* port configure error change - port failed to configure its link partner */ 343 #define PORT_CEC (1 << 23) 344 /* bit 24 reserved */ 345 /* wake on connect (enable) */ 346 #define PORT_WKCONN_E (1 << 25) 347 /* wake on disconnect (enable) */ 348 #define PORT_WKDISC_E (1 << 26) 349 /* wake on over-current (enable) */ 350 #define PORT_WKOC_E (1 << 27) 351 /* bits 28:29 reserved */ 352 /* true: device is removable - for USB 3.0 roothub emulation */ 353 #define PORT_DEV_REMOVE (1 << 30) 354 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 355 #define PORT_WR (1 << 31) 356 357 /* We mark duplicate entries with -1 */ 358 #define DUPLICATE_ENTRY ((u8)(-1)) 359 360 /* Port Power Management Status and Control - port_power_base bitmasks */ 361 /* Inactivity timer value for transitions into U1, in microseconds. 362 * Timeout can be up to 127us. 0xFF means an infinite timeout. 363 */ 364 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 365 #define PORT_U1_TIMEOUT_MASK 0xff 366 /* Inactivity timer value for transitions into U2 */ 367 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 368 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 369 /* Bits 24:31 for port testing */ 370 371 /* USB2 Protocol PORTSPMSC */ 372 #define PORT_L1S_MASK 7 373 #define PORT_L1S_SUCCESS 1 374 #define PORT_RWE (1 << 3) 375 #define PORT_HIRD(p) (((p) & 0xf) << 4) 376 #define PORT_HIRD_MASK (0xf << 4) 377 #define PORT_L1DS(p) (((p) & 0xff) << 8) 378 #define PORT_HLE (1 << 16) 379 380 /** 381 * struct xhci_intr_reg - Interrupt Register Set 382 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 383 * interrupts and check for pending interrupts. 384 * @irq_control: IMOD - Interrupt Moderation Register. 385 * Used to throttle interrupts. 386 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 387 * @erst_base: ERST base address. 388 * @erst_dequeue: Event ring dequeue pointer. 389 * 390 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 391 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 392 * multiple segments of the same size. The HC places events on the ring and 393 * "updates the Cycle bit in the TRBs to indicate to software the current 394 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 395 * updates the dequeue pointer. 396 */ 397 struct xhci_intr_reg { 398 __le32 irq_pending; 399 __le32 irq_control; 400 __le32 erst_size; 401 __le32 rsvd; 402 __le64 erst_base; 403 __le64 erst_dequeue; 404 }; 405 406 /* irq_pending bitmasks */ 407 #define ER_IRQ_PENDING(p) ((p) & 0x1) 408 /* bits 2:31 need to be preserved */ 409 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 410 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 411 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 412 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 413 414 /* irq_control bitmasks */ 415 /* Minimum interval between interrupts (in 250ns intervals). The interval 416 * between interrupts will be longer if there are no events on the event ring. 417 * Default is 4000 (1 ms). 418 */ 419 #define ER_IRQ_INTERVAL_MASK (0xffff) 420 /* Counter used to count down the time to the next interrupt - HW use only */ 421 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 422 423 /* erst_size bitmasks */ 424 /* Preserve bits 16:31 of erst_size */ 425 #define ERST_SIZE_MASK (0xffff << 16) 426 427 /* erst_dequeue bitmasks */ 428 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 429 * where the current dequeue pointer lies. This is an optional HW hint. 430 */ 431 #define ERST_DESI_MASK (0x7) 432 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 433 * a work queue (or delayed service routine)? 434 */ 435 #define ERST_EHB (1 << 3) 436 #define ERST_PTR_MASK (0xf) 437 438 /** 439 * struct xhci_run_regs 440 * @microframe_index: 441 * MFINDEX - current microframe number 442 * 443 * Section 5.5 Host Controller Runtime Registers: 444 * "Software should read and write these registers using only Dword (32 bit) 445 * or larger accesses" 446 */ 447 struct xhci_run_regs { 448 __le32 microframe_index; 449 __le32 rsvd[7]; 450 struct xhci_intr_reg ir_set[128]; 451 }; 452 453 /** 454 * struct doorbell_array 455 * 456 * Bits 0 - 7: Endpoint target 457 * Bits 8 - 15: RsvdZ 458 * Bits 16 - 31: Stream ID 459 * 460 * Section 5.6 461 */ 462 struct xhci_doorbell_array { 463 __le32 doorbell[256]; 464 }; 465 466 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 467 #define DB_VALUE_HOST 0x00000000 468 469 /** 470 * struct xhci_protocol_caps 471 * @revision: major revision, minor revision, capability ID, 472 * and next capability pointer. 473 * @name_string: Four ASCII characters to say which spec this xHC 474 * follows, typically "USB ". 475 * @port_info: Port offset, count, and protocol-defined information. 476 */ 477 struct xhci_protocol_caps { 478 u32 revision; 479 u32 name_string; 480 u32 port_info; 481 }; 482 483 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 484 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 485 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 486 487 /** 488 * struct xhci_container_ctx 489 * @type: Type of context. Used to calculated offsets to contained contexts. 490 * @size: Size of the context data 491 * @bytes: The raw context data given to HW 492 * @dma: dma address of the bytes 493 * 494 * Represents either a Device or Input context. Holds a pointer to the raw 495 * memory used for the context (bytes) and dma address of it (dma). 496 */ 497 struct xhci_container_ctx { 498 unsigned type; 499 #define XHCI_CTX_TYPE_DEVICE 0x1 500 #define XHCI_CTX_TYPE_INPUT 0x2 501 502 int size; 503 504 u8 *bytes; 505 dma_addr_t dma; 506 }; 507 508 /** 509 * struct xhci_slot_ctx 510 * @dev_info: Route string, device speed, hub info, and last valid endpoint 511 * @dev_info2: Max exit latency for device number, root hub port number 512 * @tt_info: tt_info is used to construct split transaction tokens 513 * @dev_state: slot state and device address 514 * 515 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 516 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 517 * reserved at the end of the slot context for HC internal use. 518 */ 519 struct xhci_slot_ctx { 520 __le32 dev_info; 521 __le32 dev_info2; 522 __le32 tt_info; 523 __le32 dev_state; 524 /* offset 0x10 to 0x1f reserved for HC internal use */ 525 __le32 reserved[4]; 526 }; 527 528 /* dev_info bitmasks */ 529 /* Route String - 0:19 */ 530 #define ROUTE_STRING_MASK (0xfffff) 531 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 532 #define DEV_SPEED (0xf << 20) 533 /* bit 24 reserved */ 534 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 535 #define DEV_MTT (0x1 << 25) 536 /* Set if the device is a hub - bit 26 */ 537 #define DEV_HUB (0x1 << 26) 538 /* Index of the last valid endpoint context in this device context - 27:31 */ 539 #define LAST_CTX_MASK (0x1f << 27) 540 #define LAST_CTX(p) ((p) << 27) 541 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 542 #define SLOT_FLAG (1 << 0) 543 #define EP0_FLAG (1 << 1) 544 545 /* dev_info2 bitmasks */ 546 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 547 #define MAX_EXIT (0xffff) 548 /* Root hub port number that is needed to access the USB device */ 549 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 550 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 551 /* Maximum number of ports under a hub device */ 552 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 553 554 /* tt_info bitmasks */ 555 /* 556 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 557 * The Slot ID of the hub that isolates the high speed signaling from 558 * this low or full-speed device. '0' if attached to root hub port. 559 */ 560 #define TT_SLOT (0xff) 561 /* 562 * The number of the downstream facing port of the high-speed hub 563 * '0' if the device is not low or full speed. 564 */ 565 #define TT_PORT (0xff << 8) 566 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 567 568 /* dev_state bitmasks */ 569 /* USB device address - assigned by the HC */ 570 #define DEV_ADDR_MASK (0xff) 571 /* bits 8:26 reserved */ 572 /* Slot state */ 573 #define SLOT_STATE (0x1f << 27) 574 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 575 576 #define SLOT_STATE_DISABLED 0 577 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 578 #define SLOT_STATE_DEFAULT 1 579 #define SLOT_STATE_ADDRESSED 2 580 #define SLOT_STATE_CONFIGURED 3 581 582 /** 583 * struct xhci_ep_ctx 584 * @ep_info: endpoint state, streams, mult, and interval information. 585 * @ep_info2: information on endpoint type, max packet size, max burst size, 586 * error count, and whether the HC will force an event for all 587 * transactions. 588 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 589 * defines one stream, this points to the endpoint transfer ring. 590 * Otherwise, it points to a stream context array, which has a 591 * ring pointer for each flow. 592 * @tx_info: 593 * Average TRB lengths for the endpoint ring and 594 * max payload within an Endpoint Service Interval Time (ESIT). 595 * 596 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 597 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 598 * reserved at the end of the endpoint context for HC internal use. 599 */ 600 struct xhci_ep_ctx { 601 __le32 ep_info; 602 __le32 ep_info2; 603 __le64 deq; 604 __le32 tx_info; 605 /* offset 0x14 - 0x1f reserved for HC internal use */ 606 __le32 reserved[3]; 607 }; 608 609 /* ep_info bitmasks */ 610 /* 611 * Endpoint State - bits 0:2 612 * 0 - disabled 613 * 1 - running 614 * 2 - halted due to halt condition - ok to manipulate endpoint ring 615 * 3 - stopped 616 * 4 - TRB error 617 * 5-7 - reserved 618 */ 619 #define EP_STATE_MASK (0xf) 620 #define EP_STATE_DISABLED 0 621 #define EP_STATE_RUNNING 1 622 #define EP_STATE_HALTED 2 623 #define EP_STATE_STOPPED 3 624 #define EP_STATE_ERROR 4 625 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 626 #define EP_MULT(p) (((p) & 0x3) << 8) 627 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 628 /* bits 10:14 are Max Primary Streams */ 629 /* bit 15 is Linear Stream Array */ 630 /* Interval - period between requests to an endpoint - 125u increments. */ 631 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 632 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 633 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 634 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 635 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 636 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 637 #define EP_HAS_LSA (1 << 15) 638 639 /* ep_info2 bitmasks */ 640 /* 641 * Force Event - generate transfer events for all TRBs for this endpoint 642 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 643 */ 644 #define FORCE_EVENT (0x1) 645 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 646 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 647 #define EP_TYPE(p) ((p) << 3) 648 #define ISOC_OUT_EP 1 649 #define BULK_OUT_EP 2 650 #define INT_OUT_EP 3 651 #define CTRL_EP 4 652 #define ISOC_IN_EP 5 653 #define BULK_IN_EP 6 654 #define INT_IN_EP 7 655 /* bit 6 reserved */ 656 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 657 #define MAX_BURST(p) (((p)&0xff) << 8) 658 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 659 #define MAX_PACKET(p) (((p)&0xffff) << 16) 660 #define MAX_PACKET_MASK (0xffff << 16) 661 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 662 663 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 664 * USB2.0 spec 9.6.6. 665 */ 666 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 667 668 /* tx_info bitmasks */ 669 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 670 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 671 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 672 673 /* deq bitmasks */ 674 #define EP_CTX_CYCLE_MASK (1 << 0) 675 676 677 /** 678 * struct xhci_input_control_context 679 * Input control context; see section 6.2.5. 680 * 681 * @drop_context: set the bit of the endpoint context you want to disable 682 * @add_context: set the bit of the endpoint context you want to enable 683 */ 684 struct xhci_input_control_ctx { 685 __le32 drop_flags; 686 __le32 add_flags; 687 __le32 rsvd2[6]; 688 }; 689 690 #define EP_IS_ADDED(ctrl_ctx, i) \ 691 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 692 #define EP_IS_DROPPED(ctrl_ctx, i) \ 693 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 694 695 /* Represents everything that is needed to issue a command on the command ring. 696 * It's useful to pre-allocate these for commands that cannot fail due to 697 * out-of-memory errors, like freeing streams. 698 */ 699 struct xhci_command { 700 /* Input context for changing device state */ 701 struct xhci_container_ctx *in_ctx; 702 u32 status; 703 /* If completion is null, no one is waiting on this command 704 * and the structure can be freed after the command completes. 705 */ 706 struct completion *completion; 707 union xhci_trb *command_trb; 708 struct list_head cmd_list; 709 }; 710 711 /* drop context bitmasks */ 712 #define DROP_EP(x) (0x1 << x) 713 /* add context bitmasks */ 714 #define ADD_EP(x) (0x1 << x) 715 716 struct xhci_stream_ctx { 717 /* 64-bit stream ring address, cycle state, and stream type */ 718 __le64 stream_ring; 719 /* offset 0x14 - 0x1f reserved for HC internal use */ 720 __le32 reserved[2]; 721 }; 722 723 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 724 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 725 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 726 #define SCT_SEC_TR 0 727 /* Primary stream array type, dequeue pointer is to a transfer ring */ 728 #define SCT_PRI_TR 1 729 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 730 #define SCT_SSA_8 2 731 #define SCT_SSA_16 3 732 #define SCT_SSA_32 4 733 #define SCT_SSA_64 5 734 #define SCT_SSA_128 6 735 #define SCT_SSA_256 7 736 737 /* Assume no secondary streams for now */ 738 struct xhci_stream_info { 739 struct xhci_ring **stream_rings; 740 /* Number of streams, including stream 0 (which drivers can't use) */ 741 unsigned int num_streams; 742 /* The stream context array may be bigger than 743 * the number of streams the driver asked for 744 */ 745 struct xhci_stream_ctx *stream_ctx_array; 746 unsigned int num_stream_ctxs; 747 dma_addr_t ctx_array_dma; 748 /* For mapping physical TRB addresses to segments in stream rings */ 749 struct radix_tree_root trb_address_map; 750 struct xhci_command *free_streams_command; 751 }; 752 753 #define SMALL_STREAM_ARRAY_SIZE 256 754 #define MEDIUM_STREAM_ARRAY_SIZE 1024 755 756 /* Some Intel xHCI host controllers need software to keep track of the bus 757 * bandwidth. Keep track of endpoint info here. Each root port is allocated 758 * the full bus bandwidth. We must also treat TTs (including each port under a 759 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 760 * (DMI) also limits the total bandwidth (across all domains) that can be used. 761 */ 762 struct xhci_bw_info { 763 /* ep_interval is zero-based */ 764 unsigned int ep_interval; 765 /* mult and num_packets are one-based */ 766 unsigned int mult; 767 unsigned int num_packets; 768 unsigned int max_packet_size; 769 unsigned int max_esit_payload; 770 unsigned int type; 771 }; 772 773 /* "Block" sizes in bytes the hardware uses for different device speeds. 774 * The logic in this part of the hardware limits the number of bits the hardware 775 * can use, so must represent bandwidth in a less precise manner to mimic what 776 * the scheduler hardware computes. 777 */ 778 #define FS_BLOCK 1 779 #define HS_BLOCK 4 780 #define SS_BLOCK 16 781 #define DMI_BLOCK 32 782 783 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 784 * with each byte transferred. SuperSpeed devices have an initial overhead to 785 * set up bursts. These are in blocks, see above. LS overhead has already been 786 * translated into FS blocks. 787 */ 788 #define DMI_OVERHEAD 8 789 #define DMI_OVERHEAD_BURST 4 790 #define SS_OVERHEAD 8 791 #define SS_OVERHEAD_BURST 32 792 #define HS_OVERHEAD 26 793 #define FS_OVERHEAD 20 794 #define LS_OVERHEAD 128 795 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 796 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 797 * of overhead associated with split transfers crossing microframe boundaries. 798 * 31 blocks is pure protocol overhead. 799 */ 800 #define TT_HS_OVERHEAD (31 + 94) 801 #define TT_DMI_OVERHEAD (25 + 12) 802 803 /* Bandwidth limits in blocks */ 804 #define FS_BW_LIMIT 1285 805 #define TT_BW_LIMIT 1320 806 #define HS_BW_LIMIT 1607 807 #define SS_BW_LIMIT_IN 3906 808 #define DMI_BW_LIMIT_IN 3906 809 #define SS_BW_LIMIT_OUT 3906 810 #define DMI_BW_LIMIT_OUT 3906 811 812 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 813 #define FS_BW_RESERVED 10 814 #define HS_BW_RESERVED 20 815 #define SS_BW_RESERVED 10 816 817 struct xhci_virt_ep { 818 struct xhci_ring *ring; 819 /* Related to endpoints that are configured to use stream IDs only */ 820 struct xhci_stream_info *stream_info; 821 /* Temporary storage in case the configure endpoint command fails and we 822 * have to restore the device state to the previous state 823 */ 824 struct xhci_ring *new_ring; 825 unsigned int ep_state; 826 #define SET_DEQ_PENDING (1 << 0) 827 #define EP_HALTED (1 << 1) /* For stall handling */ 828 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 829 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 830 #define EP_GETTING_STREAMS (1 << 3) 831 #define EP_HAS_STREAMS (1 << 4) 832 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 833 #define EP_GETTING_NO_STREAMS (1 << 5) 834 /* ---- Related to URB cancellation ---- */ 835 struct list_head cancelled_td_list; 836 /* The TRB that was last reported in a stopped endpoint ring */ 837 union xhci_trb *stopped_trb; 838 struct xhci_td *stopped_td; 839 unsigned int stopped_stream; 840 /* Watchdog timer for stop endpoint command to cancel URBs */ 841 struct timer_list stop_cmd_timer; 842 int stop_cmds_pending; 843 struct xhci_hcd *xhci; 844 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 845 * command. We'll need to update the ring's dequeue segment and dequeue 846 * pointer after the command completes. 847 */ 848 struct xhci_segment *queued_deq_seg; 849 union xhci_trb *queued_deq_ptr; 850 /* 851 * Sometimes the xHC can not process isochronous endpoint ring quickly 852 * enough, and it will miss some isoc tds on the ring and generate 853 * a Missed Service Error Event. 854 * Set skip flag when receive a Missed Service Error Event and 855 * process the missed tds on the endpoint ring. 856 */ 857 bool skip; 858 /* Bandwidth checking storage */ 859 struct xhci_bw_info bw_info; 860 struct list_head bw_endpoint_list; 861 }; 862 863 enum xhci_overhead_type { 864 LS_OVERHEAD_TYPE = 0, 865 FS_OVERHEAD_TYPE, 866 HS_OVERHEAD_TYPE, 867 }; 868 869 struct xhci_interval_bw { 870 unsigned int num_packets; 871 /* Sorted by max packet size. 872 * Head of the list is the greatest max packet size. 873 */ 874 struct list_head endpoints; 875 /* How many endpoints of each speed are present. */ 876 unsigned int overhead[3]; 877 }; 878 879 #define XHCI_MAX_INTERVAL 16 880 881 struct xhci_interval_bw_table { 882 unsigned int interval0_esit_payload; 883 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 884 /* Includes reserved bandwidth for async endpoints */ 885 unsigned int bw_used; 886 unsigned int ss_bw_in; 887 unsigned int ss_bw_out; 888 }; 889 890 891 struct xhci_virt_device { 892 struct usb_device *udev; 893 /* 894 * Commands to the hardware are passed an "input context" that 895 * tells the hardware what to change in its data structures. 896 * The hardware will return changes in an "output context" that 897 * software must allocate for the hardware. We need to keep 898 * track of input and output contexts separately because 899 * these commands might fail and we don't trust the hardware. 900 */ 901 struct xhci_container_ctx *out_ctx; 902 /* Used for addressing devices and configuration changes */ 903 struct xhci_container_ctx *in_ctx; 904 /* Rings saved to ensure old alt settings can be re-instated */ 905 struct xhci_ring **ring_cache; 906 int num_rings_cached; 907 /* Store xHC assigned device address */ 908 int address; 909 #define XHCI_MAX_RINGS_CACHED 31 910 struct xhci_virt_ep eps[31]; 911 struct completion cmd_completion; 912 /* Status of the last command issued for this device */ 913 u32 cmd_status; 914 struct list_head cmd_list; 915 u8 fake_port; 916 u8 real_port; 917 struct xhci_interval_bw_table *bw_table; 918 struct xhci_tt_bw_info *tt_info; 919 /* The current max exit latency for the enabled USB3 link states. */ 920 u16 current_mel; 921 }; 922 923 /* 924 * For each roothub, keep track of the bandwidth information for each periodic 925 * interval. 926 * 927 * If a high speed hub is attached to the roothub, each TT associated with that 928 * hub is a separate bandwidth domain. The interval information for the 929 * endpoints on the devices under that TT will appear in the TT structure. 930 */ 931 struct xhci_root_port_bw_info { 932 struct list_head tts; 933 unsigned int num_active_tts; 934 struct xhci_interval_bw_table bw_table; 935 }; 936 937 struct xhci_tt_bw_info { 938 struct list_head tt_list; 939 int slot_id; 940 int ttport; 941 struct xhci_interval_bw_table bw_table; 942 int active_eps; 943 }; 944 945 946 /** 947 * struct xhci_device_context_array 948 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 949 */ 950 struct xhci_device_context_array { 951 /* 64-bit device addresses; we only write 32-bit addresses */ 952 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 953 /* private xHCD pointers */ 954 dma_addr_t dma; 955 }; 956 /* TODO: write function to set the 64-bit device DMA address */ 957 /* 958 * TODO: change this to be dynamically sized at HC mem init time since the HC 959 * might not be able to handle the maximum number of devices possible. 960 */ 961 962 963 struct xhci_transfer_event { 964 /* 64-bit buffer address, or immediate data */ 965 __le64 buffer; 966 __le32 transfer_len; 967 /* This field is interpreted differently based on the type of TRB */ 968 __le32 flags; 969 }; 970 971 /** Transfer Event bit fields **/ 972 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 973 974 /* Completion Code - only applicable for some types of TRBs */ 975 #define COMP_CODE_MASK (0xff << 24) 976 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 977 #define COMP_SUCCESS 1 978 /* Data Buffer Error */ 979 #define COMP_DB_ERR 2 980 /* Babble Detected Error */ 981 #define COMP_BABBLE 3 982 /* USB Transaction Error */ 983 #define COMP_TX_ERR 4 984 /* TRB Error - some TRB field is invalid */ 985 #define COMP_TRB_ERR 5 986 /* Stall Error - USB device is stalled */ 987 #define COMP_STALL 6 988 /* Resource Error - HC doesn't have memory for that device configuration */ 989 #define COMP_ENOMEM 7 990 /* Bandwidth Error - not enough room in schedule for this dev config */ 991 #define COMP_BW_ERR 8 992 /* No Slots Available Error - HC ran out of device slots */ 993 #define COMP_ENOSLOTS 9 994 /* Invalid Stream Type Error */ 995 #define COMP_STREAM_ERR 10 996 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 997 #define COMP_EBADSLT 11 998 /* Endpoint Not Enabled Error */ 999 #define COMP_EBADEP 12 1000 /* Short Packet */ 1001 #define COMP_SHORT_TX 13 1002 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1003 #define COMP_UNDERRUN 14 1004 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1005 #define COMP_OVERRUN 15 1006 /* Virtual Function Event Ring Full Error */ 1007 #define COMP_VF_FULL 16 1008 /* Parameter Error - Context parameter is invalid */ 1009 #define COMP_EINVAL 17 1010 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1011 #define COMP_BW_OVER 18 1012 /* Context State Error - illegal context state transition requested */ 1013 #define COMP_CTX_STATE 19 1014 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1015 #define COMP_PING_ERR 20 1016 /* Event Ring is full */ 1017 #define COMP_ER_FULL 21 1018 /* Incompatible Device Error */ 1019 #define COMP_DEV_ERR 22 1020 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1021 #define COMP_MISSED_INT 23 1022 /* Successfully stopped command ring */ 1023 #define COMP_CMD_STOP 24 1024 /* Successfully aborted current command and stopped command ring */ 1025 #define COMP_CMD_ABORT 25 1026 /* Stopped - transfer was terminated by a stop endpoint command */ 1027 #define COMP_STOP 26 1028 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1029 #define COMP_STOP_INVAL 27 1030 /* Control Abort Error - Debug Capability - control pipe aborted */ 1031 #define COMP_DBG_ABORT 28 1032 /* Max Exit Latency Too Large Error */ 1033 #define COMP_MEL_ERR 29 1034 /* TRB type 30 reserved */ 1035 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1036 #define COMP_BUFF_OVER 31 1037 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1038 #define COMP_ISSUES 32 1039 /* Undefined Error - reported when other error codes don't apply */ 1040 #define COMP_UNKNOWN 33 1041 /* Invalid Stream ID Error */ 1042 #define COMP_STRID_ERR 34 1043 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1044 #define COMP_2ND_BW_ERR 35 1045 /* Split Transaction Error */ 1046 #define COMP_SPLIT_ERR 36 1047 1048 struct xhci_link_trb { 1049 /* 64-bit segment pointer*/ 1050 __le64 segment_ptr; 1051 __le32 intr_target; 1052 __le32 control; 1053 }; 1054 1055 /* control bitfields */ 1056 #define LINK_TOGGLE (0x1<<1) 1057 1058 /* Command completion event TRB */ 1059 struct xhci_event_cmd { 1060 /* Pointer to command TRB, or the value passed by the event data trb */ 1061 __le64 cmd_trb; 1062 __le32 status; 1063 __le32 flags; 1064 }; 1065 1066 /* flags bitmasks */ 1067 /* bits 16:23 are the virtual function ID */ 1068 /* bits 24:31 are the slot ID */ 1069 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1070 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1071 1072 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1073 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1074 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1075 1076 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1077 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1078 #define LAST_EP_INDEX 30 1079 1080 /* Set TR Dequeue Pointer command TRB fields */ 1081 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1082 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1083 1084 1085 /* Port Status Change Event TRB fields */ 1086 /* Port ID - bits 31:24 */ 1087 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1088 1089 /* Normal TRB fields */ 1090 /* transfer_len bitmasks - bits 0:16 */ 1091 #define TRB_LEN(p) ((p) & 0x1ffff) 1092 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1093 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1094 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1095 #define TRB_TBC(p) (((p) & 0x3) << 7) 1096 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1097 1098 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1099 #define TRB_CYCLE (1<<0) 1100 /* 1101 * Force next event data TRB to be evaluated before task switch. 1102 * Used to pass OS data back after a TD completes. 1103 */ 1104 #define TRB_ENT (1<<1) 1105 /* Interrupt on short packet */ 1106 #define TRB_ISP (1<<2) 1107 /* Set PCIe no snoop attribute */ 1108 #define TRB_NO_SNOOP (1<<3) 1109 /* Chain multiple TRBs into a TD */ 1110 #define TRB_CHAIN (1<<4) 1111 /* Interrupt on completion */ 1112 #define TRB_IOC (1<<5) 1113 /* The buffer pointer contains immediate data */ 1114 #define TRB_IDT (1<<6) 1115 1116 /* Block Event Interrupt */ 1117 #define TRB_BEI (1<<9) 1118 1119 /* Control transfer TRB specific fields */ 1120 #define TRB_DIR_IN (1<<16) 1121 #define TRB_TX_TYPE(p) ((p) << 16) 1122 #define TRB_DATA_OUT 2 1123 #define TRB_DATA_IN 3 1124 1125 /* Isochronous TRB specific fields */ 1126 #define TRB_SIA (1<<31) 1127 1128 struct xhci_generic_trb { 1129 __le32 field[4]; 1130 }; 1131 1132 union xhci_trb { 1133 struct xhci_link_trb link; 1134 struct xhci_transfer_event trans_event; 1135 struct xhci_event_cmd event_cmd; 1136 struct xhci_generic_trb generic; 1137 }; 1138 1139 /* TRB bit mask */ 1140 #define TRB_TYPE_BITMASK (0xfc00) 1141 #define TRB_TYPE(p) ((p) << 10) 1142 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1143 /* TRB type IDs */ 1144 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1145 #define TRB_NORMAL 1 1146 /* setup stage for control transfers */ 1147 #define TRB_SETUP 2 1148 /* data stage for control transfers */ 1149 #define TRB_DATA 3 1150 /* status stage for control transfers */ 1151 #define TRB_STATUS 4 1152 /* isoc transfers */ 1153 #define TRB_ISOC 5 1154 /* TRB for linking ring segments */ 1155 #define TRB_LINK 6 1156 #define TRB_EVENT_DATA 7 1157 /* Transfer Ring No-op (not for the command ring) */ 1158 #define TRB_TR_NOOP 8 1159 /* Command TRBs */ 1160 /* Enable Slot Command */ 1161 #define TRB_ENABLE_SLOT 9 1162 /* Disable Slot Command */ 1163 #define TRB_DISABLE_SLOT 10 1164 /* Address Device Command */ 1165 #define TRB_ADDR_DEV 11 1166 /* Configure Endpoint Command */ 1167 #define TRB_CONFIG_EP 12 1168 /* Evaluate Context Command */ 1169 #define TRB_EVAL_CONTEXT 13 1170 /* Reset Endpoint Command */ 1171 #define TRB_RESET_EP 14 1172 /* Stop Transfer Ring Command */ 1173 #define TRB_STOP_RING 15 1174 /* Set Transfer Ring Dequeue Pointer Command */ 1175 #define TRB_SET_DEQ 16 1176 /* Reset Device Command */ 1177 #define TRB_RESET_DEV 17 1178 /* Force Event Command (opt) */ 1179 #define TRB_FORCE_EVENT 18 1180 /* Negotiate Bandwidth Command (opt) */ 1181 #define TRB_NEG_BANDWIDTH 19 1182 /* Set Latency Tolerance Value Command (opt) */ 1183 #define TRB_SET_LT 20 1184 /* Get port bandwidth Command */ 1185 #define TRB_GET_BW 21 1186 /* Force Header Command - generate a transaction or link management packet */ 1187 #define TRB_FORCE_HEADER 22 1188 /* No-op Command - not for transfer rings */ 1189 #define TRB_CMD_NOOP 23 1190 /* TRB IDs 24-31 reserved */ 1191 /* Event TRBS */ 1192 /* Transfer Event */ 1193 #define TRB_TRANSFER 32 1194 /* Command Completion Event */ 1195 #define TRB_COMPLETION 33 1196 /* Port Status Change Event */ 1197 #define TRB_PORT_STATUS 34 1198 /* Bandwidth Request Event (opt) */ 1199 #define TRB_BANDWIDTH_EVENT 35 1200 /* Doorbell Event (opt) */ 1201 #define TRB_DOORBELL 36 1202 /* Host Controller Event */ 1203 #define TRB_HC_EVENT 37 1204 /* Device Notification Event - device sent function wake notification */ 1205 #define TRB_DEV_NOTE 38 1206 /* MFINDEX Wrap Event - microframe counter wrapped */ 1207 #define TRB_MFINDEX_WRAP 39 1208 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1209 1210 /* Nec vendor-specific command completion event. */ 1211 #define TRB_NEC_CMD_COMP 48 1212 /* Get NEC firmware revision. */ 1213 #define TRB_NEC_GET_FW 49 1214 1215 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1216 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1217 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1218 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1219 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1220 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1221 1222 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1223 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1224 1225 /* 1226 * TRBS_PER_SEGMENT must be a multiple of 4, 1227 * since the command ring is 64-byte aligned. 1228 * It must also be greater than 16. 1229 */ 1230 #define TRBS_PER_SEGMENT 64 1231 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1232 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1233 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1234 #define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE)) 1235 /* TRB buffer pointers can't cross 64KB boundaries */ 1236 #define TRB_MAX_BUFF_SHIFT 16 1237 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1238 1239 struct xhci_segment { 1240 union xhci_trb *trbs; 1241 /* private to HCD */ 1242 struct xhci_segment *next; 1243 dma_addr_t dma; 1244 }; 1245 1246 struct xhci_td { 1247 struct list_head td_list; 1248 struct list_head cancelled_td_list; 1249 struct urb *urb; 1250 struct xhci_segment *start_seg; 1251 union xhci_trb *first_trb; 1252 union xhci_trb *last_trb; 1253 }; 1254 1255 struct xhci_dequeue_state { 1256 struct xhci_segment *new_deq_seg; 1257 union xhci_trb *new_deq_ptr; 1258 int new_cycle_state; 1259 }; 1260 1261 enum xhci_ring_type { 1262 TYPE_CTRL = 0, 1263 TYPE_ISOC, 1264 TYPE_BULK, 1265 TYPE_INTR, 1266 TYPE_STREAM, 1267 TYPE_COMMAND, 1268 TYPE_EVENT, 1269 }; 1270 1271 struct xhci_ring { 1272 struct xhci_segment *first_seg; 1273 struct xhci_segment *last_seg; 1274 union xhci_trb *enqueue; 1275 struct xhci_segment *enq_seg; 1276 unsigned int enq_updates; 1277 union xhci_trb *dequeue; 1278 struct xhci_segment *deq_seg; 1279 unsigned int deq_updates; 1280 struct list_head td_list; 1281 /* 1282 * Write the cycle state into the TRB cycle field to give ownership of 1283 * the TRB to the host controller (if we are the producer), or to check 1284 * if we own the TRB (if we are the consumer). See section 4.9.1. 1285 */ 1286 u32 cycle_state; 1287 unsigned int stream_id; 1288 unsigned int num_segs; 1289 unsigned int num_trbs_free; 1290 unsigned int num_trbs_free_temp; 1291 enum xhci_ring_type type; 1292 bool last_td_was_short; 1293 }; 1294 1295 struct xhci_erst_entry { 1296 /* 64-bit event ring segment address */ 1297 __le64 seg_addr; 1298 __le32 seg_size; 1299 /* Set to zero */ 1300 __le32 rsvd; 1301 }; 1302 1303 struct xhci_erst { 1304 struct xhci_erst_entry *entries; 1305 unsigned int num_entries; 1306 /* xhci->event_ring keeps track of segment dma addresses */ 1307 dma_addr_t erst_dma_addr; 1308 /* Num entries the ERST can contain */ 1309 unsigned int erst_size; 1310 }; 1311 1312 struct xhci_scratchpad { 1313 u64 *sp_array; 1314 dma_addr_t sp_dma; 1315 void **sp_buffers; 1316 dma_addr_t *sp_dma_buffers; 1317 }; 1318 1319 struct urb_priv { 1320 int length; 1321 int td_cnt; 1322 struct xhci_td *td[0]; 1323 }; 1324 1325 /* 1326 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1327 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1328 * meaning 64 ring segments. 1329 * Initial allocated size of the ERST, in number of entries */ 1330 #define ERST_NUM_SEGS 1 1331 /* Initial allocated size of the ERST, in number of entries */ 1332 #define ERST_SIZE 64 1333 /* Initial number of event segment rings allocated */ 1334 #define ERST_ENTRIES 1 1335 /* Poll every 60 seconds */ 1336 #define POLL_TIMEOUT 60 1337 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1338 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1339 /* XXX: Make these module parameters */ 1340 1341 struct s3_save { 1342 u32 command; 1343 u32 dev_nt; 1344 u64 dcbaa_ptr; 1345 u32 config_reg; 1346 u32 irq_pending; 1347 u32 irq_control; 1348 u32 erst_size; 1349 u64 erst_base; 1350 u64 erst_dequeue; 1351 }; 1352 1353 /* Use for lpm */ 1354 struct dev_info { 1355 u32 dev_id; 1356 struct list_head list; 1357 }; 1358 1359 struct xhci_bus_state { 1360 unsigned long bus_suspended; 1361 unsigned long next_statechange; 1362 1363 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1364 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1365 u32 port_c_suspend; 1366 u32 suspended_ports; 1367 u32 port_remote_wakeup; 1368 unsigned long resume_done[USB_MAXCHILDREN]; 1369 /* which ports have started to resume */ 1370 unsigned long resuming_ports; 1371 }; 1372 1373 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1374 { 1375 if (hcd->speed == HCD_USB3) 1376 return 0; 1377 else 1378 return 1; 1379 } 1380 1381 /* There is one xhci_hcd structure per controller */ 1382 struct xhci_hcd { 1383 struct usb_hcd *main_hcd; 1384 struct usb_hcd *shared_hcd; 1385 /* glue to PCI and HCD framework */ 1386 struct xhci_cap_regs __iomem *cap_regs; 1387 struct xhci_op_regs __iomem *op_regs; 1388 struct xhci_run_regs __iomem *run_regs; 1389 struct xhci_doorbell_array __iomem *dba; 1390 /* Our HCD's current interrupter register set */ 1391 struct xhci_intr_reg __iomem *ir_set; 1392 1393 /* Cached register copies of read-only HC data */ 1394 __u32 hcs_params1; 1395 __u32 hcs_params2; 1396 __u32 hcs_params3; 1397 __u32 hcc_params; 1398 1399 spinlock_t lock; 1400 1401 /* packed release number */ 1402 u8 sbrn; 1403 u16 hci_version; 1404 u8 max_slots; 1405 u8 max_interrupters; 1406 u8 max_ports; 1407 u8 isoc_threshold; 1408 int event_ring_max; 1409 int addr_64; 1410 /* 4KB min, 128MB max */ 1411 int page_size; 1412 /* Valid values are 12 to 20, inclusive */ 1413 int page_shift; 1414 /* msi-x vectors */ 1415 int msix_count; 1416 struct msix_entry *msix_entries; 1417 /* data structures */ 1418 struct xhci_device_context_array *dcbaa; 1419 struct xhci_ring *cmd_ring; 1420 unsigned int cmd_ring_reserved_trbs; 1421 struct xhci_ring *event_ring; 1422 struct xhci_erst erst; 1423 /* Scratchpad */ 1424 struct xhci_scratchpad *scratchpad; 1425 /* Store LPM test failed devices' information */ 1426 struct list_head lpm_failed_devs; 1427 1428 /* slot enabling and address device helpers */ 1429 struct completion addr_dev; 1430 int slot_id; 1431 /* For USB 3.0 LPM enable/disable. */ 1432 struct xhci_command *lpm_command; 1433 /* Internal mirror of the HW's dcbaa */ 1434 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1435 /* For keeping track of bandwidth domains per roothub. */ 1436 struct xhci_root_port_bw_info *rh_bw; 1437 1438 /* DMA pools */ 1439 struct dma_pool *device_pool; 1440 struct dma_pool *segment_pool; 1441 struct dma_pool *small_streams_pool; 1442 struct dma_pool *medium_streams_pool; 1443 1444 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1445 /* Poll the rings - for debugging */ 1446 struct timer_list event_ring_timer; 1447 int zombie; 1448 #endif 1449 /* Host controller watchdog timer structures */ 1450 unsigned int xhc_state; 1451 1452 u32 command; 1453 struct s3_save s3; 1454 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1455 * 1456 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1457 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1458 * that sees this status (other than the timer that set it) should stop touching 1459 * hardware immediately. Interrupt handlers should return immediately when 1460 * they see this status (any time they drop and re-acquire xhci->lock). 1461 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1462 * putting the TD on the canceled list, etc. 1463 * 1464 * There are no reports of xHCI host controllers that display this issue. 1465 */ 1466 #define XHCI_STATE_DYING (1 << 0) 1467 #define XHCI_STATE_HALTED (1 << 1) 1468 /* Statistics */ 1469 int error_bitmask; 1470 unsigned int quirks; 1471 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1472 #define XHCI_RESET_EP_QUIRK (1 << 1) 1473 #define XHCI_NEC_HOST (1 << 2) 1474 #define XHCI_AMD_PLL_FIX (1 << 3) 1475 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1476 /* 1477 * Certain Intel host controllers have a limit to the number of endpoint 1478 * contexts they can handle. Ideally, they would signal that they can't handle 1479 * anymore endpoint contexts by returning a Resource Error for the Configure 1480 * Endpoint command, but they don't. Instead they expect software to keep track 1481 * of the number of active endpoints for them, across configure endpoint 1482 * commands, reset device commands, disable slot commands, and address device 1483 * commands. 1484 */ 1485 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1486 #define XHCI_BROKEN_MSI (1 << 6) 1487 #define XHCI_RESET_ON_RESUME (1 << 7) 1488 #define XHCI_SW_BW_CHECKING (1 << 8) 1489 #define XHCI_AMD_0x96_HOST (1 << 9) 1490 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1491 #define XHCI_LPM_SUPPORT (1 << 11) 1492 #define XHCI_INTEL_HOST (1 << 12) 1493 unsigned int num_active_eps; 1494 unsigned int limit_active_eps; 1495 /* There are two roothubs to keep track of bus suspend info for */ 1496 struct xhci_bus_state bus_state[2]; 1497 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1498 u8 *port_array; 1499 /* Array of pointers to USB 3.0 PORTSC registers */ 1500 __le32 __iomem **usb3_ports; 1501 unsigned int num_usb3_ports; 1502 /* Array of pointers to USB 2.0 PORTSC registers */ 1503 __le32 __iomem **usb2_ports; 1504 unsigned int num_usb2_ports; 1505 /* support xHCI 0.96 spec USB2 software LPM */ 1506 unsigned sw_lpm_support:1; 1507 /* support xHCI 1.0 spec USB2 hardware LPM */ 1508 unsigned hw_lpm_support:1; 1509 }; 1510 1511 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1512 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1513 { 1514 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1515 } 1516 1517 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1518 { 1519 return xhci->main_hcd; 1520 } 1521 1522 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1523 #define XHCI_DEBUG 1 1524 #else 1525 #define XHCI_DEBUG 0 1526 #endif 1527 1528 #define xhci_dbg(xhci, fmt, args...) \ 1529 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1530 #define xhci_info(xhci, fmt, args...) \ 1531 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1532 #define xhci_err(xhci, fmt, args...) \ 1533 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1534 #define xhci_warn(xhci, fmt, args...) \ 1535 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1536 1537 /* TODO: copied from ehci.h - can be refactored? */ 1538 /* xHCI spec says all registers are little endian */ 1539 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1540 __le32 __iomem *regs) 1541 { 1542 return readl(regs); 1543 } 1544 static inline void xhci_writel(struct xhci_hcd *xhci, 1545 const unsigned int val, __le32 __iomem *regs) 1546 { 1547 writel(val, regs); 1548 } 1549 1550 /* 1551 * Registers should always be accessed with double word or quad word accesses. 1552 * 1553 * Some xHCI implementations may support 64-bit address pointers. Registers 1554 * with 64-bit address pointers should be written to with dword accesses by 1555 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1556 * xHCI implementations that do not support 64-bit address pointers will ignore 1557 * the high dword, and write order is irrelevant. 1558 */ 1559 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1560 __le64 __iomem *regs) 1561 { 1562 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1563 u64 val_lo = readl(ptr); 1564 u64 val_hi = readl(ptr + 1); 1565 return val_lo + (val_hi << 32); 1566 } 1567 static inline void xhci_write_64(struct xhci_hcd *xhci, 1568 const u64 val, __le64 __iomem *regs) 1569 { 1570 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1571 u32 val_lo = lower_32_bits(val); 1572 u32 val_hi = upper_32_bits(val); 1573 1574 writel(val_lo, ptr); 1575 writel(val_hi, ptr + 1); 1576 } 1577 1578 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1579 { 1580 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1581 } 1582 1583 /* xHCI debugging */ 1584 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1585 void xhci_print_registers(struct xhci_hcd *xhci); 1586 void xhci_dbg_regs(struct xhci_hcd *xhci); 1587 void xhci_print_run_regs(struct xhci_hcd *xhci); 1588 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1589 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1590 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1591 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1592 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1593 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1594 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1595 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1596 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1597 struct xhci_container_ctx *ctx); 1598 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1599 unsigned int slot_id, unsigned int ep_index, 1600 struct xhci_virt_ep *ep); 1601 1602 /* xHCI memory management */ 1603 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1604 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1605 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1606 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1607 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1608 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1609 struct usb_device *udev); 1610 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1611 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1612 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1613 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1614 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1615 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1616 struct xhci_bw_info *ep_bw, 1617 struct xhci_interval_bw_table *bw_table, 1618 struct usb_device *udev, 1619 struct xhci_virt_ep *virt_ep, 1620 struct xhci_tt_bw_info *tt_info); 1621 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1622 struct xhci_virt_device *virt_dev, 1623 int old_active_eps); 1624 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1625 void xhci_update_bw_info(struct xhci_hcd *xhci, 1626 struct xhci_container_ctx *in_ctx, 1627 struct xhci_input_control_ctx *ctrl_ctx, 1628 struct xhci_virt_device *virt_dev); 1629 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1630 struct xhci_container_ctx *in_ctx, 1631 struct xhci_container_ctx *out_ctx, 1632 unsigned int ep_index); 1633 void xhci_slot_copy(struct xhci_hcd *xhci, 1634 struct xhci_container_ctx *in_ctx, 1635 struct xhci_container_ctx *out_ctx); 1636 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1637 struct usb_device *udev, struct usb_host_endpoint *ep, 1638 gfp_t mem_flags); 1639 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1640 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1641 unsigned int num_trbs, gfp_t flags); 1642 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1643 struct xhci_virt_device *virt_dev, 1644 unsigned int ep_index); 1645 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1646 unsigned int num_stream_ctxs, 1647 unsigned int num_streams, gfp_t flags); 1648 void xhci_free_stream_info(struct xhci_hcd *xhci, 1649 struct xhci_stream_info *stream_info); 1650 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1651 struct xhci_ep_ctx *ep_ctx, 1652 struct xhci_stream_info *stream_info); 1653 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1654 struct xhci_ep_ctx *ep_ctx, 1655 struct xhci_virt_ep *ep); 1656 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1657 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1658 struct xhci_ring *xhci_dma_to_transfer_ring( 1659 struct xhci_virt_ep *ep, 1660 u64 address); 1661 struct xhci_ring *xhci_stream_id_to_ring( 1662 struct xhci_virt_device *dev, 1663 unsigned int ep_index, 1664 unsigned int stream_id); 1665 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1666 bool allocate_in_ctx, bool allocate_completion, 1667 gfp_t mem_flags); 1668 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1669 void xhci_free_command(struct xhci_hcd *xhci, 1670 struct xhci_command *command); 1671 1672 #ifdef CONFIG_PCI 1673 /* xHCI PCI glue */ 1674 int xhci_register_pci(void); 1675 void xhci_unregister_pci(void); 1676 #else 1677 static inline int xhci_register_pci(void) { return 0; } 1678 static inline void xhci_unregister_pci(void) {} 1679 #endif 1680 1681 #if defined(CONFIG_USB_XHCI_PLATFORM) \ 1682 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE) 1683 int xhci_register_plat(void); 1684 void xhci_unregister_plat(void); 1685 #else 1686 static inline int xhci_register_plat(void) 1687 { return 0; } 1688 static inline void xhci_unregister_plat(void) 1689 { } 1690 #endif 1691 1692 /* xHCI host controller glue */ 1693 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1694 void xhci_quiesce(struct xhci_hcd *xhci); 1695 int xhci_halt(struct xhci_hcd *xhci); 1696 int xhci_reset(struct xhci_hcd *xhci); 1697 int xhci_init(struct usb_hcd *hcd); 1698 int xhci_run(struct usb_hcd *hcd); 1699 void xhci_stop(struct usb_hcd *hcd); 1700 void xhci_shutdown(struct usb_hcd *hcd); 1701 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1702 1703 #ifdef CONFIG_PM 1704 int xhci_suspend(struct xhci_hcd *xhci); 1705 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1706 #else 1707 #define xhci_suspend NULL 1708 #define xhci_resume NULL 1709 #endif 1710 1711 int xhci_get_frame(struct usb_hcd *hcd); 1712 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1713 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1714 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1715 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1716 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1717 struct xhci_virt_device *virt_dev, 1718 struct usb_device *hdev, 1719 struct usb_tt *tt, gfp_t mem_flags); 1720 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1721 struct usb_host_endpoint **eps, unsigned int num_eps, 1722 unsigned int num_streams, gfp_t mem_flags); 1723 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1724 struct usb_host_endpoint **eps, unsigned int num_eps, 1725 gfp_t mem_flags); 1726 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1727 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1728 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1729 struct usb_device *udev, int enable); 1730 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1731 struct usb_tt *tt, gfp_t mem_flags); 1732 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1733 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1734 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1735 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1736 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1737 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1738 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1739 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1740 1741 /* xHCI ring, segment, TRB, and TD functions */ 1742 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1743 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1744 union xhci_trb *start_trb, union xhci_trb *end_trb, 1745 dma_addr_t suspect_dma); 1746 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1747 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1748 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1749 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1750 u32 slot_id); 1751 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1752 u32 field1, u32 field2, u32 field3, u32 field4); 1753 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1754 unsigned int ep_index, int suspend); 1755 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1756 int slot_id, unsigned int ep_index); 1757 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1758 int slot_id, unsigned int ep_index); 1759 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1760 int slot_id, unsigned int ep_index); 1761 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1762 struct urb *urb, int slot_id, unsigned int ep_index); 1763 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1764 u32 slot_id, bool command_must_succeed); 1765 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1766 u32 slot_id, bool command_must_succeed); 1767 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1768 unsigned int ep_index); 1769 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1770 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1771 unsigned int slot_id, unsigned int ep_index, 1772 unsigned int stream_id, struct xhci_td *cur_td, 1773 struct xhci_dequeue_state *state); 1774 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1775 unsigned int slot_id, unsigned int ep_index, 1776 unsigned int stream_id, 1777 struct xhci_dequeue_state *deq_state); 1778 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1779 struct usb_device *udev, unsigned int ep_index); 1780 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1781 unsigned int slot_id, unsigned int ep_index, 1782 struct xhci_dequeue_state *deq_state); 1783 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1784 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1785 unsigned int ep_index, unsigned int stream_id); 1786 1787 /* xHCI roothub code */ 1788 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1789 int port_id, u32 link_state); 1790 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1791 struct usb_device *udev, enum usb3_link_state state); 1792 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1793 struct usb_device *udev, enum usb3_link_state state); 1794 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1795 int port_id, u32 port_bit); 1796 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1797 char *buf, u16 wLength); 1798 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1799 1800 #ifdef CONFIG_PM 1801 int xhci_bus_suspend(struct usb_hcd *hcd); 1802 int xhci_bus_resume(struct usb_hcd *hcd); 1803 #else 1804 #define xhci_bus_suspend NULL 1805 #define xhci_bus_resume NULL 1806 #endif /* CONFIG_PM */ 1807 1808 u32 xhci_port_state_to_neutral(u32 state); 1809 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1810 u16 port); 1811 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1812 1813 /* xHCI contexts */ 1814 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1815 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1816 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1817 1818 #endif /* __LINUX_XHCI_HCD_H */ 1819