1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 29 #include "../core/hcd.h" 30 /* Code sharing between pci-quirks and xhci hcd */ 31 #include "xhci-ext-caps.h" 32 33 /* xHCI PCI Configuration Registers */ 34 #define XHCI_SBRN_OFFSET (0x60) 35 36 /* Max number of USB devices for any host controller - limit in section 6.1 */ 37 #define MAX_HC_SLOTS 256 38 /* Section 5.3.3 - MaxPorts */ 39 #define MAX_HC_PORTS 127 40 41 /* 42 * xHCI register interface. 43 * This corresponds to the eXtensible Host Controller Interface (xHCI) 44 * Revision 0.95 specification 45 * 46 * Registers should always be accessed with double word or quad word accesses. 47 * 48 * Some xHCI implementations may support 64-bit address pointers. Registers 49 * with 64-bit address pointers should be written to with dword accesses by 50 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 51 * xHCI implementations that do not support 64-bit address pointers will ignore 52 * the high dword, and write order is irrelevant. 53 */ 54 55 /** 56 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 57 * @hc_capbase: length of the capabilities register and HC version number 58 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 59 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 60 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 61 * @hcc_params: HCCPARAMS - Capability Parameters 62 * @db_off: DBOFF - Doorbell array offset 63 * @run_regs_off: RTSOFF - Runtime register space offset 64 */ 65 struct xhci_cap_regs { 66 u32 hc_capbase; 67 u32 hcs_params1; 68 u32 hcs_params2; 69 u32 hcs_params3; 70 u32 hcc_params; 71 u32 db_off; 72 u32 run_regs_off; 73 /* Reserved up to (CAPLENGTH - 0x1C) */ 74 }; 75 76 /* hc_capbase bitmasks */ 77 /* bits 7:0 - how long is the Capabilities register */ 78 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 79 /* bits 31:16 */ 80 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 81 82 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 83 /* bits 0:7, Max Device Slots */ 84 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 85 #define HCS_SLOTS_MASK 0xff 86 /* bits 8:18, Max Interrupters */ 87 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 88 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 89 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 90 91 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 92 /* bits 0:3, frames or uframes that SW needs to queue transactions 93 * ahead of the HW to meet periodic deadlines */ 94 #define HCS_IST(p) (((p) >> 0) & 0xf) 95 /* bits 4:7, max number of Event Ring segments */ 96 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 97 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 98 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 126 #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1)) 127 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 128 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 129 130 /* db_off bitmask - bits 0:1 reserved */ 131 #define DBOFF_MASK (~0x3) 132 133 /* run_regs_off bitmask - bits 0:4 reserved */ 134 #define RTSOFF_MASK (~0x1f) 135 136 137 /* Number of registers per port */ 138 #define NUM_PORT_REGS 4 139 140 /** 141 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 142 * @command: USBCMD - xHC command register 143 * @status: USBSTS - xHC status register 144 * @page_size: This indicates the page size that the host controller 145 * supports. If bit n is set, the HC supports a page size 146 * of 2^(n+12), up to a 128MB page size. 147 * 4K is the minimum page size. 148 * @cmd_ring: CRP - 64-bit Command Ring Pointer 149 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 150 * @config_reg: CONFIG - Configure Register 151 * @port_status_base: PORTSCn - base address for Port Status and Control 152 * Each port has a Port Status and Control register, 153 * followed by a Port Power Management Status and Control 154 * register, a Port Link Info register, and a reserved 155 * register. 156 * @port_power_base: PORTPMSCn - base address for 157 * Port Power Management Status and Control 158 * @port_link_base: PORTLIn - base address for Port Link Info (current 159 * Link PM state and control) for USB 2.1 and USB 3.0 160 * devices. 161 */ 162 struct xhci_op_regs { 163 u32 command; 164 u32 status; 165 u32 page_size; 166 u32 reserved1; 167 u32 reserved2; 168 u32 dev_notification; 169 u32 cmd_ring[2]; 170 /* rsvd: offset 0x20-2F */ 171 u32 reserved3[4]; 172 u32 dcbaa_ptr[2]; 173 u32 config_reg; 174 /* rsvd: offset 0x3C-3FF */ 175 u32 reserved4[241]; 176 /* port 1 registers, which serve as a base address for other ports */ 177 u32 port_status_base; 178 u32 port_power_base; 179 u32 port_link_base; 180 u32 reserved5; 181 /* registers for ports 2-255 */ 182 u32 reserved6[NUM_PORT_REGS*254]; 183 }; 184 185 /* USBCMD - USB command - command bitmasks */ 186 /* start/stop HC execution - do not write unless HC is halted*/ 187 #define CMD_RUN XHCI_CMD_RUN 188 /* Reset HC - resets internal HC state machine and all registers (except 189 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 190 * The xHCI driver must reinitialize the xHC after setting this bit. 191 */ 192 #define CMD_RESET (1 << 1) 193 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 194 #define CMD_EIE XHCI_CMD_EIE 195 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 196 #define CMD_HSEIE XHCI_CMD_HSEIE 197 /* bits 4:6 are reserved (and should be preserved on writes). */ 198 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 199 #define CMD_LRESET (1 << 7) 200 /* FIXME: ignoring host controller save/restore state for now. */ 201 #define CMD_CSS (1 << 8) 202 #define CMD_CRS (1 << 9) 203 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 204 #define CMD_EWE XHCI_CMD_EWE 205 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 206 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 207 * '0' means the xHC can power it off if all ports are in the disconnect, 208 * disabled, or powered-off state. 209 */ 210 #define CMD_PM_INDEX (1 << 11) 211 /* bits 12:31 are reserved (and should be preserved on writes). */ 212 213 /* USBSTS - USB status - status bitmasks */ 214 /* HC not running - set to 1 when run/stop bit is cleared. */ 215 #define STS_HALT XHCI_STS_HALT 216 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 217 #define STS_FATAL (1 << 2) 218 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 219 #define STS_EINT (1 << 3) 220 /* port change detect */ 221 #define STS_PORT (1 << 4) 222 /* bits 5:7 reserved and zeroed */ 223 /* save state status - '1' means xHC is saving state */ 224 #define STS_SAVE (1 << 8) 225 /* restore state status - '1' means xHC is restoring state */ 226 #define STS_RESTORE (1 << 9) 227 /* true: save or restore error */ 228 #define STS_SRE (1 << 10) 229 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 230 #define STS_CNR XHCI_STS_CNR 231 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 232 #define STS_HCE (1 << 12) 233 /* bits 13:31 reserved and should be preserved */ 234 235 /* 236 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 237 * Generate a device notification event when the HC sees a transaction with a 238 * notification type that matches a bit set in this bit field. 239 */ 240 #define DEV_NOTE_MASK (0xffff) 241 #define ENABLE_DEV_NOTE(x) (1 << x) 242 /* Most of the device notification types should only be used for debug. 243 * SW does need to pay attention to function wake notifications. 244 */ 245 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 246 247 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 248 /* bit 0 is the command ring cycle state */ 249 /* stop ring operation after completion of the currently executing command */ 250 #define CMD_RING_PAUSE (1 << 1) 251 /* stop ring immediately - abort the currently executing command */ 252 #define CMD_RING_ABORT (1 << 2) 253 /* true: command ring is running */ 254 #define CMD_RING_RUNNING (1 << 3) 255 /* bits 4:5 reserved and should be preserved */ 256 /* Command Ring pointer - bit mask for the lower 32 bits. */ 257 #define CMD_RING_ADDR_MASK (0xffffffc0) 258 259 /* CONFIG - Configure Register - config_reg bitmasks */ 260 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 261 #define MAX_DEVS(p) ((p) & 0xff) 262 /* bits 8:31 - reserved and should be preserved */ 263 264 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 265 /* true: device connected */ 266 #define PORT_CONNECT (1 << 0) 267 /* true: port enabled */ 268 #define PORT_PE (1 << 1) 269 /* bit 2 reserved and zeroed */ 270 /* true: port has an over-current condition */ 271 #define PORT_OC (1 << 3) 272 /* true: port reset signaling asserted */ 273 #define PORT_RESET (1 << 4) 274 /* Port Link State - bits 5:8 275 * A read gives the current link PM state of the port, 276 * a write with Link State Write Strobe set sets the link state. 277 */ 278 /* true: port has power (see HCC_PPC) */ 279 #define PORT_POWER (1 << 9) 280 /* bits 10:13 indicate device speed: 281 * 0 - undefined speed - port hasn't be initialized by a reset yet 282 * 1 - full speed 283 * 2 - low speed 284 * 3 - high speed 285 * 4 - super speed 286 * 5-15 reserved 287 */ 288 #define DEV_SPEED_MASK (0xf << 10) 289 #define XDEV_FS (0x1 << 10) 290 #define XDEV_LS (0x2 << 10) 291 #define XDEV_HS (0x3 << 10) 292 #define XDEV_SS (0x4 << 10) 293 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 294 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 295 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 296 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 297 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 298 /* Bits 20:23 in the Slot Context are the speed for the device */ 299 #define SLOT_SPEED_FS (XDEV_FS << 10) 300 #define SLOT_SPEED_LS (XDEV_LS << 10) 301 #define SLOT_SPEED_HS (XDEV_HS << 10) 302 #define SLOT_SPEED_SS (XDEV_SS << 10) 303 /* Port Indicator Control */ 304 #define PORT_LED_OFF (0 << 14) 305 #define PORT_LED_AMBER (1 << 14) 306 #define PORT_LED_GREEN (2 << 14) 307 #define PORT_LED_MASK (3 << 14) 308 /* Port Link State Write Strobe - set this when changing link state */ 309 #define PORT_LINK_STROBE (1 << 16) 310 /* true: connect status change */ 311 #define PORT_CSC (1 << 17) 312 /* true: port enable change */ 313 #define PORT_PEC (1 << 18) 314 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 315 * into an enabled state, and the device into the default state. A "warm" reset 316 * also resets the link, forcing the device through the link training sequence. 317 * SW can also look at the Port Reset register to see when warm reset is done. 318 */ 319 #define PORT_WRC (1 << 19) 320 /* true: over-current change */ 321 #define PORT_OCC (1 << 20) 322 /* true: reset change - 1 to 0 transition of PORT_RESET */ 323 #define PORT_RC (1 << 21) 324 /* port link status change - set on some port link state transitions: 325 * Transition Reason 326 * ------------------------------------------------------------------------------ 327 * - U3 to Resume Wakeup signaling from a device 328 * - Resume to Recovery to U0 USB 3.0 device resume 329 * - Resume to U0 USB 2.0 device resume 330 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 331 * - U3 to U0 Software resume of USB 2.0 device complete 332 * - U2 to U0 L1 resume of USB 2.1 device complete 333 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 334 * - U0 to disabled L1 entry error with USB 2.1 device 335 * - Any state to inactive Error on USB 3.0 port 336 */ 337 #define PORT_PLC (1 << 22) 338 /* port configure error change - port failed to configure its link partner */ 339 #define PORT_CEC (1 << 23) 340 /* bit 24 reserved */ 341 /* wake on connect (enable) */ 342 #define PORT_WKCONN_E (1 << 25) 343 /* wake on disconnect (enable) */ 344 #define PORT_WKDISC_E (1 << 26) 345 /* wake on over-current (enable) */ 346 #define PORT_WKOC_E (1 << 27) 347 /* bits 28:29 reserved */ 348 /* true: device is removable - for USB 3.0 roothub emulation */ 349 #define PORT_DEV_REMOVE (1 << 30) 350 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 351 #define PORT_WR (1 << 31) 352 353 /* Port Power Management Status and Control - port_power_base bitmasks */ 354 /* Inactivity timer value for transitions into U1, in microseconds. 355 * Timeout can be up to 127us. 0xFF means an infinite timeout. 356 */ 357 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 358 /* Inactivity timer value for transitions into U2 */ 359 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 360 /* Bits 24:31 for port testing */ 361 362 363 /** 364 * struct xhci_intr_reg - Interrupt Register Set 365 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 366 * interrupts and check for pending interrupts. 367 * @irq_control: IMOD - Interrupt Moderation Register. 368 * Used to throttle interrupts. 369 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 370 * @erst_base: ERST base address. 371 * @erst_dequeue: Event ring dequeue pointer. 372 * 373 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 374 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 375 * multiple segments of the same size. The HC places events on the ring and 376 * "updates the Cycle bit in the TRBs to indicate to software the current 377 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 378 * updates the dequeue pointer. 379 */ 380 struct xhci_intr_reg { 381 u32 irq_pending; 382 u32 irq_control; 383 u32 erst_size; 384 u32 rsvd; 385 u32 erst_base[2]; 386 u32 erst_dequeue[2]; 387 }; 388 389 /* irq_pending bitmasks */ 390 #define ER_IRQ_PENDING(p) ((p) & 0x1) 391 /* bits 2:31 need to be preserved */ 392 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 393 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 394 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 395 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 396 397 /* irq_control bitmasks */ 398 /* Minimum interval between interrupts (in 250ns intervals). The interval 399 * between interrupts will be longer if there are no events on the event ring. 400 * Default is 4000 (1 ms). 401 */ 402 #define ER_IRQ_INTERVAL_MASK (0xffff) 403 /* Counter used to count down the time to the next interrupt - HW use only */ 404 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 405 406 /* erst_size bitmasks */ 407 /* Preserve bits 16:31 of erst_size */ 408 #define ERST_SIZE_MASK (0xffff << 16) 409 410 /* erst_dequeue bitmasks */ 411 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 412 * where the current dequeue pointer lies. This is an optional HW hint. 413 */ 414 #define ERST_DESI_MASK (0x7) 415 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 416 * a work queue (or delayed service routine)? 417 */ 418 #define ERST_EHB (1 << 3) 419 #define ERST_PTR_MASK (0xf) 420 421 /** 422 * struct xhci_run_regs 423 * @microframe_index: 424 * MFINDEX - current microframe number 425 * 426 * Section 5.5 Host Controller Runtime Registers: 427 * "Software should read and write these registers using only Dword (32 bit) 428 * or larger accesses" 429 */ 430 struct xhci_run_regs { 431 u32 microframe_index; 432 u32 rsvd[7]; 433 struct xhci_intr_reg ir_set[128]; 434 }; 435 436 /** 437 * struct doorbell_array 438 * 439 * Section 5.6 440 */ 441 struct xhci_doorbell_array { 442 u32 doorbell[256]; 443 }; 444 445 #define DB_TARGET_MASK 0xFFFFFF00 446 #define DB_STREAM_ID_MASK 0x0000FFFF 447 #define DB_TARGET_HOST 0x0 448 #define DB_STREAM_ID_HOST 0x0 449 #define DB_MASK (0xff << 8) 450 451 /* Endpoint Target - bits 0:7 */ 452 #define EPI_TO_DB(p) (((p) + 1) & 0xff) 453 454 455 /** 456 * struct xhci_slot_ctx 457 * @dev_info: Route string, device speed, hub info, and last valid endpoint 458 * @dev_info2: Max exit latency for device number, root hub port number 459 * @tt_info: tt_info is used to construct split transaction tokens 460 * @dev_state: slot state and device address 461 * 462 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 463 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 464 * reserved at the end of the slot context for HC internal use. 465 */ 466 struct xhci_slot_ctx { 467 u32 dev_info; 468 u32 dev_info2; 469 u32 tt_info; 470 u32 dev_state; 471 /* offset 0x10 to 0x1f reserved for HC internal use */ 472 u32 reserved[4]; 473 }; 474 475 /* dev_info bitmasks */ 476 /* Route String - 0:19 */ 477 #define ROUTE_STRING_MASK (0xfffff) 478 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 479 #define DEV_SPEED (0xf << 20) 480 /* bit 24 reserved */ 481 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 482 #define DEV_MTT (0x1 << 25) 483 /* Set if the device is a hub - bit 26 */ 484 #define DEV_HUB (0x1 << 26) 485 /* Index of the last valid endpoint context in this device context - 27:31 */ 486 #define LAST_CTX_MASK (0x1f << 27) 487 #define LAST_CTX(p) ((p) << 27) 488 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 489 #define SLOT_FLAG (1 << 0) 490 #define EP0_FLAG (1 << 1) 491 492 /* dev_info2 bitmasks */ 493 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 494 #define MAX_EXIT (0xffff) 495 /* Root hub port number that is needed to access the USB device */ 496 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 497 498 /* tt_info bitmasks */ 499 /* 500 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 501 * The Slot ID of the hub that isolates the high speed signaling from 502 * this low or full-speed device. '0' if attached to root hub port. 503 */ 504 #define TT_SLOT (0xff) 505 /* 506 * The number of the downstream facing port of the high-speed hub 507 * '0' if the device is not low or full speed. 508 */ 509 #define TT_PORT (0xff << 8) 510 511 /* dev_state bitmasks */ 512 /* USB device address - assigned by the HC */ 513 #define DEV_ADDR_MASK (0xff) 514 /* bits 8:26 reserved */ 515 /* Slot state */ 516 #define SLOT_STATE (0x1f << 27) 517 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 518 519 520 /** 521 * struct xhci_ep_ctx 522 * @ep_info: endpoint state, streams, mult, and interval information. 523 * @ep_info2: information on endpoint type, max packet size, max burst size, 524 * error count, and whether the HC will force an event for all 525 * transactions. 526 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 527 * defines one stream, this points to the endpoint transfer ring. 528 * Otherwise, it points to a stream context array, which has a 529 * ring pointer for each flow. 530 * @tx_info: 531 * Average TRB lengths for the endpoint ring and 532 * max payload within an Endpoint Service Interval Time (ESIT). 533 * 534 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 535 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 536 * reserved at the end of the endpoint context for HC internal use. 537 */ 538 struct xhci_ep_ctx { 539 u32 ep_info; 540 u32 ep_info2; 541 u32 deq[2]; 542 u32 tx_info; 543 /* offset 0x14 - 0x1f reserved for HC internal use */ 544 u32 reserved[3]; 545 }; 546 547 /* ep_info bitmasks */ 548 /* 549 * Endpoint State - bits 0:2 550 * 0 - disabled 551 * 1 - running 552 * 2 - halted due to halt condition - ok to manipulate endpoint ring 553 * 3 - stopped 554 * 4 - TRB error 555 * 5-7 - reserved 556 */ 557 #define EP_STATE_MASK (0xf) 558 #define EP_STATE_DISABLED 0 559 #define EP_STATE_RUNNING 1 560 #define EP_STATE_HALTED 2 561 #define EP_STATE_STOPPED 3 562 #define EP_STATE_ERROR 4 563 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 564 #define EP_MULT(p) ((p & 0x3) << 8) 565 /* bits 10:14 are Max Primary Streams */ 566 /* bit 15 is Linear Stream Array */ 567 /* Interval - period between requests to an endpoint - 125u increments. */ 568 #define EP_INTERVAL(p) ((p & 0xff) << 16) 569 570 /* ep_info2 bitmasks */ 571 /* 572 * Force Event - generate transfer events for all TRBs for this endpoint 573 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 574 */ 575 #define FORCE_EVENT (0x1) 576 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 577 #define EP_TYPE(p) ((p) << 3) 578 #define ISOC_OUT_EP 1 579 #define BULK_OUT_EP 2 580 #define INT_OUT_EP 3 581 #define CTRL_EP 4 582 #define ISOC_IN_EP 5 583 #define BULK_IN_EP 6 584 #define INT_IN_EP 7 585 /* bit 6 reserved */ 586 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 587 #define MAX_BURST(p) (((p)&0xff) << 8) 588 #define MAX_PACKET(p) (((p)&0xffff) << 16) 589 590 591 /** 592 * struct xhci_device_control 593 * Input/Output context; see section 6.2.5. 594 * 595 * @drop_context: set the bit of the endpoint context you want to disable 596 * @add_context: set the bit of the endpoint context you want to enable 597 */ 598 struct xhci_device_control { 599 u32 drop_flags; 600 u32 add_flags; 601 u32 rsvd[6]; 602 struct xhci_slot_ctx slot; 603 struct xhci_ep_ctx ep[31]; 604 }; 605 606 /* drop context bitmasks */ 607 #define DROP_EP(x) (0x1 << x) 608 /* add context bitmasks */ 609 #define ADD_EP(x) (0x1 << x) 610 611 612 struct xhci_virt_device { 613 /* 614 * Commands to the hardware are passed an "input context" that 615 * tells the hardware what to change in its data structures. 616 * The hardware will return changes in an "output context" that 617 * software must allocate for the hardware. We need to keep 618 * track of input and output contexts separately because 619 * these commands might fail and we don't trust the hardware. 620 */ 621 struct xhci_device_control *out_ctx; 622 dma_addr_t out_ctx_dma; 623 /* Used for addressing devices and configuration changes */ 624 struct xhci_device_control *in_ctx; 625 dma_addr_t in_ctx_dma; 626 /* FIXME when stream support is added */ 627 struct xhci_ring *ep_rings[31]; 628 /* Temporary storage in case the configure endpoint command fails and we 629 * have to restore the device state to the previous state 630 */ 631 struct xhci_ring *new_ep_rings[31]; 632 struct completion cmd_completion; 633 /* Status of the last command issued for this device */ 634 u32 cmd_status; 635 }; 636 637 638 /** 639 * struct xhci_device_context_array 640 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 641 */ 642 struct xhci_device_context_array { 643 /* 64-bit device addresses; we only write 32-bit addresses */ 644 u32 dev_context_ptrs[2*MAX_HC_SLOTS]; 645 /* private xHCD pointers */ 646 dma_addr_t dma; 647 }; 648 /* TODO: write function to set the 64-bit device DMA address */ 649 /* 650 * TODO: change this to be dynamically sized at HC mem init time since the HC 651 * might not be able to handle the maximum number of devices possible. 652 */ 653 654 655 struct xhci_stream_ctx { 656 /* 64-bit stream ring address, cycle state, and stream type */ 657 u32 stream_ring[2]; 658 /* offset 0x14 - 0x1f reserved for HC internal use */ 659 u32 reserved[2]; 660 }; 661 662 663 struct xhci_transfer_event { 664 /* 64-bit buffer address, or immediate data */ 665 u32 buffer[2]; 666 u32 transfer_len; 667 /* This field is interpreted differently based on the type of TRB */ 668 u32 flags; 669 }; 670 671 /** Transfer Event bit fields **/ 672 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 673 674 /* Completion Code - only applicable for some types of TRBs */ 675 #define COMP_CODE_MASK (0xff << 24) 676 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 677 #define COMP_SUCCESS 1 678 /* Data Buffer Error */ 679 #define COMP_DB_ERR 2 680 /* Babble Detected Error */ 681 #define COMP_BABBLE 3 682 /* USB Transaction Error */ 683 #define COMP_TX_ERR 4 684 /* TRB Error - some TRB field is invalid */ 685 #define COMP_TRB_ERR 5 686 /* Stall Error - USB device is stalled */ 687 #define COMP_STALL 6 688 /* Resource Error - HC doesn't have memory for that device configuration */ 689 #define COMP_ENOMEM 7 690 /* Bandwidth Error - not enough room in schedule for this dev config */ 691 #define COMP_BW_ERR 8 692 /* No Slots Available Error - HC ran out of device slots */ 693 #define COMP_ENOSLOTS 9 694 /* Invalid Stream Type Error */ 695 #define COMP_STREAM_ERR 10 696 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 697 #define COMP_EBADSLT 11 698 /* Endpoint Not Enabled Error */ 699 #define COMP_EBADEP 12 700 /* Short Packet */ 701 #define COMP_SHORT_TX 13 702 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 703 #define COMP_UNDERRUN 14 704 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 705 #define COMP_OVERRUN 15 706 /* Virtual Function Event Ring Full Error */ 707 #define COMP_VF_FULL 16 708 /* Parameter Error - Context parameter is invalid */ 709 #define COMP_EINVAL 17 710 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 711 #define COMP_BW_OVER 18 712 /* Context State Error - illegal context state transition requested */ 713 #define COMP_CTX_STATE 19 714 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 715 #define COMP_PING_ERR 20 716 /* Event Ring is full */ 717 #define COMP_ER_FULL 21 718 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 719 #define COMP_MISSED_INT 23 720 /* Successfully stopped command ring */ 721 #define COMP_CMD_STOP 24 722 /* Successfully aborted current command and stopped command ring */ 723 #define COMP_CMD_ABORT 25 724 /* Stopped - transfer was terminated by a stop endpoint command */ 725 #define COMP_STOP 26 726 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ 727 #define COMP_STOP_INVAL 27 728 /* Control Abort Error - Debug Capability - control pipe aborted */ 729 #define COMP_DBG_ABORT 28 730 /* TRB type 29 and 30 reserved */ 731 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 732 #define COMP_BUFF_OVER 31 733 /* Event Lost Error - xHC has an "internal event overrun condition" */ 734 #define COMP_ISSUES 32 735 /* Undefined Error - reported when other error codes don't apply */ 736 #define COMP_UNKNOWN 33 737 /* Invalid Stream ID Error */ 738 #define COMP_STRID_ERR 34 739 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 740 /* FIXME - check for this */ 741 #define COMP_2ND_BW_ERR 35 742 /* Split Transaction Error */ 743 #define COMP_SPLIT_ERR 36 744 745 struct xhci_link_trb { 746 /* 64-bit segment pointer*/ 747 u32 segment_ptr[2]; 748 u32 intr_target; 749 u32 control; 750 }; 751 752 /* control bitfields */ 753 #define LINK_TOGGLE (0x1<<1) 754 755 /* Command completion event TRB */ 756 struct xhci_event_cmd { 757 /* Pointer to command TRB, or the value passed by the event data trb */ 758 u32 cmd_trb[2]; 759 u32 status; 760 u32 flags; 761 }; 762 763 /* flags bitmasks */ 764 /* bits 16:23 are the virtual function ID */ 765 /* bits 24:31 are the slot ID */ 766 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 767 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 768 769 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 770 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 771 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 772 773 774 /* Port Status Change Event TRB fields */ 775 /* Port ID - bits 31:24 */ 776 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 777 778 /* Normal TRB fields */ 779 /* transfer_len bitmasks - bits 0:16 */ 780 #define TRB_LEN(p) ((p) & 0x1ffff) 781 /* TD size - number of bytes remaining in the TD (including this TRB): 782 * bits 17 - 21. Shift the number of bytes by 10. */ 783 #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17) 784 /* Interrupter Target - which MSI-X vector to target the completion event at */ 785 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 786 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 787 788 /* Cycle bit - indicates TRB ownership by HC or HCD */ 789 #define TRB_CYCLE (1<<0) 790 /* 791 * Force next event data TRB to be evaluated before task switch. 792 * Used to pass OS data back after a TD completes. 793 */ 794 #define TRB_ENT (1<<1) 795 /* Interrupt on short packet */ 796 #define TRB_ISP (1<<2) 797 /* Set PCIe no snoop attribute */ 798 #define TRB_NO_SNOOP (1<<3) 799 /* Chain multiple TRBs into a TD */ 800 #define TRB_CHAIN (1<<4) 801 /* Interrupt on completion */ 802 #define TRB_IOC (1<<5) 803 /* The buffer pointer contains immediate data */ 804 #define TRB_IDT (1<<6) 805 806 807 /* Control transfer TRB specific fields */ 808 #define TRB_DIR_IN (1<<16) 809 810 struct xhci_generic_trb { 811 u32 field[4]; 812 }; 813 814 union xhci_trb { 815 struct xhci_link_trb link; 816 struct xhci_transfer_event trans_event; 817 struct xhci_event_cmd event_cmd; 818 struct xhci_generic_trb generic; 819 }; 820 821 /* TRB bit mask */ 822 #define TRB_TYPE_BITMASK (0xfc00) 823 #define TRB_TYPE(p) ((p) << 10) 824 /* TRB type IDs */ 825 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 826 #define TRB_NORMAL 1 827 /* setup stage for control transfers */ 828 #define TRB_SETUP 2 829 /* data stage for control transfers */ 830 #define TRB_DATA 3 831 /* status stage for control transfers */ 832 #define TRB_STATUS 4 833 /* isoc transfers */ 834 #define TRB_ISOC 5 835 /* TRB for linking ring segments */ 836 #define TRB_LINK 6 837 #define TRB_EVENT_DATA 7 838 /* Transfer Ring No-op (not for the command ring) */ 839 #define TRB_TR_NOOP 8 840 /* Command TRBs */ 841 /* Enable Slot Command */ 842 #define TRB_ENABLE_SLOT 9 843 /* Disable Slot Command */ 844 #define TRB_DISABLE_SLOT 10 845 /* Address Device Command */ 846 #define TRB_ADDR_DEV 11 847 /* Configure Endpoint Command */ 848 #define TRB_CONFIG_EP 12 849 /* Evaluate Context Command */ 850 #define TRB_EVAL_CONTEXT 13 851 /* Reset Transfer Ring Command */ 852 #define TRB_RESET_RING 14 853 /* Stop Transfer Ring Command */ 854 #define TRB_STOP_RING 15 855 /* Set Transfer Ring Dequeue Pointer Command */ 856 #define TRB_SET_DEQ 16 857 /* Reset Device Command */ 858 #define TRB_RESET_DEV 17 859 /* Force Event Command (opt) */ 860 #define TRB_FORCE_EVENT 18 861 /* Negotiate Bandwidth Command (opt) */ 862 #define TRB_NEG_BANDWIDTH 19 863 /* Set Latency Tolerance Value Command (opt) */ 864 #define TRB_SET_LT 20 865 /* Get port bandwidth Command */ 866 #define TRB_GET_BW 21 867 /* Force Header Command - generate a transaction or link management packet */ 868 #define TRB_FORCE_HEADER 22 869 /* No-op Command - not for transfer rings */ 870 #define TRB_CMD_NOOP 23 871 /* TRB IDs 24-31 reserved */ 872 /* Event TRBS */ 873 /* Transfer Event */ 874 #define TRB_TRANSFER 32 875 /* Command Completion Event */ 876 #define TRB_COMPLETION 33 877 /* Port Status Change Event */ 878 #define TRB_PORT_STATUS 34 879 /* Bandwidth Request Event (opt) */ 880 #define TRB_BANDWIDTH_EVENT 35 881 /* Doorbell Event (opt) */ 882 #define TRB_DOORBELL 36 883 /* Host Controller Event */ 884 #define TRB_HC_EVENT 37 885 /* Device Notification Event - device sent function wake notification */ 886 #define TRB_DEV_NOTE 38 887 /* MFINDEX Wrap Event - microframe counter wrapped */ 888 #define TRB_MFINDEX_WRAP 39 889 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 890 891 /* 892 * TRBS_PER_SEGMENT must be a multiple of 4, 893 * since the command ring is 64-byte aligned. 894 * It must also be greater than 16. 895 */ 896 #define TRBS_PER_SEGMENT 64 897 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 898 /* TRB buffer pointers can't cross 64KB boundaries */ 899 #define TRB_MAX_BUFF_SHIFT 16 900 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 901 902 struct xhci_segment { 903 union xhci_trb *trbs; 904 /* private to HCD */ 905 struct xhci_segment *next; 906 dma_addr_t dma; 907 }; 908 909 struct xhci_td { 910 struct list_head td_list; 911 struct list_head cancelled_td_list; 912 struct urb *urb; 913 struct xhci_segment *start_seg; 914 union xhci_trb *first_trb; 915 union xhci_trb *last_trb; 916 }; 917 918 struct xhci_ring { 919 struct xhci_segment *first_seg; 920 union xhci_trb *enqueue; 921 struct xhci_segment *enq_seg; 922 unsigned int enq_updates; 923 union xhci_trb *dequeue; 924 struct xhci_segment *deq_seg; 925 unsigned int deq_updates; 926 struct list_head td_list; 927 /* ---- Related to URB cancellation ---- */ 928 struct list_head cancelled_td_list; 929 unsigned int cancels_pending; 930 unsigned int state; 931 #define SET_DEQ_PENDING (1 << 0) 932 /* The TRB that was last reported in a stopped endpoint ring */ 933 union xhci_trb *stopped_trb; 934 struct xhci_td *stopped_td; 935 /* 936 * Write the cycle state into the TRB cycle field to give ownership of 937 * the TRB to the host controller (if we are the producer), or to check 938 * if we own the TRB (if we are the consumer). See section 4.9.1. 939 */ 940 u32 cycle_state; 941 }; 942 943 struct xhci_erst_entry { 944 /* 64-bit event ring segment address */ 945 u32 seg_addr[2]; 946 u32 seg_size; 947 /* Set to zero */ 948 u32 rsvd; 949 }; 950 951 struct xhci_erst { 952 struct xhci_erst_entry *entries; 953 unsigned int num_entries; 954 /* xhci->event_ring keeps track of segment dma addresses */ 955 dma_addr_t erst_dma_addr; 956 /* Num entries the ERST can contain */ 957 unsigned int erst_size; 958 }; 959 960 /* 961 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 962 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 963 * meaning 64 ring segments. 964 * Initial allocated size of the ERST, in number of entries */ 965 #define ERST_NUM_SEGS 1 966 /* Initial allocated size of the ERST, in number of entries */ 967 #define ERST_SIZE 64 968 /* Initial number of event segment rings allocated */ 969 #define ERST_ENTRIES 1 970 /* Poll every 60 seconds */ 971 #define POLL_TIMEOUT 60 972 /* XXX: Make these module parameters */ 973 974 975 /* There is one ehci_hci structure per controller */ 976 struct xhci_hcd { 977 /* glue to PCI and HCD framework */ 978 struct xhci_cap_regs __iomem *cap_regs; 979 struct xhci_op_regs __iomem *op_regs; 980 struct xhci_run_regs __iomem *run_regs; 981 struct xhci_doorbell_array __iomem *dba; 982 /* Our HCD's current interrupter register set */ 983 struct xhci_intr_reg __iomem *ir_set; 984 985 /* Cached register copies of read-only HC data */ 986 __u32 hcs_params1; 987 __u32 hcs_params2; 988 __u32 hcs_params3; 989 __u32 hcc_params; 990 991 spinlock_t lock; 992 993 /* packed release number */ 994 u8 sbrn; 995 u16 hci_version; 996 u8 max_slots; 997 u8 max_interrupters; 998 u8 max_ports; 999 u8 isoc_threshold; 1000 int event_ring_max; 1001 int addr_64; 1002 /* 4KB min, 128MB max */ 1003 int page_size; 1004 /* Valid values are 12 to 20, inclusive */ 1005 int page_shift; 1006 /* only one MSI vector for now, but might need more later */ 1007 int msix_count; 1008 struct msix_entry *msix_entries; 1009 /* data structures */ 1010 struct xhci_device_context_array *dcbaa; 1011 struct xhci_ring *cmd_ring; 1012 struct xhci_ring *event_ring; 1013 struct xhci_erst erst; 1014 /* slot enabling and address device helpers */ 1015 struct completion addr_dev; 1016 int slot_id; 1017 /* Internal mirror of the HW's dcbaa */ 1018 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1019 1020 /* DMA pools */ 1021 struct dma_pool *device_pool; 1022 struct dma_pool *segment_pool; 1023 1024 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1025 /* Poll the rings - for debugging */ 1026 struct timer_list event_ring_timer; 1027 int zombie; 1028 #endif 1029 /* Statistics */ 1030 int noops_submitted; 1031 int noops_handled; 1032 int error_bitmask; 1033 }; 1034 1035 /* For testing purposes */ 1036 #define NUM_TEST_NOOPS 0 1037 1038 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1039 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1040 { 1041 return (struct xhci_hcd *) (hcd->hcd_priv); 1042 } 1043 1044 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1045 { 1046 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1047 } 1048 1049 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1050 #define XHCI_DEBUG 1 1051 #else 1052 #define XHCI_DEBUG 0 1053 #endif 1054 1055 #define xhci_dbg(xhci, fmt, args...) \ 1056 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1057 #define xhci_info(xhci, fmt, args...) \ 1058 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1059 #define xhci_err(xhci, fmt, args...) \ 1060 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1061 #define xhci_warn(xhci, fmt, args...) \ 1062 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1063 1064 /* TODO: copied from ehci.h - can be refactored? */ 1065 /* xHCI spec says all registers are little endian */ 1066 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1067 __u32 __iomem *regs) 1068 { 1069 return readl(regs); 1070 } 1071 static inline void xhci_writel(struct xhci_hcd *xhci, 1072 const unsigned int val, __u32 __iomem *regs) 1073 { 1074 if (!in_interrupt()) 1075 xhci_dbg(xhci, 1076 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1077 regs, val); 1078 writel(val, regs); 1079 } 1080 1081 /* xHCI debugging */ 1082 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); 1083 void xhci_print_registers(struct xhci_hcd *xhci); 1084 void xhci_dbg_regs(struct xhci_hcd *xhci); 1085 void xhci_print_run_regs(struct xhci_hcd *xhci); 1086 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1087 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1088 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1089 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1090 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1091 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1092 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1093 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_device_control *ctx, dma_addr_t dma, unsigned int last_ep); 1094 1095 /* xHCI memory managment */ 1096 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1097 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1098 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1099 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1100 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1101 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1102 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1103 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1104 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1105 struct usb_device *udev, struct usb_host_endpoint *ep, 1106 gfp_t mem_flags); 1107 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1108 1109 #ifdef CONFIG_PCI 1110 /* xHCI PCI glue */ 1111 int xhci_register_pci(void); 1112 void xhci_unregister_pci(void); 1113 #endif 1114 1115 /* xHCI host controller glue */ 1116 int xhci_halt(struct xhci_hcd *xhci); 1117 int xhci_reset(struct xhci_hcd *xhci); 1118 int xhci_init(struct usb_hcd *hcd); 1119 int xhci_run(struct usb_hcd *hcd); 1120 void xhci_stop(struct usb_hcd *hcd); 1121 void xhci_shutdown(struct usb_hcd *hcd); 1122 int xhci_get_frame(struct usb_hcd *hcd); 1123 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1124 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1125 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1126 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1127 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1128 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1129 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1130 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1131 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1132 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1133 1134 /* xHCI ring, segment, TRB, and TD functions */ 1135 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1136 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1137 void *xhci_setup_one_noop(struct xhci_hcd *xhci); 1138 void xhci_handle_event(struct xhci_hcd *xhci); 1139 void xhci_set_hc_event_deq(struct xhci_hcd *xhci); 1140 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1141 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1142 u32 slot_id); 1143 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1144 unsigned int ep_index); 1145 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1146 int slot_id, unsigned int ep_index); 1147 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1148 int slot_id, unsigned int ep_index); 1149 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1150 u32 slot_id); 1151 1152 /* xHCI roothub code */ 1153 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1154 char *buf, u16 wLength); 1155 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1156 1157 #endif /* __LINUX_XHCI_HCD_H */ 1158