1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
21
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
25
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
28
29 /* max buffer size for trace and debug messages */
30 #define XHCI_MSG_MAX 500
31
32 /* xHCI PCI Configuration Registers */
33 #define XHCI_SBRN_OFFSET (0x60)
34
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
36 #define MAX_HC_SLOTS 256
37 /* Section 5.3.3 - MaxPorts */
38 #define MAX_HC_PORTS 127
39
40 /*
41 * xHCI register interface.
42 * This corresponds to the eXtensible Host Controller Interface (xHCI)
43 * Revision 0.95 specification
44 */
45
46 /**
47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
48 * @hc_capbase: length of the capabilities register and HC version number
49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
52 * @hcc_params: HCCPARAMS - Capability Parameters
53 * @db_off: DBOFF - Doorbell array offset
54 * @run_regs_off: RTSOFF - Runtime register space offset
55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
56 */
57 struct xhci_cap_regs {
58 __le32 hc_capbase;
59 __le32 hcs_params1;
60 __le32 hcs_params2;
61 __le32 hcs_params3;
62 __le32 hcc_params;
63 __le32 db_off;
64 __le32 run_regs_off;
65 __le32 hcc_params2; /* xhci 1.1 */
66 /* Reserved up to (CAPLENGTH - 0x1C) */
67 };
68
69 /* Number of registers per port */
70 #define NUM_PORT_REGS 4
71
72 #define PORTSC 0
73 #define PORTPMSC 1
74 #define PORTLI 2
75 #define PORTHLPMC 3
76
77 /**
78 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79 * @command: USBCMD - xHC command register
80 * @status: USBSTS - xHC status register
81 * @page_size: This indicates the page size that the host controller
82 * supports. If bit n is set, the HC supports a page size
83 * of 2^(n+12), up to a 128MB page size.
84 * 4K is the minimum page size.
85 * @cmd_ring: CRP - 64-bit Command Ring Pointer
86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
87 * @config_reg: CONFIG - Configure Register
88 * @port_status_base: PORTSCn - base address for Port Status and Control
89 * Each port has a Port Status and Control register,
90 * followed by a Port Power Management Status and Control
91 * register, a Port Link Info register, and a reserved
92 * register.
93 * @port_power_base: PORTPMSCn - base address for
94 * Port Power Management Status and Control
95 * @port_link_base: PORTLIn - base address for Port Link Info (current
96 * Link PM state and control) for USB 2.1 and USB 3.0
97 * devices.
98 */
99 struct xhci_op_regs {
100 __le32 command;
101 __le32 status;
102 __le32 page_size;
103 __le32 reserved1;
104 __le32 reserved2;
105 __le32 dev_notification;
106 __le64 cmd_ring;
107 /* rsvd: offset 0x20-2F */
108 __le32 reserved3[4];
109 __le64 dcbaa_ptr;
110 __le32 config_reg;
111 /* rsvd: offset 0x3C-3FF */
112 __le32 reserved4[241];
113 /* port 1 registers, which serve as a base address for other ports */
114 __le32 port_status_base;
115 __le32 port_power_base;
116 __le32 port_link_base;
117 __le32 reserved5;
118 /* registers for ports 2-255 */
119 __le32 reserved6[NUM_PORT_REGS*254];
120 };
121
122 /* USBCMD - USB command - command bitmasks */
123 /* start/stop HC execution - do not write unless HC is halted*/
124 #define CMD_RUN XHCI_CMD_RUN
125 /* Reset HC - resets internal HC state machine and all registers (except
126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
127 * The xHCI driver must reinitialize the xHC after setting this bit.
128 */
129 #define CMD_RESET (1 << 1)
130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
131 #define CMD_EIE XHCI_CMD_EIE
132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
133 #define CMD_HSEIE XHCI_CMD_HSEIE
134 /* bits 4:6 are reserved (and should be preserved on writes). */
135 /* light reset (port status stays unchanged) - reset completed when this is 0 */
136 #define CMD_LRESET (1 << 7)
137 /* host controller save/restore state. */
138 #define CMD_CSS (1 << 8)
139 #define CMD_CRS (1 << 9)
140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
141 #define CMD_EWE XHCI_CMD_EWE
142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
144 * '0' means the xHC can power it off if all ports are in the disconnect,
145 * disabled, or powered-off state.
146 */
147 #define CMD_PM_INDEX (1 << 11)
148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
149 #define CMD_ETE (1 << 14)
150 /* bits 15:31 are reserved (and should be preserved on writes). */
151
152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
153 #define XHCI_RESET_SHORT_USEC (250 * 1000)
154
155 /* IMAN - Interrupt Management Register */
156 #define IMAN_IE (1 << 1)
157 #define IMAN_IP (1 << 0)
158
159 /* USBSTS - USB status - status bitmasks */
160 /* HC not running - set to 1 when run/stop bit is cleared. */
161 #define STS_HALT XHCI_STS_HALT
162 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
163 #define STS_FATAL (1 << 2)
164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
165 #define STS_EINT (1 << 3)
166 /* port change detect */
167 #define STS_PORT (1 << 4)
168 /* bits 5:7 reserved and zeroed */
169 /* save state status - '1' means xHC is saving state */
170 #define STS_SAVE (1 << 8)
171 /* restore state status - '1' means xHC is restoring state */
172 #define STS_RESTORE (1 << 9)
173 /* true: save or restore error */
174 #define STS_SRE (1 << 10)
175 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
176 #define STS_CNR XHCI_STS_CNR
177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
178 #define STS_HCE (1 << 12)
179 /* bits 13:31 reserved and should be preserved */
180
181 /*
182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
183 * Generate a device notification event when the HC sees a transaction with a
184 * notification type that matches a bit set in this bit field.
185 */
186 #define DEV_NOTE_MASK (0xffff)
187 #define ENABLE_DEV_NOTE(x) (1 << (x))
188 /* Most of the device notification types should only be used for debug.
189 * SW does need to pay attention to function wake notifications.
190 */
191 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
192
193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
194 /* bit 0 is the command ring cycle state */
195 /* stop ring operation after completion of the currently executing command */
196 #define CMD_RING_PAUSE (1 << 1)
197 /* stop ring immediately - abort the currently executing command */
198 #define CMD_RING_ABORT (1 << 2)
199 /* true: command ring is running */
200 #define CMD_RING_RUNNING (1 << 3)
201 /* bits 4:5 reserved and should be preserved */
202 /* Command Ring pointer - bit mask for the lower 32 bits. */
203 #define CMD_RING_RSVD_BITS (0x3f)
204
205 /* CONFIG - Configure Register - config_reg bitmasks */
206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
207 #define MAX_DEVS(p) ((p) & 0xff)
208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
209 #define CONFIG_U3E (1 << 8)
210 /* bit 9: Configuration Information Enable, xhci 1.1 */
211 #define CONFIG_CIE (1 << 9)
212 /* bits 10:31 - reserved and should be preserved */
213
214 /**
215 * struct xhci_intr_reg - Interrupt Register Set
216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
217 * interrupts and check for pending interrupts.
218 * @irq_control: IMOD - Interrupt Moderation Register.
219 * Used to throttle interrupts.
220 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
221 * @erst_base: ERST base address.
222 * @erst_dequeue: Event ring dequeue pointer.
223 *
224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
225 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
226 * multiple segments of the same size. The HC places events on the ring and
227 * "updates the Cycle bit in the TRBs to indicate to software the current
228 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
229 * updates the dequeue pointer.
230 */
231 struct xhci_intr_reg {
232 __le32 irq_pending;
233 __le32 irq_control;
234 __le32 erst_size;
235 __le32 rsvd;
236 __le64 erst_base;
237 __le64 erst_dequeue;
238 };
239
240 /* irq_pending bitmasks */
241 #define ER_IRQ_PENDING(p) ((p) & 0x1)
242 /* bits 2:31 need to be preserved */
243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
244 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
245 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
246 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
247
248 /* irq_control bitmasks */
249 /* Minimum interval between interrupts (in 250ns intervals). The interval
250 * between interrupts will be longer if there are no events on the event ring.
251 * Default is 4000 (1 ms).
252 */
253 #define ER_IRQ_INTERVAL_MASK (0xffff)
254 /* Counter used to count down the time to the next interrupt - HW use only */
255 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
256
257 /* erst_size bitmasks */
258 /* Preserve bits 16:31 of erst_size */
259 #define ERST_SIZE_MASK (0xffff << 16)
260
261 /* erst_base bitmasks */
262 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
263
264 /* erst_dequeue bitmasks */
265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
266 * where the current dequeue pointer lies. This is an optional HW hint.
267 */
268 #define ERST_DESI_MASK (0x7)
269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
270 * a work queue (or delayed service routine)?
271 */
272 #define ERST_EHB (1 << 3)
273 #define ERST_PTR_MASK (GENMASK_ULL(63, 4))
274
275 /**
276 * struct xhci_run_regs
277 * @microframe_index:
278 * MFINDEX - current microframe number
279 *
280 * Section 5.5 Host Controller Runtime Registers:
281 * "Software should read and write these registers using only Dword (32 bit)
282 * or larger accesses"
283 */
284 struct xhci_run_regs {
285 __le32 microframe_index;
286 __le32 rsvd[7];
287 struct xhci_intr_reg ir_set[128];
288 };
289
290 /**
291 * struct doorbell_array
292 *
293 * Bits 0 - 7: Endpoint target
294 * Bits 8 - 15: RsvdZ
295 * Bits 16 - 31: Stream ID
296 *
297 * Section 5.6
298 */
299 struct xhci_doorbell_array {
300 __le32 doorbell[256];
301 };
302
303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
304 #define DB_VALUE_HOST 0x00000000
305
306 #define PLT_MASK (0x03 << 6)
307 #define PLT_SYM (0x00 << 6)
308 #define PLT_ASYM_RX (0x02 << 6)
309 #define PLT_ASYM_TX (0x03 << 6)
310
311 /**
312 * struct xhci_container_ctx
313 * @type: Type of context. Used to calculated offsets to contained contexts.
314 * @size: Size of the context data
315 * @bytes: The raw context data given to HW
316 * @dma: dma address of the bytes
317 *
318 * Represents either a Device or Input context. Holds a pointer to the raw
319 * memory used for the context (bytes) and dma address of it (dma).
320 */
321 struct xhci_container_ctx {
322 unsigned type;
323 #define XHCI_CTX_TYPE_DEVICE 0x1
324 #define XHCI_CTX_TYPE_INPUT 0x2
325
326 int size;
327
328 u8 *bytes;
329 dma_addr_t dma;
330 };
331
332 /**
333 * struct xhci_slot_ctx
334 * @dev_info: Route string, device speed, hub info, and last valid endpoint
335 * @dev_info2: Max exit latency for device number, root hub port number
336 * @tt_info: tt_info is used to construct split transaction tokens
337 * @dev_state: slot state and device address
338 *
339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
341 * reserved at the end of the slot context for HC internal use.
342 */
343 struct xhci_slot_ctx {
344 __le32 dev_info;
345 __le32 dev_info2;
346 __le32 tt_info;
347 __le32 dev_state;
348 /* offset 0x10 to 0x1f reserved for HC internal use */
349 __le32 reserved[4];
350 };
351
352 /* dev_info bitmasks */
353 /* Route String - 0:19 */
354 #define ROUTE_STRING_MASK (0xfffff)
355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
356 #define DEV_SPEED (0xf << 20)
357 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
358 /* bit 24 reserved */
359 /* Is this LS/FS device connected through a HS hub? - bit 25 */
360 #define DEV_MTT (0x1 << 25)
361 /* Set if the device is a hub - bit 26 */
362 #define DEV_HUB (0x1 << 26)
363 /* Index of the last valid endpoint context in this device context - 27:31 */
364 #define LAST_CTX_MASK (0x1f << 27)
365 #define LAST_CTX(p) ((p) << 27)
366 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
367 #define SLOT_FLAG (1 << 0)
368 #define EP0_FLAG (1 << 1)
369
370 /* dev_info2 bitmasks */
371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
372 #define MAX_EXIT (0xffff)
373 /* Root hub port number that is needed to access the USB device */
374 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
375 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
376 /* Maximum number of ports under a hub device */
377 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
378 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
379
380 /* tt_info bitmasks */
381 /*
382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
383 * The Slot ID of the hub that isolates the high speed signaling from
384 * this low or full-speed device. '0' if attached to root hub port.
385 */
386 #define TT_SLOT (0xff)
387 /*
388 * The number of the downstream facing port of the high-speed hub
389 * '0' if the device is not low or full speed.
390 */
391 #define TT_PORT (0xff << 8)
392 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
393 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
394
395 /* dev_state bitmasks */
396 /* USB device address - assigned by the HC */
397 #define DEV_ADDR_MASK (0xff)
398 /* bits 8:26 reserved */
399 /* Slot state */
400 #define SLOT_STATE (0x1f << 27)
401 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
402
403 #define SLOT_STATE_DISABLED 0
404 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
405 #define SLOT_STATE_DEFAULT 1
406 #define SLOT_STATE_ADDRESSED 2
407 #define SLOT_STATE_CONFIGURED 3
408
409 /**
410 * struct xhci_ep_ctx
411 * @ep_info: endpoint state, streams, mult, and interval information.
412 * @ep_info2: information on endpoint type, max packet size, max burst size,
413 * error count, and whether the HC will force an event for all
414 * transactions.
415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
416 * defines one stream, this points to the endpoint transfer ring.
417 * Otherwise, it points to a stream context array, which has a
418 * ring pointer for each flow.
419 * @tx_info:
420 * Average TRB lengths for the endpoint ring and
421 * max payload within an Endpoint Service Interval Time (ESIT).
422 *
423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
425 * reserved at the end of the endpoint context for HC internal use.
426 */
427 struct xhci_ep_ctx {
428 __le32 ep_info;
429 __le32 ep_info2;
430 __le64 deq;
431 __le32 tx_info;
432 /* offset 0x14 - 0x1f reserved for HC internal use */
433 __le32 reserved[3];
434 };
435
436 /* ep_info bitmasks */
437 /*
438 * Endpoint State - bits 0:2
439 * 0 - disabled
440 * 1 - running
441 * 2 - halted due to halt condition - ok to manipulate endpoint ring
442 * 3 - stopped
443 * 4 - TRB error
444 * 5-7 - reserved
445 */
446 #define EP_STATE_MASK (0x7)
447 #define EP_STATE_DISABLED 0
448 #define EP_STATE_RUNNING 1
449 #define EP_STATE_HALTED 2
450 #define EP_STATE_STOPPED 3
451 #define EP_STATE_ERROR 4
452 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
453
454 /* Mult - Max number of burtst within an interval, in EP companion desc. */
455 #define EP_MULT(p) (((p) & 0x3) << 8)
456 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
457 /* bits 10:14 are Max Primary Streams */
458 /* bit 15 is Linear Stream Array */
459 /* Interval - period between requests to an endpoint - 125u increments. */
460 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
461 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
462 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
463 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
464 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
465 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
466 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
467 #define EP_HAS_LSA (1 << 15)
468 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
469 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
470
471 /* ep_info2 bitmasks */
472 /*
473 * Force Event - generate transfer events for all TRBs for this endpoint
474 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
475 */
476 #define FORCE_EVENT (0x1)
477 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
478 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
479 #define EP_TYPE(p) ((p) << 3)
480 #define ISOC_OUT_EP 1
481 #define BULK_OUT_EP 2
482 #define INT_OUT_EP 3
483 #define CTRL_EP 4
484 #define ISOC_IN_EP 5
485 #define BULK_IN_EP 6
486 #define INT_IN_EP 7
487 /* bit 6 reserved */
488 /* bit 7 is Host Initiate Disable - for disabling stream selection */
489 #define MAX_BURST(p) (((p)&0xff) << 8)
490 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
491 #define MAX_PACKET(p) (((p)&0xffff) << 16)
492 #define MAX_PACKET_MASK (0xffff << 16)
493 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
494
495 /* tx_info bitmasks */
496 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
497 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
498 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
499 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
500
501 /* deq bitmasks */
502 #define EP_CTX_CYCLE_MASK (1 << 0)
503 #define SCTX_DEQ_MASK (~0xfL)
504
505
506 /**
507 * struct xhci_input_control_context
508 * Input control context; see section 6.2.5.
509 *
510 * @drop_context: set the bit of the endpoint context you want to disable
511 * @add_context: set the bit of the endpoint context you want to enable
512 */
513 struct xhci_input_control_ctx {
514 __le32 drop_flags;
515 __le32 add_flags;
516 __le32 rsvd2[6];
517 };
518
519 #define EP_IS_ADDED(ctrl_ctx, i) \
520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
521 #define EP_IS_DROPPED(ctrl_ctx, i) \
522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
523
524 /* Represents everything that is needed to issue a command on the command ring.
525 * It's useful to pre-allocate these for commands that cannot fail due to
526 * out-of-memory errors, like freeing streams.
527 */
528 struct xhci_command {
529 /* Input context for changing device state */
530 struct xhci_container_ctx *in_ctx;
531 u32 status;
532 int slot_id;
533 /* If completion is null, no one is waiting on this command
534 * and the structure can be freed after the command completes.
535 */
536 struct completion *completion;
537 union xhci_trb *command_trb;
538 struct list_head cmd_list;
539 /* xHCI command response timeout in milliseconds */
540 unsigned int timeout_ms;
541 };
542
543 /* drop context bitmasks */
544 #define DROP_EP(x) (0x1 << x)
545 /* add context bitmasks */
546 #define ADD_EP(x) (0x1 << x)
547
548 struct xhci_stream_ctx {
549 /* 64-bit stream ring address, cycle state, and stream type */
550 __le64 stream_ring;
551 /* offset 0x14 - 0x1f reserved for HC internal use */
552 __le32 reserved[2];
553 };
554
555 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
556 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
557 /* Secondary stream array type, dequeue pointer is to a transfer ring */
558 #define SCT_SEC_TR 0
559 /* Primary stream array type, dequeue pointer is to a transfer ring */
560 #define SCT_PRI_TR 1
561 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
562 #define SCT_SSA_8 2
563 #define SCT_SSA_16 3
564 #define SCT_SSA_32 4
565 #define SCT_SSA_64 5
566 #define SCT_SSA_128 6
567 #define SCT_SSA_256 7
568
569 /* Assume no secondary streams for now */
570 struct xhci_stream_info {
571 struct xhci_ring **stream_rings;
572 /* Number of streams, including stream 0 (which drivers can't use) */
573 unsigned int num_streams;
574 /* The stream context array may be bigger than
575 * the number of streams the driver asked for
576 */
577 struct xhci_stream_ctx *stream_ctx_array;
578 unsigned int num_stream_ctxs;
579 dma_addr_t ctx_array_dma;
580 /* For mapping physical TRB addresses to segments in stream rings */
581 struct radix_tree_root trb_address_map;
582 struct xhci_command *free_streams_command;
583 };
584
585 #define SMALL_STREAM_ARRAY_SIZE 256
586 #define MEDIUM_STREAM_ARRAY_SIZE 1024
587
588 /* Some Intel xHCI host controllers need software to keep track of the bus
589 * bandwidth. Keep track of endpoint info here. Each root port is allocated
590 * the full bus bandwidth. We must also treat TTs (including each port under a
591 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
592 * (DMI) also limits the total bandwidth (across all domains) that can be used.
593 */
594 struct xhci_bw_info {
595 /* ep_interval is zero-based */
596 unsigned int ep_interval;
597 /* mult and num_packets are one-based */
598 unsigned int mult;
599 unsigned int num_packets;
600 unsigned int max_packet_size;
601 unsigned int max_esit_payload;
602 unsigned int type;
603 };
604
605 /* "Block" sizes in bytes the hardware uses for different device speeds.
606 * The logic in this part of the hardware limits the number of bits the hardware
607 * can use, so must represent bandwidth in a less precise manner to mimic what
608 * the scheduler hardware computes.
609 */
610 #define FS_BLOCK 1
611 #define HS_BLOCK 4
612 #define SS_BLOCK 16
613 #define DMI_BLOCK 32
614
615 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
616 * with each byte transferred. SuperSpeed devices have an initial overhead to
617 * set up bursts. These are in blocks, see above. LS overhead has already been
618 * translated into FS blocks.
619 */
620 #define DMI_OVERHEAD 8
621 #define DMI_OVERHEAD_BURST 4
622 #define SS_OVERHEAD 8
623 #define SS_OVERHEAD_BURST 32
624 #define HS_OVERHEAD 26
625 #define FS_OVERHEAD 20
626 #define LS_OVERHEAD 128
627 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
628 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
629 * of overhead associated with split transfers crossing microframe boundaries.
630 * 31 blocks is pure protocol overhead.
631 */
632 #define TT_HS_OVERHEAD (31 + 94)
633 #define TT_DMI_OVERHEAD (25 + 12)
634
635 /* Bandwidth limits in blocks */
636 #define FS_BW_LIMIT 1285
637 #define TT_BW_LIMIT 1320
638 #define HS_BW_LIMIT 1607
639 #define SS_BW_LIMIT_IN 3906
640 #define DMI_BW_LIMIT_IN 3906
641 #define SS_BW_LIMIT_OUT 3906
642 #define DMI_BW_LIMIT_OUT 3906
643
644 /* Percentage of bus bandwidth reserved for non-periodic transfers */
645 #define FS_BW_RESERVED 10
646 #define HS_BW_RESERVED 20
647 #define SS_BW_RESERVED 10
648
649 struct xhci_virt_ep {
650 struct xhci_virt_device *vdev; /* parent */
651 unsigned int ep_index;
652 struct xhci_ring *ring;
653 /* Related to endpoints that are configured to use stream IDs only */
654 struct xhci_stream_info *stream_info;
655 /* Temporary storage in case the configure endpoint command fails and we
656 * have to restore the device state to the previous state
657 */
658 struct xhci_ring *new_ring;
659 unsigned int err_count;
660 unsigned int ep_state;
661 #define SET_DEQ_PENDING (1 << 0)
662 #define EP_HALTED (1 << 1) /* For stall handling */
663 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
664 /* Transitioning the endpoint to using streams, don't enqueue URBs */
665 #define EP_GETTING_STREAMS (1 << 3)
666 #define EP_HAS_STREAMS (1 << 4)
667 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
668 #define EP_GETTING_NO_STREAMS (1 << 5)
669 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
670 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
671 /* usb_hub_clear_tt_buffer is in progress */
672 #define EP_CLEARING_TT (1 << 8)
673 /* ---- Related to URB cancellation ---- */
674 struct list_head cancelled_td_list;
675 struct xhci_hcd *xhci;
676 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
677 * command. We'll need to update the ring's dequeue segment and dequeue
678 * pointer after the command completes.
679 */
680 struct xhci_segment *queued_deq_seg;
681 union xhci_trb *queued_deq_ptr;
682 /*
683 * Sometimes the xHC can not process isochronous endpoint ring quickly
684 * enough, and it will miss some isoc tds on the ring and generate
685 * a Missed Service Error Event.
686 * Set skip flag when receive a Missed Service Error Event and
687 * process the missed tds on the endpoint ring.
688 */
689 bool skip;
690 /* Bandwidth checking storage */
691 struct xhci_bw_info bw_info;
692 struct list_head bw_endpoint_list;
693 /* Isoch Frame ID checking storage */
694 int next_frame_id;
695 /* Use new Isoch TRB layout needed for extended TBC support */
696 bool use_extended_tbc;
697 };
698
699 enum xhci_overhead_type {
700 LS_OVERHEAD_TYPE = 0,
701 FS_OVERHEAD_TYPE,
702 HS_OVERHEAD_TYPE,
703 };
704
705 struct xhci_interval_bw {
706 unsigned int num_packets;
707 /* Sorted by max packet size.
708 * Head of the list is the greatest max packet size.
709 */
710 struct list_head endpoints;
711 /* How many endpoints of each speed are present. */
712 unsigned int overhead[3];
713 };
714
715 #define XHCI_MAX_INTERVAL 16
716
717 struct xhci_interval_bw_table {
718 unsigned int interval0_esit_payload;
719 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
720 /* Includes reserved bandwidth for async endpoints */
721 unsigned int bw_used;
722 unsigned int ss_bw_in;
723 unsigned int ss_bw_out;
724 };
725
726 #define EP_CTX_PER_DEV 31
727
728 struct xhci_virt_device {
729 int slot_id;
730 struct usb_device *udev;
731 /*
732 * Commands to the hardware are passed an "input context" that
733 * tells the hardware what to change in its data structures.
734 * The hardware will return changes in an "output context" that
735 * software must allocate for the hardware. We need to keep
736 * track of input and output contexts separately because
737 * these commands might fail and we don't trust the hardware.
738 */
739 struct xhci_container_ctx *out_ctx;
740 /* Used for addressing devices and configuration changes */
741 struct xhci_container_ctx *in_ctx;
742 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
743 struct xhci_port *rhub_port;
744 struct xhci_interval_bw_table *bw_table;
745 struct xhci_tt_bw_info *tt_info;
746 /*
747 * flags for state tracking based on events and issued commands.
748 * Software can not rely on states from output contexts because of
749 * latency between events and xHC updating output context values.
750 * See xhci 1.1 section 4.8.3 for more details
751 */
752 unsigned long flags;
753 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
754
755 /* The current max exit latency for the enabled USB3 link states. */
756 u16 current_mel;
757 /* Used for the debugfs interfaces. */
758 void *debugfs_private;
759 };
760
761 /*
762 * For each roothub, keep track of the bandwidth information for each periodic
763 * interval.
764 *
765 * If a high speed hub is attached to the roothub, each TT associated with that
766 * hub is a separate bandwidth domain. The interval information for the
767 * endpoints on the devices under that TT will appear in the TT structure.
768 */
769 struct xhci_root_port_bw_info {
770 struct list_head tts;
771 unsigned int num_active_tts;
772 struct xhci_interval_bw_table bw_table;
773 };
774
775 struct xhci_tt_bw_info {
776 struct list_head tt_list;
777 int slot_id;
778 int ttport;
779 struct xhci_interval_bw_table bw_table;
780 int active_eps;
781 };
782
783
784 /**
785 * struct xhci_device_context_array
786 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
787 */
788 struct xhci_device_context_array {
789 /* 64-bit device addresses; we only write 32-bit addresses */
790 __le64 dev_context_ptrs[MAX_HC_SLOTS];
791 /* private xHCD pointers */
792 dma_addr_t dma;
793 };
794 /* TODO: write function to set the 64-bit device DMA address */
795 /*
796 * TODO: change this to be dynamically sized at HC mem init time since the HC
797 * might not be able to handle the maximum number of devices possible.
798 */
799
800
801 struct xhci_transfer_event {
802 /* 64-bit buffer address, or immediate data */
803 __le64 buffer;
804 __le32 transfer_len;
805 /* This field is interpreted differently based on the type of TRB */
806 __le32 flags;
807 };
808
809 /* Transfer event flags bitfield, also for select command completion events */
810 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff)
811 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
812
813 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
814 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16)
815
816 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
817 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
818
819 /* Transfer event TRB length bit mask */
820 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
821
822 /* Completion Code - only applicable for some types of TRBs */
823 #define COMP_CODE_MASK (0xff << 24)
824 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
825 #define COMP_INVALID 0
826 #define COMP_SUCCESS 1
827 #define COMP_DATA_BUFFER_ERROR 2
828 #define COMP_BABBLE_DETECTED_ERROR 3
829 #define COMP_USB_TRANSACTION_ERROR 4
830 #define COMP_TRB_ERROR 5
831 #define COMP_STALL_ERROR 6
832 #define COMP_RESOURCE_ERROR 7
833 #define COMP_BANDWIDTH_ERROR 8
834 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
835 #define COMP_INVALID_STREAM_TYPE_ERROR 10
836 #define COMP_SLOT_NOT_ENABLED_ERROR 11
837 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
838 #define COMP_SHORT_PACKET 13
839 #define COMP_RING_UNDERRUN 14
840 #define COMP_RING_OVERRUN 15
841 #define COMP_VF_EVENT_RING_FULL_ERROR 16
842 #define COMP_PARAMETER_ERROR 17
843 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
844 #define COMP_CONTEXT_STATE_ERROR 19
845 #define COMP_NO_PING_RESPONSE_ERROR 20
846 #define COMP_EVENT_RING_FULL_ERROR 21
847 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
848 #define COMP_MISSED_SERVICE_ERROR 23
849 #define COMP_COMMAND_RING_STOPPED 24
850 #define COMP_COMMAND_ABORTED 25
851 #define COMP_STOPPED 26
852 #define COMP_STOPPED_LENGTH_INVALID 27
853 #define COMP_STOPPED_SHORT_PACKET 28
854 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
855 #define COMP_ISOCH_BUFFER_OVERRUN 31
856 #define COMP_EVENT_LOST_ERROR 32
857 #define COMP_UNDEFINED_ERROR 33
858 #define COMP_INVALID_STREAM_ID_ERROR 34
859 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
860 #define COMP_SPLIT_TRANSACTION_ERROR 36
861
xhci_trb_comp_code_string(u8 status)862 static inline const char *xhci_trb_comp_code_string(u8 status)
863 {
864 switch (status) {
865 case COMP_INVALID:
866 return "Invalid";
867 case COMP_SUCCESS:
868 return "Success";
869 case COMP_DATA_BUFFER_ERROR:
870 return "Data Buffer Error";
871 case COMP_BABBLE_DETECTED_ERROR:
872 return "Babble Detected";
873 case COMP_USB_TRANSACTION_ERROR:
874 return "USB Transaction Error";
875 case COMP_TRB_ERROR:
876 return "TRB Error";
877 case COMP_STALL_ERROR:
878 return "Stall Error";
879 case COMP_RESOURCE_ERROR:
880 return "Resource Error";
881 case COMP_BANDWIDTH_ERROR:
882 return "Bandwidth Error";
883 case COMP_NO_SLOTS_AVAILABLE_ERROR:
884 return "No Slots Available Error";
885 case COMP_INVALID_STREAM_TYPE_ERROR:
886 return "Invalid Stream Type Error";
887 case COMP_SLOT_NOT_ENABLED_ERROR:
888 return "Slot Not Enabled Error";
889 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
890 return "Endpoint Not Enabled Error";
891 case COMP_SHORT_PACKET:
892 return "Short Packet";
893 case COMP_RING_UNDERRUN:
894 return "Ring Underrun";
895 case COMP_RING_OVERRUN:
896 return "Ring Overrun";
897 case COMP_VF_EVENT_RING_FULL_ERROR:
898 return "VF Event Ring Full Error";
899 case COMP_PARAMETER_ERROR:
900 return "Parameter Error";
901 case COMP_BANDWIDTH_OVERRUN_ERROR:
902 return "Bandwidth Overrun Error";
903 case COMP_CONTEXT_STATE_ERROR:
904 return "Context State Error";
905 case COMP_NO_PING_RESPONSE_ERROR:
906 return "No Ping Response Error";
907 case COMP_EVENT_RING_FULL_ERROR:
908 return "Event Ring Full Error";
909 case COMP_INCOMPATIBLE_DEVICE_ERROR:
910 return "Incompatible Device Error";
911 case COMP_MISSED_SERVICE_ERROR:
912 return "Missed Service Error";
913 case COMP_COMMAND_RING_STOPPED:
914 return "Command Ring Stopped";
915 case COMP_COMMAND_ABORTED:
916 return "Command Aborted";
917 case COMP_STOPPED:
918 return "Stopped";
919 case COMP_STOPPED_LENGTH_INVALID:
920 return "Stopped - Length Invalid";
921 case COMP_STOPPED_SHORT_PACKET:
922 return "Stopped - Short Packet";
923 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
924 return "Max Exit Latency Too Large Error";
925 case COMP_ISOCH_BUFFER_OVERRUN:
926 return "Isoch Buffer Overrun";
927 case COMP_EVENT_LOST_ERROR:
928 return "Event Lost Error";
929 case COMP_UNDEFINED_ERROR:
930 return "Undefined Error";
931 case COMP_INVALID_STREAM_ID_ERROR:
932 return "Invalid Stream ID Error";
933 case COMP_SECONDARY_BANDWIDTH_ERROR:
934 return "Secondary Bandwidth Error";
935 case COMP_SPLIT_TRANSACTION_ERROR:
936 return "Split Transaction Error";
937 default:
938 return "Unknown!!";
939 }
940 }
941
942 struct xhci_link_trb {
943 /* 64-bit segment pointer*/
944 __le64 segment_ptr;
945 __le32 intr_target;
946 __le32 control;
947 };
948
949 /* control bitfields */
950 #define LINK_TOGGLE (0x1<<1)
951
952 /* Command completion event TRB */
953 struct xhci_event_cmd {
954 /* Pointer to command TRB, or the value passed by the event data trb */
955 __le64 cmd_trb;
956 __le32 status;
957 __le32 flags;
958 };
959
960 /* Address device - disable SetAddress */
961 #define TRB_BSR (1<<9)
962
963 /* Configure Endpoint - Deconfigure */
964 #define TRB_DC (1<<9)
965
966 /* Stop Ring - Transfer State Preserve */
967 #define TRB_TSP (1<<9)
968
969 enum xhci_ep_reset_type {
970 EP_HARD_RESET,
971 EP_SOFT_RESET,
972 };
973
974 /* Force Event */
975 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
976 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
977
978 /* Set Latency Tolerance Value */
979 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
980
981 /* Get Port Bandwidth */
982 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
983
984 /* Force Header */
985 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
986 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
987
988 enum xhci_setup_dev {
989 SETUP_CONTEXT_ONLY,
990 SETUP_CONTEXT_ADDRESS,
991 };
992
993 /* bits 16:23 are the virtual function ID */
994 /* bits 24:31 are the slot ID */
995
996 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
997 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
998 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
999 #define LAST_EP_INDEX 30
1000
1001 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1002 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1003 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1004 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1005
1006 /* Link TRB specific fields */
1007 #define TRB_TC (1<<1)
1008
1009 /* Port Status Change Event TRB fields */
1010 /* Port ID - bits 31:24 */
1011 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1012
1013 #define EVENT_DATA (1 << 2)
1014
1015 /* Normal TRB fields */
1016 /* transfer_len bitmasks - bits 0:16 */
1017 #define TRB_LEN(p) ((p) & 0x1ffff)
1018 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1019 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1020 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1021 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1022 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1023 /* Interrupter Target - which MSI-X vector to target the completion event at */
1024 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1025 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1026 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1027 #define TRB_TBC(p) (((p) & 0x3) << 7)
1028 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1029
1030 /* Cycle bit - indicates TRB ownership by HC or HCD */
1031 #define TRB_CYCLE (1<<0)
1032 /*
1033 * Force next event data TRB to be evaluated before task switch.
1034 * Used to pass OS data back after a TD completes.
1035 */
1036 #define TRB_ENT (1<<1)
1037 /* Interrupt on short packet */
1038 #define TRB_ISP (1<<2)
1039 /* Set PCIe no snoop attribute */
1040 #define TRB_NO_SNOOP (1<<3)
1041 /* Chain multiple TRBs into a TD */
1042 #define TRB_CHAIN (1<<4)
1043 /* Interrupt on completion */
1044 #define TRB_IOC (1<<5)
1045 /* The buffer pointer contains immediate data */
1046 #define TRB_IDT (1<<6)
1047 /* TDs smaller than this might use IDT */
1048 #define TRB_IDT_MAX_SIZE 8
1049
1050 /* Block Event Interrupt */
1051 #define TRB_BEI (1<<9)
1052
1053 /* Control transfer TRB specific fields */
1054 #define TRB_DIR_IN (1<<16)
1055 #define TRB_TX_TYPE(p) ((p) << 16)
1056 #define TRB_DATA_OUT 2
1057 #define TRB_DATA_IN 3
1058
1059 /* Isochronous TRB specific fields */
1060 #define TRB_SIA (1<<31)
1061 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1062
1063 /* TRB cache size for xHC with TRB cache */
1064 #define TRB_CACHE_SIZE_HS 8
1065 #define TRB_CACHE_SIZE_SS 16
1066
1067 struct xhci_generic_trb {
1068 __le32 field[4];
1069 };
1070
1071 union xhci_trb {
1072 struct xhci_link_trb link;
1073 struct xhci_transfer_event trans_event;
1074 struct xhci_event_cmd event_cmd;
1075 struct xhci_generic_trb generic;
1076 };
1077
1078 /* TRB bit mask */
1079 #define TRB_TYPE_BITMASK (0xfc00)
1080 #define TRB_TYPE(p) ((p) << 10)
1081 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1082 /* TRB type IDs */
1083 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1084 #define TRB_NORMAL 1
1085 /* setup stage for control transfers */
1086 #define TRB_SETUP 2
1087 /* data stage for control transfers */
1088 #define TRB_DATA 3
1089 /* status stage for control transfers */
1090 #define TRB_STATUS 4
1091 /* isoc transfers */
1092 #define TRB_ISOC 5
1093 /* TRB for linking ring segments */
1094 #define TRB_LINK 6
1095 #define TRB_EVENT_DATA 7
1096 /* Transfer Ring No-op (not for the command ring) */
1097 #define TRB_TR_NOOP 8
1098 /* Command TRBs */
1099 /* Enable Slot Command */
1100 #define TRB_ENABLE_SLOT 9
1101 /* Disable Slot Command */
1102 #define TRB_DISABLE_SLOT 10
1103 /* Address Device Command */
1104 #define TRB_ADDR_DEV 11
1105 /* Configure Endpoint Command */
1106 #define TRB_CONFIG_EP 12
1107 /* Evaluate Context Command */
1108 #define TRB_EVAL_CONTEXT 13
1109 /* Reset Endpoint Command */
1110 #define TRB_RESET_EP 14
1111 /* Stop Transfer Ring Command */
1112 #define TRB_STOP_RING 15
1113 /* Set Transfer Ring Dequeue Pointer Command */
1114 #define TRB_SET_DEQ 16
1115 /* Reset Device Command */
1116 #define TRB_RESET_DEV 17
1117 /* Force Event Command (opt) */
1118 #define TRB_FORCE_EVENT 18
1119 /* Negotiate Bandwidth Command (opt) */
1120 #define TRB_NEG_BANDWIDTH 19
1121 /* Set Latency Tolerance Value Command (opt) */
1122 #define TRB_SET_LT 20
1123 /* Get port bandwidth Command */
1124 #define TRB_GET_BW 21
1125 /* Force Header Command - generate a transaction or link management packet */
1126 #define TRB_FORCE_HEADER 22
1127 /* No-op Command - not for transfer rings */
1128 #define TRB_CMD_NOOP 23
1129 /* TRB IDs 24-31 reserved */
1130 /* Event TRBS */
1131 /* Transfer Event */
1132 #define TRB_TRANSFER 32
1133 /* Command Completion Event */
1134 #define TRB_COMPLETION 33
1135 /* Port Status Change Event */
1136 #define TRB_PORT_STATUS 34
1137 /* Bandwidth Request Event (opt) */
1138 #define TRB_BANDWIDTH_EVENT 35
1139 /* Doorbell Event (opt) */
1140 #define TRB_DOORBELL 36
1141 /* Host Controller Event */
1142 #define TRB_HC_EVENT 37
1143 /* Device Notification Event - device sent function wake notification */
1144 #define TRB_DEV_NOTE 38
1145 /* MFINDEX Wrap Event - microframe counter wrapped */
1146 #define TRB_MFINDEX_WRAP 39
1147 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1148 #define TRB_VENDOR_DEFINED_LOW 48
1149 /* Nec vendor-specific command completion event. */
1150 #define TRB_NEC_CMD_COMP 48
1151 /* Get NEC firmware revision. */
1152 #define TRB_NEC_GET_FW 49
1153
xhci_trb_type_string(u8 type)1154 static inline const char *xhci_trb_type_string(u8 type)
1155 {
1156 switch (type) {
1157 case TRB_NORMAL:
1158 return "Normal";
1159 case TRB_SETUP:
1160 return "Setup Stage";
1161 case TRB_DATA:
1162 return "Data Stage";
1163 case TRB_STATUS:
1164 return "Status Stage";
1165 case TRB_ISOC:
1166 return "Isoch";
1167 case TRB_LINK:
1168 return "Link";
1169 case TRB_EVENT_DATA:
1170 return "Event Data";
1171 case TRB_TR_NOOP:
1172 return "No-Op";
1173 case TRB_ENABLE_SLOT:
1174 return "Enable Slot Command";
1175 case TRB_DISABLE_SLOT:
1176 return "Disable Slot Command";
1177 case TRB_ADDR_DEV:
1178 return "Address Device Command";
1179 case TRB_CONFIG_EP:
1180 return "Configure Endpoint Command";
1181 case TRB_EVAL_CONTEXT:
1182 return "Evaluate Context Command";
1183 case TRB_RESET_EP:
1184 return "Reset Endpoint Command";
1185 case TRB_STOP_RING:
1186 return "Stop Ring Command";
1187 case TRB_SET_DEQ:
1188 return "Set TR Dequeue Pointer Command";
1189 case TRB_RESET_DEV:
1190 return "Reset Device Command";
1191 case TRB_FORCE_EVENT:
1192 return "Force Event Command";
1193 case TRB_NEG_BANDWIDTH:
1194 return "Negotiate Bandwidth Command";
1195 case TRB_SET_LT:
1196 return "Set Latency Tolerance Value Command";
1197 case TRB_GET_BW:
1198 return "Get Port Bandwidth Command";
1199 case TRB_FORCE_HEADER:
1200 return "Force Header Command";
1201 case TRB_CMD_NOOP:
1202 return "No-Op Command";
1203 case TRB_TRANSFER:
1204 return "Transfer Event";
1205 case TRB_COMPLETION:
1206 return "Command Completion Event";
1207 case TRB_PORT_STATUS:
1208 return "Port Status Change Event";
1209 case TRB_BANDWIDTH_EVENT:
1210 return "Bandwidth Request Event";
1211 case TRB_DOORBELL:
1212 return "Doorbell Event";
1213 case TRB_HC_EVENT:
1214 return "Host Controller Event";
1215 case TRB_DEV_NOTE:
1216 return "Device Notification Event";
1217 case TRB_MFINDEX_WRAP:
1218 return "MFINDEX Wrap Event";
1219 case TRB_NEC_CMD_COMP:
1220 return "NEC Command Completion Event";
1221 case TRB_NEC_GET_FW:
1222 return "NET Get Firmware Revision Command";
1223 default:
1224 return "UNKNOWN";
1225 }
1226 }
1227
1228 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1229 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1230 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1231 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1232 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1233 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1234
1235 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1236 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1237
1238 /*
1239 * TRBS_PER_SEGMENT must be a multiple of 4,
1240 * since the command ring is 64-byte aligned.
1241 * It must also be greater than 16.
1242 */
1243 #define TRBS_PER_SEGMENT 256
1244 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1245 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1246 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1247 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1248 /* TRB buffer pointers can't cross 64KB boundaries */
1249 #define TRB_MAX_BUFF_SHIFT 16
1250 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1251 /* How much data is left before the 64KB boundary? */
1252 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1253 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1254 #define MAX_SOFT_RETRY 3
1255 /*
1256 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1257 * XHCI_AVOID_BEI quirk is in use.
1258 */
1259 #define AVOID_BEI_INTERVAL_MIN 8
1260 #define AVOID_BEI_INTERVAL_MAX 32
1261
1262 struct xhci_segment {
1263 union xhci_trb *trbs;
1264 /* private to HCD */
1265 struct xhci_segment *next;
1266 unsigned int num;
1267 dma_addr_t dma;
1268 /* Max packet sized bounce buffer for td-fragmant alignment */
1269 dma_addr_t bounce_dma;
1270 void *bounce_buf;
1271 unsigned int bounce_offs;
1272 unsigned int bounce_len;
1273 };
1274
1275 enum xhci_cancelled_td_status {
1276 TD_DIRTY = 0,
1277 TD_HALTED,
1278 TD_CLEARING_CACHE,
1279 TD_CLEARING_CACHE_DEFERRED,
1280 TD_CLEARED,
1281 };
1282
1283 struct xhci_td {
1284 struct list_head td_list;
1285 struct list_head cancelled_td_list;
1286 int status;
1287 enum xhci_cancelled_td_status cancel_status;
1288 struct urb *urb;
1289 struct xhci_segment *start_seg;
1290 union xhci_trb *first_trb;
1291 union xhci_trb *last_trb;
1292 struct xhci_segment *last_trb_seg;
1293 struct xhci_segment *bounce_seg;
1294 /* actual_length of the URB has already been set */
1295 bool urb_length_set;
1296 bool error_mid_td;
1297 };
1298
1299 /*
1300 * xHCI command default timeout value in milliseconds.
1301 * USB 3.2 spec, section 9.2.6.1
1302 */
1303 #define XHCI_CMD_DEFAULT_TIMEOUT 5000
1304
1305 /* command descriptor */
1306 struct xhci_cd {
1307 struct xhci_command *command;
1308 union xhci_trb *cmd_trb;
1309 };
1310
1311 enum xhci_ring_type {
1312 TYPE_CTRL = 0,
1313 TYPE_ISOC,
1314 TYPE_BULK,
1315 TYPE_INTR,
1316 TYPE_STREAM,
1317 TYPE_COMMAND,
1318 TYPE_EVENT,
1319 };
1320
xhci_ring_type_string(enum xhci_ring_type type)1321 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1322 {
1323 switch (type) {
1324 case TYPE_CTRL:
1325 return "CTRL";
1326 case TYPE_ISOC:
1327 return "ISOC";
1328 case TYPE_BULK:
1329 return "BULK";
1330 case TYPE_INTR:
1331 return "INTR";
1332 case TYPE_STREAM:
1333 return "STREAM";
1334 case TYPE_COMMAND:
1335 return "CMD";
1336 case TYPE_EVENT:
1337 return "EVENT";
1338 }
1339
1340 return "UNKNOWN";
1341 }
1342
1343 struct xhci_ring {
1344 struct xhci_segment *first_seg;
1345 struct xhci_segment *last_seg;
1346 union xhci_trb *enqueue;
1347 struct xhci_segment *enq_seg;
1348 union xhci_trb *dequeue;
1349 struct xhci_segment *deq_seg;
1350 struct list_head td_list;
1351 /*
1352 * Write the cycle state into the TRB cycle field to give ownership of
1353 * the TRB to the host controller (if we are the producer), or to check
1354 * if we own the TRB (if we are the consumer). See section 4.9.1.
1355 */
1356 u32 cycle_state;
1357 unsigned int stream_id;
1358 unsigned int num_segs;
1359 unsigned int num_trbs_free; /* used only by xhci DbC */
1360 unsigned int bounce_buf_len;
1361 enum xhci_ring_type type;
1362 bool last_td_was_short;
1363 struct radix_tree_root *trb_address_map;
1364 };
1365
1366 struct xhci_erst_entry {
1367 /* 64-bit event ring segment address */
1368 __le64 seg_addr;
1369 __le32 seg_size;
1370 /* Set to zero */
1371 __le32 rsvd;
1372 };
1373
1374 struct xhci_erst {
1375 struct xhci_erst_entry *entries;
1376 unsigned int num_entries;
1377 /* xhci->event_ring keeps track of segment dma addresses */
1378 dma_addr_t erst_dma_addr;
1379 };
1380
1381 struct xhci_scratchpad {
1382 u64 *sp_array;
1383 dma_addr_t sp_dma;
1384 void **sp_buffers;
1385 };
1386
1387 struct urb_priv {
1388 int num_tds;
1389 int num_tds_done;
1390 struct xhci_td td[] __counted_by(num_tds);
1391 };
1392
1393 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1394 #define ERST_DEFAULT_SEGS 2
1395 /* Poll every 60 seconds */
1396 #define POLL_TIMEOUT 60
1397 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1398 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1399 /* XXX: Make these module parameters */
1400
1401 struct s3_save {
1402 u32 command;
1403 u32 dev_nt;
1404 u64 dcbaa_ptr;
1405 u32 config_reg;
1406 };
1407
1408 /* Use for lpm */
1409 struct dev_info {
1410 u32 dev_id;
1411 struct list_head list;
1412 };
1413
1414 struct xhci_bus_state {
1415 unsigned long bus_suspended;
1416 unsigned long next_statechange;
1417
1418 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1419 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1420 u32 port_c_suspend;
1421 u32 suspended_ports;
1422 u32 port_remote_wakeup;
1423 /* which ports have started to resume */
1424 unsigned long resuming_ports;
1425 };
1426
1427 struct xhci_interrupter {
1428 struct xhci_ring *event_ring;
1429 struct xhci_erst erst;
1430 struct xhci_intr_reg __iomem *ir_set;
1431 unsigned int intr_num;
1432 bool ip_autoclear;
1433 u32 isoc_bei_interval;
1434 /* For interrupter registers save and restore over suspend/resume */
1435 u32 s3_irq_pending;
1436 u32 s3_irq_control;
1437 u32 s3_erst_size;
1438 u64 s3_erst_base;
1439 u64 s3_erst_dequeue;
1440 };
1441 /*
1442 * It can take up to 20 ms to transition from RExit to U0 on the
1443 * Intel Lynx Point LP xHCI host.
1444 */
1445 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1446 struct xhci_port_cap {
1447 u32 *psi; /* array of protocol speed ID entries */
1448 u8 psi_count;
1449 u8 psi_uid_count;
1450 u8 maj_rev;
1451 u8 min_rev;
1452 u32 protocol_caps;
1453 };
1454
1455 struct xhci_port {
1456 __le32 __iomem *addr;
1457 int hw_portnum;
1458 int hcd_portnum;
1459 struct xhci_hub *rhub;
1460 struct xhci_port_cap *port_cap;
1461 unsigned int lpm_incapable:1;
1462 unsigned long resume_timestamp;
1463 bool rexit_active;
1464 /* Slot ID is the index of the device directly connected to the port */
1465 int slot_id;
1466 struct completion rexit_done;
1467 struct completion u3exit_done;
1468 };
1469
1470 struct xhci_hub {
1471 struct xhci_port **ports;
1472 unsigned int num_ports;
1473 struct usb_hcd *hcd;
1474 /* keep track of bus suspend info */
1475 struct xhci_bus_state bus_state;
1476 /* supported prococol extended capabiliy values */
1477 u8 maj_rev;
1478 u8 min_rev;
1479 };
1480
1481 /* There is one xhci_hcd structure per controller */
1482 struct xhci_hcd {
1483 struct usb_hcd *main_hcd;
1484 struct usb_hcd *shared_hcd;
1485 /* glue to PCI and HCD framework */
1486 struct xhci_cap_regs __iomem *cap_regs;
1487 struct xhci_op_regs __iomem *op_regs;
1488 struct xhci_run_regs __iomem *run_regs;
1489 struct xhci_doorbell_array __iomem *dba;
1490
1491 /* Cached register copies of read-only HC data */
1492 __u32 hcs_params1;
1493 __u32 hcs_params2;
1494 __u32 hcs_params3;
1495 __u32 hcc_params;
1496 __u32 hcc_params2;
1497
1498 spinlock_t lock;
1499
1500 /* packed release number */
1501 u8 sbrn;
1502 u16 hci_version;
1503 u8 max_slots;
1504 u16 max_interrupters;
1505 u8 max_ports;
1506 u8 isoc_threshold;
1507 /* imod_interval in ns (I * 250ns) */
1508 u32 imod_interval;
1509 int event_ring_max;
1510 /* 4KB min, 128MB max */
1511 int page_size;
1512 /* Valid values are 12 to 20, inclusive */
1513 int page_shift;
1514 /* MSI-X/MSI vectors */
1515 int nvecs;
1516 /* optional clocks */
1517 struct clk *clk;
1518 struct clk *reg_clk;
1519 /* optional reset controller */
1520 struct reset_control *reset;
1521 /* data structures */
1522 struct xhci_device_context_array *dcbaa;
1523 struct xhci_interrupter **interrupters;
1524 struct xhci_ring *cmd_ring;
1525 unsigned int cmd_ring_state;
1526 #define CMD_RING_STATE_RUNNING (1 << 0)
1527 #define CMD_RING_STATE_ABORTED (1 << 1)
1528 #define CMD_RING_STATE_STOPPED (1 << 2)
1529 struct list_head cmd_list;
1530 unsigned int cmd_ring_reserved_trbs;
1531 struct delayed_work cmd_timer;
1532 struct completion cmd_ring_stop_completion;
1533 struct xhci_command *current_cmd;
1534
1535 /* Scratchpad */
1536 struct xhci_scratchpad *scratchpad;
1537
1538 /* slot enabling and address device helpers */
1539 /* these are not thread safe so use mutex */
1540 struct mutex mutex;
1541 /* Internal mirror of the HW's dcbaa */
1542 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1543 /* For keeping track of bandwidth domains per roothub. */
1544 struct xhci_root_port_bw_info *rh_bw;
1545
1546 /* DMA pools */
1547 struct dma_pool *device_pool;
1548 struct dma_pool *segment_pool;
1549 struct dma_pool *small_streams_pool;
1550 struct dma_pool *medium_streams_pool;
1551
1552 /* Host controller watchdog timer structures */
1553 unsigned int xhc_state;
1554 unsigned long run_graceperiod;
1555 struct s3_save s3;
1556 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1557 *
1558 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1559 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1560 * that sees this status (other than the timer that set it) should stop touching
1561 * hardware immediately. Interrupt handlers should return immediately when
1562 * they see this status (any time they drop and re-acquire xhci->lock).
1563 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1564 * putting the TD on the canceled list, etc.
1565 *
1566 * There are no reports of xHCI host controllers that display this issue.
1567 */
1568 #define XHCI_STATE_DYING (1 << 0)
1569 #define XHCI_STATE_HALTED (1 << 1)
1570 #define XHCI_STATE_REMOVING (1 << 2)
1571 unsigned long long quirks;
1572 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1573 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1574 #define XHCI_NEC_HOST BIT_ULL(2)
1575 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1576 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1577 /*
1578 * Certain Intel host controllers have a limit to the number of endpoint
1579 * contexts they can handle. Ideally, they would signal that they can't handle
1580 * anymore endpoint contexts by returning a Resource Error for the Configure
1581 * Endpoint command, but they don't. Instead they expect software to keep track
1582 * of the number of active endpoints for them, across configure endpoint
1583 * commands, reset device commands, disable slot commands, and address device
1584 * commands.
1585 */
1586 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1587 #define XHCI_BROKEN_MSI BIT_ULL(6)
1588 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1589 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1590 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1591 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */
1592 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1593 #define XHCI_INTEL_HOST BIT_ULL(12)
1594 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1595 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1596 #define XHCI_AVOID_BEI BIT_ULL(15)
1597 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1598 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1599 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1600 /* For controllers with a broken beyond repair streams implementation */
1601 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1602 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1603 #define XHCI_MTK_HOST BIT_ULL(21)
1604 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1605 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1606 #define XHCI_MISSING_CAS BIT_ULL(24)
1607 /* For controller with a broken Port Disable implementation */
1608 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1609 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1610 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1611 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1612 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1613 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1614 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1615 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1616 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1617 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1618 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1619 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1620 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1621 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1622 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1623 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1624 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1625 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1626 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1627 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1628 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1629 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1630 #define XHCI_WRITE_64_HI_LO BIT_ULL(47)
1631
1632 unsigned int num_active_eps;
1633 unsigned int limit_active_eps;
1634 struct xhci_port *hw_ports;
1635 struct xhci_hub usb2_rhub;
1636 struct xhci_hub usb3_rhub;
1637 /* support xHCI 1.0 spec USB2 hardware LPM */
1638 unsigned hw_lpm_support:1;
1639 /* Broken Suspend flag for SNPS Suspend resume issue */
1640 unsigned broken_suspend:1;
1641 /* Indicates that omitting hcd is supported if root hub has no ports */
1642 unsigned allow_single_roothub:1;
1643 /* cached extended protocol port capabilities */
1644 struct xhci_port_cap *port_caps;
1645 unsigned int num_port_caps;
1646 /* Compliance Mode Recovery Data */
1647 struct timer_list comp_mode_recovery_timer;
1648 u32 port_status_u0;
1649 u16 test_mode;
1650 /* Compliance Mode Timer Triggered every 2 seconds */
1651 #define COMP_MODE_RCVRY_MSECS 2000
1652
1653 struct dentry *debugfs_root;
1654 struct dentry *debugfs_slots;
1655 struct list_head regset_list;
1656
1657 void *dbc;
1658 /* platform-specific data -- must come last */
1659 unsigned long priv[] __aligned(sizeof(s64));
1660 };
1661
1662 /* Platform specific overrides to generic XHCI hc_driver ops */
1663 struct xhci_driver_overrides {
1664 size_t extra_priv_size;
1665 int (*reset)(struct usb_hcd *hcd);
1666 int (*start)(struct usb_hcd *hcd);
1667 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1668 struct usb_host_endpoint *ep);
1669 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1670 struct usb_host_endpoint *ep);
1671 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1672 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1673 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1674 struct usb_tt *tt, gfp_t mem_flags);
1675 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1676 u16 wIndex, char *buf, u16 wLength);
1677 };
1678
1679 #define XHCI_CFC_DELAY 10
1680
1681 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1682 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1683 {
1684 struct usb_hcd *primary_hcd;
1685
1686 if (usb_hcd_is_primary_hcd(hcd))
1687 primary_hcd = hcd;
1688 else
1689 primary_hcd = hcd->primary_hcd;
1690
1691 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1692 }
1693
xhci_to_hcd(struct xhci_hcd * xhci)1694 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1695 {
1696 return xhci->main_hcd;
1697 }
1698
xhci_get_usb3_hcd(struct xhci_hcd * xhci)1699 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1700 {
1701 if (xhci->shared_hcd)
1702 return xhci->shared_hcd;
1703
1704 if (!xhci->usb2_rhub.num_ports)
1705 return xhci->main_hcd;
1706
1707 return NULL;
1708 }
1709
xhci_hcd_is_usb3(struct usb_hcd * hcd)1710 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1711 {
1712 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1713
1714 return hcd == xhci_get_usb3_hcd(xhci);
1715 }
1716
xhci_has_one_roothub(struct xhci_hcd * xhci)1717 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1718 {
1719 return xhci->allow_single_roothub &&
1720 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1721 }
1722
1723 #define xhci_dbg(xhci, fmt, args...) \
1724 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1725 #define xhci_err(xhci, fmt, args...) \
1726 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1727 #define xhci_warn(xhci, fmt, args...) \
1728 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1729 #define xhci_info(xhci, fmt, args...) \
1730 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1731
1732 /*
1733 * Registers should always be accessed with double word or quad word accesses.
1734 *
1735 * Some xHCI implementations may support 64-bit address pointers. Registers
1736 * with 64-bit address pointers should be written to with dword accesses by
1737 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1738 * xHCI implementations that do not support 64-bit address pointers will ignore
1739 * the high dword, and write order is irrelevant.
1740 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1741 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1742 __le64 __iomem *regs)
1743 {
1744 return lo_hi_readq(regs);
1745 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1746 static inline void xhci_write_64(struct xhci_hcd *xhci,
1747 const u64 val, __le64 __iomem *regs)
1748 {
1749 lo_hi_writeq(val, regs);
1750 }
1751
1752
1753 /* Link TRB chain should always be set on 0.95 hosts, and AMD 0.96 ISOC rings */
xhci_link_chain_quirk(struct xhci_hcd * xhci,enum xhci_ring_type type)1754 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type)
1755 {
1756 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||
1757 (type == TYPE_ISOC && (xhci->quirks & XHCI_AMD_0x96_HOST));
1758 }
1759
1760 /* xHCI debugging */
1761 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1762 struct xhci_container_ctx *ctx);
1763 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1764 const char *fmt, ...);
1765
1766 /* xHCI memory management */
1767 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1768 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1769 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1770 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1771 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1772 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1773 struct usb_device *udev);
1774 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1775 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1776 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1777 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1778 struct xhci_virt_device *virt_dev,
1779 int old_active_eps);
1780 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1781 void xhci_update_bw_info(struct xhci_hcd *xhci,
1782 struct xhci_container_ctx *in_ctx,
1783 struct xhci_input_control_ctx *ctrl_ctx,
1784 struct xhci_virt_device *virt_dev);
1785 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1786 struct xhci_container_ctx *in_ctx,
1787 struct xhci_container_ctx *out_ctx,
1788 unsigned int ep_index);
1789 void xhci_slot_copy(struct xhci_hcd *xhci,
1790 struct xhci_container_ctx *in_ctx,
1791 struct xhci_container_ctx *out_ctx);
1792 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1793 struct usb_device *udev, struct usb_host_endpoint *ep,
1794 gfp_t mem_flags);
1795 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1796 unsigned int num_segs, unsigned int cycle_state,
1797 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1798 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1799 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1800 unsigned int num_trbs, gfp_t flags);
1801 void xhci_initialize_ring_info(struct xhci_ring *ring,
1802 unsigned int cycle_state);
1803 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1804 struct xhci_virt_device *virt_dev,
1805 unsigned int ep_index);
1806 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1807 unsigned int num_stream_ctxs,
1808 unsigned int num_streams,
1809 unsigned int max_packet, gfp_t flags);
1810 void xhci_free_stream_info(struct xhci_hcd *xhci,
1811 struct xhci_stream_info *stream_info);
1812 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1813 struct xhci_ep_ctx *ep_ctx,
1814 struct xhci_stream_info *stream_info);
1815 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1816 struct xhci_virt_ep *ep);
1817 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1818 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1819 struct xhci_ring *xhci_dma_to_transfer_ring(
1820 struct xhci_virt_ep *ep,
1821 u64 address);
1822 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1823 bool allocate_completion, gfp_t mem_flags);
1824 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1825 bool allocate_completion, gfp_t mem_flags);
1826 void xhci_urb_free_priv(struct urb_priv *urb_priv);
1827 void xhci_free_command(struct xhci_hcd *xhci,
1828 struct xhci_command *command);
1829 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1830 int type, gfp_t flags);
1831 void xhci_free_container_ctx(struct xhci_hcd *xhci,
1832 struct xhci_container_ctx *ctx);
1833 struct xhci_interrupter *
1834 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs);
1835 void xhci_remove_secondary_interrupter(struct usb_hcd
1836 *hcd, struct xhci_interrupter *ir);
1837
1838 /* xHCI host controller glue */
1839 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1840 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1841 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
1842 u32 mask, u32 done, int usec, unsigned int exit_state);
1843 void xhci_quiesce(struct xhci_hcd *xhci);
1844 int xhci_halt(struct xhci_hcd *xhci);
1845 int xhci_start(struct xhci_hcd *xhci);
1846 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1847 int xhci_run(struct usb_hcd *hcd);
1848 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1849 void xhci_shutdown(struct usb_hcd *hcd);
1850 void xhci_stop(struct usb_hcd *hcd);
1851 void xhci_init_driver(struct hc_driver *drv,
1852 const struct xhci_driver_overrides *over);
1853 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1854 struct usb_host_endpoint *ep);
1855 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1856 struct usb_host_endpoint *ep);
1857 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1858 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1859 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1860 struct usb_tt *tt, gfp_t mem_flags);
1861 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1862 int xhci_ext_cap_init(struct xhci_hcd *xhci);
1863
1864 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1865 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1866
1867 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1868 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1869 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1870 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1871 struct xhci_virt_device *virt_dev,
1872 struct usb_device *hdev,
1873 struct usb_tt *tt, gfp_t mem_flags);
1874
1875 /* xHCI ring, segment, TRB, and TD functions */
1876 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1877 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, struct xhci_td *td,
1878 dma_addr_t suspect_dma, bool debug);
1879 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1880 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1881 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1882 u32 trb_type, u32 slot_id);
1883 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1884 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1885 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1886 u32 field1, u32 field2, u32 field3, u32 field4);
1887 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1888 int slot_id, unsigned int ep_index, int suspend);
1889 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1890 int slot_id, unsigned int ep_index);
1891 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1892 int slot_id, unsigned int ep_index);
1893 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1894 int slot_id, unsigned int ep_index);
1895 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1896 struct urb *urb, int slot_id, unsigned int ep_index);
1897 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1898 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1899 bool command_must_succeed);
1900 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1901 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1902 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1903 int slot_id, unsigned int ep_index,
1904 enum xhci_ep_reset_type reset_type);
1905 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1906 u32 slot_id);
1907 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
1908 unsigned int ep_index, unsigned int stream_id,
1909 struct xhci_td *td);
1910 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
1911 void xhci_handle_command_timeout(struct work_struct *work);
1912
1913 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1914 unsigned int ep_index, unsigned int stream_id);
1915 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1916 unsigned int slot_id,
1917 unsigned int ep_index);
1918 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1919 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1920 unsigned int count_trbs(u64 addr, u64 len);
1921
1922 /* xHCI roothub code */
1923 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1924 u32 link_state);
1925 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1926 u32 port_bit);
1927 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1928 char *buf, u16 wLength);
1929 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1930 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1931 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1932
1933 void xhci_hc_died(struct xhci_hcd *xhci);
1934
1935 #ifdef CONFIG_PM
1936 int xhci_bus_suspend(struct usb_hcd *hcd);
1937 int xhci_bus_resume(struct usb_hcd *hcd);
1938 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1939 #else
1940 #define xhci_bus_suspend NULL
1941 #define xhci_bus_resume NULL
1942 #define xhci_get_resuming_ports NULL
1943 #endif /* CONFIG_PM */
1944
1945 u32 xhci_port_state_to_neutral(u32 state);
1946 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1947
1948 /* xHCI contexts */
1949 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1950 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1951 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1952
1953 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1954 unsigned int slot_id, unsigned int ep_index,
1955 unsigned int stream_id);
1956
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)1957 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1958 struct urb *urb)
1959 {
1960 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1961 xhci_get_endpoint_index(&urb->ep->desc),
1962 urb->stream_id);
1963 }
1964
1965 /*
1966 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
1967 * them anyways as we where unable to find a device that matches the
1968 * constraints.
1969 */
xhci_urb_suitable_for_idt(struct urb * urb)1970 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
1971 {
1972 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
1973 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
1974 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
1975 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
1976 !urb->num_sgs)
1977 return true;
1978
1979 return false;
1980 }
1981
xhci_slot_state_string(u32 state)1982 static inline char *xhci_slot_state_string(u32 state)
1983 {
1984 switch (state) {
1985 case SLOT_STATE_ENABLED:
1986 return "enabled/disabled";
1987 case SLOT_STATE_DEFAULT:
1988 return "default";
1989 case SLOT_STATE_ADDRESSED:
1990 return "addressed";
1991 case SLOT_STATE_CONFIGURED:
1992 return "configured";
1993 default:
1994 return "reserved";
1995 }
1996 }
1997
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)1998 static inline const char *xhci_decode_trb(char *str, size_t size,
1999 u32 field0, u32 field1, u32 field2, u32 field3)
2000 {
2001 int type = TRB_FIELD_TO_TYPE(field3);
2002
2003 switch (type) {
2004 case TRB_LINK:
2005 snprintf(str, size,
2006 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2007 field1, field0, GET_INTR_TARGET(field2),
2008 xhci_trb_type_string(type),
2009 field3 & TRB_IOC ? 'I' : 'i',
2010 field3 & TRB_CHAIN ? 'C' : 'c',
2011 field3 & TRB_TC ? 'T' : 't',
2012 field3 & TRB_CYCLE ? 'C' : 'c');
2013 break;
2014 case TRB_TRANSFER:
2015 case TRB_COMPLETION:
2016 case TRB_PORT_STATUS:
2017 case TRB_BANDWIDTH_EVENT:
2018 case TRB_DOORBELL:
2019 case TRB_HC_EVENT:
2020 case TRB_DEV_NOTE:
2021 case TRB_MFINDEX_WRAP:
2022 snprintf(str, size,
2023 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2024 field1, field0,
2025 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2026 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2027 TRB_TO_EP_ID(field3),
2028 xhci_trb_type_string(type),
2029 field3 & EVENT_DATA ? 'E' : 'e',
2030 field3 & TRB_CYCLE ? 'C' : 'c');
2031
2032 break;
2033 case TRB_SETUP:
2034 snprintf(str, size,
2035 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2036 field0 & 0xff,
2037 (field0 & 0xff00) >> 8,
2038 (field0 & 0xff000000) >> 24,
2039 (field0 & 0xff0000) >> 16,
2040 (field1 & 0xff00) >> 8,
2041 field1 & 0xff,
2042 (field1 & 0xff000000) >> 16 |
2043 (field1 & 0xff0000) >> 16,
2044 TRB_LEN(field2), GET_TD_SIZE(field2),
2045 GET_INTR_TARGET(field2),
2046 xhci_trb_type_string(type),
2047 field3 & TRB_IDT ? 'I' : 'i',
2048 field3 & TRB_IOC ? 'I' : 'i',
2049 field3 & TRB_CYCLE ? 'C' : 'c');
2050 break;
2051 case TRB_DATA:
2052 snprintf(str, size,
2053 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2054 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2055 GET_INTR_TARGET(field2),
2056 xhci_trb_type_string(type),
2057 field3 & TRB_IDT ? 'I' : 'i',
2058 field3 & TRB_IOC ? 'I' : 'i',
2059 field3 & TRB_CHAIN ? 'C' : 'c',
2060 field3 & TRB_NO_SNOOP ? 'S' : 's',
2061 field3 & TRB_ISP ? 'I' : 'i',
2062 field3 & TRB_ENT ? 'E' : 'e',
2063 field3 & TRB_CYCLE ? 'C' : 'c');
2064 break;
2065 case TRB_STATUS:
2066 snprintf(str, size,
2067 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2068 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2069 GET_INTR_TARGET(field2),
2070 xhci_trb_type_string(type),
2071 field3 & TRB_IOC ? 'I' : 'i',
2072 field3 & TRB_CHAIN ? 'C' : 'c',
2073 field3 & TRB_ENT ? 'E' : 'e',
2074 field3 & TRB_CYCLE ? 'C' : 'c');
2075 break;
2076 case TRB_NORMAL:
2077 case TRB_ISOC:
2078 case TRB_EVENT_DATA:
2079 case TRB_TR_NOOP:
2080 snprintf(str, size,
2081 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2082 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2083 GET_INTR_TARGET(field2),
2084 xhci_trb_type_string(type),
2085 field3 & TRB_BEI ? 'B' : 'b',
2086 field3 & TRB_IDT ? 'I' : 'i',
2087 field3 & TRB_IOC ? 'I' : 'i',
2088 field3 & TRB_CHAIN ? 'C' : 'c',
2089 field3 & TRB_NO_SNOOP ? 'S' : 's',
2090 field3 & TRB_ISP ? 'I' : 'i',
2091 field3 & TRB_ENT ? 'E' : 'e',
2092 field3 & TRB_CYCLE ? 'C' : 'c');
2093 break;
2094
2095 case TRB_CMD_NOOP:
2096 case TRB_ENABLE_SLOT:
2097 snprintf(str, size,
2098 "%s: flags %c",
2099 xhci_trb_type_string(type),
2100 field3 & TRB_CYCLE ? 'C' : 'c');
2101 break;
2102 case TRB_DISABLE_SLOT:
2103 case TRB_NEG_BANDWIDTH:
2104 snprintf(str, size,
2105 "%s: slot %d flags %c",
2106 xhci_trb_type_string(type),
2107 TRB_TO_SLOT_ID(field3),
2108 field3 & TRB_CYCLE ? 'C' : 'c');
2109 break;
2110 case TRB_ADDR_DEV:
2111 snprintf(str, size,
2112 "%s: ctx %08x%08x slot %d flags %c:%c",
2113 xhci_trb_type_string(type),
2114 field1, field0,
2115 TRB_TO_SLOT_ID(field3),
2116 field3 & TRB_BSR ? 'B' : 'b',
2117 field3 & TRB_CYCLE ? 'C' : 'c');
2118 break;
2119 case TRB_CONFIG_EP:
2120 snprintf(str, size,
2121 "%s: ctx %08x%08x slot %d flags %c:%c",
2122 xhci_trb_type_string(type),
2123 field1, field0,
2124 TRB_TO_SLOT_ID(field3),
2125 field3 & TRB_DC ? 'D' : 'd',
2126 field3 & TRB_CYCLE ? 'C' : 'c');
2127 break;
2128 case TRB_EVAL_CONTEXT:
2129 snprintf(str, size,
2130 "%s: ctx %08x%08x slot %d flags %c",
2131 xhci_trb_type_string(type),
2132 field1, field0,
2133 TRB_TO_SLOT_ID(field3),
2134 field3 & TRB_CYCLE ? 'C' : 'c');
2135 break;
2136 case TRB_RESET_EP:
2137 snprintf(str, size,
2138 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2139 xhci_trb_type_string(type),
2140 field1, field0,
2141 TRB_TO_SLOT_ID(field3),
2142 TRB_TO_EP_ID(field3),
2143 field3 & TRB_TSP ? 'T' : 't',
2144 field3 & TRB_CYCLE ? 'C' : 'c');
2145 break;
2146 case TRB_STOP_RING:
2147 snprintf(str, size,
2148 "%s: slot %d sp %d ep %d flags %c",
2149 xhci_trb_type_string(type),
2150 TRB_TO_SLOT_ID(field3),
2151 TRB_TO_SUSPEND_PORT(field3),
2152 TRB_TO_EP_ID(field3),
2153 field3 & TRB_CYCLE ? 'C' : 'c');
2154 break;
2155 case TRB_SET_DEQ:
2156 snprintf(str, size,
2157 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2158 xhci_trb_type_string(type),
2159 field1, field0,
2160 TRB_TO_STREAM_ID(field2),
2161 TRB_TO_SLOT_ID(field3),
2162 TRB_TO_EP_ID(field3),
2163 field3 & TRB_CYCLE ? 'C' : 'c');
2164 break;
2165 case TRB_RESET_DEV:
2166 snprintf(str, size,
2167 "%s: slot %d flags %c",
2168 xhci_trb_type_string(type),
2169 TRB_TO_SLOT_ID(field3),
2170 field3 & TRB_CYCLE ? 'C' : 'c');
2171 break;
2172 case TRB_FORCE_EVENT:
2173 snprintf(str, size,
2174 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2175 xhci_trb_type_string(type),
2176 field1, field0,
2177 TRB_TO_VF_INTR_TARGET(field2),
2178 TRB_TO_VF_ID(field3),
2179 field3 & TRB_CYCLE ? 'C' : 'c');
2180 break;
2181 case TRB_SET_LT:
2182 snprintf(str, size,
2183 "%s: belt %d flags %c",
2184 xhci_trb_type_string(type),
2185 TRB_TO_BELT(field3),
2186 field3 & TRB_CYCLE ? 'C' : 'c');
2187 break;
2188 case TRB_GET_BW:
2189 snprintf(str, size,
2190 "%s: ctx %08x%08x slot %d speed %d flags %c",
2191 xhci_trb_type_string(type),
2192 field1, field0,
2193 TRB_TO_SLOT_ID(field3),
2194 TRB_TO_DEV_SPEED(field3),
2195 field3 & TRB_CYCLE ? 'C' : 'c');
2196 break;
2197 case TRB_FORCE_HEADER:
2198 snprintf(str, size,
2199 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2200 xhci_trb_type_string(type),
2201 field2, field1, field0 & 0xffffffe0,
2202 TRB_TO_PACKET_TYPE(field0),
2203 TRB_TO_ROOTHUB_PORT(field3),
2204 field3 & TRB_CYCLE ? 'C' : 'c');
2205 break;
2206 default:
2207 snprintf(str, size,
2208 "type '%s' -> raw %08x %08x %08x %08x",
2209 xhci_trb_type_string(type),
2210 field0, field1, field2, field3);
2211 }
2212
2213 return str;
2214 }
2215
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2216 static inline const char *xhci_decode_ctrl_ctx(char *str,
2217 unsigned long drop, unsigned long add)
2218 {
2219 unsigned int bit;
2220 int ret = 0;
2221
2222 str[0] = '\0';
2223
2224 if (drop) {
2225 ret = sprintf(str, "Drop:");
2226 for_each_set_bit(bit, &drop, 32)
2227 ret += sprintf(str + ret, " %d%s",
2228 bit / 2,
2229 bit % 2 ? "in":"out");
2230 ret += sprintf(str + ret, ", ");
2231 }
2232
2233 if (add) {
2234 ret += sprintf(str + ret, "Add:%s%s",
2235 (add & SLOT_FLAG) ? " slot":"",
2236 (add & EP0_FLAG) ? " ep0":"");
2237 add &= ~(SLOT_FLAG | EP0_FLAG);
2238 for_each_set_bit(bit, &add, 32)
2239 ret += sprintf(str + ret, " %d%s",
2240 bit / 2,
2241 bit % 2 ? "in":"out");
2242 }
2243 return str;
2244 }
2245
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2246 static inline const char *xhci_decode_slot_context(char *str,
2247 u32 info, u32 info2, u32 tt_info, u32 state)
2248 {
2249 u32 speed;
2250 u32 hub;
2251 u32 mtt;
2252 int ret = 0;
2253
2254 speed = info & DEV_SPEED;
2255 hub = info & DEV_HUB;
2256 mtt = info & DEV_MTT;
2257
2258 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2259 info & ROUTE_STRING_MASK,
2260 ({ char *s;
2261 switch (speed) {
2262 case SLOT_SPEED_FS:
2263 s = "full-speed";
2264 break;
2265 case SLOT_SPEED_LS:
2266 s = "low-speed";
2267 break;
2268 case SLOT_SPEED_HS:
2269 s = "high-speed";
2270 break;
2271 case SLOT_SPEED_SS:
2272 s = "super-speed";
2273 break;
2274 case SLOT_SPEED_SSP:
2275 s = "super-speed plus";
2276 break;
2277 default:
2278 s = "UNKNOWN speed";
2279 } s; }),
2280 mtt ? " multi-TT" : "",
2281 hub ? " Hub" : "",
2282 (info & LAST_CTX_MASK) >> 27,
2283 info2 & MAX_EXIT,
2284 DEVINFO_TO_ROOT_HUB_PORT(info2),
2285 DEVINFO_TO_MAX_PORTS(info2));
2286
2287 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2288 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2289 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2290 state & DEV_ADDR_MASK,
2291 xhci_slot_state_string(GET_SLOT_STATE(state)));
2292
2293 return str;
2294 }
2295
2296
xhci_portsc_link_state_string(u32 portsc)2297 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2298 {
2299 switch (portsc & PORT_PLS_MASK) {
2300 case XDEV_U0:
2301 return "U0";
2302 case XDEV_U1:
2303 return "U1";
2304 case XDEV_U2:
2305 return "U2";
2306 case XDEV_U3:
2307 return "U3";
2308 case XDEV_DISABLED:
2309 return "Disabled";
2310 case XDEV_RXDETECT:
2311 return "RxDetect";
2312 case XDEV_INACTIVE:
2313 return "Inactive";
2314 case XDEV_POLLING:
2315 return "Polling";
2316 case XDEV_RECOVERY:
2317 return "Recovery";
2318 case XDEV_HOT_RESET:
2319 return "Hot Reset";
2320 case XDEV_COMP_MODE:
2321 return "Compliance mode";
2322 case XDEV_TEST_MODE:
2323 return "Test mode";
2324 case XDEV_RESUME:
2325 return "Resume";
2326 default:
2327 break;
2328 }
2329 return "Unknown";
2330 }
2331
xhci_decode_portsc(char * str,u32 portsc)2332 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2333 {
2334 int ret;
2335
2336 ret = sprintf(str, "0x%08x ", portsc);
2337
2338 if (portsc == ~(u32)0)
2339 return str;
2340
2341 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ",
2342 portsc & PORT_POWER ? "Powered" : "Powered-off",
2343 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2344 portsc & PORT_PE ? "Enabled" : "Disabled",
2345 xhci_portsc_link_state_string(portsc),
2346 DEV_PORT_SPEED(portsc));
2347
2348 if (portsc & PORT_OC)
2349 ret += sprintf(str + ret, "OverCurrent ");
2350 if (portsc & PORT_RESET)
2351 ret += sprintf(str + ret, "In-Reset ");
2352
2353 ret += sprintf(str + ret, "Change: ");
2354 if (portsc & PORT_CSC)
2355 ret += sprintf(str + ret, "CSC ");
2356 if (portsc & PORT_PEC)
2357 ret += sprintf(str + ret, "PEC ");
2358 if (portsc & PORT_WRC)
2359 ret += sprintf(str + ret, "WRC ");
2360 if (portsc & PORT_OCC)
2361 ret += sprintf(str + ret, "OCC ");
2362 if (portsc & PORT_RC)
2363 ret += sprintf(str + ret, "PRC ");
2364 if (portsc & PORT_PLC)
2365 ret += sprintf(str + ret, "PLC ");
2366 if (portsc & PORT_CEC)
2367 ret += sprintf(str + ret, "CEC ");
2368 if (portsc & PORT_CAS)
2369 ret += sprintf(str + ret, "CAS ");
2370
2371 ret += sprintf(str + ret, "Wake: ");
2372 if (portsc & PORT_WKCONN_E)
2373 ret += sprintf(str + ret, "WCE ");
2374 if (portsc & PORT_WKDISC_E)
2375 ret += sprintf(str + ret, "WDE ");
2376 if (portsc & PORT_WKOC_E)
2377 ret += sprintf(str + ret, "WOE ");
2378
2379 return str;
2380 }
2381
xhci_decode_usbsts(char * str,u32 usbsts)2382 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2383 {
2384 int ret = 0;
2385
2386 ret = sprintf(str, " 0x%08x", usbsts);
2387
2388 if (usbsts == ~(u32)0)
2389 return str;
2390
2391 if (usbsts & STS_HALT)
2392 ret += sprintf(str + ret, " HCHalted");
2393 if (usbsts & STS_FATAL)
2394 ret += sprintf(str + ret, " HSE");
2395 if (usbsts & STS_EINT)
2396 ret += sprintf(str + ret, " EINT");
2397 if (usbsts & STS_PORT)
2398 ret += sprintf(str + ret, " PCD");
2399 if (usbsts & STS_SAVE)
2400 ret += sprintf(str + ret, " SSS");
2401 if (usbsts & STS_RESTORE)
2402 ret += sprintf(str + ret, " RSS");
2403 if (usbsts & STS_SRE)
2404 ret += sprintf(str + ret, " SRE");
2405 if (usbsts & STS_CNR)
2406 ret += sprintf(str + ret, " CNR");
2407 if (usbsts & STS_HCE)
2408 ret += sprintf(str + ret, " HCE");
2409
2410 return str;
2411 }
2412
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2413 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2414 {
2415 u8 ep;
2416 u16 stream;
2417 int ret;
2418
2419 ep = (doorbell & 0xff);
2420 stream = doorbell >> 16;
2421
2422 if (slot == 0) {
2423 sprintf(str, "Command Ring %d", doorbell);
2424 return str;
2425 }
2426 ret = sprintf(str, "Slot %d ", slot);
2427 if (ep > 0 && ep < 32)
2428 ret = sprintf(str + ret, "ep%d%s",
2429 ep / 2,
2430 ep % 2 ? "in" : "out");
2431 else if (ep == 0 || ep < 248)
2432 ret = sprintf(str + ret, "Reserved %d", ep);
2433 else
2434 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2435 if (stream)
2436 ret = sprintf(str + ret, " Stream %d", stream);
2437
2438 return str;
2439 }
2440
xhci_ep_state_string(u8 state)2441 static inline const char *xhci_ep_state_string(u8 state)
2442 {
2443 switch (state) {
2444 case EP_STATE_DISABLED:
2445 return "disabled";
2446 case EP_STATE_RUNNING:
2447 return "running";
2448 case EP_STATE_HALTED:
2449 return "halted";
2450 case EP_STATE_STOPPED:
2451 return "stopped";
2452 case EP_STATE_ERROR:
2453 return "error";
2454 default:
2455 return "INVALID";
2456 }
2457 }
2458
xhci_ep_type_string(u8 type)2459 static inline const char *xhci_ep_type_string(u8 type)
2460 {
2461 switch (type) {
2462 case ISOC_OUT_EP:
2463 return "Isoc OUT";
2464 case BULK_OUT_EP:
2465 return "Bulk OUT";
2466 case INT_OUT_EP:
2467 return "Int OUT";
2468 case CTRL_EP:
2469 return "Ctrl";
2470 case ISOC_IN_EP:
2471 return "Isoc IN";
2472 case BULK_IN_EP:
2473 return "Bulk IN";
2474 case INT_IN_EP:
2475 return "Int IN";
2476 default:
2477 return "INVALID";
2478 }
2479 }
2480
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2481 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2482 u32 info2, u64 deq, u32 tx_info)
2483 {
2484 int ret;
2485
2486 u32 esit;
2487 u16 maxp;
2488 u16 avg;
2489
2490 u8 max_pstr;
2491 u8 ep_state;
2492 u8 interval;
2493 u8 ep_type;
2494 u8 burst;
2495 u8 cerr;
2496 u8 mult;
2497
2498 bool lsa;
2499 bool hid;
2500
2501 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2502 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2503
2504 ep_state = info & EP_STATE_MASK;
2505 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2506 interval = CTX_TO_EP_INTERVAL(info);
2507 mult = CTX_TO_EP_MULT(info) + 1;
2508 lsa = !!(info & EP_HAS_LSA);
2509
2510 cerr = (info2 & (3 << 1)) >> 1;
2511 ep_type = CTX_TO_EP_TYPE(info2);
2512 hid = !!(info2 & (1 << 7));
2513 burst = CTX_TO_MAX_BURST(info2);
2514 maxp = MAX_PACKET_DECODED(info2);
2515
2516 avg = EP_AVG_TRB_LENGTH(tx_info);
2517
2518 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2519 xhci_ep_state_string(ep_state), mult,
2520 max_pstr, lsa ? "LSA " : "");
2521
2522 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2523 (1 << interval) * 125, esit, cerr);
2524
2525 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2526 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2527 burst, maxp, deq);
2528
2529 ret += sprintf(str + ret, "avg trb len %d", avg);
2530
2531 return str;
2532 }
2533
2534 #endif /* __LINUX_XHCI_HCD_H */
2535