1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 #include "xhci-port.h" 27 #include "xhci-caps.h" 28 29 /* max buffer size for trace and debug messages */ 30 #define XHCI_MSG_MAX 500 31 32 /* xHCI PCI Configuration Registers */ 33 #define XHCI_SBRN_OFFSET (0x60) 34 35 /* Max number of USB devices for any host controller - limit in section 6.1 */ 36 #define MAX_HC_SLOTS 256 37 /* Section 5.3.3 - MaxPorts */ 38 #define MAX_HC_PORTS 127 39 40 /* 41 * xHCI register interface. 42 * This corresponds to the eXtensible Host Controller Interface (xHCI) 43 * Revision 0.95 specification 44 */ 45 46 /** 47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 48 * @hc_capbase: length of the capabilities register and HC version number 49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 52 * @hcc_params: HCCPARAMS - Capability Parameters 53 * @db_off: DBOFF - Doorbell array offset 54 * @run_regs_off: RTSOFF - Runtime register space offset 55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 56 */ 57 struct xhci_cap_regs { 58 __le32 hc_capbase; 59 __le32 hcs_params1; 60 __le32 hcs_params2; 61 __le32 hcs_params3; 62 __le32 hcc_params; 63 __le32 db_off; 64 __le32 run_regs_off; 65 __le32 hcc_params2; /* xhci 1.1 */ 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* Number of registers per port */ 70 #define NUM_PORT_REGS 4 71 72 #define PORTSC 0 73 #define PORTPMSC 1 74 #define PORTLI 2 75 #define PORTHLPMC 3 76 77 /** 78 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 79 * @command: USBCMD - xHC command register 80 * @status: USBSTS - xHC status register 81 * @page_size: This indicates the page size that the host controller 82 * supports. If bit n is set, the HC supports a page size 83 * of 2^(n+12), up to a 128MB page size. 84 * 4K is the minimum page size. 85 * @cmd_ring: CRP - 64-bit Command Ring Pointer 86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 87 * @config_reg: CONFIG - Configure Register 88 * @port_status_base: PORTSCn - base address for Port Status and Control 89 * Each port has a Port Status and Control register, 90 * followed by a Port Power Management Status and Control 91 * register, a Port Link Info register, and a reserved 92 * register. 93 * @port_power_base: PORTPMSCn - base address for 94 * Port Power Management Status and Control 95 * @port_link_base: PORTLIn - base address for Port Link Info (current 96 * Link PM state and control) for USB 2.1 and USB 3.0 97 * devices. 98 */ 99 struct xhci_op_regs { 100 __le32 command; 101 __le32 status; 102 __le32 page_size; 103 __le32 reserved1; 104 __le32 reserved2; 105 __le32 dev_notification; 106 __le64 cmd_ring; 107 /* rsvd: offset 0x20-2F */ 108 __le32 reserved3[4]; 109 __le64 dcbaa_ptr; 110 __le32 config_reg; 111 /* rsvd: offset 0x3C-3FF */ 112 __le32 reserved4[241]; 113 /* port 1 registers, which serve as a base address for other ports */ 114 __le32 port_status_base; 115 __le32 port_power_base; 116 __le32 port_link_base; 117 __le32 reserved5; 118 /* registers for ports 2-255 */ 119 __le32 reserved6[NUM_PORT_REGS*254]; 120 }; 121 122 /* USBCMD - USB command - command bitmasks */ 123 /* start/stop HC execution - do not write unless HC is halted*/ 124 #define CMD_RUN XHCI_CMD_RUN 125 /* Reset HC - resets internal HC state machine and all registers (except 126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 127 * The xHCI driver must reinitialize the xHC after setting this bit. 128 */ 129 #define CMD_RESET (1 << 1) 130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 131 #define CMD_EIE XHCI_CMD_EIE 132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 133 #define CMD_HSEIE XHCI_CMD_HSEIE 134 /* bits 4:6 are reserved (and should be preserved on writes). */ 135 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 136 #define CMD_LRESET (1 << 7) 137 /* host controller save/restore state. */ 138 #define CMD_CSS (1 << 8) 139 #define CMD_CRS (1 << 9) 140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 141 #define CMD_EWE XHCI_CMD_EWE 142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 144 * '0' means the xHC can power it off if all ports are in the disconnect, 145 * disabled, or powered-off state. 146 */ 147 #define CMD_PM_INDEX (1 << 11) 148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 149 #define CMD_ETE (1 << 14) 150 /* bits 15:31 are reserved (and should be preserved on writes). */ 151 152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 153 #define XHCI_RESET_SHORT_USEC (250 * 1000) 154 155 /* IMAN - Interrupt Management Register */ 156 #define IMAN_IE (1 << 1) 157 #define IMAN_IP (1 << 0) 158 159 /* USBSTS - USB status - status bitmasks */ 160 /* HC not running - set to 1 when run/stop bit is cleared. */ 161 #define STS_HALT XHCI_STS_HALT 162 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 163 #define STS_FATAL (1 << 2) 164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 165 #define STS_EINT (1 << 3) 166 /* port change detect */ 167 #define STS_PORT (1 << 4) 168 /* bits 5:7 reserved and zeroed */ 169 /* save state status - '1' means xHC is saving state */ 170 #define STS_SAVE (1 << 8) 171 /* restore state status - '1' means xHC is restoring state */ 172 #define STS_RESTORE (1 << 9) 173 /* true: save or restore error */ 174 #define STS_SRE (1 << 10) 175 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 176 #define STS_CNR XHCI_STS_CNR 177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 178 #define STS_HCE (1 << 12) 179 /* bits 13:31 reserved and should be preserved */ 180 181 /* 182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 183 * Generate a device notification event when the HC sees a transaction with a 184 * notification type that matches a bit set in this bit field. 185 */ 186 #define DEV_NOTE_MASK (0xffff) 187 #define ENABLE_DEV_NOTE(x) (1 << (x)) 188 /* Most of the device notification types should only be used for debug. 189 * SW does need to pay attention to function wake notifications. 190 */ 191 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 192 193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 194 /* bit 0 is the command ring cycle state */ 195 /* stop ring operation after completion of the currently executing command */ 196 #define CMD_RING_PAUSE (1 << 1) 197 /* stop ring immediately - abort the currently executing command */ 198 #define CMD_RING_ABORT (1 << 2) 199 /* true: command ring is running */ 200 #define CMD_RING_RUNNING (1 << 3) 201 /* bits 4:5 reserved and should be preserved */ 202 /* Command Ring pointer - bit mask for the lower 32 bits. */ 203 #define CMD_RING_RSVD_BITS (0x3f) 204 205 /* CONFIG - Configure Register - config_reg bitmasks */ 206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 207 #define MAX_DEVS(p) ((p) & 0xff) 208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 209 #define CONFIG_U3E (1 << 8) 210 /* bit 9: Configuration Information Enable, xhci 1.1 */ 211 #define CONFIG_CIE (1 << 9) 212 /* bits 10:31 - reserved and should be preserved */ 213 214 /** 215 * struct xhci_intr_reg - Interrupt Register Set 216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 217 * interrupts and check for pending interrupts. 218 * @irq_control: IMOD - Interrupt Moderation Register. 219 * Used to throttle interrupts. 220 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 221 * @erst_base: ERST base address. 222 * @erst_dequeue: Event ring dequeue pointer. 223 * 224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 225 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 226 * multiple segments of the same size. The HC places events on the ring and 227 * "updates the Cycle bit in the TRBs to indicate to software the current 228 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 229 * updates the dequeue pointer. 230 */ 231 struct xhci_intr_reg { 232 __le32 irq_pending; 233 __le32 irq_control; 234 __le32 erst_size; 235 __le32 rsvd; 236 __le64 erst_base; 237 __le64 erst_dequeue; 238 }; 239 240 /* irq_pending bitmasks */ 241 #define ER_IRQ_PENDING(p) ((p) & 0x1) 242 /* bits 2:31 need to be preserved */ 243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 244 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 245 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 246 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 247 248 /* irq_control bitmasks */ 249 /* Minimum interval between interrupts (in 250ns intervals). The interval 250 * between interrupts will be longer if there are no events on the event ring. 251 * Default is 4000 (1 ms). 252 */ 253 #define ER_IRQ_INTERVAL_MASK (0xffff) 254 /* Counter used to count down the time to the next interrupt - HW use only */ 255 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 256 257 /* erst_size bitmasks */ 258 /* Preserve bits 16:31 of erst_size */ 259 #define ERST_SIZE_MASK (0xffff << 16) 260 261 /* erst_base bitmasks */ 262 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) 263 264 /* erst_dequeue bitmasks */ 265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 266 * where the current dequeue pointer lies. This is an optional HW hint. 267 */ 268 #define ERST_DESI_MASK (0x7) 269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 270 * a work queue (or delayed service routine)? 271 */ 272 #define ERST_EHB (1 << 3) 273 #define ERST_PTR_MASK (GENMASK_ULL(63, 4)) 274 275 /** 276 * struct xhci_run_regs 277 * @microframe_index: 278 * MFINDEX - current microframe number 279 * 280 * Section 5.5 Host Controller Runtime Registers: 281 * "Software should read and write these registers using only Dword (32 bit) 282 * or larger accesses" 283 */ 284 struct xhci_run_regs { 285 __le32 microframe_index; 286 __le32 rsvd[7]; 287 struct xhci_intr_reg ir_set[128]; 288 }; 289 290 /** 291 * struct doorbell_array 292 * 293 * Bits 0 - 7: Endpoint target 294 * Bits 8 - 15: RsvdZ 295 * Bits 16 - 31: Stream ID 296 * 297 * Section 5.6 298 */ 299 struct xhci_doorbell_array { 300 __le32 doorbell[256]; 301 }; 302 303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 304 #define DB_VALUE_HOST 0x00000000 305 306 #define PLT_MASK (0x03 << 6) 307 #define PLT_SYM (0x00 << 6) 308 #define PLT_ASYM_RX (0x02 << 6) 309 #define PLT_ASYM_TX (0x03 << 6) 310 311 /** 312 * struct xhci_container_ctx 313 * @type: Type of context. Used to calculated offsets to contained contexts. 314 * @size: Size of the context data 315 * @bytes: The raw context data given to HW 316 * @dma: dma address of the bytes 317 * 318 * Represents either a Device or Input context. Holds a pointer to the raw 319 * memory used for the context (bytes) and dma address of it (dma). 320 */ 321 struct xhci_container_ctx { 322 unsigned type; 323 #define XHCI_CTX_TYPE_DEVICE 0x1 324 #define XHCI_CTX_TYPE_INPUT 0x2 325 326 int size; 327 328 u8 *bytes; 329 dma_addr_t dma; 330 }; 331 332 /** 333 * struct xhci_slot_ctx 334 * @dev_info: Route string, device speed, hub info, and last valid endpoint 335 * @dev_info2: Max exit latency for device number, root hub port number 336 * @tt_info: tt_info is used to construct split transaction tokens 337 * @dev_state: slot state and device address 338 * 339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 341 * reserved at the end of the slot context for HC internal use. 342 */ 343 struct xhci_slot_ctx { 344 __le32 dev_info; 345 __le32 dev_info2; 346 __le32 tt_info; 347 __le32 dev_state; 348 /* offset 0x10 to 0x1f reserved for HC internal use */ 349 __le32 reserved[4]; 350 }; 351 352 /* dev_info bitmasks */ 353 /* Route String - 0:19 */ 354 #define ROUTE_STRING_MASK (0xfffff) 355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 356 #define DEV_SPEED (0xf << 20) 357 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 358 /* bit 24 reserved */ 359 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 360 #define DEV_MTT (0x1 << 25) 361 /* Set if the device is a hub - bit 26 */ 362 #define DEV_HUB (0x1 << 26) 363 /* Index of the last valid endpoint context in this device context - 27:31 */ 364 #define LAST_CTX_MASK (0x1f << 27) 365 #define LAST_CTX(p) ((p) << 27) 366 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 367 #define SLOT_FLAG (1 << 0) 368 #define EP0_FLAG (1 << 1) 369 370 /* dev_info2 bitmasks */ 371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 372 #define MAX_EXIT (0xffff) 373 /* Root hub port number that is needed to access the USB device */ 374 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 375 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 376 /* Maximum number of ports under a hub device */ 377 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 378 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 379 380 /* tt_info bitmasks */ 381 /* 382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 383 * The Slot ID of the hub that isolates the high speed signaling from 384 * this low or full-speed device. '0' if attached to root hub port. 385 */ 386 #define TT_SLOT (0xff) 387 /* 388 * The number of the downstream facing port of the high-speed hub 389 * '0' if the device is not low or full speed. 390 */ 391 #define TT_PORT (0xff << 8) 392 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 393 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 394 395 /* dev_state bitmasks */ 396 /* USB device address - assigned by the HC */ 397 #define DEV_ADDR_MASK (0xff) 398 /* bits 8:26 reserved */ 399 /* Slot state */ 400 #define SLOT_STATE (0x1f << 27) 401 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 402 403 #define SLOT_STATE_DISABLED 0 404 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 405 #define SLOT_STATE_DEFAULT 1 406 #define SLOT_STATE_ADDRESSED 2 407 #define SLOT_STATE_CONFIGURED 3 408 409 /** 410 * struct xhci_ep_ctx 411 * @ep_info: endpoint state, streams, mult, and interval information. 412 * @ep_info2: information on endpoint type, max packet size, max burst size, 413 * error count, and whether the HC will force an event for all 414 * transactions. 415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 416 * defines one stream, this points to the endpoint transfer ring. 417 * Otherwise, it points to a stream context array, which has a 418 * ring pointer for each flow. 419 * @tx_info: 420 * Average TRB lengths for the endpoint ring and 421 * max payload within an Endpoint Service Interval Time (ESIT). 422 * 423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 425 * reserved at the end of the endpoint context for HC internal use. 426 */ 427 struct xhci_ep_ctx { 428 __le32 ep_info; 429 __le32 ep_info2; 430 __le64 deq; 431 __le32 tx_info; 432 /* offset 0x14 - 0x1f reserved for HC internal use */ 433 __le32 reserved[3]; 434 }; 435 436 /* ep_info bitmasks */ 437 /* 438 * Endpoint State - bits 0:2 439 * 0 - disabled 440 * 1 - running 441 * 2 - halted due to halt condition - ok to manipulate endpoint ring 442 * 3 - stopped 443 * 4 - TRB error 444 * 5-7 - reserved 445 */ 446 #define EP_STATE_MASK (0x7) 447 #define EP_STATE_DISABLED 0 448 #define EP_STATE_RUNNING 1 449 #define EP_STATE_HALTED 2 450 #define EP_STATE_STOPPED 3 451 #define EP_STATE_ERROR 4 452 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 453 454 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 455 #define EP_MULT(p) (((p) & 0x3) << 8) 456 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 457 /* bits 10:14 are Max Primary Streams */ 458 /* bit 15 is Linear Stream Array */ 459 /* Interval - period between requests to an endpoint - 125u increments. */ 460 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 461 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 462 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 463 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 464 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 465 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 466 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 467 #define EP_HAS_LSA (1 << 15) 468 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 469 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 470 471 /* ep_info2 bitmasks */ 472 /* 473 * Force Event - generate transfer events for all TRBs for this endpoint 474 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 475 */ 476 #define FORCE_EVENT (0x1) 477 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 478 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 479 #define EP_TYPE(p) ((p) << 3) 480 #define ISOC_OUT_EP 1 481 #define BULK_OUT_EP 2 482 #define INT_OUT_EP 3 483 #define CTRL_EP 4 484 #define ISOC_IN_EP 5 485 #define BULK_IN_EP 6 486 #define INT_IN_EP 7 487 /* bit 6 reserved */ 488 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 489 #define MAX_BURST(p) (((p)&0xff) << 8) 490 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 491 #define MAX_PACKET(p) (((p)&0xffff) << 16) 492 #define MAX_PACKET_MASK (0xffff << 16) 493 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 494 495 /* tx_info bitmasks */ 496 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 497 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 498 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 499 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 500 501 /* deq bitmasks */ 502 #define EP_CTX_CYCLE_MASK (1 << 0) 503 #define SCTX_DEQ_MASK (~0xfL) 504 505 506 /** 507 * struct xhci_input_control_context 508 * Input control context; see section 6.2.5. 509 * 510 * @drop_context: set the bit of the endpoint context you want to disable 511 * @add_context: set the bit of the endpoint context you want to enable 512 */ 513 struct xhci_input_control_ctx { 514 __le32 drop_flags; 515 __le32 add_flags; 516 __le32 rsvd2[6]; 517 }; 518 519 #define EP_IS_ADDED(ctrl_ctx, i) \ 520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 521 #define EP_IS_DROPPED(ctrl_ctx, i) \ 522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 523 524 /* Represents everything that is needed to issue a command on the command ring. 525 * It's useful to pre-allocate these for commands that cannot fail due to 526 * out-of-memory errors, like freeing streams. 527 */ 528 struct xhci_command { 529 /* Input context for changing device state */ 530 struct xhci_container_ctx *in_ctx; 531 u32 status; 532 u32 comp_param; 533 int slot_id; 534 /* If completion is null, no one is waiting on this command 535 * and the structure can be freed after the command completes. 536 */ 537 struct completion *completion; 538 union xhci_trb *command_trb; 539 struct list_head cmd_list; 540 /* xHCI command response timeout in milliseconds */ 541 unsigned int timeout_ms; 542 }; 543 544 /* drop context bitmasks */ 545 #define DROP_EP(x) (0x1 << x) 546 /* add context bitmasks */ 547 #define ADD_EP(x) (0x1 << x) 548 549 struct xhci_stream_ctx { 550 /* 64-bit stream ring address, cycle state, and stream type */ 551 __le64 stream_ring; 552 /* offset 0x14 - 0x1f reserved for HC internal use */ 553 __le32 reserved[2]; 554 }; 555 556 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 557 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 558 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 559 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 560 #define SCT_SEC_TR 0 561 /* Primary stream array type, dequeue pointer is to a transfer ring */ 562 #define SCT_PRI_TR 1 563 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 564 #define SCT_SSA_8 2 565 #define SCT_SSA_16 3 566 #define SCT_SSA_32 4 567 #define SCT_SSA_64 5 568 #define SCT_SSA_128 6 569 #define SCT_SSA_256 7 570 571 /* Assume no secondary streams for now */ 572 struct xhci_stream_info { 573 struct xhci_ring **stream_rings; 574 /* Number of streams, including stream 0 (which drivers can't use) */ 575 unsigned int num_streams; 576 /* The stream context array may be bigger than 577 * the number of streams the driver asked for 578 */ 579 struct xhci_stream_ctx *stream_ctx_array; 580 unsigned int num_stream_ctxs; 581 dma_addr_t ctx_array_dma; 582 /* For mapping physical TRB addresses to segments in stream rings */ 583 struct radix_tree_root trb_address_map; 584 struct xhci_command *free_streams_command; 585 }; 586 587 #define SMALL_STREAM_ARRAY_SIZE 256 588 #define MEDIUM_STREAM_ARRAY_SIZE 1024 589 590 /* Some Intel xHCI host controllers need software to keep track of the bus 591 * bandwidth. Keep track of endpoint info here. Each root port is allocated 592 * the full bus bandwidth. We must also treat TTs (including each port under a 593 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 594 * (DMI) also limits the total bandwidth (across all domains) that can be used. 595 */ 596 struct xhci_bw_info { 597 /* ep_interval is zero-based */ 598 unsigned int ep_interval; 599 /* mult and num_packets are one-based */ 600 unsigned int mult; 601 unsigned int num_packets; 602 unsigned int max_packet_size; 603 unsigned int max_esit_payload; 604 unsigned int type; 605 }; 606 607 /* "Block" sizes in bytes the hardware uses for different device speeds. 608 * The logic in this part of the hardware limits the number of bits the hardware 609 * can use, so must represent bandwidth in a less precise manner to mimic what 610 * the scheduler hardware computes. 611 */ 612 #define FS_BLOCK 1 613 #define HS_BLOCK 4 614 #define SS_BLOCK 16 615 #define DMI_BLOCK 32 616 617 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 618 * with each byte transferred. SuperSpeed devices have an initial overhead to 619 * set up bursts. These are in blocks, see above. LS overhead has already been 620 * translated into FS blocks. 621 */ 622 #define DMI_OVERHEAD 8 623 #define DMI_OVERHEAD_BURST 4 624 #define SS_OVERHEAD 8 625 #define SS_OVERHEAD_BURST 32 626 #define HS_OVERHEAD 26 627 #define FS_OVERHEAD 20 628 #define LS_OVERHEAD 128 629 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 630 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 631 * of overhead associated with split transfers crossing microframe boundaries. 632 * 31 blocks is pure protocol overhead. 633 */ 634 #define TT_HS_OVERHEAD (31 + 94) 635 #define TT_DMI_OVERHEAD (25 + 12) 636 637 /* Bandwidth limits in blocks */ 638 #define FS_BW_LIMIT 1285 639 #define TT_BW_LIMIT 1320 640 #define HS_BW_LIMIT 1607 641 #define SS_BW_LIMIT_IN 3906 642 #define DMI_BW_LIMIT_IN 3906 643 #define SS_BW_LIMIT_OUT 3906 644 #define DMI_BW_LIMIT_OUT 3906 645 646 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 647 #define FS_BW_RESERVED 10 648 #define HS_BW_RESERVED 20 649 #define SS_BW_RESERVED 10 650 651 struct xhci_virt_ep { 652 struct xhci_virt_device *vdev; /* parent */ 653 unsigned int ep_index; 654 struct xhci_ring *ring; 655 /* Related to endpoints that are configured to use stream IDs only */ 656 struct xhci_stream_info *stream_info; 657 /* Temporary storage in case the configure endpoint command fails and we 658 * have to restore the device state to the previous state 659 */ 660 struct xhci_ring *new_ring; 661 unsigned int err_count; 662 unsigned int ep_state; 663 #define SET_DEQ_PENDING (1 << 0) 664 #define EP_HALTED (1 << 1) /* For stall handling */ 665 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 666 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 667 #define EP_GETTING_STREAMS (1 << 3) 668 #define EP_HAS_STREAMS (1 << 4) 669 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 670 #define EP_GETTING_NO_STREAMS (1 << 5) 671 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 672 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 673 /* usb_hub_clear_tt_buffer is in progress */ 674 #define EP_CLEARING_TT (1 << 8) 675 /* ---- Related to URB cancellation ---- */ 676 struct list_head cancelled_td_list; 677 struct xhci_hcd *xhci; 678 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 679 * command. We'll need to update the ring's dequeue segment and dequeue 680 * pointer after the command completes. 681 */ 682 struct xhci_segment *queued_deq_seg; 683 union xhci_trb *queued_deq_ptr; 684 /* 685 * Sometimes the xHC can not process isochronous endpoint ring quickly 686 * enough, and it will miss some isoc tds on the ring and generate 687 * a Missed Service Error Event. 688 * Set skip flag when receive a Missed Service Error Event and 689 * process the missed tds on the endpoint ring. 690 */ 691 bool skip; 692 /* Bandwidth checking storage */ 693 struct xhci_bw_info bw_info; 694 struct list_head bw_endpoint_list; 695 unsigned long stop_time; 696 /* Isoch Frame ID checking storage */ 697 int next_frame_id; 698 /* Use new Isoch TRB layout needed for extended TBC support */ 699 bool use_extended_tbc; 700 }; 701 702 enum xhci_overhead_type { 703 LS_OVERHEAD_TYPE = 0, 704 FS_OVERHEAD_TYPE, 705 HS_OVERHEAD_TYPE, 706 }; 707 708 struct xhci_interval_bw { 709 unsigned int num_packets; 710 /* Sorted by max packet size. 711 * Head of the list is the greatest max packet size. 712 */ 713 struct list_head endpoints; 714 /* How many endpoints of each speed are present. */ 715 unsigned int overhead[3]; 716 }; 717 718 #define XHCI_MAX_INTERVAL 16 719 720 struct xhci_interval_bw_table { 721 unsigned int interval0_esit_payload; 722 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 723 /* Includes reserved bandwidth for async endpoints */ 724 unsigned int bw_used; 725 unsigned int ss_bw_in; 726 unsigned int ss_bw_out; 727 }; 728 729 #define EP_CTX_PER_DEV 31 730 731 struct xhci_virt_device { 732 int slot_id; 733 struct usb_device *udev; 734 /* 735 * Commands to the hardware are passed an "input context" that 736 * tells the hardware what to change in its data structures. 737 * The hardware will return changes in an "output context" that 738 * software must allocate for the hardware. We need to keep 739 * track of input and output contexts separately because 740 * these commands might fail and we don't trust the hardware. 741 */ 742 struct xhci_container_ctx *out_ctx; 743 /* Used for addressing devices and configuration changes */ 744 struct xhci_container_ctx *in_ctx; 745 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 746 struct xhci_port *rhub_port; 747 struct xhci_interval_bw_table *bw_table; 748 struct xhci_tt_bw_info *tt_info; 749 /* 750 * flags for state tracking based on events and issued commands. 751 * Software can not rely on states from output contexts because of 752 * latency between events and xHC updating output context values. 753 * See xhci 1.1 section 4.8.3 for more details 754 */ 755 unsigned long flags; 756 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 757 758 /* The current max exit latency for the enabled USB3 link states. */ 759 u16 current_mel; 760 /* Used for the debugfs interfaces. */ 761 void *debugfs_private; 762 }; 763 764 /* 765 * For each roothub, keep track of the bandwidth information for each periodic 766 * interval. 767 * 768 * If a high speed hub is attached to the roothub, each TT associated with that 769 * hub is a separate bandwidth domain. The interval information for the 770 * endpoints on the devices under that TT will appear in the TT structure. 771 */ 772 struct xhci_root_port_bw_info { 773 struct list_head tts; 774 unsigned int num_active_tts; 775 struct xhci_interval_bw_table bw_table; 776 }; 777 778 struct xhci_tt_bw_info { 779 struct list_head tt_list; 780 int slot_id; 781 int ttport; 782 struct xhci_interval_bw_table bw_table; 783 int active_eps; 784 }; 785 786 787 /** 788 * struct xhci_device_context_array 789 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 790 */ 791 struct xhci_device_context_array { 792 /* 64-bit device addresses; we only write 32-bit addresses */ 793 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 794 /* private xHCD pointers */ 795 dma_addr_t dma; 796 }; 797 /* TODO: write function to set the 64-bit device DMA address */ 798 /* 799 * TODO: change this to be dynamically sized at HC mem init time since the HC 800 * might not be able to handle the maximum number of devices possible. 801 */ 802 803 804 struct xhci_transfer_event { 805 /* 64-bit buffer address, or immediate data */ 806 __le64 buffer; 807 __le32 transfer_len; 808 /* This field is interpreted differently based on the type of TRB */ 809 __le32 flags; 810 }; 811 812 /* Transfer event flags bitfield, also for select command completion events */ 813 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 814 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 815 816 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 817 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 818 819 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 820 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 821 822 /* Transfer event TRB length bit mask */ 823 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 824 825 /* Completion Code - only applicable for some types of TRBs */ 826 #define COMP_CODE_MASK (0xff << 24) 827 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 828 #define COMP_INVALID 0 829 #define COMP_SUCCESS 1 830 #define COMP_DATA_BUFFER_ERROR 2 831 #define COMP_BABBLE_DETECTED_ERROR 3 832 #define COMP_USB_TRANSACTION_ERROR 4 833 #define COMP_TRB_ERROR 5 834 #define COMP_STALL_ERROR 6 835 #define COMP_RESOURCE_ERROR 7 836 #define COMP_BANDWIDTH_ERROR 8 837 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 838 #define COMP_INVALID_STREAM_TYPE_ERROR 10 839 #define COMP_SLOT_NOT_ENABLED_ERROR 11 840 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 841 #define COMP_SHORT_PACKET 13 842 #define COMP_RING_UNDERRUN 14 843 #define COMP_RING_OVERRUN 15 844 #define COMP_VF_EVENT_RING_FULL_ERROR 16 845 #define COMP_PARAMETER_ERROR 17 846 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 847 #define COMP_CONTEXT_STATE_ERROR 19 848 #define COMP_NO_PING_RESPONSE_ERROR 20 849 #define COMP_EVENT_RING_FULL_ERROR 21 850 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 851 #define COMP_MISSED_SERVICE_ERROR 23 852 #define COMP_COMMAND_RING_STOPPED 24 853 #define COMP_COMMAND_ABORTED 25 854 #define COMP_STOPPED 26 855 #define COMP_STOPPED_LENGTH_INVALID 27 856 #define COMP_STOPPED_SHORT_PACKET 28 857 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 858 #define COMP_ISOCH_BUFFER_OVERRUN 31 859 #define COMP_EVENT_LOST_ERROR 32 860 #define COMP_UNDEFINED_ERROR 33 861 #define COMP_INVALID_STREAM_ID_ERROR 34 862 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 863 #define COMP_SPLIT_TRANSACTION_ERROR 36 864 865 static inline const char *xhci_trb_comp_code_string(u8 status) 866 { 867 switch (status) { 868 case COMP_INVALID: 869 return "Invalid"; 870 case COMP_SUCCESS: 871 return "Success"; 872 case COMP_DATA_BUFFER_ERROR: 873 return "Data Buffer Error"; 874 case COMP_BABBLE_DETECTED_ERROR: 875 return "Babble Detected"; 876 case COMP_USB_TRANSACTION_ERROR: 877 return "USB Transaction Error"; 878 case COMP_TRB_ERROR: 879 return "TRB Error"; 880 case COMP_STALL_ERROR: 881 return "Stall Error"; 882 case COMP_RESOURCE_ERROR: 883 return "Resource Error"; 884 case COMP_BANDWIDTH_ERROR: 885 return "Bandwidth Error"; 886 case COMP_NO_SLOTS_AVAILABLE_ERROR: 887 return "No Slots Available Error"; 888 case COMP_INVALID_STREAM_TYPE_ERROR: 889 return "Invalid Stream Type Error"; 890 case COMP_SLOT_NOT_ENABLED_ERROR: 891 return "Slot Not Enabled Error"; 892 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 893 return "Endpoint Not Enabled Error"; 894 case COMP_SHORT_PACKET: 895 return "Short Packet"; 896 case COMP_RING_UNDERRUN: 897 return "Ring Underrun"; 898 case COMP_RING_OVERRUN: 899 return "Ring Overrun"; 900 case COMP_VF_EVENT_RING_FULL_ERROR: 901 return "VF Event Ring Full Error"; 902 case COMP_PARAMETER_ERROR: 903 return "Parameter Error"; 904 case COMP_BANDWIDTH_OVERRUN_ERROR: 905 return "Bandwidth Overrun Error"; 906 case COMP_CONTEXT_STATE_ERROR: 907 return "Context State Error"; 908 case COMP_NO_PING_RESPONSE_ERROR: 909 return "No Ping Response Error"; 910 case COMP_EVENT_RING_FULL_ERROR: 911 return "Event Ring Full Error"; 912 case COMP_INCOMPATIBLE_DEVICE_ERROR: 913 return "Incompatible Device Error"; 914 case COMP_MISSED_SERVICE_ERROR: 915 return "Missed Service Error"; 916 case COMP_COMMAND_RING_STOPPED: 917 return "Command Ring Stopped"; 918 case COMP_COMMAND_ABORTED: 919 return "Command Aborted"; 920 case COMP_STOPPED: 921 return "Stopped"; 922 case COMP_STOPPED_LENGTH_INVALID: 923 return "Stopped - Length Invalid"; 924 case COMP_STOPPED_SHORT_PACKET: 925 return "Stopped - Short Packet"; 926 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 927 return "Max Exit Latency Too Large Error"; 928 case COMP_ISOCH_BUFFER_OVERRUN: 929 return "Isoch Buffer Overrun"; 930 case COMP_EVENT_LOST_ERROR: 931 return "Event Lost Error"; 932 case COMP_UNDEFINED_ERROR: 933 return "Undefined Error"; 934 case COMP_INVALID_STREAM_ID_ERROR: 935 return "Invalid Stream ID Error"; 936 case COMP_SECONDARY_BANDWIDTH_ERROR: 937 return "Secondary Bandwidth Error"; 938 case COMP_SPLIT_TRANSACTION_ERROR: 939 return "Split Transaction Error"; 940 default: 941 return "Unknown!!"; 942 } 943 } 944 945 struct xhci_link_trb { 946 /* 64-bit segment pointer*/ 947 __le64 segment_ptr; 948 __le32 intr_target; 949 __le32 control; 950 }; 951 952 /* control bitfields */ 953 #define LINK_TOGGLE (0x1<<1) 954 955 /* Command completion event TRB */ 956 struct xhci_event_cmd { 957 /* Pointer to command TRB, or the value passed by the event data trb */ 958 __le64 cmd_trb; 959 __le32 status; 960 __le32 flags; 961 }; 962 963 /* status bitmasks */ 964 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 965 966 /* Address device - disable SetAddress */ 967 #define TRB_BSR (1<<9) 968 969 /* Configure Endpoint - Deconfigure */ 970 #define TRB_DC (1<<9) 971 972 /* Stop Ring - Transfer State Preserve */ 973 #define TRB_TSP (1<<9) 974 975 enum xhci_ep_reset_type { 976 EP_HARD_RESET, 977 EP_SOFT_RESET, 978 }; 979 980 /* Force Event */ 981 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 982 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 983 984 /* Set Latency Tolerance Value */ 985 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 986 987 /* Get Port Bandwidth */ 988 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 989 990 /* Force Header */ 991 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 992 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 993 994 enum xhci_setup_dev { 995 SETUP_CONTEXT_ONLY, 996 SETUP_CONTEXT_ADDRESS, 997 }; 998 999 /* bits 16:23 are the virtual function ID */ 1000 /* bits 24:31 are the slot ID */ 1001 1002 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1003 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1004 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1005 #define LAST_EP_INDEX 30 1006 1007 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1008 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1009 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1010 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1011 1012 /* Link TRB specific fields */ 1013 #define TRB_TC (1<<1) 1014 1015 /* Port Status Change Event TRB fields */ 1016 /* Port ID - bits 31:24 */ 1017 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1018 1019 #define EVENT_DATA (1 << 2) 1020 1021 /* Normal TRB fields */ 1022 /* transfer_len bitmasks - bits 0:16 */ 1023 #define TRB_LEN(p) ((p) & 0x1ffff) 1024 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1025 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1026 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1027 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1028 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1029 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1030 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1031 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1032 1033 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1034 #define TRB_CYCLE (1<<0) 1035 /* 1036 * Force next event data TRB to be evaluated before task switch. 1037 * Used to pass OS data back after a TD completes. 1038 */ 1039 #define TRB_ENT (1<<1) 1040 /* Interrupt on short packet */ 1041 #define TRB_ISP (1<<2) 1042 /* Set PCIe no snoop attribute */ 1043 #define TRB_NO_SNOOP (1<<3) 1044 /* Chain multiple TRBs into a TD */ 1045 #define TRB_CHAIN (1<<4) 1046 /* Interrupt on completion */ 1047 #define TRB_IOC (1<<5) 1048 /* The buffer pointer contains immediate data */ 1049 #define TRB_IDT (1<<6) 1050 /* TDs smaller than this might use IDT */ 1051 #define TRB_IDT_MAX_SIZE 8 1052 1053 /* Block Event Interrupt */ 1054 #define TRB_BEI (1<<9) 1055 1056 /* Control transfer TRB specific fields */ 1057 #define TRB_DIR_IN (1<<16) 1058 #define TRB_TX_TYPE(p) ((p) << 16) 1059 #define TRB_DATA_OUT 2 1060 #define TRB_DATA_IN 3 1061 1062 /* Isochronous TRB specific fields */ 1063 #define TRB_SIA (1<<31) 1064 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1065 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1066 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1067 #define TRB_TBC(p) (((p) & 0x3) << 7) 1068 #define GET_TBC(p) (((p) >> 7) & 0x3) 1069 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1070 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1071 1072 /* TRB cache size for xHC with TRB cache */ 1073 #define TRB_CACHE_SIZE_HS 8 1074 #define TRB_CACHE_SIZE_SS 16 1075 1076 struct xhci_generic_trb { 1077 __le32 field[4]; 1078 }; 1079 1080 union xhci_trb { 1081 struct xhci_link_trb link; 1082 struct xhci_transfer_event trans_event; 1083 struct xhci_event_cmd event_cmd; 1084 struct xhci_generic_trb generic; 1085 }; 1086 1087 /* TRB bit mask */ 1088 #define TRB_TYPE_BITMASK (0xfc00) 1089 #define TRB_TYPE(p) ((p) << 10) 1090 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1091 /* TRB type IDs */ 1092 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1093 #define TRB_NORMAL 1 1094 /* setup stage for control transfers */ 1095 #define TRB_SETUP 2 1096 /* data stage for control transfers */ 1097 #define TRB_DATA 3 1098 /* status stage for control transfers */ 1099 #define TRB_STATUS 4 1100 /* isoc transfers */ 1101 #define TRB_ISOC 5 1102 /* TRB for linking ring segments */ 1103 #define TRB_LINK 6 1104 #define TRB_EVENT_DATA 7 1105 /* Transfer Ring No-op (not for the command ring) */ 1106 #define TRB_TR_NOOP 8 1107 /* Command TRBs */ 1108 /* Enable Slot Command */ 1109 #define TRB_ENABLE_SLOT 9 1110 /* Disable Slot Command */ 1111 #define TRB_DISABLE_SLOT 10 1112 /* Address Device Command */ 1113 #define TRB_ADDR_DEV 11 1114 /* Configure Endpoint Command */ 1115 #define TRB_CONFIG_EP 12 1116 /* Evaluate Context Command */ 1117 #define TRB_EVAL_CONTEXT 13 1118 /* Reset Endpoint Command */ 1119 #define TRB_RESET_EP 14 1120 /* Stop Transfer Ring Command */ 1121 #define TRB_STOP_RING 15 1122 /* Set Transfer Ring Dequeue Pointer Command */ 1123 #define TRB_SET_DEQ 16 1124 /* Reset Device Command */ 1125 #define TRB_RESET_DEV 17 1126 /* Force Event Command (opt) */ 1127 #define TRB_FORCE_EVENT 18 1128 /* Negotiate Bandwidth Command (opt) */ 1129 #define TRB_NEG_BANDWIDTH 19 1130 /* Set Latency Tolerance Value Command (opt) */ 1131 #define TRB_SET_LT 20 1132 /* Get port bandwidth Command */ 1133 #define TRB_GET_BW 21 1134 /* Force Header Command - generate a transaction or link management packet */ 1135 #define TRB_FORCE_HEADER 22 1136 /* No-op Command - not for transfer rings */ 1137 #define TRB_CMD_NOOP 23 1138 /* TRB IDs 24-31 reserved */ 1139 /* Event TRBS */ 1140 /* Transfer Event */ 1141 #define TRB_TRANSFER 32 1142 /* Command Completion Event */ 1143 #define TRB_COMPLETION 33 1144 /* Port Status Change Event */ 1145 #define TRB_PORT_STATUS 34 1146 /* Bandwidth Request Event (opt) */ 1147 #define TRB_BANDWIDTH_EVENT 35 1148 /* Doorbell Event (opt) */ 1149 #define TRB_DOORBELL 36 1150 /* Host Controller Event */ 1151 #define TRB_HC_EVENT 37 1152 /* Device Notification Event - device sent function wake notification */ 1153 #define TRB_DEV_NOTE 38 1154 /* MFINDEX Wrap Event - microframe counter wrapped */ 1155 #define TRB_MFINDEX_WRAP 39 1156 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1157 #define TRB_VENDOR_DEFINED_LOW 48 1158 /* Nec vendor-specific command completion event. */ 1159 #define TRB_NEC_CMD_COMP 48 1160 /* Get NEC firmware revision. */ 1161 #define TRB_NEC_GET_FW 49 1162 1163 static inline const char *xhci_trb_type_string(u8 type) 1164 { 1165 switch (type) { 1166 case TRB_NORMAL: 1167 return "Normal"; 1168 case TRB_SETUP: 1169 return "Setup Stage"; 1170 case TRB_DATA: 1171 return "Data Stage"; 1172 case TRB_STATUS: 1173 return "Status Stage"; 1174 case TRB_ISOC: 1175 return "Isoch"; 1176 case TRB_LINK: 1177 return "Link"; 1178 case TRB_EVENT_DATA: 1179 return "Event Data"; 1180 case TRB_TR_NOOP: 1181 return "No-Op"; 1182 case TRB_ENABLE_SLOT: 1183 return "Enable Slot Command"; 1184 case TRB_DISABLE_SLOT: 1185 return "Disable Slot Command"; 1186 case TRB_ADDR_DEV: 1187 return "Address Device Command"; 1188 case TRB_CONFIG_EP: 1189 return "Configure Endpoint Command"; 1190 case TRB_EVAL_CONTEXT: 1191 return "Evaluate Context Command"; 1192 case TRB_RESET_EP: 1193 return "Reset Endpoint Command"; 1194 case TRB_STOP_RING: 1195 return "Stop Ring Command"; 1196 case TRB_SET_DEQ: 1197 return "Set TR Dequeue Pointer Command"; 1198 case TRB_RESET_DEV: 1199 return "Reset Device Command"; 1200 case TRB_FORCE_EVENT: 1201 return "Force Event Command"; 1202 case TRB_NEG_BANDWIDTH: 1203 return "Negotiate Bandwidth Command"; 1204 case TRB_SET_LT: 1205 return "Set Latency Tolerance Value Command"; 1206 case TRB_GET_BW: 1207 return "Get Port Bandwidth Command"; 1208 case TRB_FORCE_HEADER: 1209 return "Force Header Command"; 1210 case TRB_CMD_NOOP: 1211 return "No-Op Command"; 1212 case TRB_TRANSFER: 1213 return "Transfer Event"; 1214 case TRB_COMPLETION: 1215 return "Command Completion Event"; 1216 case TRB_PORT_STATUS: 1217 return "Port Status Change Event"; 1218 case TRB_BANDWIDTH_EVENT: 1219 return "Bandwidth Request Event"; 1220 case TRB_DOORBELL: 1221 return "Doorbell Event"; 1222 case TRB_HC_EVENT: 1223 return "Host Controller Event"; 1224 case TRB_DEV_NOTE: 1225 return "Device Notification Event"; 1226 case TRB_MFINDEX_WRAP: 1227 return "MFINDEX Wrap Event"; 1228 case TRB_NEC_CMD_COMP: 1229 return "NEC Command Completion Event"; 1230 case TRB_NEC_GET_FW: 1231 return "NET Get Firmware Revision Command"; 1232 default: 1233 return "UNKNOWN"; 1234 } 1235 } 1236 1237 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1238 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1239 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1240 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1241 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1242 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1243 1244 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1245 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1246 1247 /* 1248 * TRBS_PER_SEGMENT must be a multiple of 4, 1249 * since the command ring is 64-byte aligned. 1250 * It must also be greater than 16. 1251 */ 1252 #define TRBS_PER_SEGMENT 256 1253 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1254 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1255 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1256 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1257 /* TRB buffer pointers can't cross 64KB boundaries */ 1258 #define TRB_MAX_BUFF_SHIFT 16 1259 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1260 /* How much data is left before the 64KB boundary? */ 1261 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1262 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1263 #define MAX_SOFT_RETRY 3 1264 /* 1265 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1266 * XHCI_AVOID_BEI quirk is in use. 1267 */ 1268 #define AVOID_BEI_INTERVAL_MIN 8 1269 #define AVOID_BEI_INTERVAL_MAX 32 1270 1271 #define xhci_for_each_ring_seg(head, seg) \ 1272 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1273 1274 struct xhci_segment { 1275 union xhci_trb *trbs; 1276 /* private to HCD */ 1277 struct xhci_segment *next; 1278 unsigned int num; 1279 dma_addr_t dma; 1280 /* Max packet sized bounce buffer for td-fragmant alignment */ 1281 dma_addr_t bounce_dma; 1282 void *bounce_buf; 1283 unsigned int bounce_offs; 1284 unsigned int bounce_len; 1285 }; 1286 1287 enum xhci_cancelled_td_status { 1288 TD_DIRTY = 0, 1289 TD_HALTED, 1290 TD_CLEARING_CACHE, 1291 TD_CLEARING_CACHE_DEFERRED, 1292 TD_CLEARED, 1293 }; 1294 1295 struct xhci_td { 1296 struct list_head td_list; 1297 struct list_head cancelled_td_list; 1298 int status; 1299 enum xhci_cancelled_td_status cancel_status; 1300 struct urb *urb; 1301 struct xhci_segment *start_seg; 1302 union xhci_trb *start_trb; 1303 struct xhci_segment *end_seg; 1304 union xhci_trb *end_trb; 1305 struct xhci_segment *bounce_seg; 1306 /* actual_length of the URB has already been set */ 1307 bool urb_length_set; 1308 bool error_mid_td; 1309 }; 1310 1311 /* 1312 * xHCI command default timeout value in milliseconds. 1313 * USB 3.2 spec, section 9.2.6.1 1314 */ 1315 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1316 1317 /* command descriptor */ 1318 struct xhci_cd { 1319 struct xhci_command *command; 1320 union xhci_trb *cmd_trb; 1321 }; 1322 1323 enum xhci_ring_type { 1324 TYPE_CTRL = 0, 1325 TYPE_ISOC, 1326 TYPE_BULK, 1327 TYPE_INTR, 1328 TYPE_STREAM, 1329 TYPE_COMMAND, 1330 TYPE_EVENT, 1331 }; 1332 1333 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1334 { 1335 switch (type) { 1336 case TYPE_CTRL: 1337 return "CTRL"; 1338 case TYPE_ISOC: 1339 return "ISOC"; 1340 case TYPE_BULK: 1341 return "BULK"; 1342 case TYPE_INTR: 1343 return "INTR"; 1344 case TYPE_STREAM: 1345 return "STREAM"; 1346 case TYPE_COMMAND: 1347 return "CMD"; 1348 case TYPE_EVENT: 1349 return "EVENT"; 1350 } 1351 1352 return "UNKNOWN"; 1353 } 1354 1355 struct xhci_ring { 1356 struct xhci_segment *first_seg; 1357 struct xhci_segment *last_seg; 1358 union xhci_trb *enqueue; 1359 struct xhci_segment *enq_seg; 1360 union xhci_trb *dequeue; 1361 struct xhci_segment *deq_seg; 1362 struct list_head td_list; 1363 /* 1364 * Write the cycle state into the TRB cycle field to give ownership of 1365 * the TRB to the host controller (if we are the producer), or to check 1366 * if we own the TRB (if we are the consumer). See section 4.9.1. 1367 */ 1368 u32 cycle_state; 1369 unsigned int stream_id; 1370 unsigned int num_segs; 1371 unsigned int num_trbs_free; /* used only by xhci DbC */ 1372 unsigned int bounce_buf_len; 1373 enum xhci_ring_type type; 1374 bool last_td_was_short; 1375 struct radix_tree_root *trb_address_map; 1376 }; 1377 1378 struct xhci_erst_entry { 1379 /* 64-bit event ring segment address */ 1380 __le64 seg_addr; 1381 __le32 seg_size; 1382 /* Set to zero */ 1383 __le32 rsvd; 1384 }; 1385 1386 struct xhci_erst { 1387 struct xhci_erst_entry *entries; 1388 unsigned int num_entries; 1389 /* xhci->event_ring keeps track of segment dma addresses */ 1390 dma_addr_t erst_dma_addr; 1391 }; 1392 1393 struct xhci_scratchpad { 1394 u64 *sp_array; 1395 dma_addr_t sp_dma; 1396 void **sp_buffers; 1397 }; 1398 1399 struct urb_priv { 1400 int num_tds; 1401 int num_tds_done; 1402 struct xhci_td td[] __counted_by(num_tds); 1403 }; 1404 1405 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1406 #define ERST_DEFAULT_SEGS 2 1407 /* Poll every 60 seconds */ 1408 #define POLL_TIMEOUT 60 1409 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1410 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1411 /* XXX: Make these module parameters */ 1412 1413 struct s3_save { 1414 u32 command; 1415 u32 dev_nt; 1416 u64 dcbaa_ptr; 1417 u32 config_reg; 1418 }; 1419 1420 /* Use for lpm */ 1421 struct dev_info { 1422 u32 dev_id; 1423 struct list_head list; 1424 }; 1425 1426 struct xhci_bus_state { 1427 unsigned long bus_suspended; 1428 unsigned long next_statechange; 1429 1430 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1431 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1432 u32 port_c_suspend; 1433 u32 suspended_ports; 1434 u32 port_remote_wakeup; 1435 /* which ports have started to resume */ 1436 unsigned long resuming_ports; 1437 }; 1438 1439 struct xhci_interrupter { 1440 struct xhci_ring *event_ring; 1441 struct xhci_erst erst; 1442 struct xhci_intr_reg __iomem *ir_set; 1443 unsigned int intr_num; 1444 bool ip_autoclear; 1445 u32 isoc_bei_interval; 1446 /* For interrupter registers save and restore over suspend/resume */ 1447 u32 s3_irq_pending; 1448 u32 s3_irq_control; 1449 u32 s3_erst_size; 1450 u64 s3_erst_base; 1451 u64 s3_erst_dequeue; 1452 }; 1453 /* 1454 * It can take up to 20 ms to transition from RExit to U0 on the 1455 * Intel Lynx Point LP xHCI host. 1456 */ 1457 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1458 struct xhci_port_cap { 1459 u32 *psi; /* array of protocol speed ID entries */ 1460 u8 psi_count; 1461 u8 psi_uid_count; 1462 u8 maj_rev; 1463 u8 min_rev; 1464 u32 protocol_caps; 1465 }; 1466 1467 struct xhci_port { 1468 __le32 __iomem *addr; 1469 int hw_portnum; 1470 int hcd_portnum; 1471 struct xhci_hub *rhub; 1472 struct xhci_port_cap *port_cap; 1473 unsigned int lpm_incapable:1; 1474 unsigned long resume_timestamp; 1475 bool rexit_active; 1476 /* Slot ID is the index of the device directly connected to the port */ 1477 int slot_id; 1478 struct completion rexit_done; 1479 struct completion u3exit_done; 1480 }; 1481 1482 struct xhci_hub { 1483 struct xhci_port **ports; 1484 unsigned int num_ports; 1485 struct usb_hcd *hcd; 1486 /* keep track of bus suspend info */ 1487 struct xhci_bus_state bus_state; 1488 /* supported prococol extended capabiliy values */ 1489 u8 maj_rev; 1490 u8 min_rev; 1491 }; 1492 1493 /* There is one xhci_hcd structure per controller */ 1494 struct xhci_hcd { 1495 struct usb_hcd *main_hcd; 1496 struct usb_hcd *shared_hcd; 1497 /* glue to PCI and HCD framework */ 1498 struct xhci_cap_regs __iomem *cap_regs; 1499 struct xhci_op_regs __iomem *op_regs; 1500 struct xhci_run_regs __iomem *run_regs; 1501 struct xhci_doorbell_array __iomem *dba; 1502 1503 /* Cached register copies of read-only HC data */ 1504 __u32 hcs_params1; 1505 __u32 hcs_params2; 1506 __u32 hcs_params3; 1507 __u32 hcc_params; 1508 __u32 hcc_params2; 1509 1510 spinlock_t lock; 1511 1512 /* packed release number */ 1513 u16 hci_version; 1514 u16 max_interrupters; 1515 /* imod_interval in ns (I * 250ns) */ 1516 u32 imod_interval; 1517 /* 4KB min, 128MB max */ 1518 int page_size; 1519 /* Valid values are 12 to 20, inclusive */ 1520 int page_shift; 1521 /* MSI-X/MSI vectors */ 1522 int nvecs; 1523 /* optional clocks */ 1524 struct clk *clk; 1525 struct clk *reg_clk; 1526 /* optional reset controller */ 1527 struct reset_control *reset; 1528 /* data structures */ 1529 struct xhci_device_context_array *dcbaa; 1530 struct xhci_interrupter **interrupters; 1531 struct xhci_ring *cmd_ring; 1532 unsigned int cmd_ring_state; 1533 #define CMD_RING_STATE_RUNNING (1 << 0) 1534 #define CMD_RING_STATE_ABORTED (1 << 1) 1535 #define CMD_RING_STATE_STOPPED (1 << 2) 1536 struct list_head cmd_list; 1537 unsigned int cmd_ring_reserved_trbs; 1538 struct delayed_work cmd_timer; 1539 struct completion cmd_ring_stop_completion; 1540 struct xhci_command *current_cmd; 1541 1542 /* Scratchpad */ 1543 struct xhci_scratchpad *scratchpad; 1544 1545 /* slot enabling and address device helpers */ 1546 /* these are not thread safe so use mutex */ 1547 struct mutex mutex; 1548 /* Internal mirror of the HW's dcbaa */ 1549 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1550 /* For keeping track of bandwidth domains per roothub. */ 1551 struct xhci_root_port_bw_info *rh_bw; 1552 1553 /* DMA pools */ 1554 struct dma_pool *device_pool; 1555 struct dma_pool *segment_pool; 1556 struct dma_pool *small_streams_pool; 1557 struct dma_pool *medium_streams_pool; 1558 1559 /* Host controller watchdog timer structures */ 1560 unsigned int xhc_state; 1561 unsigned long run_graceperiod; 1562 struct s3_save s3; 1563 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1564 * 1565 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1566 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1567 * that sees this status (other than the timer that set it) should stop touching 1568 * hardware immediately. Interrupt handlers should return immediately when 1569 * they see this status (any time they drop and re-acquire xhci->lock). 1570 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1571 * putting the TD on the canceled list, etc. 1572 * 1573 * There are no reports of xHCI host controllers that display this issue. 1574 */ 1575 #define XHCI_STATE_DYING (1 << 0) 1576 #define XHCI_STATE_HALTED (1 << 1) 1577 #define XHCI_STATE_REMOVING (1 << 2) 1578 unsigned long long quirks; 1579 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1580 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1581 #define XHCI_NEC_HOST BIT_ULL(2) 1582 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1583 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1584 /* 1585 * Certain Intel host controllers have a limit to the number of endpoint 1586 * contexts they can handle. Ideally, they would signal that they can't handle 1587 * anymore endpoint contexts by returning a Resource Error for the Configure 1588 * Endpoint command, but they don't. Instead they expect software to keep track 1589 * of the number of active endpoints for them, across configure endpoint 1590 * commands, reset device commands, disable slot commands, and address device 1591 * commands. 1592 */ 1593 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1594 #define XHCI_BROKEN_MSI BIT_ULL(6) 1595 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1596 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1597 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1598 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1599 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1600 #define XHCI_INTEL_HOST BIT_ULL(12) 1601 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1602 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1603 #define XHCI_AVOID_BEI BIT_ULL(15) 1604 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1605 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1606 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1607 /* For controllers with a broken beyond repair streams implementation */ 1608 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1609 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1610 #define XHCI_MTK_HOST BIT_ULL(21) 1611 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1612 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1613 #define XHCI_MISSING_CAS BIT_ULL(24) 1614 /* For controller with a broken Port Disable implementation */ 1615 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1616 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1617 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1618 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1619 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1620 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1621 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1622 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1623 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1624 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1625 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1626 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1627 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1628 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1629 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1630 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1631 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1632 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1633 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1634 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1635 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1636 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1637 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1638 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1639 #define XHCI_ETRON_HOST BIT_ULL(49) 1640 1641 unsigned int num_active_eps; 1642 unsigned int limit_active_eps; 1643 struct xhci_port *hw_ports; 1644 struct xhci_hub usb2_rhub; 1645 struct xhci_hub usb3_rhub; 1646 /* support xHCI 1.0 spec USB2 hardware LPM */ 1647 unsigned hw_lpm_support:1; 1648 /* Broken Suspend flag for SNPS Suspend resume issue */ 1649 unsigned broken_suspend:1; 1650 /* Indicates that omitting hcd is supported if root hub has no ports */ 1651 unsigned allow_single_roothub:1; 1652 /* cached extended protocol port capabilities */ 1653 struct xhci_port_cap *port_caps; 1654 unsigned int num_port_caps; 1655 /* Compliance Mode Recovery Data */ 1656 struct timer_list comp_mode_recovery_timer; 1657 u32 port_status_u0; 1658 u16 test_mode; 1659 /* Compliance Mode Timer Triggered every 2 seconds */ 1660 #define COMP_MODE_RCVRY_MSECS 2000 1661 1662 struct dentry *debugfs_root; 1663 struct dentry *debugfs_slots; 1664 struct list_head regset_list; 1665 1666 void *dbc; 1667 /* platform-specific data -- must come last */ 1668 unsigned long priv[] __aligned(sizeof(s64)); 1669 }; 1670 1671 /* Platform specific overrides to generic XHCI hc_driver ops */ 1672 struct xhci_driver_overrides { 1673 size_t extra_priv_size; 1674 int (*reset)(struct usb_hcd *hcd); 1675 int (*start)(struct usb_hcd *hcd); 1676 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1677 struct usb_host_endpoint *ep); 1678 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1679 struct usb_host_endpoint *ep); 1680 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1681 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1682 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1683 struct usb_tt *tt, gfp_t mem_flags); 1684 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1685 u16 wIndex, char *buf, u16 wLength); 1686 }; 1687 1688 #define XHCI_CFC_DELAY 10 1689 1690 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1691 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1692 { 1693 struct usb_hcd *primary_hcd; 1694 1695 if (usb_hcd_is_primary_hcd(hcd)) 1696 primary_hcd = hcd; 1697 else 1698 primary_hcd = hcd->primary_hcd; 1699 1700 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1701 } 1702 1703 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1704 { 1705 return xhci->main_hcd; 1706 } 1707 1708 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1709 { 1710 if (xhci->shared_hcd) 1711 return xhci->shared_hcd; 1712 1713 if (!xhci->usb2_rhub.num_ports) 1714 return xhci->main_hcd; 1715 1716 return NULL; 1717 } 1718 1719 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1720 { 1721 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1722 1723 return hcd == xhci_get_usb3_hcd(xhci); 1724 } 1725 1726 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1727 { 1728 return xhci->allow_single_roothub && 1729 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1730 } 1731 1732 #define xhci_dbg(xhci, fmt, args...) \ 1733 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1734 #define xhci_err(xhci, fmt, args...) \ 1735 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1736 #define xhci_warn(xhci, fmt, args...) \ 1737 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1738 #define xhci_info(xhci, fmt, args...) \ 1739 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1740 1741 /* 1742 * Registers should always be accessed with double word or quad word accesses. 1743 * 1744 * Some xHCI implementations may support 64-bit address pointers. Registers 1745 * with 64-bit address pointers should be written to with dword accesses by 1746 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1747 * xHCI implementations that do not support 64-bit address pointers will ignore 1748 * the high dword, and write order is irrelevant. 1749 */ 1750 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1751 __le64 __iomem *regs) 1752 { 1753 return lo_hi_readq(regs); 1754 } 1755 static inline void xhci_write_64(struct xhci_hcd *xhci, 1756 const u64 val, __le64 __iomem *regs) 1757 { 1758 lo_hi_writeq(val, regs); 1759 } 1760 1761 1762 /* Link TRB chain should always be set on 0.95 hosts, and AMD 0.96 ISOC rings */ 1763 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1764 { 1765 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1766 (type == TYPE_ISOC && (xhci->quirks & XHCI_AMD_0x96_HOST)); 1767 } 1768 1769 /* xHCI debugging */ 1770 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1771 struct xhci_container_ctx *ctx); 1772 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1773 const char *fmt, ...); 1774 1775 /* xHCI memory management */ 1776 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1777 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1778 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1779 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1780 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1781 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1782 struct usb_device *udev); 1783 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1784 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1785 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1786 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1787 struct xhci_virt_device *virt_dev, 1788 int old_active_eps); 1789 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1790 void xhci_update_bw_info(struct xhci_hcd *xhci, 1791 struct xhci_container_ctx *in_ctx, 1792 struct xhci_input_control_ctx *ctrl_ctx, 1793 struct xhci_virt_device *virt_dev); 1794 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1795 struct xhci_container_ctx *in_ctx, 1796 struct xhci_container_ctx *out_ctx, 1797 unsigned int ep_index); 1798 void xhci_slot_copy(struct xhci_hcd *xhci, 1799 struct xhci_container_ctx *in_ctx, 1800 struct xhci_container_ctx *out_ctx); 1801 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1802 struct usb_device *udev, struct usb_host_endpoint *ep, 1803 gfp_t mem_flags); 1804 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1805 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1806 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1807 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1808 unsigned int num_trbs, gfp_t flags); 1809 void xhci_initialize_ring_info(struct xhci_ring *ring); 1810 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1811 struct xhci_virt_device *virt_dev, 1812 unsigned int ep_index); 1813 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1814 unsigned int num_stream_ctxs, 1815 unsigned int num_streams, 1816 unsigned int max_packet, gfp_t flags); 1817 void xhci_free_stream_info(struct xhci_hcd *xhci, 1818 struct xhci_stream_info *stream_info); 1819 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1820 struct xhci_ep_ctx *ep_ctx, 1821 struct xhci_stream_info *stream_info); 1822 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1823 struct xhci_virt_ep *ep); 1824 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1825 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1826 struct xhci_ring *xhci_dma_to_transfer_ring( 1827 struct xhci_virt_ep *ep, 1828 u64 address); 1829 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1830 bool allocate_completion, gfp_t mem_flags); 1831 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1832 bool allocate_completion, gfp_t mem_flags); 1833 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1834 void xhci_free_command(struct xhci_hcd *xhci, 1835 struct xhci_command *command); 1836 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1837 int type, gfp_t flags); 1838 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1839 struct xhci_container_ctx *ctx); 1840 struct xhci_interrupter * 1841 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1842 u32 imod_interval); 1843 void xhci_remove_secondary_interrupter(struct usb_hcd 1844 *hcd, struct xhci_interrupter *ir); 1845 1846 /* xHCI host controller glue */ 1847 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1848 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1849 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, 1850 u32 mask, u32 done, int usec, unsigned int exit_state); 1851 void xhci_quiesce(struct xhci_hcd *xhci); 1852 int xhci_halt(struct xhci_hcd *xhci); 1853 int xhci_start(struct xhci_hcd *xhci); 1854 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1855 int xhci_run(struct usb_hcd *hcd); 1856 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1857 void xhci_shutdown(struct usb_hcd *hcd); 1858 void xhci_stop(struct usb_hcd *hcd); 1859 void xhci_init_driver(struct hc_driver *drv, 1860 const struct xhci_driver_overrides *over); 1861 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1862 struct usb_host_endpoint *ep); 1863 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1864 struct usb_host_endpoint *ep); 1865 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1866 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1867 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1868 struct usb_tt *tt, gfp_t mem_flags); 1869 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1870 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1871 1872 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1873 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg); 1874 1875 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1876 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1877 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1878 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1879 struct xhci_virt_device *virt_dev, 1880 struct usb_device *hdev, 1881 struct usb_tt *tt, gfp_t mem_flags); 1882 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1883 u32 imod_interval); 1884 1885 /* xHCI ring, segment, TRB, and TD functions */ 1886 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1887 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, struct xhci_td *td, 1888 dma_addr_t suspect_dma, bool debug); 1889 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1890 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1891 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1892 u32 trb_type, u32 slot_id); 1893 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1894 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1895 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1896 u32 field1, u32 field2, u32 field3, u32 field4); 1897 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1898 int slot_id, unsigned int ep_index, int suspend); 1899 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1900 int slot_id, unsigned int ep_index); 1901 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1902 int slot_id, unsigned int ep_index); 1903 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1904 int slot_id, unsigned int ep_index); 1905 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1906 struct urb *urb, int slot_id, unsigned int ep_index); 1907 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1908 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1909 bool command_must_succeed); 1910 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1911 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1912 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1913 int slot_id, unsigned int ep_index, 1914 enum xhci_ep_reset_type reset_type); 1915 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1916 u32 slot_id); 1917 void xhci_handle_command_timeout(struct work_struct *work); 1918 1919 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1920 unsigned int ep_index, unsigned int stream_id); 1921 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1922 unsigned int slot_id, 1923 unsigned int ep_index); 1924 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1925 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1926 unsigned int count_trbs(u64 addr, u64 len); 1927 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1928 int suspend, gfp_t gfp_flags); 1929 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1930 1931 /* xHCI roothub code */ 1932 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1933 u32 link_state); 1934 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1935 u32 port_bit); 1936 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1937 char *buf, u16 wLength); 1938 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1939 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1940 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1941 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1942 struct xhci_port *port); 1943 void xhci_hc_died(struct xhci_hcd *xhci); 1944 1945 #ifdef CONFIG_PM 1946 int xhci_bus_suspend(struct usb_hcd *hcd); 1947 int xhci_bus_resume(struct usb_hcd *hcd); 1948 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1949 #else 1950 #define xhci_bus_suspend NULL 1951 #define xhci_bus_resume NULL 1952 #define xhci_get_resuming_ports NULL 1953 #endif /* CONFIG_PM */ 1954 1955 u32 xhci_port_state_to_neutral(u32 state); 1956 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1957 1958 /* xHCI contexts */ 1959 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1960 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1961 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1962 1963 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1964 unsigned int slot_id, unsigned int ep_index, 1965 unsigned int stream_id); 1966 1967 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 1968 struct urb *urb) 1969 { 1970 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 1971 xhci_get_endpoint_index(&urb->ep->desc), 1972 urb->stream_id); 1973 } 1974 1975 /* 1976 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 1977 * them anyways as we where unable to find a device that matches the 1978 * constraints. 1979 */ 1980 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 1981 { 1982 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 1983 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 1984 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 1985 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 1986 !urb->num_sgs) 1987 return true; 1988 1989 return false; 1990 } 1991 1992 static inline char *xhci_slot_state_string(u32 state) 1993 { 1994 switch (state) { 1995 case SLOT_STATE_ENABLED: 1996 return "enabled/disabled"; 1997 case SLOT_STATE_DEFAULT: 1998 return "default"; 1999 case SLOT_STATE_ADDRESSED: 2000 return "addressed"; 2001 case SLOT_STATE_CONFIGURED: 2002 return "configured"; 2003 default: 2004 return "reserved"; 2005 } 2006 } 2007 2008 static inline const char *xhci_decode_trb(char *str, size_t size, 2009 u32 field0, u32 field1, u32 field2, u32 field3) 2010 { 2011 int type = TRB_FIELD_TO_TYPE(field3); 2012 2013 switch (type) { 2014 case TRB_LINK: 2015 snprintf(str, size, 2016 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2017 field1, field0, GET_INTR_TARGET(field2), 2018 xhci_trb_type_string(type), 2019 field3 & TRB_IOC ? 'I' : 'i', 2020 field3 & TRB_CHAIN ? 'C' : 'c', 2021 field3 & TRB_TC ? 'T' : 't', 2022 field3 & TRB_CYCLE ? 'C' : 'c'); 2023 break; 2024 case TRB_TRANSFER: 2025 case TRB_COMPLETION: 2026 case TRB_PORT_STATUS: 2027 case TRB_BANDWIDTH_EVENT: 2028 case TRB_DOORBELL: 2029 case TRB_HC_EVENT: 2030 case TRB_DEV_NOTE: 2031 case TRB_MFINDEX_WRAP: 2032 snprintf(str, size, 2033 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2034 field1, field0, 2035 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2036 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2037 TRB_TO_EP_ID(field3), 2038 xhci_trb_type_string(type), 2039 field3 & EVENT_DATA ? 'E' : 'e', 2040 field3 & TRB_CYCLE ? 'C' : 'c'); 2041 2042 break; 2043 case TRB_SETUP: 2044 snprintf(str, size, 2045 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2046 field0 & 0xff, 2047 (field0 & 0xff00) >> 8, 2048 (field0 & 0xff000000) >> 24, 2049 (field0 & 0xff0000) >> 16, 2050 (field1 & 0xff00) >> 8, 2051 field1 & 0xff, 2052 (field1 & 0xff000000) >> 16 | 2053 (field1 & 0xff0000) >> 16, 2054 TRB_LEN(field2), GET_TD_SIZE(field2), 2055 GET_INTR_TARGET(field2), 2056 xhci_trb_type_string(type), 2057 field3 & TRB_IDT ? 'I' : 'i', 2058 field3 & TRB_IOC ? 'I' : 'i', 2059 field3 & TRB_CYCLE ? 'C' : 'c'); 2060 break; 2061 case TRB_DATA: 2062 snprintf(str, size, 2063 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2064 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2065 GET_INTR_TARGET(field2), 2066 xhci_trb_type_string(type), 2067 field3 & TRB_IDT ? 'I' : 'i', 2068 field3 & TRB_IOC ? 'I' : 'i', 2069 field3 & TRB_CHAIN ? 'C' : 'c', 2070 field3 & TRB_NO_SNOOP ? 'S' : 's', 2071 field3 & TRB_ISP ? 'I' : 'i', 2072 field3 & TRB_ENT ? 'E' : 'e', 2073 field3 & TRB_CYCLE ? 'C' : 'c'); 2074 break; 2075 case TRB_STATUS: 2076 snprintf(str, size, 2077 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2078 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2079 GET_INTR_TARGET(field2), 2080 xhci_trb_type_string(type), 2081 field3 & TRB_IOC ? 'I' : 'i', 2082 field3 & TRB_CHAIN ? 'C' : 'c', 2083 field3 & TRB_ENT ? 'E' : 'e', 2084 field3 & TRB_CYCLE ? 'C' : 'c'); 2085 break; 2086 case TRB_NORMAL: 2087 case TRB_EVENT_DATA: 2088 case TRB_TR_NOOP: 2089 snprintf(str, size, 2090 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2091 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2092 GET_INTR_TARGET(field2), 2093 xhci_trb_type_string(type), 2094 field3 & TRB_BEI ? 'B' : 'b', 2095 field3 & TRB_IDT ? 'I' : 'i', 2096 field3 & TRB_IOC ? 'I' : 'i', 2097 field3 & TRB_CHAIN ? 'C' : 'c', 2098 field3 & TRB_NO_SNOOP ? 'S' : 's', 2099 field3 & TRB_ISP ? 'I' : 'i', 2100 field3 & TRB_ENT ? 'E' : 'e', 2101 field3 & TRB_CYCLE ? 'C' : 'c'); 2102 break; 2103 case TRB_ISOC: 2104 snprintf(str, size, 2105 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2106 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2107 GET_INTR_TARGET(field2), 2108 xhci_trb_type_string(type), 2109 GET_TBC(field3), 2110 GET_TLBPC(field3), 2111 GET_FRAME_ID(field3), 2112 field3 & TRB_SIA ? 'S' : 's', 2113 field3 & TRB_BEI ? 'B' : 'b', 2114 field3 & TRB_IDT ? 'I' : 'i', 2115 field3 & TRB_IOC ? 'I' : 'i', 2116 field3 & TRB_CHAIN ? 'C' : 'c', 2117 field3 & TRB_NO_SNOOP ? 'S' : 's', 2118 field3 & TRB_ISP ? 'I' : 'i', 2119 field3 & TRB_ENT ? 'E' : 'e', 2120 field3 & TRB_CYCLE ? 'C' : 'c'); 2121 break; 2122 case TRB_CMD_NOOP: 2123 case TRB_ENABLE_SLOT: 2124 snprintf(str, size, 2125 "%s: flags %c", 2126 xhci_trb_type_string(type), 2127 field3 & TRB_CYCLE ? 'C' : 'c'); 2128 break; 2129 case TRB_DISABLE_SLOT: 2130 case TRB_NEG_BANDWIDTH: 2131 snprintf(str, size, 2132 "%s: slot %d flags %c", 2133 xhci_trb_type_string(type), 2134 TRB_TO_SLOT_ID(field3), 2135 field3 & TRB_CYCLE ? 'C' : 'c'); 2136 break; 2137 case TRB_ADDR_DEV: 2138 snprintf(str, size, 2139 "%s: ctx %08x%08x slot %d flags %c:%c", 2140 xhci_trb_type_string(type), 2141 field1, field0, 2142 TRB_TO_SLOT_ID(field3), 2143 field3 & TRB_BSR ? 'B' : 'b', 2144 field3 & TRB_CYCLE ? 'C' : 'c'); 2145 break; 2146 case TRB_CONFIG_EP: 2147 snprintf(str, size, 2148 "%s: ctx %08x%08x slot %d flags %c:%c", 2149 xhci_trb_type_string(type), 2150 field1, field0, 2151 TRB_TO_SLOT_ID(field3), 2152 field3 & TRB_DC ? 'D' : 'd', 2153 field3 & TRB_CYCLE ? 'C' : 'c'); 2154 break; 2155 case TRB_EVAL_CONTEXT: 2156 snprintf(str, size, 2157 "%s: ctx %08x%08x slot %d flags %c", 2158 xhci_trb_type_string(type), 2159 field1, field0, 2160 TRB_TO_SLOT_ID(field3), 2161 field3 & TRB_CYCLE ? 'C' : 'c'); 2162 break; 2163 case TRB_RESET_EP: 2164 snprintf(str, size, 2165 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2166 xhci_trb_type_string(type), 2167 field1, field0, 2168 TRB_TO_SLOT_ID(field3), 2169 TRB_TO_EP_ID(field3), 2170 field3 & TRB_TSP ? 'T' : 't', 2171 field3 & TRB_CYCLE ? 'C' : 'c'); 2172 break; 2173 case TRB_STOP_RING: 2174 snprintf(str, size, 2175 "%s: slot %d sp %d ep %d flags %c", 2176 xhci_trb_type_string(type), 2177 TRB_TO_SLOT_ID(field3), 2178 TRB_TO_SUSPEND_PORT(field3), 2179 TRB_TO_EP_ID(field3), 2180 field3 & TRB_CYCLE ? 'C' : 'c'); 2181 break; 2182 case TRB_SET_DEQ: 2183 snprintf(str, size, 2184 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2185 xhci_trb_type_string(type), 2186 field1, field0, 2187 TRB_TO_STREAM_ID(field2), 2188 TRB_TO_SLOT_ID(field3), 2189 TRB_TO_EP_ID(field3), 2190 field3 & TRB_CYCLE ? 'C' : 'c'); 2191 break; 2192 case TRB_RESET_DEV: 2193 snprintf(str, size, 2194 "%s: slot %d flags %c", 2195 xhci_trb_type_string(type), 2196 TRB_TO_SLOT_ID(field3), 2197 field3 & TRB_CYCLE ? 'C' : 'c'); 2198 break; 2199 case TRB_FORCE_EVENT: 2200 snprintf(str, size, 2201 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2202 xhci_trb_type_string(type), 2203 field1, field0, 2204 TRB_TO_VF_INTR_TARGET(field2), 2205 TRB_TO_VF_ID(field3), 2206 field3 & TRB_CYCLE ? 'C' : 'c'); 2207 break; 2208 case TRB_SET_LT: 2209 snprintf(str, size, 2210 "%s: belt %d flags %c", 2211 xhci_trb_type_string(type), 2212 TRB_TO_BELT(field3), 2213 field3 & TRB_CYCLE ? 'C' : 'c'); 2214 break; 2215 case TRB_GET_BW: 2216 snprintf(str, size, 2217 "%s: ctx %08x%08x slot %d speed %d flags %c", 2218 xhci_trb_type_string(type), 2219 field1, field0, 2220 TRB_TO_SLOT_ID(field3), 2221 TRB_TO_DEV_SPEED(field3), 2222 field3 & TRB_CYCLE ? 'C' : 'c'); 2223 break; 2224 case TRB_FORCE_HEADER: 2225 snprintf(str, size, 2226 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2227 xhci_trb_type_string(type), 2228 field2, field1, field0 & 0xffffffe0, 2229 TRB_TO_PACKET_TYPE(field0), 2230 TRB_TO_ROOTHUB_PORT(field3), 2231 field3 & TRB_CYCLE ? 'C' : 'c'); 2232 break; 2233 default: 2234 snprintf(str, size, 2235 "type '%s' -> raw %08x %08x %08x %08x", 2236 xhci_trb_type_string(type), 2237 field0, field1, field2, field3); 2238 } 2239 2240 return str; 2241 } 2242 2243 static inline const char *xhci_decode_ctrl_ctx(char *str, 2244 unsigned long drop, unsigned long add) 2245 { 2246 unsigned int bit; 2247 int ret = 0; 2248 2249 str[0] = '\0'; 2250 2251 if (drop) { 2252 ret = sprintf(str, "Drop:"); 2253 for_each_set_bit(bit, &drop, 32) 2254 ret += sprintf(str + ret, " %d%s", 2255 bit / 2, 2256 bit % 2 ? "in":"out"); 2257 ret += sprintf(str + ret, ", "); 2258 } 2259 2260 if (add) { 2261 ret += sprintf(str + ret, "Add:%s%s", 2262 (add & SLOT_FLAG) ? " slot":"", 2263 (add & EP0_FLAG) ? " ep0":""); 2264 add &= ~(SLOT_FLAG | EP0_FLAG); 2265 for_each_set_bit(bit, &add, 32) 2266 ret += sprintf(str + ret, " %d%s", 2267 bit / 2, 2268 bit % 2 ? "in":"out"); 2269 } 2270 return str; 2271 } 2272 2273 static inline const char *xhci_decode_slot_context(char *str, 2274 u32 info, u32 info2, u32 tt_info, u32 state) 2275 { 2276 u32 speed; 2277 u32 hub; 2278 u32 mtt; 2279 int ret = 0; 2280 2281 speed = info & DEV_SPEED; 2282 hub = info & DEV_HUB; 2283 mtt = info & DEV_MTT; 2284 2285 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2286 info & ROUTE_STRING_MASK, 2287 ({ char *s; 2288 switch (speed) { 2289 case SLOT_SPEED_FS: 2290 s = "full-speed"; 2291 break; 2292 case SLOT_SPEED_LS: 2293 s = "low-speed"; 2294 break; 2295 case SLOT_SPEED_HS: 2296 s = "high-speed"; 2297 break; 2298 case SLOT_SPEED_SS: 2299 s = "super-speed"; 2300 break; 2301 case SLOT_SPEED_SSP: 2302 s = "super-speed plus"; 2303 break; 2304 default: 2305 s = "UNKNOWN speed"; 2306 } s; }), 2307 mtt ? " multi-TT" : "", 2308 hub ? " Hub" : "", 2309 (info & LAST_CTX_MASK) >> 27, 2310 info2 & MAX_EXIT, 2311 DEVINFO_TO_ROOT_HUB_PORT(info2), 2312 DEVINFO_TO_MAX_PORTS(info2)); 2313 2314 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2315 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2316 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2317 state & DEV_ADDR_MASK, 2318 xhci_slot_state_string(GET_SLOT_STATE(state))); 2319 2320 return str; 2321 } 2322 2323 2324 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2325 { 2326 switch (portsc & PORT_PLS_MASK) { 2327 case XDEV_U0: 2328 return "U0"; 2329 case XDEV_U1: 2330 return "U1"; 2331 case XDEV_U2: 2332 return "U2"; 2333 case XDEV_U3: 2334 return "U3"; 2335 case XDEV_DISABLED: 2336 return "Disabled"; 2337 case XDEV_RXDETECT: 2338 return "RxDetect"; 2339 case XDEV_INACTIVE: 2340 return "Inactive"; 2341 case XDEV_POLLING: 2342 return "Polling"; 2343 case XDEV_RECOVERY: 2344 return "Recovery"; 2345 case XDEV_HOT_RESET: 2346 return "Hot Reset"; 2347 case XDEV_COMP_MODE: 2348 return "Compliance mode"; 2349 case XDEV_TEST_MODE: 2350 return "Test mode"; 2351 case XDEV_RESUME: 2352 return "Resume"; 2353 default: 2354 break; 2355 } 2356 return "Unknown"; 2357 } 2358 2359 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2360 { 2361 int ret; 2362 2363 ret = sprintf(str, "0x%08x ", portsc); 2364 2365 if (portsc == ~(u32)0) 2366 return str; 2367 2368 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ", 2369 portsc & PORT_POWER ? "Powered" : "Powered-off", 2370 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2371 portsc & PORT_PE ? "Enabled" : "Disabled", 2372 xhci_portsc_link_state_string(portsc), 2373 DEV_PORT_SPEED(portsc)); 2374 2375 if (portsc & PORT_OC) 2376 ret += sprintf(str + ret, "OverCurrent "); 2377 if (portsc & PORT_RESET) 2378 ret += sprintf(str + ret, "In-Reset "); 2379 2380 ret += sprintf(str + ret, "Change: "); 2381 if (portsc & PORT_CSC) 2382 ret += sprintf(str + ret, "CSC "); 2383 if (portsc & PORT_PEC) 2384 ret += sprintf(str + ret, "PEC "); 2385 if (portsc & PORT_WRC) 2386 ret += sprintf(str + ret, "WRC "); 2387 if (portsc & PORT_OCC) 2388 ret += sprintf(str + ret, "OCC "); 2389 if (portsc & PORT_RC) 2390 ret += sprintf(str + ret, "PRC "); 2391 if (portsc & PORT_PLC) 2392 ret += sprintf(str + ret, "PLC "); 2393 if (portsc & PORT_CEC) 2394 ret += sprintf(str + ret, "CEC "); 2395 if (portsc & PORT_CAS) 2396 ret += sprintf(str + ret, "CAS "); 2397 2398 ret += sprintf(str + ret, "Wake: "); 2399 if (portsc & PORT_WKCONN_E) 2400 ret += sprintf(str + ret, "WCE "); 2401 if (portsc & PORT_WKDISC_E) 2402 ret += sprintf(str + ret, "WDE "); 2403 if (portsc & PORT_WKOC_E) 2404 ret += sprintf(str + ret, "WOE "); 2405 2406 return str; 2407 } 2408 2409 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2410 { 2411 int ret = 0; 2412 2413 ret = sprintf(str, " 0x%08x", usbsts); 2414 2415 if (usbsts == ~(u32)0) 2416 return str; 2417 2418 if (usbsts & STS_HALT) 2419 ret += sprintf(str + ret, " HCHalted"); 2420 if (usbsts & STS_FATAL) 2421 ret += sprintf(str + ret, " HSE"); 2422 if (usbsts & STS_EINT) 2423 ret += sprintf(str + ret, " EINT"); 2424 if (usbsts & STS_PORT) 2425 ret += sprintf(str + ret, " PCD"); 2426 if (usbsts & STS_SAVE) 2427 ret += sprintf(str + ret, " SSS"); 2428 if (usbsts & STS_RESTORE) 2429 ret += sprintf(str + ret, " RSS"); 2430 if (usbsts & STS_SRE) 2431 ret += sprintf(str + ret, " SRE"); 2432 if (usbsts & STS_CNR) 2433 ret += sprintf(str + ret, " CNR"); 2434 if (usbsts & STS_HCE) 2435 ret += sprintf(str + ret, " HCE"); 2436 2437 return str; 2438 } 2439 2440 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2441 { 2442 u8 ep; 2443 u16 stream; 2444 int ret; 2445 2446 ep = (doorbell & 0xff); 2447 stream = doorbell >> 16; 2448 2449 if (slot == 0) { 2450 sprintf(str, "Command Ring %d", doorbell); 2451 return str; 2452 } 2453 ret = sprintf(str, "Slot %d ", slot); 2454 if (ep > 0 && ep < 32) 2455 ret = sprintf(str + ret, "ep%d%s", 2456 ep / 2, 2457 ep % 2 ? "in" : "out"); 2458 else if (ep == 0 || ep < 248) 2459 ret = sprintf(str + ret, "Reserved %d", ep); 2460 else 2461 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2462 if (stream) 2463 ret = sprintf(str + ret, " Stream %d", stream); 2464 2465 return str; 2466 } 2467 2468 static inline const char *xhci_ep_state_string(u8 state) 2469 { 2470 switch (state) { 2471 case EP_STATE_DISABLED: 2472 return "disabled"; 2473 case EP_STATE_RUNNING: 2474 return "running"; 2475 case EP_STATE_HALTED: 2476 return "halted"; 2477 case EP_STATE_STOPPED: 2478 return "stopped"; 2479 case EP_STATE_ERROR: 2480 return "error"; 2481 default: 2482 return "INVALID"; 2483 } 2484 } 2485 2486 static inline const char *xhci_ep_type_string(u8 type) 2487 { 2488 switch (type) { 2489 case ISOC_OUT_EP: 2490 return "Isoc OUT"; 2491 case BULK_OUT_EP: 2492 return "Bulk OUT"; 2493 case INT_OUT_EP: 2494 return "Int OUT"; 2495 case CTRL_EP: 2496 return "Ctrl"; 2497 case ISOC_IN_EP: 2498 return "Isoc IN"; 2499 case BULK_IN_EP: 2500 return "Bulk IN"; 2501 case INT_IN_EP: 2502 return "Int IN"; 2503 default: 2504 return "INVALID"; 2505 } 2506 } 2507 2508 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2509 u32 info2, u64 deq, u32 tx_info) 2510 { 2511 int ret; 2512 2513 u32 esit; 2514 u16 maxp; 2515 u16 avg; 2516 2517 u8 max_pstr; 2518 u8 ep_state; 2519 u8 interval; 2520 u8 ep_type; 2521 u8 burst; 2522 u8 cerr; 2523 u8 mult; 2524 2525 bool lsa; 2526 bool hid; 2527 2528 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2529 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2530 2531 ep_state = info & EP_STATE_MASK; 2532 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2533 interval = CTX_TO_EP_INTERVAL(info); 2534 mult = CTX_TO_EP_MULT(info) + 1; 2535 lsa = !!(info & EP_HAS_LSA); 2536 2537 cerr = (info2 & (3 << 1)) >> 1; 2538 ep_type = CTX_TO_EP_TYPE(info2); 2539 hid = !!(info2 & (1 << 7)); 2540 burst = CTX_TO_MAX_BURST(info2); 2541 maxp = MAX_PACKET_DECODED(info2); 2542 2543 avg = EP_AVG_TRB_LENGTH(tx_info); 2544 2545 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2546 xhci_ep_state_string(ep_state), mult, 2547 max_pstr, lsa ? "LSA " : ""); 2548 2549 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2550 (1 << interval) * 125, esit, cerr); 2551 2552 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2553 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2554 burst, maxp, deq); 2555 2556 ret += sprintf(str + ret, "avg trb len %d", avg); 2557 2558 return str; 2559 } 2560 2561 #endif /* __LINUX_XHCI_HCD_H */ 2562