1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/phy/phy.h> 20 #include <linux/phy/tegra/xusb.h> 21 #include <linux/platform_device.h> 22 #include <linux/usb/ch9.h> 23 #include <linux/pm.h> 24 #include <linux/pm_domain.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/slab.h> 29 #include <linux/string_choices.h> 30 #include <linux/usb/otg.h> 31 #include <linux/usb/phy.h> 32 #include <linux/usb/role.h> 33 #include <soc/tegra/pmc.h> 34 35 #include "xhci.h" 36 37 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 38 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 39 40 /* FPCI CFG registers */ 41 #define XUSB_CFG_1 0x004 42 #define XUSB_IO_SPACE_EN BIT(0) 43 #define XUSB_MEM_SPACE_EN BIT(1) 44 #define XUSB_BUS_MASTER_EN BIT(2) 45 #define XUSB_CFG_4 0x010 46 #define XUSB_BASE_ADDR_SHIFT 15 47 #define XUSB_BASE_ADDR_MASK 0x1ffff 48 #define XUSB_CFG_7 0x01c 49 #define XUSB_BASE2_ADDR_SHIFT 16 50 #define XUSB_BASE2_ADDR_MASK 0xffff 51 #define XUSB_CFG_16 0x040 52 #define XUSB_CFG_24 0x060 53 #define XUSB_CFG_AXI_CFG 0x0f8 54 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 55 #define XUSB_CFG_ARU_CONTEXT 0x43c 56 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478 57 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c 58 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480 59 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484 60 #define XUSB_CFG_CSB_BASE_ADDR 0x800 61 62 /* FPCI mailbox registers */ 63 /* XUSB_CFG_ARU_MBOX_CMD */ 64 #define MBOX_DEST_FALC BIT(27) 65 #define MBOX_DEST_PME BIT(28) 66 #define MBOX_DEST_SMI BIT(29) 67 #define MBOX_DEST_XHCI BIT(30) 68 #define MBOX_INT_EN BIT(31) 69 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ 70 #define CMD_DATA_SHIFT 0 71 #define CMD_DATA_MASK 0xffffff 72 #define CMD_TYPE_SHIFT 24 73 #define CMD_TYPE_MASK 0xff 74 /* XUSB_CFG_ARU_MBOX_OWNER */ 75 #define MBOX_OWNER_NONE 0 76 #define MBOX_OWNER_FW 1 77 #define MBOX_OWNER_SW 2 78 #define XUSB_CFG_ARU_SMI_INTR 0x428 79 #define MBOX_SMI_INTR_FW_HANG BIT(1) 80 #define MBOX_SMI_INTR_EN BIT(3) 81 82 /* BAR2 registers */ 83 #define XUSB_BAR2_ARU_MBOX_CMD 0x004 84 #define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 85 #define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c 86 #define XUSB_BAR2_ARU_MBOX_OWNER 0x010 87 #define XUSB_BAR2_ARU_SMI_INTR 0x014 88 #define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c 89 #define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 90 #define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 91 #define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 92 #define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c 93 #define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 94 #define XUSB_BAR2_CSB_BASE_ADDR 0x2000 95 96 /* IPFS registers */ 97 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 98 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 99 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8 100 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100 101 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140 102 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 103 #define IPFS_EN_FPCI BIT(0) 104 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184 105 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 106 #define IPFS_IP_INT_MASK BIT(16) 107 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198 108 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c 109 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 110 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc 111 112 #define CSB_PAGE_SELECT_MASK 0x7fffff 113 #define CSB_PAGE_SELECT_SHIFT 9 114 #define CSB_PAGE_OFFSET_MASK 0x1ff 115 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 116 CSB_PAGE_SELECT_MASK) 117 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 118 119 /* Falcon CSB registers */ 120 #define XUSB_FALC_CPUCTL 0x100 121 #define CPUCTL_STARTCPU BIT(1) 122 #define CPUCTL_STATE_HALTED BIT(4) 123 #define CPUCTL_STATE_STOPPED BIT(5) 124 #define XUSB_FALC_BOOTVEC 0x104 125 #define XUSB_FALC_DMACTL 0x10c 126 #define XUSB_FALC_IMFILLRNG1 0x154 127 #define IMFILLRNG1_TAG_MASK 0xffff 128 #define IMFILLRNG1_TAG_LO_SHIFT 0 129 #define IMFILLRNG1_TAG_HI_SHIFT 16 130 #define XUSB_FALC_IMFILLCTL 0x158 131 132 /* CSB ARU registers */ 133 #define XUSB_CSB_ARU_SCRATCH0 0x100100 134 135 /* MP CSB registers */ 136 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 137 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 138 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 139 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 140 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 141 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 142 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 143 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 144 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 145 #define L2IMEMOP_ACTION_SHIFT 24 146 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 147 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 148 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18 149 #define L2IMEMOP_RESULT_VLD BIT(31) 150 #define XUSB_CSB_MP_APMAP 0x10181c 151 #define APMAP_BOOTPATH BIT(31) 152 153 #define IMEM_BLOCK_SIZE 256 154 155 #define FW_IOCTL_TYPE_SHIFT 24 156 #define FW_IOCTL_CFGTBL_READ 17 157 158 struct tegra_xusb_fw_header { 159 __le32 boot_loadaddr_in_imem; 160 __le32 boot_codedfi_offset; 161 __le32 boot_codetag; 162 __le32 boot_codesize; 163 __le32 phys_memaddr; 164 __le16 reqphys_memsize; 165 __le16 alloc_phys_memsize; 166 __le32 rodata_img_offset; 167 __le32 rodata_section_start; 168 __le32 rodata_section_end; 169 __le32 main_fnaddr; 170 __le32 fwimg_cksum; 171 __le32 fwimg_created_time; 172 __le32 imem_resident_start; 173 __le32 imem_resident_end; 174 __le32 idirect_start; 175 __le32 idirect_end; 176 __le32 l2_imem_start; 177 __le32 l2_imem_end; 178 __le32 version_id; 179 u8 init_ddirect; 180 u8 reserved[3]; 181 __le32 phys_addr_log_buffer; 182 __le32 total_log_entries; 183 __le32 dequeue_ptr; 184 __le32 dummy_var[2]; 185 __le32 fwimg_len; 186 u8 magic[8]; 187 __le32 ss_low_power_entry_timeout; 188 u8 num_hsic_port; 189 u8 padding[139]; /* Pad to 256 bytes */ 190 }; 191 192 struct tegra_xusb_phy_type { 193 const char *name; 194 unsigned int num; 195 }; 196 197 struct tegra_xusb_mbox_regs { 198 u16 cmd; 199 u16 data_in; 200 u16 data_out; 201 u16 owner; 202 u16 smi_intr; 203 }; 204 205 struct tegra_xusb_context_soc { 206 struct { 207 const unsigned int *offsets; 208 unsigned int num_offsets; 209 } ipfs; 210 211 struct { 212 const unsigned int *offsets; 213 unsigned int num_offsets; 214 } fpci; 215 }; 216 217 struct tegra_xusb; 218 struct tegra_xusb_soc_ops { 219 u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); 220 void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); 221 u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); 222 void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); 223 }; 224 225 struct tegra_xusb_soc { 226 const char *firmware; 227 const char * const *supply_names; 228 unsigned int num_supplies; 229 const struct tegra_xusb_phy_type *phy_types; 230 unsigned int num_types; 231 const struct tegra_xusb_context_soc *context; 232 233 struct { 234 struct { 235 unsigned int offset; 236 unsigned int count; 237 } usb2, ulpi, hsic, usb3; 238 } ports; 239 240 struct tegra_xusb_mbox_regs mbox; 241 const struct tegra_xusb_soc_ops *ops; 242 243 bool scale_ss_clock; 244 bool has_ipfs; 245 bool lpm_support; 246 bool otg_reset_sspi; 247 248 bool has_bar2; 249 }; 250 251 struct tegra_xusb_context { 252 u32 *ipfs; 253 u32 *fpci; 254 }; 255 256 struct tegra_xusb { 257 struct device *dev; 258 void __iomem *regs; 259 struct usb_hcd *hcd; 260 261 struct mutex lock; 262 263 int xhci_irq; 264 int mbox_irq; 265 int padctl_irq; 266 267 void __iomem *ipfs_base; 268 void __iomem *fpci_base; 269 void __iomem *bar2_base; 270 struct resource *bar2; 271 272 const struct tegra_xusb_soc *soc; 273 274 struct regulator_bulk_data *supplies; 275 276 struct tegra_xusb_padctl *padctl; 277 278 struct clk *host_clk; 279 struct clk *falcon_clk; 280 struct clk *ss_clk; 281 struct clk *ss_src_clk; 282 struct clk *hs_src_clk; 283 struct clk *fs_src_clk; 284 struct clk *pll_u_480m; 285 struct clk *clk_m; 286 struct clk *pll_e; 287 288 struct reset_control *host_rst; 289 struct reset_control *ss_rst; 290 291 struct device *genpd_dev_host; 292 struct device *genpd_dev_ss; 293 bool use_genpd; 294 295 struct phy **phys; 296 unsigned int num_phys; 297 298 struct usb_phy **usbphy; 299 unsigned int num_usb_phys; 300 int otg_usb2_port; 301 int otg_usb3_port; 302 bool host_mode; 303 struct notifier_block id_nb; 304 struct work_struct id_work; 305 306 /* Firmware loading related */ 307 struct { 308 size_t size; 309 void *virt; 310 dma_addr_t phys; 311 } fw; 312 313 bool suspended; 314 struct tegra_xusb_context context; 315 u8 lp0_utmi_pad_mask; 316 }; 317 318 static struct hc_driver __read_mostly tegra_xhci_hc_driver; 319 320 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 321 { 322 return readl(tegra->fpci_base + offset); 323 } 324 325 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 326 unsigned int offset) 327 { 328 writel(value, tegra->fpci_base + offset); 329 } 330 331 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 332 { 333 return readl(tegra->ipfs_base + offset); 334 } 335 336 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 337 unsigned int offset) 338 { 339 writel(value, tegra->ipfs_base + offset); 340 } 341 342 static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) 343 { 344 return readl(tegra->bar2_base + offset); 345 } 346 347 static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, 348 unsigned int offset) 349 { 350 writel(value, tegra->bar2_base + offset); 351 } 352 353 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 354 { 355 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 356 357 return ops->csb_reg_readl(tegra, offset); 358 } 359 360 static void csb_writel(struct tegra_xusb *tegra, u32 value, 361 unsigned int offset) 362 { 363 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 364 365 ops->csb_reg_writel(tegra, value, offset); 366 } 367 368 static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) 369 { 370 u32 page = CSB_PAGE_SELECT(offset); 371 u32 ofs = CSB_PAGE_OFFSET(offset); 372 373 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 374 375 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 376 } 377 378 static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, 379 unsigned int offset) 380 { 381 u32 page = CSB_PAGE_SELECT(offset); 382 u32 ofs = CSB_PAGE_OFFSET(offset); 383 384 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 385 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 386 } 387 388 static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) 389 { 390 u32 page = CSB_PAGE_SELECT(offset); 391 u32 ofs = CSB_PAGE_OFFSET(offset); 392 393 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); 394 395 return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); 396 } 397 398 static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, 399 unsigned int offset) 400 { 401 u32 page = CSB_PAGE_SELECT(offset); 402 u32 ofs = CSB_PAGE_OFFSET(offset); 403 404 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); 405 bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); 406 } 407 408 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 409 unsigned long rate) 410 { 411 unsigned long new_parent_rate, old_parent_rate; 412 struct clk *clk = tegra->ss_src_clk; 413 unsigned int div; 414 int err; 415 416 if (clk_get_rate(clk) == rate) 417 return 0; 418 419 switch (rate) { 420 case TEGRA_XHCI_SS_HIGH_SPEED: 421 /* 422 * Reparent to PLLU_480M. Set divider first to avoid 423 * overclocking. 424 */ 425 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 426 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 427 div = new_parent_rate / rate; 428 429 err = clk_set_rate(clk, old_parent_rate / div); 430 if (err) 431 return err; 432 433 err = clk_set_parent(clk, tegra->pll_u_480m); 434 if (err) 435 return err; 436 437 /* 438 * The rate should already be correct, but set it again just 439 * to be sure. 440 */ 441 err = clk_set_rate(clk, rate); 442 if (err) 443 return err; 444 445 break; 446 447 case TEGRA_XHCI_SS_LOW_SPEED: 448 /* Reparent to CLK_M */ 449 err = clk_set_parent(clk, tegra->clk_m); 450 if (err) 451 return err; 452 453 err = clk_set_rate(clk, rate); 454 if (err) 455 return err; 456 457 break; 458 459 default: 460 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 461 return -EINVAL; 462 } 463 464 if (clk_get_rate(clk) != rate) { 465 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 466 return -EINVAL; 467 } 468 469 return 0; 470 } 471 472 static unsigned long extract_field(u32 value, unsigned int start, 473 unsigned int count) 474 { 475 return (value >> start) & ((1 << count) - 1); 476 } 477 478 /* Command requests from the firmware */ 479 enum tegra_xusb_mbox_cmd { 480 MBOX_CMD_MSG_ENABLED = 1, 481 MBOX_CMD_INC_FALC_CLOCK, 482 MBOX_CMD_DEC_FALC_CLOCK, 483 MBOX_CMD_INC_SSPI_CLOCK, 484 MBOX_CMD_DEC_SSPI_CLOCK, 485 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 486 MBOX_CMD_SET_SS_PWR_GATING, 487 MBOX_CMD_SET_SS_PWR_UNGATING, 488 MBOX_CMD_SAVE_DFE_CTLE_CTX, 489 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 490 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 491 MBOX_CMD_START_HSIC_IDLE, 492 MBOX_CMD_STOP_HSIC_IDLE, 493 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 494 MBOX_CMD_HSIC_PRETEND_CONNECT, 495 MBOX_CMD_RESET_SSPI, 496 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 497 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 498 499 MBOX_CMD_MAX, 500 501 /* Response message to above commands */ 502 MBOX_CMD_ACK = 128, 503 MBOX_CMD_NAK 504 }; 505 506 struct tegra_xusb_mbox_msg { 507 u32 cmd; 508 u32 data; 509 }; 510 511 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 512 { 513 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 514 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 515 } 516 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 517 u32 value) 518 { 519 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 520 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 521 } 522 523 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 524 { 525 switch (cmd) { 526 case MBOX_CMD_SET_BW: 527 case MBOX_CMD_ACK: 528 case MBOX_CMD_NAK: 529 return false; 530 531 default: 532 return true; 533 } 534 } 535 536 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 537 const struct tegra_xusb_mbox_msg *msg) 538 { 539 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 540 bool wait_for_idle = false; 541 u32 value; 542 543 /* 544 * Acquire the mailbox. The firmware still owns the mailbox for 545 * ACK/NAK messages. 546 */ 547 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 548 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 549 if (value != MBOX_OWNER_NONE) { 550 dev_err(tegra->dev, "mailbox is busy\n"); 551 return -EBUSY; 552 } 553 554 ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); 555 556 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 557 if (value != MBOX_OWNER_SW) { 558 dev_err(tegra->dev, "failed to acquire mailbox\n"); 559 return -EBUSY; 560 } 561 562 wait_for_idle = true; 563 } 564 565 value = tegra_xusb_mbox_pack(msg); 566 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); 567 568 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); 569 value |= MBOX_INT_EN | MBOX_DEST_FALC; 570 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); 571 572 if (wait_for_idle) { 573 unsigned long timeout = jiffies + msecs_to_jiffies(250); 574 575 while (time_before(jiffies, timeout)) { 576 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 577 if (value == MBOX_OWNER_NONE) 578 break; 579 580 usleep_range(10, 20); 581 } 582 583 if (time_after(jiffies, timeout)) 584 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 585 586 if (value != MBOX_OWNER_NONE) 587 return -ETIMEDOUT; 588 } 589 590 return 0; 591 } 592 593 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 594 { 595 struct tegra_xusb *tegra = data; 596 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 597 u32 value; 598 599 /* clear mailbox interrupts */ 600 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); 601 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); 602 603 if (value & MBOX_SMI_INTR_FW_HANG) 604 dev_err(tegra->dev, "controller firmware hang\n"); 605 606 return IRQ_WAKE_THREAD; 607 } 608 609 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 610 const struct tegra_xusb_mbox_msg *msg) 611 { 612 struct tegra_xusb_padctl *padctl = tegra->padctl; 613 const struct tegra_xusb_soc *soc = tegra->soc; 614 struct device *dev = tegra->dev; 615 struct tegra_xusb_mbox_msg rsp; 616 unsigned long mask; 617 unsigned int port; 618 bool idle, enable; 619 int err = 0; 620 621 memset(&rsp, 0, sizeof(rsp)); 622 623 switch (msg->cmd) { 624 case MBOX_CMD_INC_FALC_CLOCK: 625 case MBOX_CMD_DEC_FALC_CLOCK: 626 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 627 if (rsp.data != msg->data) 628 rsp.cmd = MBOX_CMD_NAK; 629 else 630 rsp.cmd = MBOX_CMD_ACK; 631 632 break; 633 634 case MBOX_CMD_INC_SSPI_CLOCK: 635 case MBOX_CMD_DEC_SSPI_CLOCK: 636 if (tegra->soc->scale_ss_clock) { 637 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 638 if (err < 0) 639 rsp.cmd = MBOX_CMD_NAK; 640 else 641 rsp.cmd = MBOX_CMD_ACK; 642 643 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 644 } else { 645 rsp.cmd = MBOX_CMD_ACK; 646 rsp.data = msg->data; 647 } 648 649 break; 650 651 case MBOX_CMD_SET_BW: 652 /* 653 * TODO: Request bandwidth once EMC scaling is supported. 654 * Ignore for now since ACK/NAK is not required for SET_BW 655 * messages. 656 */ 657 break; 658 659 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 660 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 661 if (err < 0) { 662 dev_err(dev, "failed to save context for USB3#%u: %d\n", 663 msg->data, err); 664 rsp.cmd = MBOX_CMD_NAK; 665 } else { 666 rsp.cmd = MBOX_CMD_ACK; 667 } 668 669 rsp.data = msg->data; 670 break; 671 672 case MBOX_CMD_START_HSIC_IDLE: 673 case MBOX_CMD_STOP_HSIC_IDLE: 674 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 675 idle = false; 676 else 677 idle = true; 678 679 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 680 soc->ports.hsic.count); 681 682 for_each_set_bit(port, &mask, 32) { 683 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 684 idle); 685 if (err < 0) 686 break; 687 } 688 689 if (err < 0) { 690 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 691 idle ? "idle" : "busy", err); 692 rsp.cmd = MBOX_CMD_NAK; 693 } else { 694 rsp.cmd = MBOX_CMD_ACK; 695 } 696 697 rsp.data = msg->data; 698 break; 699 700 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 701 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 702 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 703 enable = false; 704 else 705 enable = true; 706 707 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 708 soc->ports.usb3.count); 709 710 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 711 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 712 port, 713 enable); 714 if (err < 0) 715 break; 716 717 /* 718 * wait 500us for LFPS detector to be disabled before 719 * sending ACK 720 */ 721 if (!enable) 722 usleep_range(500, 1000); 723 } 724 725 if (err < 0) { 726 dev_err(dev, 727 "failed to %s LFPS detection on USB3#%u: %d\n", 728 str_enable_disable(enable), port, err); 729 rsp.cmd = MBOX_CMD_NAK; 730 } else { 731 rsp.cmd = MBOX_CMD_ACK; 732 } 733 734 rsp.data = msg->data; 735 break; 736 737 default: 738 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 739 break; 740 } 741 742 if (rsp.cmd) { 743 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 744 745 err = tegra_xusb_mbox_send(tegra, &rsp); 746 if (err < 0) 747 dev_err(dev, "failed to send %s: %d\n", cmd, err); 748 } 749 } 750 751 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 752 { 753 struct tegra_xusb *tegra = data; 754 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 755 struct tegra_xusb_mbox_msg msg; 756 u32 value; 757 758 mutex_lock(&tegra->lock); 759 760 if (pm_runtime_suspended(tegra->dev) || tegra->suspended) 761 goto out; 762 763 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); 764 tegra_xusb_mbox_unpack(&msg, value); 765 766 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); 767 value &= ~MBOX_DEST_SMI; 768 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); 769 770 /* clear mailbox owner if no ACK/NAK is required */ 771 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 772 ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); 773 774 tegra_xusb_mbox_handle(tegra, &msg); 775 776 out: 777 mutex_unlock(&tegra->lock); 778 return IRQ_HANDLED; 779 } 780 781 static void tegra_xusb_config(struct tegra_xusb *tegra) 782 { 783 u32 regs = tegra->hcd->rsrc_start; 784 u32 value; 785 786 if (tegra->soc->has_ipfs) { 787 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 788 value |= IPFS_EN_FPCI; 789 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 790 791 usleep_range(10, 20); 792 } 793 794 /* Program BAR0 space */ 795 value = fpci_readl(tegra, XUSB_CFG_4); 796 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 797 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 798 fpci_writel(tegra, value, XUSB_CFG_4); 799 800 /* Program BAR2 space */ 801 if (tegra->bar2) { 802 value = fpci_readl(tegra, XUSB_CFG_7); 803 value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); 804 value |= tegra->bar2->start & 805 (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); 806 fpci_writel(tegra, value, XUSB_CFG_7); 807 } 808 809 usleep_range(100, 200); 810 811 /* Enable bus master */ 812 value = fpci_readl(tegra, XUSB_CFG_1); 813 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 814 fpci_writel(tegra, value, XUSB_CFG_1); 815 816 if (tegra->soc->has_ipfs) { 817 /* Enable interrupt assertion */ 818 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 819 value |= IPFS_IP_INT_MASK; 820 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 821 822 /* Set hysteresis */ 823 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 824 } 825 } 826 827 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 828 { 829 int err; 830 831 err = clk_prepare_enable(tegra->pll_e); 832 if (err < 0) 833 return err; 834 835 err = clk_prepare_enable(tegra->host_clk); 836 if (err < 0) 837 goto disable_plle; 838 839 err = clk_prepare_enable(tegra->ss_clk); 840 if (err < 0) 841 goto disable_host; 842 843 err = clk_prepare_enable(tegra->falcon_clk); 844 if (err < 0) 845 goto disable_ss; 846 847 err = clk_prepare_enable(tegra->fs_src_clk); 848 if (err < 0) 849 goto disable_falc; 850 851 err = clk_prepare_enable(tegra->hs_src_clk); 852 if (err < 0) 853 goto disable_fs_src; 854 855 if (tegra->soc->scale_ss_clock) { 856 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 857 if (err < 0) 858 goto disable_hs_src; 859 } 860 861 return 0; 862 863 disable_hs_src: 864 clk_disable_unprepare(tegra->hs_src_clk); 865 disable_fs_src: 866 clk_disable_unprepare(tegra->fs_src_clk); 867 disable_falc: 868 clk_disable_unprepare(tegra->falcon_clk); 869 disable_ss: 870 clk_disable_unprepare(tegra->ss_clk); 871 disable_host: 872 clk_disable_unprepare(tegra->host_clk); 873 disable_plle: 874 clk_disable_unprepare(tegra->pll_e); 875 return err; 876 } 877 878 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 879 { 880 clk_disable_unprepare(tegra->pll_e); 881 clk_disable_unprepare(tegra->host_clk); 882 clk_disable_unprepare(tegra->ss_clk); 883 clk_disable_unprepare(tegra->falcon_clk); 884 clk_disable_unprepare(tegra->fs_src_clk); 885 clk_disable_unprepare(tegra->hs_src_clk); 886 } 887 888 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 889 { 890 unsigned int i; 891 int err; 892 893 for (i = 0; i < tegra->num_phys; i++) { 894 err = phy_init(tegra->phys[i]); 895 if (err) 896 goto disable_phy; 897 898 err = phy_power_on(tegra->phys[i]); 899 if (err) { 900 phy_exit(tegra->phys[i]); 901 goto disable_phy; 902 } 903 } 904 905 return 0; 906 907 disable_phy: 908 while (i--) { 909 phy_power_off(tegra->phys[i]); 910 phy_exit(tegra->phys[i]); 911 } 912 913 return err; 914 } 915 916 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 917 { 918 unsigned int i; 919 920 for (i = 0; i < tegra->num_phys; i++) { 921 phy_power_off(tegra->phys[i]); 922 phy_exit(tegra->phys[i]); 923 } 924 } 925 926 #ifdef CONFIG_PM_SLEEP 927 static int tegra_xusb_init_context(struct tegra_xusb *tegra) 928 { 929 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 930 931 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets, 932 sizeof(u32), GFP_KERNEL); 933 if (!tegra->context.ipfs) 934 return -ENOMEM; 935 936 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets, 937 sizeof(u32), GFP_KERNEL); 938 if (!tegra->context.fpci) 939 return -ENOMEM; 940 941 return 0; 942 } 943 #else 944 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra) 945 { 946 return 0; 947 } 948 #endif 949 950 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) 951 { 952 struct tegra_xusb_fw_header *header; 953 const struct firmware *fw; 954 int err; 955 956 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 957 if (err < 0) { 958 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 959 return err; 960 } 961 962 /* Load Falcon controller with its firmware. */ 963 header = (struct tegra_xusb_fw_header *)fw->data; 964 tegra->fw.size = le32_to_cpu(header->fwimg_len); 965 966 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 967 &tegra->fw.phys, GFP_KERNEL); 968 if (!tegra->fw.virt) { 969 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 970 release_firmware(fw); 971 return -ENOMEM; 972 } 973 974 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 975 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 976 release_firmware(fw); 977 978 return 0; 979 } 980 981 static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) 982 { 983 struct xhci_cap_regs __iomem *cap_regs; 984 struct xhci_op_regs __iomem *op_regs; 985 int ret; 986 u32 value; 987 988 cap_regs = tegra->regs; 989 op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); 990 991 ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000); 992 993 if (ret) 994 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", 995 csb_readl(tegra, XUSB_FALC_CPUCTL)); 996 997 return ret; 998 } 999 1000 static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra) 1001 { 1002 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 1003 struct tegra_xusb_fw_header *header; 1004 struct device *dev = tegra->dev; 1005 time64_t timestamp; 1006 u64 address; 1007 u32 value; 1008 int err; 1009 1010 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 1011 1012 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 1013 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 1014 csb_readl(tegra, XUSB_FALC_CPUCTL)); 1015 return 0; 1016 } 1017 1018 /* Program the size of DFI into ILOAD_ATTR. */ 1019 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 1020 1021 /* 1022 * Boot code of the firmware reads the ILOAD_BASE registers 1023 * to get to the start of the DFI in system memory. 1024 */ 1025 address = tegra->fw.phys + sizeof(*header); 1026 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 1027 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 1028 1029 /* Set BOOTPATH to 1 in APMAP. */ 1030 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 1031 1032 /* Invalidate L2IMEM. */ 1033 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 1034 1035 /* 1036 * Initiate fetch of bootcode from system memory into L2IMEM. 1037 * Program bootcode location and size in system memory. 1038 */ 1039 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 1040 IMEM_BLOCK_SIZE); 1041 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 1042 IMEM_BLOCK_SIZE); 1043 code_blocks = code_tag_blocks + code_size_blocks; 1044 1045 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 1046 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 1047 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 1048 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 1049 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 1050 1051 /* Trigger L2IMEM load operation. */ 1052 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 1053 XUSB_CSB_MP_L2IMEMOP_TRIG); 1054 1055 /* Setup Falcon auto-fill. */ 1056 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 1057 1058 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 1059 IMFILLRNG1_TAG_LO_SHIFT) | 1060 ((code_blocks & IMFILLRNG1_TAG_MASK) << 1061 IMFILLRNG1_TAG_HI_SHIFT); 1062 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 1063 1064 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 1065 1066 /* wait for RESULT_VLD to get set */ 1067 #define tegra_csb_readl(offset) csb_readl(tegra, offset) 1068 err = readx_poll_timeout(tegra_csb_readl, 1069 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value, 1070 value & L2IMEMOP_RESULT_VLD, 100, 10000); 1071 if (err < 0) { 1072 dev_err(dev, "DMA controller not ready %#010x\n", value); 1073 return err; 1074 } 1075 #undef tegra_csb_readl 1076 1077 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 1078 XUSB_FALC_BOOTVEC); 1079 1080 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ 1081 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 1082 1083 if (tegra_xusb_wait_for_falcon(tegra)) 1084 return -EIO; 1085 1086 timestamp = le32_to_cpu(header->fwimg_created_time); 1087 1088 dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); 1089 1090 return 0; 1091 } 1092 1093 static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) 1094 { 1095 /* 1096 * We only accept reading the firmware config table 1097 * The offset should not exceed the fw header structure 1098 */ 1099 if (offset >= sizeof(struct tegra_xusb_fw_header)) 1100 return 0; 1101 1102 bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, 1103 XUSB_BAR2_ARU_FW_SCRATCH); 1104 return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); 1105 } 1106 1107 static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) 1108 { 1109 time64_t timestamp; 1110 1111 if (tegra_xusb_wait_for_falcon(tegra)) 1112 return -EIO; 1113 1114 #define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) 1115 timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header, 1116 fwimg_created_time) << 2); 1117 1118 dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); 1119 1120 return 0; 1121 } 1122 1123 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 1124 { 1125 if (!tegra->soc->firmware) 1126 return tegra_xusb_init_ifr_firmware(tegra); 1127 else 1128 return tegra_xusb_load_firmware_rom(tegra); 1129 } 1130 1131 static void tegra_xusb_powerdomain_remove(struct device *dev, 1132 struct tegra_xusb *tegra) 1133 { 1134 if (!tegra->use_genpd) 1135 return; 1136 1137 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) 1138 dev_pm_domain_detach(tegra->genpd_dev_ss, true); 1139 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) 1140 dev_pm_domain_detach(tegra->genpd_dev_host, true); 1141 } 1142 1143 static int tegra_xusb_powerdomain_init(struct device *dev, 1144 struct tegra_xusb *tegra) 1145 { 1146 int err; 1147 1148 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); 1149 if (IS_ERR(tegra->genpd_dev_host)) { 1150 err = PTR_ERR(tegra->genpd_dev_host); 1151 dev_err(dev, "failed to get host pm-domain: %d\n", err); 1152 return err; 1153 } 1154 1155 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); 1156 if (IS_ERR(tegra->genpd_dev_ss)) { 1157 err = PTR_ERR(tegra->genpd_dev_ss); 1158 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); 1159 return err; 1160 } 1161 1162 tegra->use_genpd = true; 1163 1164 return 0; 1165 } 1166 1167 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra) 1168 { 1169 struct device *dev = tegra->dev; 1170 int rc; 1171 1172 if (tegra->use_genpd) { 1173 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss); 1174 if (rc < 0) { 1175 dev_err(dev, "failed to enable XUSB SS partition\n"); 1176 return rc; 1177 } 1178 1179 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host); 1180 if (rc < 0) { 1181 dev_err(dev, "failed to enable XUSB Host partition\n"); 1182 pm_runtime_put_sync(tegra->genpd_dev_ss); 1183 return rc; 1184 } 1185 } else { 1186 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 1187 tegra->ss_clk, 1188 tegra->ss_rst); 1189 if (rc < 0) { 1190 dev_err(dev, "failed to enable XUSB SS partition\n"); 1191 return rc; 1192 } 1193 1194 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1195 tegra->host_clk, 1196 tegra->host_rst); 1197 if (rc < 0) { 1198 dev_err(dev, "failed to enable XUSB Host partition\n"); 1199 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1200 return rc; 1201 } 1202 } 1203 1204 return 0; 1205 } 1206 1207 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra) 1208 { 1209 struct device *dev = tegra->dev; 1210 int rc; 1211 1212 if (tegra->use_genpd) { 1213 rc = pm_runtime_put_sync(tegra->genpd_dev_host); 1214 if (rc < 0) { 1215 dev_err(dev, "failed to disable XUSB Host partition\n"); 1216 return rc; 1217 } 1218 1219 rc = pm_runtime_put_sync(tegra->genpd_dev_ss); 1220 if (rc < 0) { 1221 dev_err(dev, "failed to disable XUSB SS partition\n"); 1222 pm_runtime_get_sync(tegra->genpd_dev_host); 1223 return rc; 1224 } 1225 } else { 1226 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1227 if (rc < 0) { 1228 dev_err(dev, "failed to disable XUSB Host partition\n"); 1229 return rc; 1230 } 1231 1232 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1233 if (rc < 0) { 1234 dev_err(dev, "failed to disable XUSB SS partition\n"); 1235 tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1236 tegra->host_clk, 1237 tegra->host_rst); 1238 return rc; 1239 } 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1246 { 1247 struct tegra_xusb_mbox_msg msg; 1248 int err; 1249 1250 /* Enable firmware messages from controller. */ 1251 msg.cmd = MBOX_CMD_MSG_ENABLED; 1252 msg.data = 0; 1253 1254 err = tegra_xusb_mbox_send(tegra, &msg); 1255 if (err < 0) 1256 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 1257 1258 return err; 1259 } 1260 1261 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data) 1262 { 1263 struct tegra_xusb *tegra = data; 1264 1265 mutex_lock(&tegra->lock); 1266 1267 if (tegra->suspended) { 1268 mutex_unlock(&tegra->lock); 1269 return IRQ_HANDLED; 1270 } 1271 1272 mutex_unlock(&tegra->lock); 1273 1274 pm_runtime_resume(tegra->dev); 1275 1276 return IRQ_HANDLED; 1277 } 1278 1279 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1280 { 1281 int err; 1282 1283 mutex_lock(&tegra->lock); 1284 err = __tegra_xusb_enable_firmware_messages(tegra); 1285 mutex_unlock(&tegra->lock); 1286 1287 return err; 1288 } 1289 1290 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main, 1291 bool set) 1292 { 1293 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1294 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; 1295 unsigned int wait = (!main && !set) ? 1000 : 10; 1296 u16 typeReq = set ? SetPortFeature : ClearPortFeature; 1297 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1; 1298 u32 status; 1299 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER; 1300 u32 status_val = set ? stat_power : 0; 1301 1302 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__, 1303 set ? "set" : "clear", main ? "HS" : "SS"); 1304 1305 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex, 1306 NULL, 0); 1307 1308 do { 1309 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex, 1310 (char *) &status, sizeof(status)); 1311 if (status_val == (status & stat_power)) 1312 break; 1313 1314 if (!main && !set) 1315 usleep_range(600, 700); 1316 else 1317 usleep_range(10, 20); 1318 } while (--wait > 0); 1319 1320 if (status_val != (status & stat_power)) 1321 dev_info(tegra->dev, "failed to %s %s PP %d\n", 1322 set ? "set" : "clear", 1323 main ? "HS" : "SS", status); 1324 } 1325 1326 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name, 1327 int port) 1328 { 1329 unsigned int i, phy_count = 0; 1330 1331 for (i = 0; i < tegra->soc->num_types; i++) { 1332 if (!strncmp(tegra->soc->phy_types[i].name, name, 1333 strlen(name))) 1334 return tegra->phys[phy_count+port]; 1335 1336 phy_count += tegra->soc->phy_types[i].num; 1337 } 1338 1339 return NULL; 1340 } 1341 1342 static void tegra_xhci_id_work(struct work_struct *work) 1343 { 1344 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb, 1345 id_work); 1346 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1347 struct tegra_xusb_mbox_msg msg; 1348 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", 1349 tegra->otg_usb2_port); 1350 u32 status; 1351 int ret; 1352 1353 dev_dbg(tegra->dev, "host mode %s\n", str_on_off(tegra->host_mode)); 1354 1355 mutex_lock(&tegra->lock); 1356 1357 if (tegra->host_mode) 1358 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST); 1359 else 1360 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); 1361 1362 mutex_unlock(&tegra->lock); 1363 1364 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(tegra->padctl, 1365 tegra->otg_usb2_port); 1366 1367 if (tegra->host_mode) { 1368 /* switch to host mode */ 1369 if (tegra->otg_usb3_port >= 0) { 1370 if (tegra->soc->otg_reset_sspi) { 1371 /* set PP=0 */ 1372 tegra_xhci_hc_driver.hub_control( 1373 xhci->shared_hcd, GetPortStatus, 1374 0, tegra->otg_usb3_port+1, 1375 (char *) &status, sizeof(status)); 1376 if (status & USB_SS_PORT_STAT_POWER) 1377 tegra_xhci_set_port_power(tegra, false, 1378 false); 1379 1380 /* reset OTG port SSPI */ 1381 msg.cmd = MBOX_CMD_RESET_SSPI; 1382 msg.data = tegra->otg_usb3_port+1; 1383 1384 ret = tegra_xusb_mbox_send(tegra, &msg); 1385 if (ret < 0) { 1386 dev_info(tegra->dev, 1387 "failed to RESET_SSPI %d\n", 1388 ret); 1389 } 1390 } 1391 1392 tegra_xhci_set_port_power(tegra, false, true); 1393 } 1394 1395 tegra_xhci_set_port_power(tegra, true, true); 1396 1397 } else { 1398 if (tegra->otg_usb3_port >= 0) 1399 tegra_xhci_set_port_power(tegra, false, false); 1400 1401 tegra_xhci_set_port_power(tegra, true, false); 1402 } 1403 } 1404 1405 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP) 1406 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index) 1407 { 1408 return (tegra->usbphy[index] != NULL); 1409 } 1410 1411 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index) 1412 { 1413 struct tegra_xusb_padctl *padctl = tegra->padctl; 1414 unsigned int i; 1415 int port; 1416 1417 for (i = 0; i < tegra->num_usb_phys; i++) { 1418 if (is_usb2_otg_phy(tegra, i)) { 1419 port = tegra_xusb_padctl_get_usb3_companion(padctl, i); 1420 if ((port >= 0) && (index == (unsigned int)port)) 1421 return true; 1422 } 1423 } 1424 1425 return false; 1426 } 1427 1428 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index) 1429 { 1430 if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0) 1431 return true; 1432 1433 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) { 1434 if (is_usb2_otg_phy(tegra, index)) 1435 return ((index == tegra->otg_usb2_port) && tegra->host_mode); 1436 else 1437 return true; 1438 } 1439 1440 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) { 1441 if (is_usb3_otg_phy(tegra, index)) 1442 return ((index == tegra->otg_usb3_port) && tegra->host_mode); 1443 else 1444 return true; 1445 } 1446 1447 return false; 1448 } 1449 #endif 1450 1451 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra, 1452 struct usb_phy *usbphy) 1453 { 1454 unsigned int i; 1455 1456 for (i = 0; i < tegra->num_usb_phys; i++) { 1457 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i]) 1458 return i; 1459 } 1460 1461 return -1; 1462 } 1463 1464 static int tegra_xhci_id_notify(struct notifier_block *nb, 1465 unsigned long action, void *data) 1466 { 1467 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb, 1468 id_nb); 1469 struct usb_phy *usbphy = (struct usb_phy *)data; 1470 1471 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event); 1472 1473 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) || 1474 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) { 1475 dev_dbg(tegra->dev, "Same role(%d) received. Ignore", 1476 tegra->host_mode); 1477 return NOTIFY_OK; 1478 } 1479 1480 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy); 1481 1482 tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false; 1483 1484 schedule_work(&tegra->id_work); 1485 1486 return NOTIFY_OK; 1487 } 1488 1489 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra) 1490 { 1491 unsigned int i; 1492 1493 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys, 1494 sizeof(*tegra->usbphy), GFP_KERNEL); 1495 if (!tegra->usbphy) 1496 return -ENOMEM; 1497 1498 INIT_WORK(&tegra->id_work, tegra_xhci_id_work); 1499 tegra->id_nb.notifier_call = tegra_xhci_id_notify; 1500 tegra->otg_usb2_port = -EINVAL; 1501 tegra->otg_usb3_port = -EINVAL; 1502 1503 for (i = 0; i < tegra->num_usb_phys; i++) { 1504 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); 1505 1506 if (!phy) 1507 continue; 1508 1509 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev, 1510 phy->dev.of_node, 1511 &tegra->id_nb); 1512 if (!IS_ERR(tegra->usbphy[i])) { 1513 dev_dbg(tegra->dev, "usbphy-%d registered", i); 1514 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self); 1515 } else { 1516 /* 1517 * usb-phy is optional, continue if its not available. 1518 */ 1519 tegra->usbphy[i] = NULL; 1520 } 1521 } 1522 1523 return 0; 1524 } 1525 1526 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra) 1527 { 1528 unsigned int i; 1529 1530 cancel_work_sync(&tegra->id_work); 1531 1532 for (i = 0; i < tegra->num_usb_phys; i++) 1533 if (tegra->usbphy[i]) 1534 otg_set_host(tegra->usbphy[i]->otg, NULL); 1535 } 1536 1537 static int tegra_xusb_probe(struct platform_device *pdev) 1538 { 1539 struct tegra_xusb *tegra; 1540 struct device_node *np; 1541 struct resource *regs; 1542 struct xhci_hcd *xhci; 1543 unsigned int i, j, k; 1544 struct phy *phy; 1545 int err; 1546 1547 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 1548 1549 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 1550 if (!tegra) 1551 return -ENOMEM; 1552 1553 tegra->soc = of_device_get_match_data(&pdev->dev); 1554 mutex_init(&tegra->lock); 1555 tegra->dev = &pdev->dev; 1556 1557 err = tegra_xusb_init_context(tegra); 1558 if (err < 0) 1559 return err; 1560 1561 tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1562 if (IS_ERR(tegra->regs)) 1563 return PTR_ERR(tegra->regs); 1564 1565 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1); 1566 if (IS_ERR(tegra->fpci_base)) 1567 return PTR_ERR(tegra->fpci_base); 1568 1569 if (tegra->soc->has_ipfs) { 1570 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); 1571 if (IS_ERR(tegra->ipfs_base)) 1572 return PTR_ERR(tegra->ipfs_base); 1573 } else if (tegra->soc->has_bar2) { 1574 tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2); 1575 if (IS_ERR(tegra->bar2_base)) 1576 return PTR_ERR(tegra->bar2_base); 1577 } 1578 1579 tegra->xhci_irq = platform_get_irq(pdev, 0); 1580 if (tegra->xhci_irq < 0) 1581 return tegra->xhci_irq; 1582 1583 tegra->mbox_irq = platform_get_irq(pdev, 1); 1584 if (tegra->mbox_irq < 0) 1585 return tegra->mbox_irq; 1586 1587 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 1588 if (IS_ERR(tegra->padctl)) 1589 return PTR_ERR(tegra->padctl); 1590 1591 np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0); 1592 if (!np) { 1593 err = -ENODEV; 1594 goto put_padctl; 1595 } 1596 1597 tegra->padctl_irq = of_irq_get(np, 0); 1598 if (tegra->padctl_irq == -EPROBE_DEFER) { 1599 err = tegra->padctl_irq; 1600 goto put_padctl; 1601 } else if (tegra->padctl_irq <= 0) { 1602 /* Older device-trees don't have padctrl interrupt */ 1603 tegra->padctl_irq = 0; 1604 dev_dbg(&pdev->dev, 1605 "%pOF is missing an interrupt, disabling PM support\n", np); 1606 } 1607 1608 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 1609 if (IS_ERR(tegra->host_clk)) { 1610 err = PTR_ERR(tegra->host_clk); 1611 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 1612 goto put_padctl; 1613 } 1614 1615 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 1616 if (IS_ERR(tegra->falcon_clk)) { 1617 err = PTR_ERR(tegra->falcon_clk); 1618 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 1619 goto put_padctl; 1620 } 1621 1622 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 1623 if (IS_ERR(tegra->ss_clk)) { 1624 err = PTR_ERR(tegra->ss_clk); 1625 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 1626 goto put_padctl; 1627 } 1628 1629 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 1630 if (IS_ERR(tegra->ss_src_clk)) { 1631 err = PTR_ERR(tegra->ss_src_clk); 1632 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 1633 goto put_padctl; 1634 } 1635 1636 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 1637 if (IS_ERR(tegra->hs_src_clk)) { 1638 err = PTR_ERR(tegra->hs_src_clk); 1639 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 1640 goto put_padctl; 1641 } 1642 1643 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 1644 if (IS_ERR(tegra->fs_src_clk)) { 1645 err = PTR_ERR(tegra->fs_src_clk); 1646 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 1647 goto put_padctl; 1648 } 1649 1650 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 1651 if (IS_ERR(tegra->pll_u_480m)) { 1652 err = PTR_ERR(tegra->pll_u_480m); 1653 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 1654 goto put_padctl; 1655 } 1656 1657 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 1658 if (IS_ERR(tegra->clk_m)) { 1659 err = PTR_ERR(tegra->clk_m); 1660 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1661 goto put_padctl; 1662 } 1663 1664 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1665 if (IS_ERR(tegra->pll_e)) { 1666 err = PTR_ERR(tegra->pll_e); 1667 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1668 goto put_padctl; 1669 } 1670 1671 if (!of_property_present(pdev->dev.of_node, "power-domains")) { 1672 tegra->host_rst = devm_reset_control_get(&pdev->dev, 1673 "xusb_host"); 1674 if (IS_ERR(tegra->host_rst)) { 1675 err = PTR_ERR(tegra->host_rst); 1676 dev_err(&pdev->dev, 1677 "failed to get xusb_host reset: %d\n", err); 1678 goto put_padctl; 1679 } 1680 1681 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 1682 if (IS_ERR(tegra->ss_rst)) { 1683 err = PTR_ERR(tegra->ss_rst); 1684 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", 1685 err); 1686 goto put_padctl; 1687 } 1688 } else { 1689 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); 1690 if (err) 1691 goto put_powerdomains; 1692 } 1693 1694 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1695 sizeof(*tegra->supplies), GFP_KERNEL); 1696 if (!tegra->supplies) { 1697 err = -ENOMEM; 1698 goto put_powerdomains; 1699 } 1700 1701 regulator_bulk_set_supply_names(tegra->supplies, 1702 tegra->soc->supply_names, 1703 tegra->soc->num_supplies); 1704 1705 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1706 tegra->supplies); 1707 if (err) { 1708 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1709 goto put_powerdomains; 1710 } 1711 1712 for (i = 0; i < tegra->soc->num_types; i++) { 1713 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4)) 1714 tegra->num_usb_phys = tegra->soc->phy_types[i].num; 1715 tegra->num_phys += tegra->soc->phy_types[i].num; 1716 } 1717 1718 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1719 sizeof(*tegra->phys), GFP_KERNEL); 1720 if (!tegra->phys) { 1721 err = -ENOMEM; 1722 goto put_powerdomains; 1723 } 1724 1725 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1726 char prop[8]; 1727 1728 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1729 snprintf(prop, sizeof(prop), "%s-%d", 1730 tegra->soc->phy_types[i].name, j); 1731 1732 phy = devm_phy_optional_get(&pdev->dev, prop); 1733 if (IS_ERR(phy)) { 1734 dev_err(&pdev->dev, 1735 "failed to get PHY %s: %ld\n", prop, 1736 PTR_ERR(phy)); 1737 err = PTR_ERR(phy); 1738 goto put_powerdomains; 1739 } 1740 1741 tegra->phys[k++] = phy; 1742 } 1743 } 1744 1745 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1746 dev_name(&pdev->dev)); 1747 if (!tegra->hcd) { 1748 err = -ENOMEM; 1749 goto put_powerdomains; 1750 } 1751 1752 tegra->hcd->skip_phy_initialization = 1; 1753 tegra->hcd->regs = tegra->regs; 1754 tegra->hcd->rsrc_start = regs->start; 1755 tegra->hcd->rsrc_len = resource_size(regs); 1756 1757 /* 1758 * This must happen after usb_create_hcd(), because usb_create_hcd() 1759 * will overwrite the drvdata of the device with the hcd it creates. 1760 */ 1761 platform_set_drvdata(pdev, tegra); 1762 1763 err = tegra_xusb_clk_enable(tegra); 1764 if (err) { 1765 dev_err(tegra->dev, "failed to enable clocks: %d\n", err); 1766 goto put_hcd; 1767 } 1768 1769 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 1770 if (err) { 1771 dev_err(tegra->dev, "failed to enable regulators: %d\n", err); 1772 goto disable_clk; 1773 } 1774 1775 err = tegra_xusb_phy_enable(tegra); 1776 if (err < 0) { 1777 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); 1778 goto disable_regulator; 1779 } 1780 1781 /* 1782 * The XUSB Falcon microcontroller can only address 40 bits, so set 1783 * the DMA mask accordingly. 1784 */ 1785 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40)); 1786 if (err < 0) { 1787 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 1788 goto disable_phy; 1789 } 1790 1791 if (tegra->soc->firmware) { 1792 err = tegra_xusb_request_firmware(tegra); 1793 if (err < 0) { 1794 dev_err(&pdev->dev, 1795 "failed to request firmware: %d\n", err); 1796 goto disable_phy; 1797 } 1798 } 1799 1800 err = tegra_xusb_unpowergate_partitions(tegra); 1801 if (err) 1802 goto free_firmware; 1803 1804 tegra_xusb_config(tegra); 1805 1806 err = tegra_xusb_load_firmware(tegra); 1807 if (err < 0) { 1808 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1809 goto powergate; 1810 } 1811 1812 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1813 if (err < 0) { 1814 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1815 goto powergate; 1816 } 1817 1818 device_wakeup_enable(tegra->hcd->self.controller); 1819 1820 xhci = hcd_to_xhci(tegra->hcd); 1821 1822 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1823 &pdev->dev, 1824 dev_name(&pdev->dev), 1825 tegra->hcd); 1826 if (!xhci->shared_hcd) { 1827 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1828 err = -ENOMEM; 1829 goto remove_usb2; 1830 } 1831 1832 if (HCC_MAX_PSA(xhci->hcc_params) >= 4) 1833 xhci->shared_hcd->can_do_streams = 1; 1834 1835 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1836 if (err < 0) { 1837 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1838 goto put_usb3; 1839 } 1840 1841 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1842 tegra_xusb_mbox_irq, 1843 tegra_xusb_mbox_thread, 0, 1844 dev_name(&pdev->dev), tegra); 1845 if (err < 0) { 1846 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1847 goto remove_usb3; 1848 } 1849 1850 if (tegra->padctl_irq) { 1851 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq, 1852 NULL, tegra_xusb_padctl_irq, 1853 IRQF_ONESHOT, dev_name(&pdev->dev), 1854 tegra); 1855 if (err < 0) { 1856 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err); 1857 goto remove_usb3; 1858 } 1859 } 1860 1861 err = tegra_xusb_enable_firmware_messages(tegra); 1862 if (err < 0) { 1863 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1864 goto remove_usb3; 1865 } 1866 1867 err = tegra_xusb_init_usb_phy(tegra); 1868 if (err < 0) { 1869 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err); 1870 goto remove_usb3; 1871 } 1872 1873 /* Enable wake for both USB 2.0 and USB 3.0 roothubs */ 1874 device_init_wakeup(&tegra->hcd->self.root_hub->dev, true); 1875 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true); 1876 1877 pm_runtime_use_autosuspend(tegra->dev); 1878 pm_runtime_set_autosuspend_delay(tegra->dev, 2000); 1879 pm_runtime_mark_last_busy(tegra->dev); 1880 pm_runtime_set_active(tegra->dev); 1881 1882 if (tegra->padctl_irq) { 1883 device_init_wakeup(tegra->dev, true); 1884 pm_runtime_enable(tegra->dev); 1885 } 1886 1887 return 0; 1888 1889 remove_usb3: 1890 usb_remove_hcd(xhci->shared_hcd); 1891 put_usb3: 1892 usb_put_hcd(xhci->shared_hcd); 1893 remove_usb2: 1894 usb_remove_hcd(tegra->hcd); 1895 powergate: 1896 tegra_xusb_powergate_partitions(tegra); 1897 free_firmware: 1898 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1899 tegra->fw.phys); 1900 disable_phy: 1901 tegra_xusb_phy_disable(tegra); 1902 disable_regulator: 1903 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1904 disable_clk: 1905 tegra_xusb_clk_disable(tegra); 1906 put_hcd: 1907 usb_put_hcd(tegra->hcd); 1908 put_powerdomains: 1909 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1910 put_padctl: 1911 of_node_put(np); 1912 tegra_xusb_padctl_put(tegra->padctl); 1913 return err; 1914 } 1915 1916 static void tegra_xusb_disable(struct tegra_xusb *tegra) 1917 { 1918 tegra_xusb_powergate_partitions(tegra); 1919 tegra_xusb_powerdomain_remove(tegra->dev, tegra); 1920 tegra_xusb_phy_disable(tegra); 1921 tegra_xusb_clk_disable(tegra); 1922 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1923 } 1924 1925 static void tegra_xusb_remove(struct platform_device *pdev) 1926 { 1927 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1928 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1929 1930 tegra_xusb_deinit_usb_phy(tegra); 1931 1932 pm_runtime_get_sync(&pdev->dev); 1933 usb_remove_hcd(xhci->shared_hcd); 1934 usb_put_hcd(xhci->shared_hcd); 1935 xhci->shared_hcd = NULL; 1936 usb_remove_hcd(tegra->hcd); 1937 usb_put_hcd(tegra->hcd); 1938 1939 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1940 tegra->fw.phys); 1941 1942 if (tegra->padctl_irq) 1943 pm_runtime_disable(&pdev->dev); 1944 1945 pm_runtime_put(&pdev->dev); 1946 1947 tegra_xusb_disable(tegra); 1948 tegra_xusb_padctl_put(tegra->padctl); 1949 } 1950 1951 static void tegra_xusb_shutdown(struct platform_device *pdev) 1952 { 1953 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1954 1955 pm_runtime_get_sync(&pdev->dev); 1956 disable_irq(tegra->xhci_irq); 1957 xhci_shutdown(tegra->hcd); 1958 tegra_xusb_disable(tegra); 1959 } 1960 1961 static bool xhci_hub_ports_suspended(struct xhci_hub *hub) 1962 { 1963 struct device *dev = hub->hcd->self.controller; 1964 bool status = true; 1965 unsigned int i; 1966 u32 value; 1967 1968 for (i = 0; i < hub->num_ports; i++) { 1969 value = readl(hub->ports[i]->addr); 1970 if ((value & PORT_PE) == 0) 1971 continue; 1972 1973 if ((value & PORT_PLS_MASK) != XDEV_U3) { 1974 dev_info(dev, "%u-%u isn't suspended: %#010x\n", 1975 hub->hcd->self.busnum, i + 1, value); 1976 status = false; 1977 } 1978 } 1979 1980 return status; 1981 } 1982 1983 static int tegra_xusb_check_ports(struct tegra_xusb *tegra) 1984 { 1985 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1986 struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state; 1987 unsigned long flags; 1988 int err = 0; 1989 1990 if (bus_state->bus_suspended) { 1991 /* xusb_hub_suspend() has just directed one or more USB2 port(s) 1992 * to U3 state, it takes 3ms to enter U3. 1993 */ 1994 usleep_range(3000, 4000); 1995 } 1996 1997 spin_lock_irqsave(&xhci->lock, flags); 1998 1999 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) || 2000 !xhci_hub_ports_suspended(&xhci->usb3_rhub)) 2001 err = -EBUSY; 2002 2003 spin_unlock_irqrestore(&xhci->lock, flags); 2004 2005 return err; 2006 } 2007 2008 static void tegra_xusb_save_context(struct tegra_xusb *tegra) 2009 { 2010 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 2011 struct tegra_xusb_context *ctx = &tegra->context; 2012 unsigned int i; 2013 2014 if (soc->ipfs.num_offsets > 0) { 2015 for (i = 0; i < soc->ipfs.num_offsets; i++) 2016 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]); 2017 } 2018 2019 if (soc->fpci.num_offsets > 0) { 2020 for (i = 0; i < soc->fpci.num_offsets; i++) 2021 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]); 2022 } 2023 } 2024 2025 static void tegra_xusb_restore_context(struct tegra_xusb *tegra) 2026 { 2027 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 2028 struct tegra_xusb_context *ctx = &tegra->context; 2029 unsigned int i; 2030 2031 if (soc->fpci.num_offsets > 0) { 2032 for (i = 0; i < soc->fpci.num_offsets; i++) 2033 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]); 2034 } 2035 2036 if (soc->ipfs.num_offsets > 0) { 2037 for (i = 0; i < soc->ipfs.num_offsets; i++) 2038 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]); 2039 } 2040 } 2041 2042 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc) 2043 { 2044 if (DEV_LOWSPEED(portsc)) 2045 return USB_SPEED_LOW; 2046 2047 if (DEV_HIGHSPEED(portsc)) 2048 return USB_SPEED_HIGH; 2049 2050 if (DEV_FULLSPEED(portsc)) 2051 return USB_SPEED_FULL; 2052 2053 if (DEV_SUPERSPEED_ANY(portsc)) 2054 return USB_SPEED_SUPER; 2055 2056 return USB_SPEED_UNKNOWN; 2057 } 2058 2059 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra) 2060 { 2061 struct tegra_xusb_padctl *padctl = tegra->padctl; 2062 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2063 enum usb_device_speed speed; 2064 struct phy *phy; 2065 unsigned int index, offset; 2066 unsigned int i, j, k; 2067 struct xhci_hub *rhub; 2068 u32 portsc; 2069 2070 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 2071 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0) 2072 rhub = &xhci->usb3_rhub; 2073 else 2074 rhub = &xhci->usb2_rhub; 2075 2076 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0) 2077 offset = tegra->soc->ports.usb2.count; 2078 else 2079 offset = 0; 2080 2081 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 2082 phy = tegra->phys[k++]; 2083 2084 if (!phy) 2085 continue; 2086 2087 index = j + offset; 2088 2089 if (index >= rhub->num_ports) 2090 continue; 2091 2092 if (!is_host_mode_phy(tegra, i, j)) 2093 continue; 2094 2095 portsc = readl(rhub->ports[index]->addr); 2096 speed = tegra_xhci_portsc_to_speed(tegra, portsc); 2097 tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed); 2098 tegra_xusb_padctl_enable_phy_wake(padctl, phy); 2099 } 2100 } 2101 } 2102 2103 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra) 2104 { 2105 struct tegra_xusb_padctl *padctl = tegra->padctl; 2106 unsigned int i; 2107 2108 for (i = 0; i < tegra->num_usb_phys; i++) { 2109 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); 2110 2111 if (!phy) 2112 continue; 2113 2114 if (tegra_xusb_padctl_remote_wake_detected(padctl, phy)) 2115 tegra_phy_xusb_utmi_pad_power_on(phy); 2116 } 2117 2118 for (i = 0; i < tegra->num_phys; i++) { 2119 if (!tegra->phys[i]) 2120 continue; 2121 2122 if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i])) 2123 dev_dbg(tegra->dev, "%pOF remote wake detected\n", 2124 tegra->phys[i]->dev.of_node); 2125 2126 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]); 2127 } 2128 } 2129 2130 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra) 2131 { 2132 struct tegra_xusb_padctl *padctl = tegra->padctl; 2133 unsigned int i; 2134 2135 for (i = 0; i < tegra->num_phys; i++) { 2136 if (!tegra->phys[i]) 2137 continue; 2138 2139 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]); 2140 } 2141 } 2142 2143 static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra) 2144 { 2145 unsigned int i, index_to_usb2; 2146 struct phy *phy; 2147 2148 for (i = 0; i < tegra->soc->num_types; i++) { 2149 if (strcmp(tegra->soc->phy_types[i].name, "usb2") == 0) 2150 index_to_usb2 = i; 2151 } 2152 2153 for (i = 0; i < tegra->num_usb_phys; i++) { 2154 if (!is_host_mode_phy(tegra, index_to_usb2, i)) 2155 continue; 2156 2157 phy = tegra_xusb_get_phy(tegra, "usb2", i); 2158 if (tegra->lp0_utmi_pad_mask & BIT(i)) 2159 tegra_phy_xusb_utmi_pad_power_on(phy); 2160 else 2161 tegra_phy_xusb_utmi_pad_power_down(phy); 2162 } 2163 } 2164 2165 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime) 2166 { 2167 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2168 struct device *dev = tegra->dev; 2169 bool wakeup = runtime ? true : device_may_wakeup(dev); 2170 unsigned int i; 2171 int err; 2172 u32 usbcmd; 2173 u32 portsc; 2174 2175 dev_dbg(dev, "entering ELPG\n"); 2176 2177 usbcmd = readl(&xhci->op_regs->command); 2178 usbcmd &= ~CMD_EIE; 2179 writel(usbcmd, &xhci->op_regs->command); 2180 2181 err = tegra_xusb_check_ports(tegra); 2182 if (err < 0) { 2183 dev_err(tegra->dev, "not all ports suspended: %d\n", err); 2184 goto out; 2185 } 2186 2187 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) { 2188 if (!xhci->usb2_rhub.ports[i]) 2189 continue; 2190 portsc = readl(xhci->usb2_rhub.ports[i]->addr); 2191 tegra->lp0_utmi_pad_mask &= ~BIT(i); 2192 if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS)) 2193 tegra->lp0_utmi_pad_mask |= BIT(i); 2194 } 2195 2196 err = xhci_suspend(xhci, wakeup); 2197 if (err < 0) { 2198 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err); 2199 goto out; 2200 } 2201 2202 tegra_xusb_save_context(tegra); 2203 2204 if (wakeup) 2205 tegra_xhci_enable_phy_sleepwalk_wake(tegra); 2206 2207 tegra_xusb_powergate_partitions(tegra); 2208 2209 for (i = 0; i < tegra->num_phys; i++) { 2210 if (!tegra->phys[i]) 2211 continue; 2212 2213 phy_power_off(tegra->phys[i]); 2214 if (!wakeup) 2215 phy_exit(tegra->phys[i]); 2216 } 2217 2218 tegra_xusb_clk_disable(tegra); 2219 2220 out: 2221 if (!err) 2222 dev_dbg(tegra->dev, "entering ELPG done\n"); 2223 else { 2224 usbcmd = readl(&xhci->op_regs->command); 2225 usbcmd |= CMD_EIE; 2226 writel(usbcmd, &xhci->op_regs->command); 2227 2228 dev_dbg(tegra->dev, "entering ELPG failed\n"); 2229 pm_runtime_mark_last_busy(tegra->dev); 2230 } 2231 2232 return err; 2233 } 2234 2235 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime) 2236 { 2237 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2238 struct device *dev = tegra->dev; 2239 bool wakeup = runtime ? true : device_may_wakeup(dev); 2240 unsigned int i; 2241 u32 usbcmd; 2242 int err; 2243 2244 dev_dbg(dev, "exiting ELPG\n"); 2245 pm_runtime_mark_last_busy(tegra->dev); 2246 2247 err = tegra_xusb_clk_enable(tegra); 2248 if (err < 0) { 2249 dev_err(tegra->dev, "failed to enable clocks: %d\n", err); 2250 goto out; 2251 } 2252 2253 err = tegra_xusb_unpowergate_partitions(tegra); 2254 if (err) 2255 goto disable_clks; 2256 2257 if (wakeup) 2258 tegra_xhci_disable_phy_wake(tegra); 2259 2260 for (i = 0; i < tegra->num_phys; i++) { 2261 if (!tegra->phys[i]) 2262 continue; 2263 2264 if (!wakeup) 2265 phy_init(tegra->phys[i]); 2266 2267 phy_power_on(tegra->phys[i]); 2268 } 2269 if (tegra->suspended) 2270 tegra_xhci_program_utmi_power_lp0_exit(tegra); 2271 2272 tegra_xusb_config(tegra); 2273 tegra_xusb_restore_context(tegra); 2274 2275 err = tegra_xusb_load_firmware(tegra); 2276 if (err < 0) { 2277 dev_err(tegra->dev, "failed to load firmware: %d\n", err); 2278 goto disable_phy; 2279 } 2280 2281 err = __tegra_xusb_enable_firmware_messages(tegra); 2282 if (err < 0) { 2283 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 2284 goto disable_phy; 2285 } 2286 2287 if (wakeup) 2288 tegra_xhci_disable_phy_sleepwalk(tegra); 2289 2290 err = xhci_resume(xhci, runtime ? PMSG_AUTO_RESUME : PMSG_RESUME); 2291 if (err < 0) { 2292 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err); 2293 goto disable_phy; 2294 } 2295 2296 usbcmd = readl(&xhci->op_regs->command); 2297 usbcmd |= CMD_EIE; 2298 writel(usbcmd, &xhci->op_regs->command); 2299 2300 goto out; 2301 2302 disable_phy: 2303 for (i = 0; i < tegra->num_phys; i++) { 2304 if (!tegra->phys[i]) 2305 continue; 2306 2307 phy_power_off(tegra->phys[i]); 2308 if (!wakeup) 2309 phy_exit(tegra->phys[i]); 2310 } 2311 tegra_xusb_powergate_partitions(tegra); 2312 disable_clks: 2313 tegra_xusb_clk_disable(tegra); 2314 out: 2315 if (!err) 2316 dev_dbg(dev, "exiting ELPG done\n"); 2317 else 2318 dev_dbg(dev, "exiting ELPG failed\n"); 2319 2320 return err; 2321 } 2322 2323 static __maybe_unused int tegra_xusb_suspend(struct device *dev) 2324 { 2325 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2326 int err; 2327 2328 synchronize_irq(tegra->mbox_irq); 2329 2330 mutex_lock(&tegra->lock); 2331 2332 if (pm_runtime_suspended(dev)) { 2333 err = tegra_xusb_exit_elpg(tegra, true); 2334 if (err < 0) 2335 goto out; 2336 } 2337 2338 err = tegra_xusb_enter_elpg(tegra, false); 2339 if (err < 0) { 2340 if (pm_runtime_suspended(dev)) { 2341 pm_runtime_disable(dev); 2342 pm_runtime_set_active(dev); 2343 pm_runtime_enable(dev); 2344 } 2345 2346 goto out; 2347 } 2348 2349 out: 2350 if (!err) { 2351 tegra->suspended = true; 2352 pm_runtime_disable(dev); 2353 2354 if (device_may_wakeup(dev)) { 2355 if (enable_irq_wake(tegra->padctl_irq)) 2356 dev_err(dev, "failed to enable padctl wakes\n"); 2357 } 2358 } 2359 2360 mutex_unlock(&tegra->lock); 2361 2362 return err; 2363 } 2364 2365 static __maybe_unused int tegra_xusb_resume(struct device *dev) 2366 { 2367 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2368 int err; 2369 2370 mutex_lock(&tegra->lock); 2371 2372 if (!tegra->suspended) { 2373 mutex_unlock(&tegra->lock); 2374 return 0; 2375 } 2376 2377 err = tegra_xusb_exit_elpg(tegra, false); 2378 if (err < 0) { 2379 mutex_unlock(&tegra->lock); 2380 return err; 2381 } 2382 2383 if (device_may_wakeup(dev)) { 2384 if (disable_irq_wake(tegra->padctl_irq)) 2385 dev_err(dev, "failed to disable padctl wakes\n"); 2386 } 2387 tegra->suspended = false; 2388 mutex_unlock(&tegra->lock); 2389 2390 pm_runtime_set_active(dev); 2391 pm_runtime_enable(dev); 2392 2393 return 0; 2394 } 2395 2396 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev) 2397 { 2398 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2399 int ret; 2400 2401 synchronize_irq(tegra->mbox_irq); 2402 mutex_lock(&tegra->lock); 2403 ret = tegra_xusb_enter_elpg(tegra, true); 2404 mutex_unlock(&tegra->lock); 2405 2406 return ret; 2407 } 2408 2409 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev) 2410 { 2411 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2412 int err; 2413 2414 mutex_lock(&tegra->lock); 2415 err = tegra_xusb_exit_elpg(tegra, true); 2416 mutex_unlock(&tegra->lock); 2417 2418 return err; 2419 } 2420 2421 static const struct dev_pm_ops tegra_xusb_pm_ops = { 2422 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, 2423 tegra_xusb_runtime_resume, NULL) 2424 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 2425 }; 2426 2427 static const char * const tegra124_supply_names[] = { 2428 "avddio-pex", 2429 "dvddio-pex", 2430 "avdd-usb", 2431 "hvdd-usb-ss", 2432 }; 2433 2434 static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 2435 { .name = "usb3", .num = 2, }, 2436 { .name = "usb2", .num = 3, }, 2437 { .name = "hsic", .num = 2, }, 2438 }; 2439 2440 static const unsigned int tegra124_xusb_context_ipfs[] = { 2441 IPFS_XUSB_HOST_MSI_BAR_SZ_0, 2442 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0, 2443 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0, 2444 IPFS_XUSB_HOST_MSI_VEC0_0, 2445 IPFS_XUSB_HOST_MSI_EN_VEC0_0, 2446 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0, 2447 IPFS_XUSB_HOST_INTR_MASK_0, 2448 IPFS_XUSB_HOST_INTR_ENABLE_0, 2449 IPFS_XUSB_HOST_UFPCI_CONFIG_0, 2450 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0, 2451 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0, 2452 }; 2453 2454 static const unsigned int tegra124_xusb_context_fpci[] = { 2455 XUSB_CFG_ARU_CONTEXT_HS_PLS, 2456 XUSB_CFG_ARU_CONTEXT_FS_PLS, 2457 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED, 2458 XUSB_CFG_ARU_CONTEXT_HSFS_PP, 2459 XUSB_CFG_ARU_CONTEXT, 2460 XUSB_CFG_AXI_CFG, 2461 XUSB_CFG_24, 2462 XUSB_CFG_16, 2463 }; 2464 2465 static const struct tegra_xusb_context_soc tegra124_xusb_context = { 2466 .ipfs = { 2467 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs), 2468 .offsets = tegra124_xusb_context_ipfs, 2469 }, 2470 .fpci = { 2471 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 2472 .offsets = tegra124_xusb_context_fpci, 2473 }, 2474 }; 2475 2476 static const struct tegra_xusb_soc_ops tegra124_ops = { 2477 .mbox_reg_readl = &fpci_readl, 2478 .mbox_reg_writel = &fpci_writel, 2479 .csb_reg_readl = &fpci_csb_readl, 2480 .csb_reg_writel = &fpci_csb_writel, 2481 }; 2482 2483 static const struct tegra_xusb_soc tegra124_soc = { 2484 .firmware = "nvidia/tegra124/xusb.bin", 2485 .supply_names = tegra124_supply_names, 2486 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 2487 .phy_types = tegra124_phy_types, 2488 .num_types = ARRAY_SIZE(tegra124_phy_types), 2489 .context = &tegra124_xusb_context, 2490 .ports = { 2491 .usb2 = { .offset = 4, .count = 4, }, 2492 .hsic = { .offset = 6, .count = 2, }, 2493 .usb3 = { .offset = 0, .count = 2, }, 2494 }, 2495 .scale_ss_clock = true, 2496 .has_ipfs = true, 2497 .otg_reset_sspi = false, 2498 .ops = &tegra124_ops, 2499 .mbox = { 2500 .cmd = 0xe4, 2501 .data_in = 0xe8, 2502 .data_out = 0xec, 2503 .owner = 0xf0, 2504 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2505 }, 2506 }; 2507 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 2508 2509 static const char * const tegra210_supply_names[] = { 2510 "dvddio-pex", 2511 "hvddio-pex", 2512 "avdd-usb", 2513 }; 2514 2515 static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 2516 { .name = "usb3", .num = 4, }, 2517 { .name = "usb2", .num = 4, }, 2518 { .name = "hsic", .num = 1, }, 2519 }; 2520 2521 static const struct tegra_xusb_soc tegra210_soc = { 2522 .firmware = "nvidia/tegra210/xusb.bin", 2523 .supply_names = tegra210_supply_names, 2524 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 2525 .phy_types = tegra210_phy_types, 2526 .num_types = ARRAY_SIZE(tegra210_phy_types), 2527 .context = &tegra124_xusb_context, 2528 .ports = { 2529 .usb2 = { .offset = 4, .count = 4, }, 2530 .hsic = { .offset = 8, .count = 1, }, 2531 .usb3 = { .offset = 0, .count = 4, }, 2532 }, 2533 .scale_ss_clock = false, 2534 .has_ipfs = true, 2535 .otg_reset_sspi = true, 2536 .ops = &tegra124_ops, 2537 .mbox = { 2538 .cmd = 0xe4, 2539 .data_in = 0xe8, 2540 .data_out = 0xec, 2541 .owner = 0xf0, 2542 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2543 }, 2544 }; 2545 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 2546 2547 static const char * const tegra186_supply_names[] = { 2548 }; 2549 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin"); 2550 2551 static const struct tegra_xusb_phy_type tegra186_phy_types[] = { 2552 { .name = "usb3", .num = 3, }, 2553 { .name = "usb2", .num = 3, }, 2554 { .name = "hsic", .num = 1, }, 2555 }; 2556 2557 static const struct tegra_xusb_context_soc tegra186_xusb_context = { 2558 .fpci = { 2559 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 2560 .offsets = tegra124_xusb_context_fpci, 2561 }, 2562 }; 2563 2564 static const struct tegra_xusb_soc tegra186_soc = { 2565 .firmware = "nvidia/tegra186/xusb.bin", 2566 .supply_names = tegra186_supply_names, 2567 .num_supplies = ARRAY_SIZE(tegra186_supply_names), 2568 .phy_types = tegra186_phy_types, 2569 .num_types = ARRAY_SIZE(tegra186_phy_types), 2570 .context = &tegra186_xusb_context, 2571 .ports = { 2572 .usb3 = { .offset = 0, .count = 3, }, 2573 .usb2 = { .offset = 3, .count = 3, }, 2574 .hsic = { .offset = 6, .count = 1, }, 2575 }, 2576 .scale_ss_clock = false, 2577 .has_ipfs = false, 2578 .otg_reset_sspi = false, 2579 .ops = &tegra124_ops, 2580 .mbox = { 2581 .cmd = 0xe4, 2582 .data_in = 0xe8, 2583 .data_out = 0xec, 2584 .owner = 0xf0, 2585 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2586 }, 2587 .lpm_support = true, 2588 }; 2589 2590 static const char * const tegra194_supply_names[] = { 2591 }; 2592 2593 static const struct tegra_xusb_phy_type tegra194_phy_types[] = { 2594 { .name = "usb3", .num = 4, }, 2595 { .name = "usb2", .num = 4, }, 2596 }; 2597 2598 static const struct tegra_xusb_soc tegra194_soc = { 2599 .firmware = "nvidia/tegra194/xusb.bin", 2600 .supply_names = tegra194_supply_names, 2601 .num_supplies = ARRAY_SIZE(tegra194_supply_names), 2602 .phy_types = tegra194_phy_types, 2603 .num_types = ARRAY_SIZE(tegra194_phy_types), 2604 .context = &tegra186_xusb_context, 2605 .ports = { 2606 .usb3 = { .offset = 0, .count = 4, }, 2607 .usb2 = { .offset = 4, .count = 4, }, 2608 }, 2609 .scale_ss_clock = false, 2610 .has_ipfs = false, 2611 .otg_reset_sspi = false, 2612 .ops = &tegra124_ops, 2613 .mbox = { 2614 .cmd = 0x68, 2615 .data_in = 0x6c, 2616 .data_out = 0x70, 2617 .owner = 0x74, 2618 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2619 }, 2620 .lpm_support = true, 2621 }; 2622 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); 2623 2624 static const struct tegra_xusb_soc_ops tegra234_ops = { 2625 .mbox_reg_readl = &bar2_readl, 2626 .mbox_reg_writel = &bar2_writel, 2627 .csb_reg_readl = &bar2_csb_readl, 2628 .csb_reg_writel = &bar2_csb_writel, 2629 }; 2630 2631 static const struct tegra_xusb_soc tegra234_soc = { 2632 .supply_names = tegra194_supply_names, 2633 .num_supplies = ARRAY_SIZE(tegra194_supply_names), 2634 .phy_types = tegra194_phy_types, 2635 .num_types = ARRAY_SIZE(tegra194_phy_types), 2636 .context = &tegra186_xusb_context, 2637 .ports = { 2638 .usb3 = { .offset = 0, .count = 4, }, 2639 .usb2 = { .offset = 4, .count = 4, }, 2640 }, 2641 .scale_ss_clock = false, 2642 .has_ipfs = false, 2643 .otg_reset_sspi = false, 2644 .ops = &tegra234_ops, 2645 .mbox = { 2646 .cmd = XUSB_BAR2_ARU_MBOX_CMD, 2647 .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, 2648 .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, 2649 .owner = XUSB_BAR2_ARU_MBOX_OWNER, 2650 .smi_intr = XUSB_BAR2_ARU_SMI_INTR, 2651 }, 2652 .lpm_support = true, 2653 .has_bar2 = true, 2654 }; 2655 2656 static const struct of_device_id tegra_xusb_of_match[] = { 2657 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 2658 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 2659 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, 2660 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, 2661 { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, 2662 { }, 2663 }; 2664 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 2665 2666 static struct platform_driver tegra_xusb_driver = { 2667 .probe = tegra_xusb_probe, 2668 .remove = tegra_xusb_remove, 2669 .shutdown = tegra_xusb_shutdown, 2670 .driver = { 2671 .name = "tegra-xusb", 2672 .pm = &tegra_xusb_pm_ops, 2673 .of_match_table = tegra_xusb_of_match, 2674 }, 2675 }; 2676 2677 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 2678 { 2679 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2680 2681 if (tegra && tegra->soc->lpm_support) 2682 xhci->quirks |= XHCI_LPM_SUPPORT; 2683 } 2684 2685 static int tegra_xhci_setup(struct usb_hcd *hcd) 2686 { 2687 return xhci_gen_setup(hcd, tegra_xhci_quirks); 2688 } 2689 2690 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index, 2691 char *buf, u16 length) 2692 { 2693 struct tegra_xusb *tegra = dev_get_drvdata(hcd->self.controller); 2694 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2695 struct xhci_hub *rhub; 2696 struct xhci_bus_state *bus_state; 2697 int port = (index & 0xff) - 1; 2698 unsigned int i; 2699 struct xhci_port **ports; 2700 u32 portsc; 2701 int ret; 2702 struct phy *phy; 2703 2704 rhub = &xhci->usb2_rhub; 2705 bus_state = &rhub->bus_state; 2706 if (bus_state->resuming_ports && hcd->speed == HCD_USB2) { 2707 ports = rhub->ports; 2708 i = rhub->num_ports; 2709 while (i--) { 2710 if (!test_bit(i, &bus_state->resuming_ports)) 2711 continue; 2712 portsc = readl(ports[i]->addr); 2713 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME) 2714 tegra_phy_xusb_utmi_pad_power_on( 2715 tegra_xusb_get_phy(tegra, "usb2", (int) i)); 2716 } 2717 } 2718 2719 if (hcd->speed == HCD_USB2) { 2720 phy = tegra_xusb_get_phy(tegra, "usb2", port); 2721 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) { 2722 if (!index || index > rhub->num_ports) 2723 return -EPIPE; 2724 tegra_phy_xusb_utmi_pad_power_on(phy); 2725 } 2726 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) { 2727 if (!index || index > rhub->num_ports) 2728 return -EPIPE; 2729 ports = rhub->ports; 2730 portsc = readl(ports[port]->addr); 2731 if (portsc & PORT_CONNECT) 2732 tegra_phy_xusb_utmi_pad_power_on(phy); 2733 } 2734 } 2735 2736 ret = xhci_hub_control(hcd, type_req, value, index, buf, length); 2737 if (ret < 0) 2738 return ret; 2739 2740 if (hcd->speed == HCD_USB2) { 2741 /* Use phy where we set previously */ 2742 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) 2743 /* We don't suspend the PAD while HNP role swap happens on the OTG port */ 2744 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) 2745 tegra_phy_xusb_utmi_pad_power_down(phy); 2746 2747 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) { 2748 ports = rhub->ports; 2749 portsc = readl(ports[port]->addr); 2750 if (!(portsc & PORT_CONNECT)) { 2751 /* We don't suspend the PAD while HNP role swap happens on the OTG 2752 * port 2753 */ 2754 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) 2755 tegra_phy_xusb_utmi_pad_power_down(phy); 2756 } 2757 } 2758 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST)) 2759 tegra_phy_xusb_utmi_pad_power_on(phy); 2760 } 2761 2762 return ret; 2763 } 2764 2765 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 2766 .reset = tegra_xhci_setup, 2767 .hub_control = tegra_xhci_hub_control, 2768 }; 2769 2770 static int __init tegra_xusb_init(void) 2771 { 2772 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 2773 2774 return platform_driver_register(&tegra_xusb_driver); 2775 } 2776 module_init(tegra_xusb_init); 2777 2778 static void __exit tegra_xusb_exit(void) 2779 { 2780 platform_driver_unregister(&tegra_xusb_driver); 2781 } 2782 module_exit(tegra_xusb_exit); 2783 2784 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 2785 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 2786 MODULE_LICENSE("GPL v2"); 2787