1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (C) 2014 NVIDIA Corporation 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/phy/tegra/xusb.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include "xhci.h" 26 27 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 28 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 29 30 /* FPCI CFG registers */ 31 #define XUSB_CFG_1 0x004 32 #define XUSB_IO_SPACE_EN BIT(0) 33 #define XUSB_MEM_SPACE_EN BIT(1) 34 #define XUSB_BUS_MASTER_EN BIT(2) 35 #define XUSB_CFG_4 0x010 36 #define XUSB_BASE_ADDR_SHIFT 15 37 #define XUSB_BASE_ADDR_MASK 0x1ffff 38 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 39 #define XUSB_CFG_CSB_BASE_ADDR 0x800 40 41 /* FPCI mailbox registers */ 42 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4 43 #define MBOX_DEST_FALC BIT(27) 44 #define MBOX_DEST_PME BIT(28) 45 #define MBOX_DEST_SMI BIT(29) 46 #define MBOX_DEST_XHCI BIT(30) 47 #define MBOX_INT_EN BIT(31) 48 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8 49 #define CMD_DATA_SHIFT 0 50 #define CMD_DATA_MASK 0xffffff 51 #define CMD_TYPE_SHIFT 24 52 #define CMD_TYPE_MASK 0xff 53 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec 54 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0 55 #define MBOX_OWNER_NONE 0 56 #define MBOX_OWNER_FW 1 57 #define MBOX_OWNER_SW 2 58 #define XUSB_CFG_ARU_SMI_INTR 0x428 59 #define MBOX_SMI_INTR_FW_HANG BIT(1) 60 #define MBOX_SMI_INTR_EN BIT(3) 61 62 /* IPFS registers */ 63 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 64 #define IPFS_EN_FPCI BIT(0) 65 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 66 #define IPFS_IP_INT_MASK BIT(16) 67 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 68 69 #define CSB_PAGE_SELECT_MASK 0x7fffff 70 #define CSB_PAGE_SELECT_SHIFT 9 71 #define CSB_PAGE_OFFSET_MASK 0x1ff 72 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 73 CSB_PAGE_SELECT_MASK) 74 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 75 76 /* Falcon CSB registers */ 77 #define XUSB_FALC_CPUCTL 0x100 78 #define CPUCTL_STARTCPU BIT(1) 79 #define CPUCTL_STATE_HALTED BIT(4) 80 #define CPUCTL_STATE_STOPPED BIT(5) 81 #define XUSB_FALC_BOOTVEC 0x104 82 #define XUSB_FALC_DMACTL 0x10c 83 #define XUSB_FALC_IMFILLRNG1 0x154 84 #define IMFILLRNG1_TAG_MASK 0xffff 85 #define IMFILLRNG1_TAG_LO_SHIFT 0 86 #define IMFILLRNG1_TAG_HI_SHIFT 16 87 #define XUSB_FALC_IMFILLCTL 0x158 88 89 /* MP CSB registers */ 90 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 91 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 92 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 93 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 94 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 95 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 96 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 97 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 98 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 99 #define L2IMEMOP_ACTION_SHIFT 24 100 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 101 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 102 #define XUSB_CSB_MP_APMAP 0x10181c 103 #define APMAP_BOOTPATH BIT(31) 104 105 #define IMEM_BLOCK_SIZE 256 106 107 struct tegra_xusb_fw_header { 108 u32 boot_loadaddr_in_imem; 109 u32 boot_codedfi_offset; 110 u32 boot_codetag; 111 u32 boot_codesize; 112 u32 phys_memaddr; 113 u16 reqphys_memsize; 114 u16 alloc_phys_memsize; 115 u32 rodata_img_offset; 116 u32 rodata_section_start; 117 u32 rodata_section_end; 118 u32 main_fnaddr; 119 u32 fwimg_cksum; 120 u32 fwimg_created_time; 121 u32 imem_resident_start; 122 u32 imem_resident_end; 123 u32 idirect_start; 124 u32 idirect_end; 125 u32 l2_imem_start; 126 u32 l2_imem_end; 127 u32 version_id; 128 u8 init_ddirect; 129 u8 reserved[3]; 130 u32 phys_addr_log_buffer; 131 u32 total_log_entries; 132 u32 dequeue_ptr; 133 u32 dummy_var[2]; 134 u32 fwimg_len; 135 u8 magic[8]; 136 u32 ss_low_power_entry_timeout; 137 u8 num_hsic_port; 138 u8 padding[139]; /* Pad to 256 bytes */ 139 }; 140 141 struct tegra_xusb_phy_type { 142 const char *name; 143 unsigned int num; 144 }; 145 146 struct tegra_xusb_soc { 147 const char *firmware; 148 const char * const *supply_names; 149 unsigned int num_supplies; 150 const struct tegra_xusb_phy_type *phy_types; 151 unsigned int num_types; 152 153 struct { 154 struct { 155 unsigned int offset; 156 unsigned int count; 157 } usb2, ulpi, hsic, usb3; 158 } ports; 159 160 bool scale_ss_clock; 161 }; 162 163 struct tegra_xusb { 164 struct device *dev; 165 void __iomem *regs; 166 struct usb_hcd *hcd; 167 168 struct mutex lock; 169 170 int xhci_irq; 171 int mbox_irq; 172 173 void __iomem *ipfs_base; 174 void __iomem *fpci_base; 175 176 const struct tegra_xusb_soc *soc; 177 178 struct regulator_bulk_data *supplies; 179 180 struct tegra_xusb_padctl *padctl; 181 182 struct clk *host_clk; 183 struct clk *falcon_clk; 184 struct clk *ss_clk; 185 struct clk *ss_src_clk; 186 struct clk *hs_src_clk; 187 struct clk *fs_src_clk; 188 struct clk *pll_u_480m; 189 struct clk *clk_m; 190 struct clk *pll_e; 191 192 struct reset_control *host_rst; 193 struct reset_control *ss_rst; 194 195 struct phy **phys; 196 unsigned int num_phys; 197 198 /* Firmware loading related */ 199 struct { 200 size_t size; 201 void *virt; 202 dma_addr_t phys; 203 } fw; 204 }; 205 206 static struct hc_driver __read_mostly tegra_xhci_hc_driver; 207 208 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 209 { 210 return readl(tegra->fpci_base + offset); 211 } 212 213 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 214 unsigned int offset) 215 { 216 writel(value, tegra->fpci_base + offset); 217 } 218 219 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 220 { 221 return readl(tegra->ipfs_base + offset); 222 } 223 224 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 225 unsigned int offset) 226 { 227 writel(value, tegra->ipfs_base + offset); 228 } 229 230 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 231 { 232 u32 page = CSB_PAGE_SELECT(offset); 233 u32 ofs = CSB_PAGE_OFFSET(offset); 234 235 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 236 237 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 238 } 239 240 static void csb_writel(struct tegra_xusb *tegra, u32 value, 241 unsigned int offset) 242 { 243 u32 page = CSB_PAGE_SELECT(offset); 244 u32 ofs = CSB_PAGE_OFFSET(offset); 245 246 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 247 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 248 } 249 250 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 251 unsigned long rate) 252 { 253 unsigned long new_parent_rate, old_parent_rate; 254 struct clk *clk = tegra->ss_src_clk; 255 unsigned int div; 256 int err; 257 258 if (clk_get_rate(clk) == rate) 259 return 0; 260 261 switch (rate) { 262 case TEGRA_XHCI_SS_HIGH_SPEED: 263 /* 264 * Reparent to PLLU_480M. Set divider first to avoid 265 * overclocking. 266 */ 267 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 268 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 269 div = new_parent_rate / rate; 270 271 err = clk_set_rate(clk, old_parent_rate / div); 272 if (err) 273 return err; 274 275 err = clk_set_parent(clk, tegra->pll_u_480m); 276 if (err) 277 return err; 278 279 /* 280 * The rate should already be correct, but set it again just 281 * to be sure. 282 */ 283 err = clk_set_rate(clk, rate); 284 if (err) 285 return err; 286 287 break; 288 289 case TEGRA_XHCI_SS_LOW_SPEED: 290 /* Reparent to CLK_M */ 291 err = clk_set_parent(clk, tegra->clk_m); 292 if (err) 293 return err; 294 295 err = clk_set_rate(clk, rate); 296 if (err) 297 return err; 298 299 break; 300 301 default: 302 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 303 return -EINVAL; 304 } 305 306 if (clk_get_rate(clk) != rate) { 307 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 308 return -EINVAL; 309 } 310 311 return 0; 312 } 313 314 static unsigned long extract_field(u32 value, unsigned int start, 315 unsigned int count) 316 { 317 return (value >> start) & ((1 << count) - 1); 318 } 319 320 /* Command requests from the firmware */ 321 enum tegra_xusb_mbox_cmd { 322 MBOX_CMD_MSG_ENABLED = 1, 323 MBOX_CMD_INC_FALC_CLOCK, 324 MBOX_CMD_DEC_FALC_CLOCK, 325 MBOX_CMD_INC_SSPI_CLOCK, 326 MBOX_CMD_DEC_SSPI_CLOCK, 327 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 328 MBOX_CMD_SET_SS_PWR_GATING, 329 MBOX_CMD_SET_SS_PWR_UNGATING, 330 MBOX_CMD_SAVE_DFE_CTLE_CTX, 331 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 332 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 333 MBOX_CMD_START_HSIC_IDLE, 334 MBOX_CMD_STOP_HSIC_IDLE, 335 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 336 MBOX_CMD_HSIC_PRETEND_CONNECT, 337 MBOX_CMD_RESET_SSPI, 338 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 339 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 340 341 MBOX_CMD_MAX, 342 343 /* Response message to above commands */ 344 MBOX_CMD_ACK = 128, 345 MBOX_CMD_NAK 346 }; 347 348 static const char * const mbox_cmd_name[] = { 349 [ 1] = "MSG_ENABLE", 350 [ 2] = "INC_FALCON_CLOCK", 351 [ 3] = "DEC_FALCON_CLOCK", 352 [ 4] = "INC_SSPI_CLOCK", 353 [ 5] = "DEC_SSPI_CLOCK", 354 [ 6] = "SET_BW", 355 [ 7] = "SET_SS_PWR_GATING", 356 [ 8] = "SET_SS_PWR_UNGATING", 357 [ 9] = "SAVE_DFE_CTLE_CTX", 358 [ 10] = "AIRPLANE_MODE_ENABLED", 359 [ 11] = "AIRPLANE_MODE_DISABLED", 360 [ 12] = "START_HSIC_IDLE", 361 [ 13] = "STOP_HSIC_IDLE", 362 [ 14] = "DBC_WAKE_STACK", 363 [ 15] = "HSIC_PRETEND_CONNECT", 364 [ 16] = "RESET_SSPI", 365 [ 17] = "DISABLE_SS_LFPS_DETECTION", 366 [ 18] = "ENABLE_SS_LFPS_DETECTION", 367 [128] = "ACK", 368 [129] = "NAK", 369 }; 370 371 struct tegra_xusb_mbox_msg { 372 u32 cmd; 373 u32 data; 374 }; 375 376 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 377 { 378 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 379 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 380 } 381 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 382 u32 value) 383 { 384 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 385 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 386 } 387 388 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 389 { 390 switch (cmd) { 391 case MBOX_CMD_SET_BW: 392 case MBOX_CMD_ACK: 393 case MBOX_CMD_NAK: 394 return false; 395 396 default: 397 return true; 398 } 399 } 400 401 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 402 const struct tegra_xusb_mbox_msg *msg) 403 { 404 bool wait_for_idle = false; 405 u32 value; 406 407 /* 408 * Acquire the mailbox. The firmware still owns the mailbox for 409 * ACK/NAK messages. 410 */ 411 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 412 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 413 if (value != MBOX_OWNER_NONE) { 414 dev_err(tegra->dev, "mailbox is busy\n"); 415 return -EBUSY; 416 } 417 418 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER); 419 420 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 421 if (value != MBOX_OWNER_SW) { 422 dev_err(tegra->dev, "failed to acquire mailbox\n"); 423 return -EBUSY; 424 } 425 426 wait_for_idle = true; 427 } 428 429 value = tegra_xusb_mbox_pack(msg); 430 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN); 431 432 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 433 value |= MBOX_INT_EN | MBOX_DEST_FALC; 434 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 435 436 if (wait_for_idle) { 437 unsigned long timeout = jiffies + msecs_to_jiffies(250); 438 439 while (time_before(jiffies, timeout)) { 440 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 441 if (value == MBOX_OWNER_NONE) 442 break; 443 444 usleep_range(10, 20); 445 } 446 447 if (time_after(jiffies, timeout)) 448 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 449 450 if (value != MBOX_OWNER_NONE) 451 return -ETIMEDOUT; 452 } 453 454 return 0; 455 } 456 457 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 458 { 459 struct tegra_xusb *tegra = data; 460 u32 value; 461 462 /* clear mailbox interrupts */ 463 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); 464 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); 465 466 if (value & MBOX_SMI_INTR_FW_HANG) 467 dev_err(tegra->dev, "controller firmware hang\n"); 468 469 return IRQ_WAKE_THREAD; 470 } 471 472 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 473 const struct tegra_xusb_mbox_msg *msg) 474 { 475 struct tegra_xusb_padctl *padctl = tegra->padctl; 476 const struct tegra_xusb_soc *soc = tegra->soc; 477 struct device *dev = tegra->dev; 478 struct tegra_xusb_mbox_msg rsp; 479 unsigned long mask; 480 unsigned int port; 481 bool idle, enable; 482 int err; 483 484 memset(&rsp, 0, sizeof(rsp)); 485 486 switch (msg->cmd) { 487 case MBOX_CMD_INC_FALC_CLOCK: 488 case MBOX_CMD_DEC_FALC_CLOCK: 489 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 490 if (rsp.data != msg->data) 491 rsp.cmd = MBOX_CMD_NAK; 492 else 493 rsp.cmd = MBOX_CMD_ACK; 494 495 break; 496 497 case MBOX_CMD_INC_SSPI_CLOCK: 498 case MBOX_CMD_DEC_SSPI_CLOCK: 499 if (tegra->soc->scale_ss_clock) { 500 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 501 if (err < 0) 502 rsp.cmd = MBOX_CMD_NAK; 503 else 504 rsp.cmd = MBOX_CMD_ACK; 505 506 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 507 } else { 508 rsp.cmd = MBOX_CMD_ACK; 509 rsp.data = msg->data; 510 } 511 512 break; 513 514 case MBOX_CMD_SET_BW: 515 /* 516 * TODO: Request bandwidth once EMC scaling is supported. 517 * Ignore for now since ACK/NAK is not required for SET_BW 518 * messages. 519 */ 520 break; 521 522 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 523 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 524 if (err < 0) { 525 dev_err(dev, "failed to save context for USB3#%u: %d\n", 526 msg->data, err); 527 rsp.cmd = MBOX_CMD_NAK; 528 } else { 529 rsp.cmd = MBOX_CMD_ACK; 530 } 531 532 rsp.data = msg->data; 533 break; 534 535 case MBOX_CMD_START_HSIC_IDLE: 536 case MBOX_CMD_STOP_HSIC_IDLE: 537 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 538 idle = false; 539 else 540 idle = true; 541 542 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 543 soc->ports.hsic.count); 544 545 for_each_set_bit(port, &mask, 32) { 546 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 547 idle); 548 if (err < 0) 549 break; 550 } 551 552 if (err < 0) { 553 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 554 idle ? "idle" : "busy", err); 555 rsp.cmd = MBOX_CMD_NAK; 556 } else { 557 rsp.cmd = MBOX_CMD_ACK; 558 } 559 560 rsp.data = msg->data; 561 break; 562 563 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 564 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 565 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 566 enable = false; 567 else 568 enable = true; 569 570 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 571 soc->ports.usb3.count); 572 573 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 574 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 575 port, 576 enable); 577 if (err < 0) 578 break; 579 } 580 581 if (err < 0) { 582 dev_err(dev, 583 "failed to %s LFPS detection on USB3#%u: %d\n", 584 enable ? "enable" : "disable", port, err); 585 rsp.cmd = MBOX_CMD_NAK; 586 } else { 587 rsp.cmd = MBOX_CMD_ACK; 588 } 589 590 rsp.data = msg->data; 591 break; 592 593 default: 594 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 595 break; 596 } 597 598 if (rsp.cmd) { 599 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 600 601 err = tegra_xusb_mbox_send(tegra, &rsp); 602 if (err < 0) 603 dev_err(dev, "failed to send %s: %d\n", cmd, err); 604 } 605 } 606 607 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 608 { 609 struct tegra_xusb *tegra = data; 610 struct tegra_xusb_mbox_msg msg; 611 u32 value; 612 613 mutex_lock(&tegra->lock); 614 615 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT); 616 tegra_xusb_mbox_unpack(&msg, value); 617 618 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 619 value &= ~MBOX_DEST_SMI; 620 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 621 622 /* clear mailbox owner if no ACK/NAK is required */ 623 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 624 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER); 625 626 tegra_xusb_mbox_handle(tegra, &msg); 627 628 mutex_unlock(&tegra->lock); 629 return IRQ_HANDLED; 630 } 631 632 static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra, 633 struct resource *regs) 634 { 635 u32 value; 636 637 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 638 value |= IPFS_EN_FPCI; 639 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 640 641 usleep_range(10, 20); 642 643 /* Program BAR0 space */ 644 value = fpci_readl(tegra, XUSB_CFG_4); 645 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 646 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 647 fpci_writel(tegra, value, XUSB_CFG_4); 648 649 usleep_range(100, 200); 650 651 /* Enable bus master */ 652 value = fpci_readl(tegra, XUSB_CFG_1); 653 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 654 fpci_writel(tegra, value, XUSB_CFG_1); 655 656 /* Enable interrupt assertion */ 657 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 658 value |= IPFS_IP_INT_MASK; 659 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 660 661 /* Set hysteresis */ 662 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 663 } 664 665 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 666 { 667 int err; 668 669 err = clk_prepare_enable(tegra->pll_e); 670 if (err < 0) 671 return err; 672 673 err = clk_prepare_enable(tegra->host_clk); 674 if (err < 0) 675 goto disable_plle; 676 677 err = clk_prepare_enable(tegra->ss_clk); 678 if (err < 0) 679 goto disable_host; 680 681 err = clk_prepare_enable(tegra->falcon_clk); 682 if (err < 0) 683 goto disable_ss; 684 685 err = clk_prepare_enable(tegra->fs_src_clk); 686 if (err < 0) 687 goto disable_falc; 688 689 err = clk_prepare_enable(tegra->hs_src_clk); 690 if (err < 0) 691 goto disable_fs_src; 692 693 if (tegra->soc->scale_ss_clock) { 694 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 695 if (err < 0) 696 goto disable_hs_src; 697 } 698 699 return 0; 700 701 disable_hs_src: 702 clk_disable_unprepare(tegra->hs_src_clk); 703 disable_fs_src: 704 clk_disable_unprepare(tegra->fs_src_clk); 705 disable_falc: 706 clk_disable_unprepare(tegra->falcon_clk); 707 disable_ss: 708 clk_disable_unprepare(tegra->ss_clk); 709 disable_host: 710 clk_disable_unprepare(tegra->host_clk); 711 disable_plle: 712 clk_disable_unprepare(tegra->pll_e); 713 return err; 714 } 715 716 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 717 { 718 clk_disable_unprepare(tegra->pll_e); 719 clk_disable_unprepare(tegra->host_clk); 720 clk_disable_unprepare(tegra->ss_clk); 721 clk_disable_unprepare(tegra->falcon_clk); 722 clk_disable_unprepare(tegra->fs_src_clk); 723 clk_disable_unprepare(tegra->hs_src_clk); 724 } 725 726 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 727 { 728 unsigned int i; 729 int err; 730 731 for (i = 0; i < tegra->num_phys; i++) { 732 err = phy_init(tegra->phys[i]); 733 if (err) 734 goto disable_phy; 735 736 err = phy_power_on(tegra->phys[i]); 737 if (err) { 738 phy_exit(tegra->phys[i]); 739 goto disable_phy; 740 } 741 } 742 743 return 0; 744 745 disable_phy: 746 while (i--) { 747 phy_power_off(tegra->phys[i]); 748 phy_exit(tegra->phys[i]); 749 } 750 751 return err; 752 } 753 754 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 755 { 756 unsigned int i; 757 758 for (i = 0; i < tegra->num_phys; i++) { 759 phy_power_off(tegra->phys[i]); 760 phy_exit(tegra->phys[i]); 761 } 762 } 763 764 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 765 { 766 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 767 struct tegra_xusb_fw_header *header; 768 struct device *dev = tegra->dev; 769 const struct firmware *fw; 770 unsigned long timeout; 771 time64_t timestamp; 772 struct tm time; 773 u64 address; 774 u32 value; 775 int err; 776 777 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 778 if (err < 0) { 779 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 780 return err; 781 } 782 783 /* Load Falcon controller with its firmware. */ 784 header = (struct tegra_xusb_fw_header *)fw->data; 785 tegra->fw.size = le32_to_cpu(header->fwimg_len); 786 787 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 788 &tegra->fw.phys, GFP_KERNEL); 789 if (!tegra->fw.virt) { 790 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 791 release_firmware(fw); 792 return -ENOMEM; 793 } 794 795 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 796 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 797 release_firmware(fw); 798 799 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 800 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 801 csb_readl(tegra, XUSB_FALC_CPUCTL)); 802 return 0; 803 } 804 805 /* Program the size of DFI into ILOAD_ATTR. */ 806 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 807 808 /* 809 * Boot code of the firmware reads the ILOAD_BASE registers 810 * to get to the start of the DFI in system memory. 811 */ 812 address = tegra->fw.phys + sizeof(*header); 813 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 814 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 815 816 /* Set BOOTPATH to 1 in APMAP. */ 817 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 818 819 /* Invalidate L2IMEM. */ 820 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 821 822 /* 823 * Initiate fetch of bootcode from system memory into L2IMEM. 824 * Program bootcode location and size in system memory. 825 */ 826 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 827 IMEM_BLOCK_SIZE); 828 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 829 IMEM_BLOCK_SIZE); 830 code_blocks = code_tag_blocks + code_size_blocks; 831 832 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 833 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 834 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 835 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 836 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 837 838 /* Trigger L2IMEM load operation. */ 839 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 840 XUSB_CSB_MP_L2IMEMOP_TRIG); 841 842 /* Setup Falcon auto-fill. */ 843 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 844 845 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 846 IMFILLRNG1_TAG_LO_SHIFT) | 847 ((code_blocks & IMFILLRNG1_TAG_MASK) << 848 IMFILLRNG1_TAG_HI_SHIFT); 849 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 850 851 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 852 853 msleep(50); 854 855 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 856 XUSB_FALC_BOOTVEC); 857 858 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */ 859 timeout = jiffies + msecs_to_jiffies(5); 860 861 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 862 863 while (time_before(jiffies, timeout)) { 864 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED) 865 break; 866 867 usleep_range(100, 200); 868 } 869 870 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) { 871 dev_err(dev, "Falcon failed to start, state: %#x\n", 872 csb_readl(tegra, XUSB_FALC_CPUCTL)); 873 return -EIO; 874 } 875 876 timestamp = le32_to_cpu(header->fwimg_created_time); 877 time64_to_tm(timestamp, 0, &time); 878 879 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", 880 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, 881 time.tm_hour, time.tm_min, time.tm_sec); 882 883 return 0; 884 } 885 886 static int tegra_xusb_probe(struct platform_device *pdev) 887 { 888 struct tegra_xusb_mbox_msg msg; 889 struct resource *res, *regs; 890 struct tegra_xusb *tegra; 891 struct xhci_hcd *xhci; 892 unsigned int i, j, k; 893 struct phy *phy; 894 int err; 895 896 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 897 898 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 899 if (!tegra) 900 return -ENOMEM; 901 902 tegra->soc = of_device_get_match_data(&pdev->dev); 903 mutex_init(&tegra->lock); 904 tegra->dev = &pdev->dev; 905 906 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 907 tegra->regs = devm_ioremap_resource(&pdev->dev, regs); 908 if (IS_ERR(tegra->regs)) 909 return PTR_ERR(tegra->regs); 910 911 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 912 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res); 913 if (IS_ERR(tegra->fpci_base)) 914 return PTR_ERR(tegra->fpci_base); 915 916 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 917 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res); 918 if (IS_ERR(tegra->ipfs_base)) 919 return PTR_ERR(tegra->ipfs_base); 920 921 tegra->xhci_irq = platform_get_irq(pdev, 0); 922 if (tegra->xhci_irq < 0) 923 return tegra->xhci_irq; 924 925 tegra->mbox_irq = platform_get_irq(pdev, 1); 926 if (tegra->mbox_irq < 0) 927 return tegra->mbox_irq; 928 929 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 930 if (IS_ERR(tegra->padctl)) 931 return PTR_ERR(tegra->padctl); 932 933 tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host"); 934 if (IS_ERR(tegra->host_rst)) { 935 err = PTR_ERR(tegra->host_rst); 936 dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err); 937 goto put_padctl; 938 } 939 940 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 941 if (IS_ERR(tegra->ss_rst)) { 942 err = PTR_ERR(tegra->ss_rst); 943 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err); 944 goto put_padctl; 945 } 946 947 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 948 if (IS_ERR(tegra->host_clk)) { 949 err = PTR_ERR(tegra->host_clk); 950 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 951 goto put_padctl; 952 } 953 954 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 955 if (IS_ERR(tegra->falcon_clk)) { 956 err = PTR_ERR(tegra->falcon_clk); 957 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 958 goto put_padctl; 959 } 960 961 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 962 if (IS_ERR(tegra->ss_clk)) { 963 err = PTR_ERR(tegra->ss_clk); 964 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 965 goto put_padctl; 966 } 967 968 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 969 if (IS_ERR(tegra->ss_src_clk)) { 970 err = PTR_ERR(tegra->ss_src_clk); 971 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 972 goto put_padctl; 973 } 974 975 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 976 if (IS_ERR(tegra->hs_src_clk)) { 977 err = PTR_ERR(tegra->hs_src_clk); 978 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 979 goto put_padctl; 980 } 981 982 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 983 if (IS_ERR(tegra->fs_src_clk)) { 984 err = PTR_ERR(tegra->fs_src_clk); 985 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 986 goto put_padctl; 987 } 988 989 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 990 if (IS_ERR(tegra->pll_u_480m)) { 991 err = PTR_ERR(tegra->pll_u_480m); 992 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 993 goto put_padctl; 994 } 995 996 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 997 if (IS_ERR(tegra->clk_m)) { 998 err = PTR_ERR(tegra->clk_m); 999 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1000 goto put_padctl; 1001 } 1002 1003 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1004 if (IS_ERR(tegra->pll_e)) { 1005 err = PTR_ERR(tegra->pll_e); 1006 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1007 goto put_padctl; 1008 } 1009 1010 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1011 sizeof(*tegra->supplies), GFP_KERNEL); 1012 if (!tegra->supplies) { 1013 err = -ENOMEM; 1014 goto put_padctl; 1015 } 1016 1017 for (i = 0; i < tegra->soc->num_supplies; i++) 1018 tegra->supplies[i].supply = tegra->soc->supply_names[i]; 1019 1020 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1021 tegra->supplies); 1022 if (err) { 1023 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1024 goto put_padctl; 1025 } 1026 1027 for (i = 0; i < tegra->soc->num_types; i++) 1028 tegra->num_phys += tegra->soc->phy_types[i].num; 1029 1030 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1031 sizeof(*tegra->phys), GFP_KERNEL); 1032 if (!tegra->phys) { 1033 err = -ENOMEM; 1034 goto put_padctl; 1035 } 1036 1037 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1038 char prop[8]; 1039 1040 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1041 snprintf(prop, sizeof(prop), "%s-%d", 1042 tegra->soc->phy_types[i].name, j); 1043 1044 phy = devm_phy_optional_get(&pdev->dev, prop); 1045 if (IS_ERR(phy)) { 1046 dev_err(&pdev->dev, 1047 "failed to get PHY %s: %ld\n", prop, 1048 PTR_ERR(phy)); 1049 err = PTR_ERR(phy); 1050 goto put_padctl; 1051 } 1052 1053 tegra->phys[k++] = phy; 1054 } 1055 } 1056 1057 err = tegra_xusb_clk_enable(tegra); 1058 if (err) { 1059 dev_err(&pdev->dev, "failed to enable clocks: %d\n", err); 1060 goto put_padctl; 1061 } 1062 1063 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 1064 if (err) { 1065 dev_err(&pdev->dev, "failed to enable regulators: %d\n", err); 1066 goto disable_clk; 1067 } 1068 1069 err = tegra_xusb_phy_enable(tegra); 1070 if (err < 0) { 1071 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); 1072 goto disable_regulator; 1073 } 1074 1075 tegra_xusb_ipfs_config(tegra, regs); 1076 1077 err = tegra_xusb_load_firmware(tegra); 1078 if (err < 0) { 1079 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1080 goto disable_phy; 1081 } 1082 1083 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1084 dev_name(&pdev->dev)); 1085 if (!tegra->hcd) { 1086 err = -ENOMEM; 1087 goto disable_phy; 1088 } 1089 1090 /* 1091 * This must happen after usb_create_hcd(), because usb_create_hcd() 1092 * will overwrite the drvdata of the device with the hcd it creates. 1093 */ 1094 platform_set_drvdata(pdev, tegra); 1095 1096 tegra->hcd->regs = tegra->regs; 1097 tegra->hcd->rsrc_start = regs->start; 1098 tegra->hcd->rsrc_len = resource_size(regs); 1099 1100 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1101 if (err < 0) { 1102 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1103 goto put_usb2; 1104 } 1105 1106 device_wakeup_enable(tegra->hcd->self.controller); 1107 1108 xhci = hcd_to_xhci(tegra->hcd); 1109 1110 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1111 &pdev->dev, 1112 dev_name(&pdev->dev), 1113 tegra->hcd); 1114 if (!xhci->shared_hcd) { 1115 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1116 err = -ENOMEM; 1117 goto remove_usb2; 1118 } 1119 1120 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1121 if (err < 0) { 1122 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1123 goto put_usb3; 1124 } 1125 1126 mutex_lock(&tegra->lock); 1127 1128 /* Enable firmware messages from controller. */ 1129 msg.cmd = MBOX_CMD_MSG_ENABLED; 1130 msg.data = 0; 1131 1132 err = tegra_xusb_mbox_send(tegra, &msg); 1133 if (err < 0) { 1134 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1135 mutex_unlock(&tegra->lock); 1136 goto remove_usb3; 1137 } 1138 1139 mutex_unlock(&tegra->lock); 1140 1141 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1142 tegra_xusb_mbox_irq, 1143 tegra_xusb_mbox_thread, 0, 1144 dev_name(&pdev->dev), tegra); 1145 if (err < 0) { 1146 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1147 goto remove_usb3; 1148 } 1149 1150 return 0; 1151 1152 remove_usb3: 1153 usb_remove_hcd(xhci->shared_hcd); 1154 put_usb3: 1155 usb_put_hcd(xhci->shared_hcd); 1156 remove_usb2: 1157 usb_remove_hcd(tegra->hcd); 1158 put_usb2: 1159 usb_put_hcd(tegra->hcd); 1160 disable_phy: 1161 tegra_xusb_phy_disable(tegra); 1162 disable_regulator: 1163 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1164 disable_clk: 1165 tegra_xusb_clk_disable(tegra); 1166 put_padctl: 1167 tegra_xusb_padctl_put(tegra->padctl); 1168 return err; 1169 } 1170 1171 static int tegra_xusb_remove(struct platform_device *pdev) 1172 { 1173 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1174 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1175 1176 usb_remove_hcd(xhci->shared_hcd); 1177 usb_put_hcd(xhci->shared_hcd); 1178 usb_remove_hcd(tegra->hcd); 1179 usb_put_hcd(tegra->hcd); 1180 1181 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1182 tegra->fw.phys); 1183 1184 tegra_xusb_phy_disable(tegra); 1185 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1186 tegra_xusb_clk_disable(tegra); 1187 1188 tegra_xusb_padctl_put(tegra->padctl); 1189 1190 return 0; 1191 } 1192 1193 #ifdef CONFIG_PM_SLEEP 1194 static int tegra_xusb_suspend(struct device *dev) 1195 { 1196 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1197 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1198 bool wakeup = device_may_wakeup(dev); 1199 1200 /* TODO: Powergate controller across suspend/resume. */ 1201 return xhci_suspend(xhci, wakeup); 1202 } 1203 1204 static int tegra_xusb_resume(struct device *dev) 1205 { 1206 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1207 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1208 1209 return xhci_resume(xhci, 0); 1210 } 1211 #endif 1212 1213 static const struct dev_pm_ops tegra_xusb_pm_ops = { 1214 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 1215 }; 1216 1217 static const char * const tegra124_supply_names[] = { 1218 "avddio-pex", 1219 "dvddio-pex", 1220 "avdd-usb", 1221 "avdd-pll-utmip", 1222 "avdd-pll-erefe", 1223 "avdd-usb-ss-pll", 1224 "hvdd-usb-ss", 1225 "hvdd-usb-ss-pll-e", 1226 }; 1227 1228 static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 1229 { .name = "usb3", .num = 2, }, 1230 { .name = "usb2", .num = 3, }, 1231 { .name = "hsic", .num = 2, }, 1232 }; 1233 1234 static const struct tegra_xusb_soc tegra124_soc = { 1235 .firmware = "nvidia/tegra124/xusb.bin", 1236 .supply_names = tegra124_supply_names, 1237 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 1238 .phy_types = tegra124_phy_types, 1239 .num_types = ARRAY_SIZE(tegra124_phy_types), 1240 .ports = { 1241 .usb2 = { .offset = 4, .count = 4, }, 1242 .hsic = { .offset = 6, .count = 2, }, 1243 .usb3 = { .offset = 0, .count = 2, }, 1244 }, 1245 .scale_ss_clock = true, 1246 }; 1247 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 1248 1249 static const char * const tegra210_supply_names[] = { 1250 "dvddio-pex", 1251 "hvddio-pex", 1252 "avdd-usb", 1253 "avdd-pll-utmip", 1254 "avdd-pll-uerefe", 1255 "dvdd-pex-pll", 1256 "hvdd-pex-pll-e", 1257 }; 1258 1259 static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 1260 { .name = "usb3", .num = 4, }, 1261 { .name = "usb2", .num = 4, }, 1262 { .name = "hsic", .num = 1, }, 1263 }; 1264 1265 static const struct tegra_xusb_soc tegra210_soc = { 1266 .firmware = "nvidia/tegra210/xusb.bin", 1267 .supply_names = tegra210_supply_names, 1268 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 1269 .phy_types = tegra210_phy_types, 1270 .num_types = ARRAY_SIZE(tegra210_phy_types), 1271 .ports = { 1272 .usb2 = { .offset = 4, .count = 4, }, 1273 .hsic = { .offset = 8, .count = 1, }, 1274 .usb3 = { .offset = 0, .count = 4, }, 1275 }, 1276 .scale_ss_clock = false, 1277 }; 1278 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 1279 1280 static const struct of_device_id tegra_xusb_of_match[] = { 1281 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 1282 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 1283 { }, 1284 }; 1285 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 1286 1287 static struct platform_driver tegra_xusb_driver = { 1288 .probe = tegra_xusb_probe, 1289 .remove = tegra_xusb_remove, 1290 .driver = { 1291 .name = "tegra-xusb", 1292 .pm = &tegra_xusb_pm_ops, 1293 .of_match_table = tegra_xusb_of_match, 1294 }, 1295 }; 1296 1297 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 1298 { 1299 xhci->quirks |= XHCI_PLAT; 1300 } 1301 1302 static int tegra_xhci_setup(struct usb_hcd *hcd) 1303 { 1304 return xhci_gen_setup(hcd, tegra_xhci_quirks); 1305 } 1306 1307 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 1308 .reset = tegra_xhci_setup, 1309 }; 1310 1311 static int __init tegra_xusb_init(void) 1312 { 1313 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 1314 1315 return platform_driver_register(&tegra_xusb_driver); 1316 } 1317 module_init(tegra_xusb_init); 1318 1319 static void __exit tegra_xusb_exit(void) 1320 { 1321 platform_driver_unregister(&tegra_xusb_driver); 1322 } 1323 module_exit(tegra_xusb_exit); 1324 1325 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 1326 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 1327 MODULE_LICENSE("GPL v2"); 1328