1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 * Ring initialization rules: 25 * 1. Each segment is initialized to zero, except for link TRBs. 26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 27 * Consumer Cycle State (CCS), depending on ring function. 28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 29 * 30 * Ring behavior rules: 31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 32 * least one free TRB in the ring. This is useful if you want to turn that 33 * into a link TRB and expand the ring. 34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 35 * link TRB, then load the pointer with the address in the link TRB. If the 36 * link TRB had its toggle bit set, you may need to update the ring cycle 37 * state (see cycle bit rules). You may have to do this multiple times 38 * until you reach a non-link TRB. 39 * 3. A ring is full if enqueue++ (for the definition of increment above) 40 * equals the dequeue pointer. 41 * 42 * Cycle bit rules: 43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 44 * in a link TRB, it must toggle the ring cycle state. 45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 46 * in a link TRB, it must toggle the ring cycle state. 47 * 48 * Producer rules: 49 * 1. Check if ring is full before you enqueue. 50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 51 * Update enqueue pointer between each write (which may update the ring 52 * cycle state). 53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 54 * and endpoint rings. If HC is the producer for the event ring, 55 * and it generates an interrupt according to interrupt modulation rules. 56 * 57 * Consumer rules: 58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 59 * the TRB is owned by the consumer. 60 * 2. Update dequeue pointer (which may update the ring cycle state) and 61 * continue processing TRBs until you reach a TRB which is not owned by you. 62 * 3. Notify the producer. SW is the consumer for the event ring, and it 63 * updates event ring dequeue pointer. HC is the consumer for the command and 64 * endpoint rings; it generates events on the event ring for these. 65 */ 66 67 #include <linux/scatterlist.h> 68 #include <linux/slab.h> 69 #include "xhci.h" 70 71 /* 72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 73 * address of the TRB. 74 */ 75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 76 union xhci_trb *trb) 77 { 78 unsigned long segment_offset; 79 80 if (!seg || !trb || trb < seg->trbs) 81 return 0; 82 /* offset in TRBs */ 83 segment_offset = trb - seg->trbs; 84 if (segment_offset > TRBS_PER_SEGMENT) 85 return 0; 86 return seg->dma + (segment_offset * sizeof(*trb)); 87 } 88 89 /* Does this link TRB point to the first segment in a ring, 90 * or was the previous TRB the last TRB on the last segment in the ERST? 91 */ 92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, 93 struct xhci_segment *seg, union xhci_trb *trb) 94 { 95 if (ring == xhci->event_ring) 96 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && 97 (seg->next == xhci->event_ring->first_seg); 98 else 99 return trb->link.control & LINK_TOGGLE; 100 } 101 102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring 103 * segment? I.e. would the updated event TRB pointer step off the end of the 104 * event seg? 105 */ 106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 107 struct xhci_segment *seg, union xhci_trb *trb) 108 { 109 if (ring == xhci->event_ring) 110 return trb == &seg->trbs[TRBS_PER_SEGMENT]; 111 else 112 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); 113 } 114 115 static inline int enqueue_is_link_trb(struct xhci_ring *ring) 116 { 117 struct xhci_link_trb *link = &ring->enqueue->link; 118 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)); 119 } 120 121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 122 * TRB is in a new segment. This does not skip over link TRBs, and it does not 123 * effect the ring dequeue or enqueue pointers. 124 */ 125 static void next_trb(struct xhci_hcd *xhci, 126 struct xhci_ring *ring, 127 struct xhci_segment **seg, 128 union xhci_trb **trb) 129 { 130 if (last_trb(xhci, ring, *seg, *trb)) { 131 *seg = (*seg)->next; 132 *trb = ((*seg)->trbs); 133 } else { 134 *trb = (*trb)++; 135 } 136 } 137 138 /* 139 * See Cycle bit rules. SW is the consumer for the event ring only. 140 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 141 */ 142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) 143 { 144 union xhci_trb *next = ++(ring->dequeue); 145 unsigned long long addr; 146 147 ring->deq_updates++; 148 /* Update the dequeue pointer further if that was a link TRB or we're at 149 * the end of an event ring segment (which doesn't have link TRBS) 150 */ 151 while (last_trb(xhci, ring, ring->deq_seg, next)) { 152 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { 153 ring->cycle_state = (ring->cycle_state ? 0 : 1); 154 if (!in_interrupt()) 155 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", 156 ring, 157 (unsigned int) ring->cycle_state); 158 } 159 ring->deq_seg = ring->deq_seg->next; 160 ring->dequeue = ring->deq_seg->trbs; 161 next = ring->dequeue; 162 } 163 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); 164 if (ring == xhci->event_ring) 165 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); 166 else if (ring == xhci->cmd_ring) 167 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); 168 else 169 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); 170 } 171 172 /* 173 * See Cycle bit rules. SW is the consumer for the event ring only. 174 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 175 * 176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 177 * chain bit is set), then set the chain bit in all the following link TRBs. 178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 179 * have their chain bit cleared (so that each Link TRB is a separate TD). 180 * 181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 182 * set, but other sections talk about dealing with the chain bit set. This was 183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 184 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 185 * 186 * @more_trbs_coming: Will you enqueue more TRBs before calling 187 * prepare_transfer()? 188 */ 189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 190 bool consumer, bool more_trbs_coming) 191 { 192 u32 chain; 193 union xhci_trb *next; 194 unsigned long long addr; 195 196 chain = ring->enqueue->generic.field[3] & TRB_CHAIN; 197 next = ++(ring->enqueue); 198 199 ring->enq_updates++; 200 /* Update the dequeue pointer further if that was a link TRB or we're at 201 * the end of an event ring segment (which doesn't have link TRBS) 202 */ 203 while (last_trb(xhci, ring, ring->enq_seg, next)) { 204 if (!consumer) { 205 if (ring != xhci->event_ring) { 206 /* 207 * If the caller doesn't plan on enqueueing more 208 * TDs before ringing the doorbell, then we 209 * don't want to give the link TRB to the 210 * hardware just yet. We'll give the link TRB 211 * back in prepare_ring() just before we enqueue 212 * the TD at the top of the ring. 213 */ 214 if (!chain && !more_trbs_coming) 215 break; 216 217 /* If we're not dealing with 0.95 hardware, 218 * carry over the chain bit of the previous TRB 219 * (which may mean the chain bit is cleared). 220 */ 221 if (!xhci_link_trb_quirk(xhci)) { 222 next->link.control &= ~TRB_CHAIN; 223 next->link.control |= chain; 224 } 225 /* Give this link TRB to the hardware */ 226 wmb(); 227 next->link.control ^= TRB_CYCLE; 228 } 229 /* Toggle the cycle bit after the last ring segment. */ 230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { 231 ring->cycle_state = (ring->cycle_state ? 0 : 1); 232 if (!in_interrupt()) 233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", 234 ring, 235 (unsigned int) ring->cycle_state); 236 } 237 } 238 ring->enq_seg = ring->enq_seg->next; 239 ring->enqueue = ring->enq_seg->trbs; 240 next = ring->enqueue; 241 } 242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); 243 if (ring == xhci->event_ring) 244 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); 245 else if (ring == xhci->cmd_ring) 246 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); 247 else 248 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); 249 } 250 251 /* 252 * Check to see if there's room to enqueue num_trbs on the ring. See rules 253 * above. 254 * FIXME: this would be simpler and faster if we just kept track of the number 255 * of free TRBs in a ring. 256 */ 257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 258 unsigned int num_trbs) 259 { 260 int i; 261 union xhci_trb *enq = ring->enqueue; 262 struct xhci_segment *enq_seg = ring->enq_seg; 263 struct xhci_segment *cur_seg; 264 unsigned int left_on_ring; 265 266 /* If we are currently pointing to a link TRB, advance the 267 * enqueue pointer before checking for space */ 268 while (last_trb(xhci, ring, enq_seg, enq)) { 269 enq_seg = enq_seg->next; 270 enq = enq_seg->trbs; 271 } 272 273 /* Check if ring is empty */ 274 if (enq == ring->dequeue) { 275 /* Can't use link trbs */ 276 left_on_ring = TRBS_PER_SEGMENT - 1; 277 for (cur_seg = enq_seg->next; cur_seg != enq_seg; 278 cur_seg = cur_seg->next) 279 left_on_ring += TRBS_PER_SEGMENT - 1; 280 281 /* Always need one TRB free in the ring. */ 282 left_on_ring -= 1; 283 if (num_trbs > left_on_ring) { 284 xhci_warn(xhci, "Not enough room on ring; " 285 "need %u TRBs, %u TRBs left\n", 286 num_trbs, left_on_ring); 287 return 0; 288 } 289 return 1; 290 } 291 /* Make sure there's an extra empty TRB available */ 292 for (i = 0; i <= num_trbs; ++i) { 293 if (enq == ring->dequeue) 294 return 0; 295 enq++; 296 while (last_trb(xhci, ring, enq_seg, enq)) { 297 enq_seg = enq_seg->next; 298 enq = enq_seg->trbs; 299 } 300 } 301 return 1; 302 } 303 304 /* Ring the host controller doorbell after placing a command on the ring */ 305 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 306 { 307 u32 temp; 308 309 xhci_dbg(xhci, "// Ding dong!\n"); 310 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; 311 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); 312 /* Flush PCI posted writes */ 313 xhci_readl(xhci, &xhci->dba->doorbell[0]); 314 } 315 316 static void ring_ep_doorbell(struct xhci_hcd *xhci, 317 unsigned int slot_id, 318 unsigned int ep_index, 319 unsigned int stream_id) 320 { 321 struct xhci_virt_ep *ep; 322 unsigned int ep_state; 323 u32 field; 324 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 325 326 ep = &xhci->devs[slot_id]->eps[ep_index]; 327 ep_state = ep->ep_state; 328 /* Don't ring the doorbell for this endpoint if there are pending 329 * cancellations because the we don't want to interrupt processing. 330 * We don't want to restart any stream rings if there's a set dequeue 331 * pointer command pending because the device can choose to start any 332 * stream once the endpoint is on the HW schedule. 333 * FIXME - check all the stream rings for pending cancellations. 334 */ 335 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) 336 && !(ep_state & EP_HALTED)) { 337 field = xhci_readl(xhci, db_addr) & DB_MASK; 338 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id); 339 xhci_writel(xhci, field, db_addr); 340 } 341 } 342 343 /* Ring the doorbell for any rings with pending URBs */ 344 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 345 unsigned int slot_id, 346 unsigned int ep_index) 347 { 348 unsigned int stream_id; 349 struct xhci_virt_ep *ep; 350 351 ep = &xhci->devs[slot_id]->eps[ep_index]; 352 353 /* A ring has pending URBs if its TD list is not empty */ 354 if (!(ep->ep_state & EP_HAS_STREAMS)) { 355 if (!(list_empty(&ep->ring->td_list))) 356 ring_ep_doorbell(xhci, slot_id, ep_index, 0); 357 return; 358 } 359 360 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 361 stream_id++) { 362 struct xhci_stream_info *stream_info = ep->stream_info; 363 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 364 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 365 } 366 } 367 368 /* 369 * Find the segment that trb is in. Start searching in start_seg. 370 * If we must move past a segment that has a link TRB with a toggle cycle state 371 * bit set, then we will toggle the value pointed at by cycle_state. 372 */ 373 static struct xhci_segment *find_trb_seg( 374 struct xhci_segment *start_seg, 375 union xhci_trb *trb, int *cycle_state) 376 { 377 struct xhci_segment *cur_seg = start_seg; 378 struct xhci_generic_trb *generic_trb; 379 380 while (cur_seg->trbs > trb || 381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { 382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; 383 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == 384 TRB_TYPE(TRB_LINK) && 385 (generic_trb->field[3] & LINK_TOGGLE)) 386 *cycle_state = ~(*cycle_state) & 0x1; 387 cur_seg = cur_seg->next; 388 if (cur_seg == start_seg) 389 /* Looped over the entire list. Oops! */ 390 return NULL; 391 } 392 return cur_seg; 393 } 394 395 396 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 397 unsigned int slot_id, unsigned int ep_index, 398 unsigned int stream_id) 399 { 400 struct xhci_virt_ep *ep; 401 402 ep = &xhci->devs[slot_id]->eps[ep_index]; 403 /* Common case: no streams */ 404 if (!(ep->ep_state & EP_HAS_STREAMS)) 405 return ep->ring; 406 407 if (stream_id == 0) { 408 xhci_warn(xhci, 409 "WARN: Slot ID %u, ep index %u has streams, " 410 "but URB has no stream ID.\n", 411 slot_id, ep_index); 412 return NULL; 413 } 414 415 if (stream_id < ep->stream_info->num_streams) 416 return ep->stream_info->stream_rings[stream_id]; 417 418 xhci_warn(xhci, 419 "WARN: Slot ID %u, ep index %u has " 420 "stream IDs 1 to %u allocated, " 421 "but stream ID %u is requested.\n", 422 slot_id, ep_index, 423 ep->stream_info->num_streams - 1, 424 stream_id); 425 return NULL; 426 } 427 428 /* Get the right ring for the given URB. 429 * If the endpoint supports streams, boundary check the URB's stream ID. 430 * If the endpoint doesn't support streams, return the singular endpoint ring. 431 */ 432 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 433 struct urb *urb) 434 { 435 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 436 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); 437 } 438 439 /* 440 * Move the xHC's endpoint ring dequeue pointer past cur_td. 441 * Record the new state of the xHC's endpoint ring dequeue segment, 442 * dequeue pointer, and new consumer cycle state in state. 443 * Update our internal representation of the ring's dequeue pointer. 444 * 445 * We do this in three jumps: 446 * - First we update our new ring state to be the same as when the xHC stopped. 447 * - Then we traverse the ring to find the segment that contains 448 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass 449 * any link TRBs with the toggle cycle bit set. 450 * - Finally we move the dequeue state one TRB further, toggling the cycle bit 451 * if we've moved it past a link TRB with the toggle cycle bit set. 452 */ 453 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 454 unsigned int slot_id, unsigned int ep_index, 455 unsigned int stream_id, struct xhci_td *cur_td, 456 struct xhci_dequeue_state *state) 457 { 458 struct xhci_virt_device *dev = xhci->devs[slot_id]; 459 struct xhci_ring *ep_ring; 460 struct xhci_generic_trb *trb; 461 struct xhci_ep_ctx *ep_ctx; 462 dma_addr_t addr; 463 464 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 465 ep_index, stream_id); 466 if (!ep_ring) { 467 xhci_warn(xhci, "WARN can't find new dequeue state " 468 "for invalid stream ID %u.\n", 469 stream_id); 470 return; 471 } 472 state->new_cycle_state = 0; 473 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); 474 state->new_deq_seg = find_trb_seg(cur_td->start_seg, 475 dev->eps[ep_index].stopped_trb, 476 &state->new_cycle_state); 477 if (!state->new_deq_seg) 478 BUG(); 479 /* Dig out the cycle state saved by the xHC during the stop ep cmd */ 480 xhci_dbg(xhci, "Finding endpoint context\n"); 481 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 482 state->new_cycle_state = 0x1 & ep_ctx->deq; 483 484 state->new_deq_ptr = cur_td->last_trb; 485 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); 486 state->new_deq_seg = find_trb_seg(state->new_deq_seg, 487 state->new_deq_ptr, 488 &state->new_cycle_state); 489 if (!state->new_deq_seg) 490 BUG(); 491 492 trb = &state->new_deq_ptr->generic; 493 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && 494 (trb->field[3] & LINK_TOGGLE)) 495 state->new_cycle_state = ~(state->new_cycle_state) & 0x1; 496 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); 497 498 /* Don't update the ring cycle state for the producer (us). */ 499 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", 500 state->new_deq_seg); 501 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 502 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", 503 (unsigned long long) addr); 504 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); 505 ep_ring->dequeue = state->new_deq_ptr; 506 ep_ring->deq_seg = state->new_deq_seg; 507 } 508 509 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 510 struct xhci_td *cur_td) 511 { 512 struct xhci_segment *cur_seg; 513 union xhci_trb *cur_trb; 514 515 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; 516 true; 517 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 518 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == 519 TRB_TYPE(TRB_LINK)) { 520 /* Unchain any chained Link TRBs, but 521 * leave the pointers intact. 522 */ 523 cur_trb->generic.field[3] &= ~TRB_CHAIN; 524 xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); 525 xhci_dbg(xhci, "Address = %p (0x%llx dma); " 526 "in seg %p (0x%llx dma)\n", 527 cur_trb, 528 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), 529 cur_seg, 530 (unsigned long long)cur_seg->dma); 531 } else { 532 cur_trb->generic.field[0] = 0; 533 cur_trb->generic.field[1] = 0; 534 cur_trb->generic.field[2] = 0; 535 /* Preserve only the cycle bit of this TRB */ 536 cur_trb->generic.field[3] &= TRB_CYCLE; 537 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); 538 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " 539 "in seg %p (0x%llx dma)\n", 540 cur_trb, 541 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), 542 cur_seg, 543 (unsigned long long)cur_seg->dma); 544 } 545 if (cur_trb == cur_td->last_trb) 546 break; 547 } 548 } 549 550 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, 551 unsigned int ep_index, unsigned int stream_id, 552 struct xhci_segment *deq_seg, 553 union xhci_trb *deq_ptr, u32 cycle_state); 554 555 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 556 unsigned int slot_id, unsigned int ep_index, 557 unsigned int stream_id, 558 struct xhci_dequeue_state *deq_state) 559 { 560 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 561 562 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " 563 "new deq ptr = %p (0x%llx dma), new cycle = %u\n", 564 deq_state->new_deq_seg, 565 (unsigned long long)deq_state->new_deq_seg->dma, 566 deq_state->new_deq_ptr, 567 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), 568 deq_state->new_cycle_state); 569 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, 570 deq_state->new_deq_seg, 571 deq_state->new_deq_ptr, 572 (u32) deq_state->new_cycle_state); 573 /* Stop the TD queueing code from ringing the doorbell until 574 * this command completes. The HC won't set the dequeue pointer 575 * if the ring is running, and ringing the doorbell starts the 576 * ring running. 577 */ 578 ep->ep_state |= SET_DEQ_PENDING; 579 } 580 581 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, 582 struct xhci_virt_ep *ep) 583 { 584 ep->ep_state &= ~EP_HALT_PENDING; 585 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the 586 * timer is running on another CPU, we don't decrement stop_cmds_pending 587 * (since we didn't successfully stop the watchdog timer). 588 */ 589 if (del_timer(&ep->stop_cmd_timer)) 590 ep->stop_cmds_pending--; 591 } 592 593 /* Must be called with xhci->lock held in interrupt context */ 594 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 595 struct xhci_td *cur_td, int status, char *adjective) 596 { 597 struct usb_hcd *hcd = xhci_to_hcd(xhci); 598 struct urb *urb; 599 struct urb_priv *urb_priv; 600 601 urb = cur_td->urb; 602 urb_priv = urb->hcpriv; 603 urb_priv->td_cnt++; 604 605 /* Only giveback urb when this is the last td in urb */ 606 if (urb_priv->td_cnt == urb_priv->length) { 607 usb_hcd_unlink_urb_from_ep(hcd, urb); 608 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); 609 610 spin_unlock(&xhci->lock); 611 usb_hcd_giveback_urb(hcd, urb, status); 612 xhci_urb_free_priv(xhci, urb_priv); 613 spin_lock(&xhci->lock); 614 xhci_dbg(xhci, "%s URB given back\n", adjective); 615 } 616 } 617 618 /* 619 * When we get a command completion for a Stop Endpoint Command, we need to 620 * unlink any cancelled TDs from the ring. There are two ways to do that: 621 * 622 * 1. If the HW was in the middle of processing the TD that needs to be 623 * cancelled, then we must move the ring's dequeue pointer past the last TRB 624 * in the TD with a Set Dequeue Pointer Command. 625 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 626 * bit cleared) so that the HW will skip over them. 627 */ 628 static void handle_stopped_endpoint(struct xhci_hcd *xhci, 629 union xhci_trb *trb) 630 { 631 unsigned int slot_id; 632 unsigned int ep_index; 633 struct xhci_ring *ep_ring; 634 struct xhci_virt_ep *ep; 635 struct list_head *entry; 636 struct xhci_td *cur_td = NULL; 637 struct xhci_td *last_unlinked_td; 638 639 struct xhci_dequeue_state deq_state; 640 641 memset(&deq_state, 0, sizeof(deq_state)); 642 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); 643 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); 644 ep = &xhci->devs[slot_id]->eps[ep_index]; 645 646 if (list_empty(&ep->cancelled_td_list)) { 647 xhci_stop_watchdog_timer_in_irq(xhci, ep); 648 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 649 return; 650 } 651 652 /* Fix up the ep ring first, so HW stops executing cancelled TDs. 653 * We have the xHCI lock, so nothing can modify this list until we drop 654 * it. We're also in the event handler, so we can't get re-interrupted 655 * if another Stop Endpoint command completes 656 */ 657 list_for_each(entry, &ep->cancelled_td_list) { 658 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); 659 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", 660 cur_td->first_trb, 661 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); 662 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 663 if (!ep_ring) { 664 /* This shouldn't happen unless a driver is mucking 665 * with the stream ID after submission. This will 666 * leave the TD on the hardware ring, and the hardware 667 * will try to execute it, and may access a buffer 668 * that has already been freed. In the best case, the 669 * hardware will execute it, and the event handler will 670 * ignore the completion event for that TD, since it was 671 * removed from the td_list for that endpoint. In 672 * short, don't muck with the stream ID after 673 * submission. 674 */ 675 xhci_warn(xhci, "WARN Cancelled URB %p " 676 "has invalid stream ID %u.\n", 677 cur_td->urb, 678 cur_td->urb->stream_id); 679 goto remove_finished_td; 680 } 681 /* 682 * If we stopped on the TD we need to cancel, then we have to 683 * move the xHC endpoint ring dequeue pointer past this TD. 684 */ 685 if (cur_td == ep->stopped_td) 686 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, 687 cur_td->urb->stream_id, 688 cur_td, &deq_state); 689 else 690 td_to_noop(xhci, ep_ring, cur_td); 691 remove_finished_td: 692 /* 693 * The event handler won't see a completion for this TD anymore, 694 * so remove it from the endpoint ring's TD list. Keep it in 695 * the cancelled TD list for URB completion later. 696 */ 697 list_del(&cur_td->td_list); 698 } 699 last_unlinked_td = cur_td; 700 xhci_stop_watchdog_timer_in_irq(xhci, ep); 701 702 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ 703 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { 704 xhci_queue_new_dequeue_state(xhci, 705 slot_id, ep_index, 706 ep->stopped_td->urb->stream_id, 707 &deq_state); 708 xhci_ring_cmd_db(xhci); 709 } else { 710 /* Otherwise ring the doorbell(s) to restart queued transfers */ 711 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 712 } 713 ep->stopped_td = NULL; 714 ep->stopped_trb = NULL; 715 716 /* 717 * Drop the lock and complete the URBs in the cancelled TD list. 718 * New TDs to be cancelled might be added to the end of the list before 719 * we can complete all the URBs for the TDs we already unlinked. 720 * So stop when we've completed the URB for the last TD we unlinked. 721 */ 722 do { 723 cur_td = list_entry(ep->cancelled_td_list.next, 724 struct xhci_td, cancelled_td_list); 725 list_del(&cur_td->cancelled_td_list); 726 727 /* Clean up the cancelled URB */ 728 /* Doesn't matter what we pass for status, since the core will 729 * just overwrite it (because the URB has been unlinked). 730 */ 731 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); 732 733 /* Stop processing the cancelled list if the watchdog timer is 734 * running. 735 */ 736 if (xhci->xhc_state & XHCI_STATE_DYING) 737 return; 738 } while (cur_td != last_unlinked_td); 739 740 /* Return to the event handler with xhci->lock re-acquired */ 741 } 742 743 /* Watchdog timer function for when a stop endpoint command fails to complete. 744 * In this case, we assume the host controller is broken or dying or dead. The 745 * host may still be completing some other events, so we have to be careful to 746 * let the event ring handler and the URB dequeueing/enqueueing functions know 747 * through xhci->state. 748 * 749 * The timer may also fire if the host takes a very long time to respond to the 750 * command, and the stop endpoint command completion handler cannot delete the 751 * timer before the timer function is called. Another endpoint cancellation may 752 * sneak in before the timer function can grab the lock, and that may queue 753 * another stop endpoint command and add the timer back. So we cannot use a 754 * simple flag to say whether there is a pending stop endpoint command for a 755 * particular endpoint. 756 * 757 * Instead we use a combination of that flag and a counter for the number of 758 * pending stop endpoint commands. If the timer is the tail end of the last 759 * stop endpoint command, and the endpoint's command is still pending, we assume 760 * the host is dying. 761 */ 762 void xhci_stop_endpoint_command_watchdog(unsigned long arg) 763 { 764 struct xhci_hcd *xhci; 765 struct xhci_virt_ep *ep; 766 struct xhci_virt_ep *temp_ep; 767 struct xhci_ring *ring; 768 struct xhci_td *cur_td; 769 int ret, i, j; 770 771 ep = (struct xhci_virt_ep *) arg; 772 xhci = ep->xhci; 773 774 spin_lock(&xhci->lock); 775 776 ep->stop_cmds_pending--; 777 if (xhci->xhc_state & XHCI_STATE_DYING) { 778 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " 779 "xHCI as DYING, exiting.\n"); 780 spin_unlock(&xhci->lock); 781 return; 782 } 783 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { 784 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " 785 "exiting.\n"); 786 spin_unlock(&xhci->lock); 787 return; 788 } 789 790 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); 791 xhci_warn(xhci, "Assuming host is dying, halting host.\n"); 792 /* Oops, HC is dead or dying or at least not responding to the stop 793 * endpoint command. 794 */ 795 xhci->xhc_state |= XHCI_STATE_DYING; 796 /* Disable interrupts from the host controller and start halting it */ 797 xhci_quiesce(xhci); 798 spin_unlock(&xhci->lock); 799 800 ret = xhci_halt(xhci); 801 802 spin_lock(&xhci->lock); 803 if (ret < 0) { 804 /* This is bad; the host is not responding to commands and it's 805 * not allowing itself to be halted. At least interrupts are 806 * disabled, so we can set HC_STATE_HALT and notify the 807 * USB core. But if we call usb_hc_died(), it will attempt to 808 * disconnect all device drivers under this host. Those 809 * disconnect() methods will wait for all URBs to be unlinked, 810 * so we must complete them. 811 */ 812 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); 813 xhci_warn(xhci, "Completing active URBs anyway.\n"); 814 /* We could turn all TDs on the rings to no-ops. This won't 815 * help if the host has cached part of the ring, and is slow if 816 * we want to preserve the cycle bit. Skip it and hope the host 817 * doesn't touch the memory. 818 */ 819 } 820 for (i = 0; i < MAX_HC_SLOTS; i++) { 821 if (!xhci->devs[i]) 822 continue; 823 for (j = 0; j < 31; j++) { 824 temp_ep = &xhci->devs[i]->eps[j]; 825 ring = temp_ep->ring; 826 if (!ring) 827 continue; 828 xhci_dbg(xhci, "Killing URBs for slot ID %u, " 829 "ep index %u\n", i, j); 830 while (!list_empty(&ring->td_list)) { 831 cur_td = list_first_entry(&ring->td_list, 832 struct xhci_td, 833 td_list); 834 list_del(&cur_td->td_list); 835 if (!list_empty(&cur_td->cancelled_td_list)) 836 list_del(&cur_td->cancelled_td_list); 837 xhci_giveback_urb_in_irq(xhci, cur_td, 838 -ESHUTDOWN, "killed"); 839 } 840 while (!list_empty(&temp_ep->cancelled_td_list)) { 841 cur_td = list_first_entry( 842 &temp_ep->cancelled_td_list, 843 struct xhci_td, 844 cancelled_td_list); 845 list_del(&cur_td->cancelled_td_list); 846 xhci_giveback_urb_in_irq(xhci, cur_td, 847 -ESHUTDOWN, "killed"); 848 } 849 } 850 } 851 spin_unlock(&xhci->lock); 852 xhci_to_hcd(xhci)->state = HC_STATE_HALT; 853 xhci_dbg(xhci, "Calling usb_hc_died()\n"); 854 usb_hc_died(xhci_to_hcd(xhci)); 855 xhci_dbg(xhci, "xHCI host controller is dead.\n"); 856 } 857 858 /* 859 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 860 * we need to clear the set deq pending flag in the endpoint ring state, so that 861 * the TD queueing code can ring the doorbell again. We also need to ring the 862 * endpoint doorbell to restart the ring, but only if there aren't more 863 * cancellations pending. 864 */ 865 static void handle_set_deq_completion(struct xhci_hcd *xhci, 866 struct xhci_event_cmd *event, 867 union xhci_trb *trb) 868 { 869 unsigned int slot_id; 870 unsigned int ep_index; 871 unsigned int stream_id; 872 struct xhci_ring *ep_ring; 873 struct xhci_virt_device *dev; 874 struct xhci_ep_ctx *ep_ctx; 875 struct xhci_slot_ctx *slot_ctx; 876 877 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); 878 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); 879 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]); 880 dev = xhci->devs[slot_id]; 881 882 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); 883 if (!ep_ring) { 884 xhci_warn(xhci, "WARN Set TR deq ptr command for " 885 "freed stream ID %u\n", 886 stream_id); 887 /* XXX: Harmless??? */ 888 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 889 return; 890 } 891 892 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 893 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); 894 895 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { 896 unsigned int ep_state; 897 unsigned int slot_state; 898 899 switch (GET_COMP_CODE(event->status)) { 900 case COMP_TRB_ERR: 901 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " 902 "of stream ID configuration\n"); 903 break; 904 case COMP_CTX_STATE: 905 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " 906 "to incorrect slot or ep state.\n"); 907 ep_state = ep_ctx->ep_info; 908 ep_state &= EP_STATE_MASK; 909 slot_state = slot_ctx->dev_state; 910 slot_state = GET_SLOT_STATE(slot_state); 911 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", 912 slot_state, ep_state); 913 break; 914 case COMP_EBADSLT: 915 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " 916 "slot %u was not enabled.\n", slot_id); 917 break; 918 default: 919 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " 920 "completion code of %u.\n", 921 GET_COMP_CODE(event->status)); 922 break; 923 } 924 /* OK what do we do now? The endpoint state is hosed, and we 925 * should never get to this point if the synchronization between 926 * queueing, and endpoint state are correct. This might happen 927 * if the device gets disconnected after we've finished 928 * cancelling URBs, which might not be an error... 929 */ 930 } else { 931 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", 932 ep_ctx->deq); 933 } 934 935 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 936 /* Restart any rings with pending URBs */ 937 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 938 } 939 940 static void handle_reset_ep_completion(struct xhci_hcd *xhci, 941 struct xhci_event_cmd *event, 942 union xhci_trb *trb) 943 { 944 int slot_id; 945 unsigned int ep_index; 946 947 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); 948 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); 949 /* This command will only fail if the endpoint wasn't halted, 950 * but we don't care. 951 */ 952 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", 953 (unsigned int) GET_COMP_CODE(event->status)); 954 955 /* HW with the reset endpoint quirk needs to have a configure endpoint 956 * command complete before the endpoint can be used. Queue that here 957 * because the HW can't handle two commands being queued in a row. 958 */ 959 if (xhci->quirks & XHCI_RESET_EP_QUIRK) { 960 xhci_dbg(xhci, "Queueing configure endpoint command\n"); 961 xhci_queue_configure_endpoint(xhci, 962 xhci->devs[slot_id]->in_ctx->dma, slot_id, 963 false); 964 xhci_ring_cmd_db(xhci); 965 } else { 966 /* Clear our internal halted state and restart the ring(s) */ 967 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; 968 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 969 } 970 } 971 972 /* Check to see if a command in the device's command queue matches this one. 973 * Signal the completion or free the command, and return 1. Return 0 if the 974 * completed command isn't at the head of the command list. 975 */ 976 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, 977 struct xhci_virt_device *virt_dev, 978 struct xhci_event_cmd *event) 979 { 980 struct xhci_command *command; 981 982 if (list_empty(&virt_dev->cmd_list)) 983 return 0; 984 985 command = list_entry(virt_dev->cmd_list.next, 986 struct xhci_command, cmd_list); 987 if (xhci->cmd_ring->dequeue != command->command_trb) 988 return 0; 989 990 command->status = 991 GET_COMP_CODE(event->status); 992 list_del(&command->cmd_list); 993 if (command->completion) 994 complete(command->completion); 995 else 996 xhci_free_command(xhci, command); 997 return 1; 998 } 999 1000 static void handle_cmd_completion(struct xhci_hcd *xhci, 1001 struct xhci_event_cmd *event) 1002 { 1003 int slot_id = TRB_TO_SLOT_ID(event->flags); 1004 u64 cmd_dma; 1005 dma_addr_t cmd_dequeue_dma; 1006 struct xhci_input_control_ctx *ctrl_ctx; 1007 struct xhci_virt_device *virt_dev; 1008 unsigned int ep_index; 1009 struct xhci_ring *ep_ring; 1010 unsigned int ep_state; 1011 1012 cmd_dma = event->cmd_trb; 1013 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1014 xhci->cmd_ring->dequeue); 1015 /* Is the command ring deq ptr out of sync with the deq seg ptr? */ 1016 if (cmd_dequeue_dma == 0) { 1017 xhci->error_bitmask |= 1 << 4; 1018 return; 1019 } 1020 /* Does the DMA address match our internal dequeue pointer address? */ 1021 if (cmd_dma != (u64) cmd_dequeue_dma) { 1022 xhci->error_bitmask |= 1 << 5; 1023 return; 1024 } 1025 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { 1026 case TRB_TYPE(TRB_ENABLE_SLOT): 1027 if (GET_COMP_CODE(event->status) == COMP_SUCCESS) 1028 xhci->slot_id = slot_id; 1029 else 1030 xhci->slot_id = 0; 1031 complete(&xhci->addr_dev); 1032 break; 1033 case TRB_TYPE(TRB_DISABLE_SLOT): 1034 if (xhci->devs[slot_id]) 1035 xhci_free_virt_device(xhci, slot_id); 1036 break; 1037 case TRB_TYPE(TRB_CONFIG_EP): 1038 virt_dev = xhci->devs[slot_id]; 1039 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) 1040 break; 1041 /* 1042 * Configure endpoint commands can come from the USB core 1043 * configuration or alt setting changes, or because the HW 1044 * needed an extra configure endpoint command after a reset 1045 * endpoint command or streams were being configured. 1046 * If the command was for a halted endpoint, the xHCI driver 1047 * is not waiting on the configure endpoint command. 1048 */ 1049 ctrl_ctx = xhci_get_input_control_ctx(xhci, 1050 virt_dev->in_ctx); 1051 /* Input ctx add_flags are the endpoint index plus one */ 1052 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; 1053 /* A usb_set_interface() call directly after clearing a halted 1054 * condition may race on this quirky hardware. Not worth 1055 * worrying about, since this is prototype hardware. Not sure 1056 * if this will work for streams, but streams support was 1057 * untested on this prototype. 1058 */ 1059 if (xhci->quirks & XHCI_RESET_EP_QUIRK && 1060 ep_index != (unsigned int) -1 && 1061 ctrl_ctx->add_flags - SLOT_FLAG == 1062 ctrl_ctx->drop_flags) { 1063 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 1064 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; 1065 if (!(ep_state & EP_HALTED)) 1066 goto bandwidth_change; 1067 xhci_dbg(xhci, "Completed config ep cmd - " 1068 "last ep index = %d, state = %d\n", 1069 ep_index, ep_state); 1070 /* Clear internal halted state and restart ring(s) */ 1071 xhci->devs[slot_id]->eps[ep_index].ep_state &= 1072 ~EP_HALTED; 1073 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1074 break; 1075 } 1076 bandwidth_change: 1077 xhci_dbg(xhci, "Completed config ep cmd\n"); 1078 xhci->devs[slot_id]->cmd_status = 1079 GET_COMP_CODE(event->status); 1080 complete(&xhci->devs[slot_id]->cmd_completion); 1081 break; 1082 case TRB_TYPE(TRB_EVAL_CONTEXT): 1083 virt_dev = xhci->devs[slot_id]; 1084 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) 1085 break; 1086 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); 1087 complete(&xhci->devs[slot_id]->cmd_completion); 1088 break; 1089 case TRB_TYPE(TRB_ADDR_DEV): 1090 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); 1091 complete(&xhci->addr_dev); 1092 break; 1093 case TRB_TYPE(TRB_STOP_RING): 1094 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); 1095 break; 1096 case TRB_TYPE(TRB_SET_DEQ): 1097 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); 1098 break; 1099 case TRB_TYPE(TRB_CMD_NOOP): 1100 ++xhci->noops_handled; 1101 break; 1102 case TRB_TYPE(TRB_RESET_EP): 1103 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); 1104 break; 1105 case TRB_TYPE(TRB_RESET_DEV): 1106 xhci_dbg(xhci, "Completed reset device command.\n"); 1107 slot_id = TRB_TO_SLOT_ID( 1108 xhci->cmd_ring->dequeue->generic.field[3]); 1109 virt_dev = xhci->devs[slot_id]; 1110 if (virt_dev) 1111 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); 1112 else 1113 xhci_warn(xhci, "Reset device command completion " 1114 "for disabled slot %u\n", slot_id); 1115 break; 1116 case TRB_TYPE(TRB_NEC_GET_FW): 1117 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1118 xhci->error_bitmask |= 1 << 6; 1119 break; 1120 } 1121 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", 1122 NEC_FW_MAJOR(event->status), 1123 NEC_FW_MINOR(event->status)); 1124 break; 1125 default: 1126 /* Skip over unknown commands on the event ring */ 1127 xhci->error_bitmask |= 1 << 6; 1128 break; 1129 } 1130 inc_deq(xhci, xhci->cmd_ring, false); 1131 } 1132 1133 static void handle_vendor_event(struct xhci_hcd *xhci, 1134 union xhci_trb *event) 1135 { 1136 u32 trb_type; 1137 1138 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); 1139 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1140 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1141 handle_cmd_completion(xhci, &event->event_cmd); 1142 } 1143 1144 static void handle_port_status(struct xhci_hcd *xhci, 1145 union xhci_trb *event) 1146 { 1147 u32 port_id; 1148 1149 /* Port status change events always have a successful completion code */ 1150 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { 1151 xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); 1152 xhci->error_bitmask |= 1 << 8; 1153 } 1154 /* FIXME: core doesn't care about all port link state changes yet */ 1155 port_id = GET_PORT_ID(event->generic.field[0]); 1156 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); 1157 1158 /* Update event ring dequeue pointer before dropping the lock */ 1159 inc_deq(xhci, xhci->event_ring, true); 1160 1161 spin_unlock(&xhci->lock); 1162 /* Pass this up to the core */ 1163 usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); 1164 spin_lock(&xhci->lock); 1165 } 1166 1167 /* 1168 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 1169 * at end_trb, which may be in another segment. If the suspect DMA address is a 1170 * TRB in this TD, this function returns that TRB's segment. Otherwise it 1171 * returns 0. 1172 */ 1173 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1174 union xhci_trb *start_trb, 1175 union xhci_trb *end_trb, 1176 dma_addr_t suspect_dma) 1177 { 1178 dma_addr_t start_dma; 1179 dma_addr_t end_seg_dma; 1180 dma_addr_t end_trb_dma; 1181 struct xhci_segment *cur_seg; 1182 1183 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 1184 cur_seg = start_seg; 1185 1186 do { 1187 if (start_dma == 0) 1188 return NULL; 1189 /* We may get an event for a Link TRB in the middle of a TD */ 1190 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 1191 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 1192 /* If the end TRB isn't in this segment, this is set to 0 */ 1193 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 1194 1195 if (end_trb_dma > 0) { 1196 /* The end TRB is in this segment, so suspect should be here */ 1197 if (start_dma <= end_trb_dma) { 1198 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 1199 return cur_seg; 1200 } else { 1201 /* Case for one segment with 1202 * a TD wrapped around to the top 1203 */ 1204 if ((suspect_dma >= start_dma && 1205 suspect_dma <= end_seg_dma) || 1206 (suspect_dma >= cur_seg->dma && 1207 suspect_dma <= end_trb_dma)) 1208 return cur_seg; 1209 } 1210 return NULL; 1211 } else { 1212 /* Might still be somewhere in this segment */ 1213 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 1214 return cur_seg; 1215 } 1216 cur_seg = cur_seg->next; 1217 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 1218 } while (cur_seg != start_seg); 1219 1220 return NULL; 1221 } 1222 1223 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, 1224 unsigned int slot_id, unsigned int ep_index, 1225 unsigned int stream_id, 1226 struct xhci_td *td, union xhci_trb *event_trb) 1227 { 1228 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 1229 ep->ep_state |= EP_HALTED; 1230 ep->stopped_td = td; 1231 ep->stopped_trb = event_trb; 1232 ep->stopped_stream = stream_id; 1233 1234 xhci_queue_reset_ep(xhci, slot_id, ep_index); 1235 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); 1236 1237 ep->stopped_td = NULL; 1238 ep->stopped_trb = NULL; 1239 ep->stopped_stream = 0; 1240 1241 xhci_ring_cmd_db(xhci); 1242 } 1243 1244 /* Check if an error has halted the endpoint ring. The class driver will 1245 * cleanup the halt for a non-default control endpoint if we indicate a stall. 1246 * However, a babble and other errors also halt the endpoint ring, and the class 1247 * driver won't clear the halt in that case, so we need to issue a Set Transfer 1248 * Ring Dequeue Pointer command manually. 1249 */ 1250 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 1251 struct xhci_ep_ctx *ep_ctx, 1252 unsigned int trb_comp_code) 1253 { 1254 /* TRB completion codes that may require a manual halt cleanup */ 1255 if (trb_comp_code == COMP_TX_ERR || 1256 trb_comp_code == COMP_BABBLE || 1257 trb_comp_code == COMP_SPLIT_ERR) 1258 /* The 0.96 spec says a babbling control endpoint 1259 * is not halted. The 0.96 spec says it is. Some HW 1260 * claims to be 0.95 compliant, but it halts the control 1261 * endpoint anyway. Check if a babble halted the 1262 * endpoint. 1263 */ 1264 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) 1265 return 1; 1266 1267 return 0; 1268 } 1269 1270 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 1271 { 1272 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 1273 /* Vendor defined "informational" completion code, 1274 * treat as not-an-error. 1275 */ 1276 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 1277 trb_comp_code); 1278 xhci_dbg(xhci, "Treating code as success.\n"); 1279 return 1; 1280 } 1281 return 0; 1282 } 1283 1284 /* 1285 * Finish the td processing, remove the td from td list; 1286 * Return 1 if the urb can be given back. 1287 */ 1288 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, 1289 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1290 struct xhci_virt_ep *ep, int *status, bool skip) 1291 { 1292 struct xhci_virt_device *xdev; 1293 struct xhci_ring *ep_ring; 1294 unsigned int slot_id; 1295 int ep_index; 1296 struct urb *urb = NULL; 1297 struct xhci_ep_ctx *ep_ctx; 1298 int ret = 0; 1299 struct urb_priv *urb_priv; 1300 u32 trb_comp_code; 1301 1302 slot_id = TRB_TO_SLOT_ID(event->flags); 1303 xdev = xhci->devs[slot_id]; 1304 ep_index = TRB_TO_EP_ID(event->flags) - 1; 1305 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); 1306 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1307 trb_comp_code = GET_COMP_CODE(event->transfer_len); 1308 1309 if (skip) 1310 goto td_cleanup; 1311 1312 if (trb_comp_code == COMP_STOP_INVAL || 1313 trb_comp_code == COMP_STOP) { 1314 /* The Endpoint Stop Command completion will take care of any 1315 * stopped TDs. A stopped TD may be restarted, so don't update 1316 * the ring dequeue pointer or take this TD off any lists yet. 1317 */ 1318 ep->stopped_td = td; 1319 ep->stopped_trb = event_trb; 1320 return 0; 1321 } else { 1322 if (trb_comp_code == COMP_STALL) { 1323 /* The transfer is completed from the driver's 1324 * perspective, but we need to issue a set dequeue 1325 * command for this stalled endpoint to move the dequeue 1326 * pointer past the TD. We can't do that here because 1327 * the halt condition must be cleared first. Let the 1328 * USB class driver clear the stall later. 1329 */ 1330 ep->stopped_td = td; 1331 ep->stopped_trb = event_trb; 1332 ep->stopped_stream = ep_ring->stream_id; 1333 } else if (xhci_requires_manual_halt_cleanup(xhci, 1334 ep_ctx, trb_comp_code)) { 1335 /* Other types of errors halt the endpoint, but the 1336 * class driver doesn't call usb_reset_endpoint() unless 1337 * the error is -EPIPE. Clear the halted status in the 1338 * xHCI hardware manually. 1339 */ 1340 xhci_cleanup_halted_endpoint(xhci, 1341 slot_id, ep_index, ep_ring->stream_id, 1342 td, event_trb); 1343 } else { 1344 /* Update ring dequeue pointer */ 1345 while (ep_ring->dequeue != td->last_trb) 1346 inc_deq(xhci, ep_ring, false); 1347 inc_deq(xhci, ep_ring, false); 1348 } 1349 1350 td_cleanup: 1351 /* Clean up the endpoint's TD list */ 1352 urb = td->urb; 1353 urb_priv = urb->hcpriv; 1354 1355 /* Do one last check of the actual transfer length. 1356 * If the host controller said we transferred more data than 1357 * the buffer length, urb->actual_length will be a very big 1358 * number (since it's unsigned). Play it safe and say we didn't 1359 * transfer anything. 1360 */ 1361 if (urb->actual_length > urb->transfer_buffer_length) { 1362 xhci_warn(xhci, "URB transfer length is wrong, " 1363 "xHC issue? req. len = %u, " 1364 "act. len = %u\n", 1365 urb->transfer_buffer_length, 1366 urb->actual_length); 1367 urb->actual_length = 0; 1368 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1369 *status = -EREMOTEIO; 1370 else 1371 *status = 0; 1372 } 1373 list_del(&td->td_list); 1374 /* Was this TD slated to be cancelled but completed anyway? */ 1375 if (!list_empty(&td->cancelled_td_list)) 1376 list_del(&td->cancelled_td_list); 1377 1378 urb_priv->td_cnt++; 1379 /* Giveback the urb when all the tds are completed */ 1380 if (urb_priv->td_cnt == urb_priv->length) 1381 ret = 1; 1382 } 1383 1384 return ret; 1385 } 1386 1387 /* 1388 * Process control tds, update urb status and actual_length. 1389 */ 1390 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, 1391 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1392 struct xhci_virt_ep *ep, int *status) 1393 { 1394 struct xhci_virt_device *xdev; 1395 struct xhci_ring *ep_ring; 1396 unsigned int slot_id; 1397 int ep_index; 1398 struct xhci_ep_ctx *ep_ctx; 1399 u32 trb_comp_code; 1400 1401 slot_id = TRB_TO_SLOT_ID(event->flags); 1402 xdev = xhci->devs[slot_id]; 1403 ep_index = TRB_TO_EP_ID(event->flags) - 1; 1404 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); 1405 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1406 trb_comp_code = GET_COMP_CODE(event->transfer_len); 1407 1408 xhci_debug_trb(xhci, xhci->event_ring->dequeue); 1409 switch (trb_comp_code) { 1410 case COMP_SUCCESS: 1411 if (event_trb == ep_ring->dequeue) { 1412 xhci_warn(xhci, "WARN: Success on ctrl setup TRB " 1413 "without IOC set??\n"); 1414 *status = -ESHUTDOWN; 1415 } else if (event_trb != td->last_trb) { 1416 xhci_warn(xhci, "WARN: Success on ctrl data TRB " 1417 "without IOC set??\n"); 1418 *status = -ESHUTDOWN; 1419 } else { 1420 xhci_dbg(xhci, "Successful control transfer!\n"); 1421 *status = 0; 1422 } 1423 break; 1424 case COMP_SHORT_TX: 1425 xhci_warn(xhci, "WARN: short transfer on control ep\n"); 1426 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1427 *status = -EREMOTEIO; 1428 else 1429 *status = 0; 1430 break; 1431 default: 1432 if (!xhci_requires_manual_halt_cleanup(xhci, 1433 ep_ctx, trb_comp_code)) 1434 break; 1435 xhci_dbg(xhci, "TRB error code %u, " 1436 "halted endpoint index = %u\n", 1437 trb_comp_code, ep_index); 1438 /* else fall through */ 1439 case COMP_STALL: 1440 /* Did we transfer part of the data (middle) phase? */ 1441 if (event_trb != ep_ring->dequeue && 1442 event_trb != td->last_trb) 1443 td->urb->actual_length = 1444 td->urb->transfer_buffer_length 1445 - TRB_LEN(event->transfer_len); 1446 else 1447 td->urb->actual_length = 0; 1448 1449 xhci_cleanup_halted_endpoint(xhci, 1450 slot_id, ep_index, 0, td, event_trb); 1451 return finish_td(xhci, td, event_trb, event, ep, status, true); 1452 } 1453 /* 1454 * Did we transfer any data, despite the errors that might have 1455 * happened? I.e. did we get past the setup stage? 1456 */ 1457 if (event_trb != ep_ring->dequeue) { 1458 /* The event was for the status stage */ 1459 if (event_trb == td->last_trb) { 1460 if (td->urb->actual_length != 0) { 1461 /* Don't overwrite a previously set error code 1462 */ 1463 if ((*status == -EINPROGRESS || *status == 0) && 1464 (td->urb->transfer_flags 1465 & URB_SHORT_NOT_OK)) 1466 /* Did we already see a short data 1467 * stage? */ 1468 *status = -EREMOTEIO; 1469 } else { 1470 td->urb->actual_length = 1471 td->urb->transfer_buffer_length; 1472 } 1473 } else { 1474 /* Maybe the event was for the data stage? */ 1475 if (trb_comp_code != COMP_STOP_INVAL) { 1476 /* We didn't stop on a link TRB in the middle */ 1477 td->urb->actual_length = 1478 td->urb->transfer_buffer_length - 1479 TRB_LEN(event->transfer_len); 1480 xhci_dbg(xhci, "Waiting for status " 1481 "stage event\n"); 1482 return 0; 1483 } 1484 } 1485 } 1486 1487 return finish_td(xhci, td, event_trb, event, ep, status, false); 1488 } 1489 1490 /* 1491 * Process isochronous tds, update urb packet status and actual_length. 1492 */ 1493 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 1494 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1495 struct xhci_virt_ep *ep, int *status) 1496 { 1497 struct xhci_ring *ep_ring; 1498 struct urb_priv *urb_priv; 1499 int idx; 1500 int len = 0; 1501 int skip_td = 0; 1502 union xhci_trb *cur_trb; 1503 struct xhci_segment *cur_seg; 1504 u32 trb_comp_code; 1505 1506 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); 1507 trb_comp_code = GET_COMP_CODE(event->transfer_len); 1508 urb_priv = td->urb->hcpriv; 1509 idx = urb_priv->td_cnt; 1510 1511 if (ep->skip) { 1512 /* The transfer is partly done */ 1513 *status = -EXDEV; 1514 td->urb->iso_frame_desc[idx].status = -EXDEV; 1515 } else { 1516 /* handle completion code */ 1517 switch (trb_comp_code) { 1518 case COMP_SUCCESS: 1519 td->urb->iso_frame_desc[idx].status = 0; 1520 xhci_dbg(xhci, "Successful isoc transfer!\n"); 1521 break; 1522 case COMP_SHORT_TX: 1523 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1524 td->urb->iso_frame_desc[idx].status = 1525 -EREMOTEIO; 1526 else 1527 td->urb->iso_frame_desc[idx].status = 0; 1528 break; 1529 case COMP_BW_OVER: 1530 td->urb->iso_frame_desc[idx].status = -ECOMM; 1531 skip_td = 1; 1532 break; 1533 case COMP_BUFF_OVER: 1534 case COMP_BABBLE: 1535 td->urb->iso_frame_desc[idx].status = -EOVERFLOW; 1536 skip_td = 1; 1537 break; 1538 case COMP_STALL: 1539 td->urb->iso_frame_desc[idx].status = -EPROTO; 1540 skip_td = 1; 1541 break; 1542 case COMP_STOP: 1543 case COMP_STOP_INVAL: 1544 break; 1545 default: 1546 td->urb->iso_frame_desc[idx].status = -1; 1547 break; 1548 } 1549 } 1550 1551 /* calc actual length */ 1552 if (ep->skip) { 1553 td->urb->iso_frame_desc[idx].actual_length = 0; 1554 return finish_td(xhci, td, event_trb, event, ep, status, true); 1555 } 1556 1557 if (trb_comp_code == COMP_SUCCESS || skip_td == 1) { 1558 td->urb->iso_frame_desc[idx].actual_length = 1559 td->urb->iso_frame_desc[idx].length; 1560 td->urb->actual_length += 1561 td->urb->iso_frame_desc[idx].length; 1562 } else { 1563 for (cur_trb = ep_ring->dequeue, 1564 cur_seg = ep_ring->deq_seg; cur_trb != event_trb; 1565 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 1566 if ((cur_trb->generic.field[3] & 1567 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && 1568 (cur_trb->generic.field[3] & 1569 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) 1570 len += 1571 TRB_LEN(cur_trb->generic.field[2]); 1572 } 1573 len += TRB_LEN(cur_trb->generic.field[2]) - 1574 TRB_LEN(event->transfer_len); 1575 1576 if (trb_comp_code != COMP_STOP_INVAL) { 1577 td->urb->iso_frame_desc[idx].actual_length = len; 1578 td->urb->actual_length += len; 1579 } 1580 } 1581 1582 if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS) 1583 *status = 0; 1584 1585 return finish_td(xhci, td, event_trb, event, ep, status, false); 1586 } 1587 1588 /* 1589 * Process bulk and interrupt tds, update urb status and actual_length. 1590 */ 1591 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, 1592 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1593 struct xhci_virt_ep *ep, int *status) 1594 { 1595 struct xhci_ring *ep_ring; 1596 union xhci_trb *cur_trb; 1597 struct xhci_segment *cur_seg; 1598 u32 trb_comp_code; 1599 1600 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); 1601 trb_comp_code = GET_COMP_CODE(event->transfer_len); 1602 1603 switch (trb_comp_code) { 1604 case COMP_SUCCESS: 1605 /* Double check that the HW transferred everything. */ 1606 if (event_trb != td->last_trb) { 1607 xhci_warn(xhci, "WARN Successful completion " 1608 "on short TX\n"); 1609 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1610 *status = -EREMOTEIO; 1611 else 1612 *status = 0; 1613 } else { 1614 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) 1615 xhci_dbg(xhci, "Successful bulk " 1616 "transfer!\n"); 1617 else 1618 xhci_dbg(xhci, "Successful interrupt " 1619 "transfer!\n"); 1620 *status = 0; 1621 } 1622 break; 1623 case COMP_SHORT_TX: 1624 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1625 *status = -EREMOTEIO; 1626 else 1627 *status = 0; 1628 break; 1629 default: 1630 /* Others already handled above */ 1631 break; 1632 } 1633 dev_dbg(&td->urb->dev->dev, 1634 "ep %#x - asked for %d bytes, " 1635 "%d bytes untransferred\n", 1636 td->urb->ep->desc.bEndpointAddress, 1637 td->urb->transfer_buffer_length, 1638 TRB_LEN(event->transfer_len)); 1639 /* Fast path - was this the last TRB in the TD for this URB? */ 1640 if (event_trb == td->last_trb) { 1641 if (TRB_LEN(event->transfer_len) != 0) { 1642 td->urb->actual_length = 1643 td->urb->transfer_buffer_length - 1644 TRB_LEN(event->transfer_len); 1645 if (td->urb->transfer_buffer_length < 1646 td->urb->actual_length) { 1647 xhci_warn(xhci, "HC gave bad length " 1648 "of %d bytes left\n", 1649 TRB_LEN(event->transfer_len)); 1650 td->urb->actual_length = 0; 1651 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1652 *status = -EREMOTEIO; 1653 else 1654 *status = 0; 1655 } 1656 /* Don't overwrite a previously set error code */ 1657 if (*status == -EINPROGRESS) { 1658 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1659 *status = -EREMOTEIO; 1660 else 1661 *status = 0; 1662 } 1663 } else { 1664 td->urb->actual_length = 1665 td->urb->transfer_buffer_length; 1666 /* Ignore a short packet completion if the 1667 * untransferred length was zero. 1668 */ 1669 if (*status == -EREMOTEIO) 1670 *status = 0; 1671 } 1672 } else { 1673 /* Slow path - walk the list, starting from the dequeue 1674 * pointer, to get the actual length transferred. 1675 */ 1676 td->urb->actual_length = 0; 1677 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; 1678 cur_trb != event_trb; 1679 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 1680 if ((cur_trb->generic.field[3] & 1681 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && 1682 (cur_trb->generic.field[3] & 1683 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) 1684 td->urb->actual_length += 1685 TRB_LEN(cur_trb->generic.field[2]); 1686 } 1687 /* If the ring didn't stop on a Link or No-op TRB, add 1688 * in the actual bytes transferred from the Normal TRB 1689 */ 1690 if (trb_comp_code != COMP_STOP_INVAL) 1691 td->urb->actual_length += 1692 TRB_LEN(cur_trb->generic.field[2]) - 1693 TRB_LEN(event->transfer_len); 1694 } 1695 1696 return finish_td(xhci, td, event_trb, event, ep, status, false); 1697 } 1698 1699 /* 1700 * If this function returns an error condition, it means it got a Transfer 1701 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 1702 * At this point, the host controller is probably hosed and should be reset. 1703 */ 1704 static int handle_tx_event(struct xhci_hcd *xhci, 1705 struct xhci_transfer_event *event) 1706 { 1707 struct xhci_virt_device *xdev; 1708 struct xhci_virt_ep *ep; 1709 struct xhci_ring *ep_ring; 1710 unsigned int slot_id; 1711 int ep_index; 1712 struct xhci_td *td = NULL; 1713 dma_addr_t event_dma; 1714 struct xhci_segment *event_seg; 1715 union xhci_trb *event_trb; 1716 struct urb *urb = NULL; 1717 int status = -EINPROGRESS; 1718 struct urb_priv *urb_priv; 1719 struct xhci_ep_ctx *ep_ctx; 1720 u32 trb_comp_code; 1721 int ret = 0; 1722 1723 slot_id = TRB_TO_SLOT_ID(event->flags); 1724 xdev = xhci->devs[slot_id]; 1725 if (!xdev) { 1726 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); 1727 return -ENODEV; 1728 } 1729 1730 /* Endpoint ID is 1 based, our index is zero based */ 1731 ep_index = TRB_TO_EP_ID(event->flags) - 1; 1732 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); 1733 ep = &xdev->eps[ep_index]; 1734 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); 1735 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1736 if (!ep_ring || 1737 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { 1738 xhci_err(xhci, "ERROR Transfer event for disabled endpoint " 1739 "or incorrect stream ring\n"); 1740 return -ENODEV; 1741 } 1742 1743 event_dma = event->buffer; 1744 trb_comp_code = GET_COMP_CODE(event->transfer_len); 1745 /* Look for common error cases */ 1746 switch (trb_comp_code) { 1747 /* Skip codes that require special handling depending on 1748 * transfer type 1749 */ 1750 case COMP_SUCCESS: 1751 case COMP_SHORT_TX: 1752 break; 1753 case COMP_STOP: 1754 xhci_dbg(xhci, "Stopped on Transfer TRB\n"); 1755 break; 1756 case COMP_STOP_INVAL: 1757 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); 1758 break; 1759 case COMP_STALL: 1760 xhci_warn(xhci, "WARN: Stalled endpoint\n"); 1761 ep->ep_state |= EP_HALTED; 1762 status = -EPIPE; 1763 break; 1764 case COMP_TRB_ERR: 1765 xhci_warn(xhci, "WARN: TRB error on endpoint\n"); 1766 status = -EILSEQ; 1767 break; 1768 case COMP_SPLIT_ERR: 1769 case COMP_TX_ERR: 1770 xhci_warn(xhci, "WARN: transfer error on endpoint\n"); 1771 status = -EPROTO; 1772 break; 1773 case COMP_BABBLE: 1774 xhci_warn(xhci, "WARN: babble error on endpoint\n"); 1775 status = -EOVERFLOW; 1776 break; 1777 case COMP_DB_ERR: 1778 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); 1779 status = -ENOSR; 1780 break; 1781 case COMP_BW_OVER: 1782 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); 1783 break; 1784 case COMP_BUFF_OVER: 1785 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); 1786 break; 1787 case COMP_UNDERRUN: 1788 /* 1789 * When the Isoch ring is empty, the xHC will generate 1790 * a Ring Overrun Event for IN Isoch endpoint or Ring 1791 * Underrun Event for OUT Isoch endpoint. 1792 */ 1793 xhci_dbg(xhci, "underrun event on endpoint\n"); 1794 if (!list_empty(&ep_ring->td_list)) 1795 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 1796 "still with TDs queued?\n", 1797 TRB_TO_SLOT_ID(event->flags), ep_index); 1798 goto cleanup; 1799 case COMP_OVERRUN: 1800 xhci_dbg(xhci, "overrun event on endpoint\n"); 1801 if (!list_empty(&ep_ring->td_list)) 1802 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 1803 "still with TDs queued?\n", 1804 TRB_TO_SLOT_ID(event->flags), ep_index); 1805 goto cleanup; 1806 case COMP_MISSED_INT: 1807 /* 1808 * When encounter missed service error, one or more isoc tds 1809 * may be missed by xHC. 1810 * Set skip flag of the ep_ring; Complete the missed tds as 1811 * short transfer when process the ep_ring next time. 1812 */ 1813 ep->skip = true; 1814 xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); 1815 goto cleanup; 1816 default: 1817 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 1818 status = 0; 1819 break; 1820 } 1821 xhci_warn(xhci, "ERROR Unknown event condition, HC probably " 1822 "busted\n"); 1823 goto cleanup; 1824 } 1825 1826 do { 1827 /* This TRB should be in the TD at the head of this ring's 1828 * TD list. 1829 */ 1830 if (list_empty(&ep_ring->td_list)) { 1831 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " 1832 "with no TDs queued?\n", 1833 TRB_TO_SLOT_ID(event->flags), ep_index); 1834 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", 1835 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); 1836 xhci_print_trb_offsets(xhci, (union xhci_trb *) event); 1837 if (ep->skip) { 1838 ep->skip = false; 1839 xhci_dbg(xhci, "td_list is empty while skip " 1840 "flag set. Clear skip flag.\n"); 1841 } 1842 ret = 0; 1843 goto cleanup; 1844 } 1845 1846 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); 1847 /* Is this a TRB in the currently executing TD? */ 1848 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, 1849 td->last_trb, event_dma); 1850 if (event_seg && ep->skip) { 1851 xhci_dbg(xhci, "Found td. Clear skip flag.\n"); 1852 ep->skip = false; 1853 } 1854 if (!event_seg && 1855 (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) { 1856 /* HC is busted, give up! */ 1857 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not " 1858 "part of current TD\n"); 1859 return -ESHUTDOWN; 1860 } 1861 1862 if (event_seg) { 1863 event_trb = &event_seg->trbs[(event_dma - 1864 event_seg->dma) / sizeof(*event_trb)]; 1865 /* 1866 * No-op TRB should not trigger interrupts. 1867 * If event_trb is a no-op TRB, it means the 1868 * corresponding TD has been cancelled. Just ignore 1869 * the TD. 1870 */ 1871 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK) 1872 == TRB_TYPE(TRB_TR_NOOP)) { 1873 xhci_dbg(xhci, "event_trb is a no-op TRB. " 1874 "Skip it\n"); 1875 goto cleanup; 1876 } 1877 } 1878 1879 /* Now update the urb's actual_length and give back to 1880 * the core 1881 */ 1882 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 1883 ret = process_ctrl_td(xhci, td, event_trb, event, ep, 1884 &status); 1885 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 1886 ret = process_isoc_td(xhci, td, event_trb, event, ep, 1887 &status); 1888 else 1889 ret = process_bulk_intr_td(xhci, td, event_trb, event, 1890 ep, &status); 1891 1892 cleanup: 1893 /* 1894 * Do not update event ring dequeue pointer if ep->skip is set. 1895 * Will roll back to continue process missed tds. 1896 */ 1897 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { 1898 inc_deq(xhci, xhci->event_ring, true); 1899 } 1900 1901 if (ret) { 1902 urb = td->urb; 1903 urb_priv = urb->hcpriv; 1904 /* Leave the TD around for the reset endpoint function 1905 * to use(but only if it's not a control endpoint, 1906 * since we already queued the Set TR dequeue pointer 1907 * command for stalled control endpoints). 1908 */ 1909 if (usb_endpoint_xfer_control(&urb->ep->desc) || 1910 (trb_comp_code != COMP_STALL && 1911 trb_comp_code != COMP_BABBLE)) 1912 xhci_urb_free_priv(xhci, urb_priv); 1913 1914 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); 1915 xhci_dbg(xhci, "Giveback URB %p, len = %d, " 1916 "status = %d\n", 1917 urb, urb->actual_length, status); 1918 spin_unlock(&xhci->lock); 1919 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); 1920 spin_lock(&xhci->lock); 1921 } 1922 1923 /* 1924 * If ep->skip is set, it means there are missed tds on the 1925 * endpoint ring need to take care of. 1926 * Process them as short transfer until reach the td pointed by 1927 * the event. 1928 */ 1929 } while (ep->skip && trb_comp_code != COMP_MISSED_INT); 1930 1931 return 0; 1932 } 1933 1934 /* 1935 * This function handles all OS-owned events on the event ring. It may drop 1936 * xhci->lock between event processing (e.g. to pass up port status changes). 1937 */ 1938 static void xhci_handle_event(struct xhci_hcd *xhci) 1939 { 1940 union xhci_trb *event; 1941 int update_ptrs = 1; 1942 int ret; 1943 1944 xhci_dbg(xhci, "In %s\n", __func__); 1945 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 1946 xhci->error_bitmask |= 1 << 1; 1947 return; 1948 } 1949 1950 event = xhci->event_ring->dequeue; 1951 /* Does the HC or OS own the TRB? */ 1952 if ((event->event_cmd.flags & TRB_CYCLE) != 1953 xhci->event_ring->cycle_state) { 1954 xhci->error_bitmask |= 1 << 2; 1955 return; 1956 } 1957 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); 1958 1959 /* FIXME: Handle more event types. */ 1960 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { 1961 case TRB_TYPE(TRB_COMPLETION): 1962 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); 1963 handle_cmd_completion(xhci, &event->event_cmd); 1964 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); 1965 break; 1966 case TRB_TYPE(TRB_PORT_STATUS): 1967 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); 1968 handle_port_status(xhci, event); 1969 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); 1970 update_ptrs = 0; 1971 break; 1972 case TRB_TYPE(TRB_TRANSFER): 1973 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); 1974 ret = handle_tx_event(xhci, &event->trans_event); 1975 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); 1976 if (ret < 0) 1977 xhci->error_bitmask |= 1 << 9; 1978 else 1979 update_ptrs = 0; 1980 break; 1981 default: 1982 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) 1983 handle_vendor_event(xhci, event); 1984 else 1985 xhci->error_bitmask |= 1 << 3; 1986 } 1987 /* Any of the above functions may drop and re-acquire the lock, so check 1988 * to make sure a watchdog timer didn't mark the host as non-responsive. 1989 */ 1990 if (xhci->xhc_state & XHCI_STATE_DYING) { 1991 xhci_dbg(xhci, "xHCI host dying, returning from " 1992 "event handler.\n"); 1993 return; 1994 } 1995 1996 if (update_ptrs) 1997 /* Update SW event ring dequeue pointer */ 1998 inc_deq(xhci, xhci->event_ring, true); 1999 2000 /* Are there more items on the event ring? */ 2001 xhci_handle_event(xhci); 2002 } 2003 2004 /* 2005 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 2006 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 2007 * indicators of an event TRB error, but we check the status *first* to be safe. 2008 */ 2009 irqreturn_t xhci_irq(struct usb_hcd *hcd) 2010 { 2011 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2012 u32 status; 2013 union xhci_trb *trb; 2014 u64 temp_64; 2015 union xhci_trb *event_ring_deq; 2016 dma_addr_t deq; 2017 2018 spin_lock(&xhci->lock); 2019 trb = xhci->event_ring->dequeue; 2020 /* Check if the xHC generated the interrupt, or the irq is shared */ 2021 status = xhci_readl(xhci, &xhci->op_regs->status); 2022 if (status == 0xffffffff) 2023 goto hw_died; 2024 2025 if (!(status & STS_EINT)) { 2026 spin_unlock(&xhci->lock); 2027 xhci_warn(xhci, "Spurious interrupt.\n"); 2028 return IRQ_NONE; 2029 } 2030 xhci_dbg(xhci, "op reg status = %08x\n", status); 2031 xhci_dbg(xhci, "Event ring dequeue ptr:\n"); 2032 xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", 2033 (unsigned long long) 2034 xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), 2035 lower_32_bits(trb->link.segment_ptr), 2036 upper_32_bits(trb->link.segment_ptr), 2037 (unsigned int) trb->link.intr_target, 2038 (unsigned int) trb->link.control); 2039 2040 if (status & STS_FATAL) { 2041 xhci_warn(xhci, "WARNING: Host System Error\n"); 2042 xhci_halt(xhci); 2043 hw_died: 2044 xhci_to_hcd(xhci)->state = HC_STATE_HALT; 2045 spin_unlock(&xhci->lock); 2046 return -ESHUTDOWN; 2047 } 2048 2049 /* 2050 * Clear the op reg interrupt status first, 2051 * so we can receive interrupts from other MSI-X interrupters. 2052 * Write 1 to clear the interrupt status. 2053 */ 2054 status |= STS_EINT; 2055 xhci_writel(xhci, status, &xhci->op_regs->status); 2056 /* FIXME when MSI-X is supported and there are multiple vectors */ 2057 /* Clear the MSI-X event interrupt status */ 2058 2059 if (hcd->irq != -1) { 2060 u32 irq_pending; 2061 /* Acknowledge the PCI interrupt */ 2062 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); 2063 irq_pending |= 0x3; 2064 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); 2065 } 2066 2067 if (xhci->xhc_state & XHCI_STATE_DYING) { 2068 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 2069 "Shouldn't IRQs be disabled?\n"); 2070 /* Clear the event handler busy flag (RW1C); 2071 * the event ring should be empty. 2072 */ 2073 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2074 xhci_write_64(xhci, temp_64 | ERST_EHB, 2075 &xhci->ir_set->erst_dequeue); 2076 spin_unlock(&xhci->lock); 2077 2078 return IRQ_HANDLED; 2079 } 2080 2081 event_ring_deq = xhci->event_ring->dequeue; 2082 /* FIXME this should be a delayed service routine 2083 * that clears the EHB. 2084 */ 2085 xhci_handle_event(xhci); 2086 2087 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2088 /* If necessary, update the HW's version of the event ring deq ptr. */ 2089 if (event_ring_deq != xhci->event_ring->dequeue) { 2090 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2091 xhci->event_ring->dequeue); 2092 if (deq == 0) 2093 xhci_warn(xhci, "WARN something wrong with SW event " 2094 "ring dequeue ptr.\n"); 2095 /* Update HC event ring dequeue pointer */ 2096 temp_64 &= ERST_PTR_MASK; 2097 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 2098 } 2099 2100 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2101 temp_64 |= ERST_EHB; 2102 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); 2103 2104 spin_unlock(&xhci->lock); 2105 2106 return IRQ_HANDLED; 2107 } 2108 2109 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) 2110 { 2111 irqreturn_t ret; 2112 2113 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 2114 2115 ret = xhci_irq(hcd); 2116 2117 return ret; 2118 } 2119 2120 /**** Endpoint Ring Operations ****/ 2121 2122 /* 2123 * Generic function for queueing a TRB on a ring. 2124 * The caller must have checked to make sure there's room on the ring. 2125 * 2126 * @more_trbs_coming: Will you enqueue more TRBs before calling 2127 * prepare_transfer()? 2128 */ 2129 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 2130 bool consumer, bool more_trbs_coming, 2131 u32 field1, u32 field2, u32 field3, u32 field4) 2132 { 2133 struct xhci_generic_trb *trb; 2134 2135 trb = &ring->enqueue->generic; 2136 trb->field[0] = field1; 2137 trb->field[1] = field2; 2138 trb->field[2] = field3; 2139 trb->field[3] = field4; 2140 inc_enq(xhci, ring, consumer, more_trbs_coming); 2141 } 2142 2143 /* 2144 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 2145 * FIXME allocate segments if the ring is full. 2146 */ 2147 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 2148 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2149 { 2150 /* Make sure the endpoint has been added to xHC schedule */ 2151 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); 2152 switch (ep_state) { 2153 case EP_STATE_DISABLED: 2154 /* 2155 * USB core changed config/interfaces without notifying us, 2156 * or hardware is reporting the wrong state. 2157 */ 2158 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 2159 return -ENOENT; 2160 case EP_STATE_ERROR: 2161 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 2162 /* FIXME event handling code for error needs to clear it */ 2163 /* XXX not sure if this should be -ENOENT or not */ 2164 return -EINVAL; 2165 case EP_STATE_HALTED: 2166 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 2167 case EP_STATE_STOPPED: 2168 case EP_STATE_RUNNING: 2169 break; 2170 default: 2171 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 2172 /* 2173 * FIXME issue Configure Endpoint command to try to get the HC 2174 * back into a known state. 2175 */ 2176 return -EINVAL; 2177 } 2178 if (!room_on_ring(xhci, ep_ring, num_trbs)) { 2179 /* FIXME allocate more room */ 2180 xhci_err(xhci, "ERROR no room on ep ring\n"); 2181 return -ENOMEM; 2182 } 2183 2184 if (enqueue_is_link_trb(ep_ring)) { 2185 struct xhci_ring *ring = ep_ring; 2186 union xhci_trb *next; 2187 2188 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); 2189 next = ring->enqueue; 2190 2191 while (last_trb(xhci, ring, ring->enq_seg, next)) { 2192 2193 /* If we're not dealing with 0.95 hardware, 2194 * clear the chain bit. 2195 */ 2196 if (!xhci_link_trb_quirk(xhci)) 2197 next->link.control &= ~TRB_CHAIN; 2198 else 2199 next->link.control |= TRB_CHAIN; 2200 2201 wmb(); 2202 next->link.control ^= (u32) TRB_CYCLE; 2203 2204 /* Toggle the cycle bit after the last ring segment. */ 2205 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { 2206 ring->cycle_state = (ring->cycle_state ? 0 : 1); 2207 if (!in_interrupt()) { 2208 xhci_dbg(xhci, "queue_trb: Toggle cycle " 2209 "state for ring %p = %i\n", 2210 ring, (unsigned int)ring->cycle_state); 2211 } 2212 } 2213 ring->enq_seg = ring->enq_seg->next; 2214 ring->enqueue = ring->enq_seg->trbs; 2215 next = ring->enqueue; 2216 } 2217 } 2218 2219 return 0; 2220 } 2221 2222 static int prepare_transfer(struct xhci_hcd *xhci, 2223 struct xhci_virt_device *xdev, 2224 unsigned int ep_index, 2225 unsigned int stream_id, 2226 unsigned int num_trbs, 2227 struct urb *urb, 2228 unsigned int td_index, 2229 gfp_t mem_flags) 2230 { 2231 int ret; 2232 struct urb_priv *urb_priv; 2233 struct xhci_td *td; 2234 struct xhci_ring *ep_ring; 2235 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2236 2237 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); 2238 if (!ep_ring) { 2239 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 2240 stream_id); 2241 return -EINVAL; 2242 } 2243 2244 ret = prepare_ring(xhci, ep_ring, 2245 ep_ctx->ep_info & EP_STATE_MASK, 2246 num_trbs, mem_flags); 2247 if (ret) 2248 return ret; 2249 2250 urb_priv = urb->hcpriv; 2251 td = urb_priv->td[td_index]; 2252 2253 INIT_LIST_HEAD(&td->td_list); 2254 INIT_LIST_HEAD(&td->cancelled_td_list); 2255 2256 if (td_index == 0) { 2257 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); 2258 if (unlikely(ret)) { 2259 xhci_urb_free_priv(xhci, urb_priv); 2260 urb->hcpriv = NULL; 2261 return ret; 2262 } 2263 } 2264 2265 td->urb = urb; 2266 /* Add this TD to the tail of the endpoint ring's TD list */ 2267 list_add_tail(&td->td_list, &ep_ring->td_list); 2268 td->start_seg = ep_ring->enq_seg; 2269 td->first_trb = ep_ring->enqueue; 2270 2271 urb_priv->td[td_index] = td; 2272 2273 return 0; 2274 } 2275 2276 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) 2277 { 2278 int num_sgs, num_trbs, running_total, temp, i; 2279 struct scatterlist *sg; 2280 2281 sg = NULL; 2282 num_sgs = urb->num_sgs; 2283 temp = urb->transfer_buffer_length; 2284 2285 xhci_dbg(xhci, "count sg list trbs: \n"); 2286 num_trbs = 0; 2287 for_each_sg(urb->sg, sg, num_sgs, i) { 2288 unsigned int previous_total_trbs = num_trbs; 2289 unsigned int len = sg_dma_len(sg); 2290 2291 /* Scatter gather list entries may cross 64KB boundaries */ 2292 running_total = TRB_MAX_BUFF_SIZE - 2293 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2294 if (running_total != 0) 2295 num_trbs++; 2296 2297 /* How many more 64KB chunks to transfer, how many more TRBs? */ 2298 while (running_total < sg_dma_len(sg)) { 2299 num_trbs++; 2300 running_total += TRB_MAX_BUFF_SIZE; 2301 } 2302 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", 2303 i, (unsigned long long)sg_dma_address(sg), 2304 len, len, num_trbs - previous_total_trbs); 2305 2306 len = min_t(int, len, temp); 2307 temp -= len; 2308 if (temp == 0) 2309 break; 2310 } 2311 xhci_dbg(xhci, "\n"); 2312 if (!in_interrupt()) 2313 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", 2314 urb->ep->desc.bEndpointAddress, 2315 urb->transfer_buffer_length, 2316 num_trbs); 2317 return num_trbs; 2318 } 2319 2320 static void check_trb_math(struct urb *urb, int num_trbs, int running_total) 2321 { 2322 if (num_trbs != 0) 2323 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " 2324 "TRBs, %d left\n", __func__, 2325 urb->ep->desc.bEndpointAddress, num_trbs); 2326 if (running_total != urb->transfer_buffer_length) 2327 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 2328 "queued %#x (%d), asked for %#x (%d)\n", 2329 __func__, 2330 urb->ep->desc.bEndpointAddress, 2331 running_total, running_total, 2332 urb->transfer_buffer_length, 2333 urb->transfer_buffer_length); 2334 } 2335 2336 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 2337 unsigned int ep_index, unsigned int stream_id, int start_cycle, 2338 struct xhci_generic_trb *start_trb, struct xhci_td *td) 2339 { 2340 /* 2341 * Pass all the TRBs to the hardware at once and make sure this write 2342 * isn't reordered. 2343 */ 2344 wmb(); 2345 start_trb->field[3] |= start_cycle; 2346 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 2347 } 2348 2349 /* 2350 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 2351 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 2352 * (comprised of sg list entries) can take several service intervals to 2353 * transmit. 2354 */ 2355 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 2356 struct urb *urb, int slot_id, unsigned int ep_index) 2357 { 2358 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, 2359 xhci->devs[slot_id]->out_ctx, ep_index); 2360 int xhci_interval; 2361 int ep_interval; 2362 2363 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); 2364 ep_interval = urb->interval; 2365 /* Convert to microframes */ 2366 if (urb->dev->speed == USB_SPEED_LOW || 2367 urb->dev->speed == USB_SPEED_FULL) 2368 ep_interval *= 8; 2369 /* FIXME change this to a warning and a suggestion to use the new API 2370 * to set the polling interval (once the API is added). 2371 */ 2372 if (xhci_interval != ep_interval) { 2373 if (!printk_ratelimit()) 2374 dev_dbg(&urb->dev->dev, "Driver uses different interval" 2375 " (%d microframe%s) than xHCI " 2376 "(%d microframe%s)\n", 2377 ep_interval, 2378 ep_interval == 1 ? "" : "s", 2379 xhci_interval, 2380 xhci_interval == 1 ? "" : "s"); 2381 urb->interval = xhci_interval; 2382 /* Convert back to frames for LS/FS devices */ 2383 if (urb->dev->speed == USB_SPEED_LOW || 2384 urb->dev->speed == USB_SPEED_FULL) 2385 urb->interval /= 8; 2386 } 2387 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); 2388 } 2389 2390 /* 2391 * The TD size is the number of bytes remaining in the TD (including this TRB), 2392 * right shifted by 10. 2393 * It must fit in bits 21:17, so it can't be bigger than 31. 2394 */ 2395 static u32 xhci_td_remainder(unsigned int remainder) 2396 { 2397 u32 max = (1 << (21 - 17 + 1)) - 1; 2398 2399 if ((remainder >> 10) >= max) 2400 return max << 17; 2401 else 2402 return (remainder >> 10) << 17; 2403 } 2404 2405 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 2406 struct urb *urb, int slot_id, unsigned int ep_index) 2407 { 2408 struct xhci_ring *ep_ring; 2409 unsigned int num_trbs; 2410 struct urb_priv *urb_priv; 2411 struct xhci_td *td; 2412 struct scatterlist *sg; 2413 int num_sgs; 2414 int trb_buff_len, this_sg_len, running_total; 2415 bool first_trb; 2416 u64 addr; 2417 bool more_trbs_coming; 2418 2419 struct xhci_generic_trb *start_trb; 2420 int start_cycle; 2421 2422 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 2423 if (!ep_ring) 2424 return -EINVAL; 2425 2426 num_trbs = count_sg_trbs_needed(xhci, urb); 2427 num_sgs = urb->num_sgs; 2428 2429 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], 2430 ep_index, urb->stream_id, 2431 num_trbs, urb, 0, mem_flags); 2432 if (trb_buff_len < 0) 2433 return trb_buff_len; 2434 2435 urb_priv = urb->hcpriv; 2436 td = urb_priv->td[0]; 2437 2438 /* 2439 * Don't give the first TRB to the hardware (by toggling the cycle bit) 2440 * until we've finished creating all the other TRBs. The ring's cycle 2441 * state may change as we enqueue the other TRBs, so save it too. 2442 */ 2443 start_trb = &ep_ring->enqueue->generic; 2444 start_cycle = ep_ring->cycle_state; 2445 2446 running_total = 0; 2447 /* 2448 * How much data is in the first TRB? 2449 * 2450 * There are three forces at work for TRB buffer pointers and lengths: 2451 * 1. We don't want to walk off the end of this sg-list entry buffer. 2452 * 2. The transfer length that the driver requested may be smaller than 2453 * the amount of memory allocated for this scatter-gather list. 2454 * 3. TRBs buffers can't cross 64KB boundaries. 2455 */ 2456 sg = urb->sg; 2457 addr = (u64) sg_dma_address(sg); 2458 this_sg_len = sg_dma_len(sg); 2459 trb_buff_len = TRB_MAX_BUFF_SIZE - 2460 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2461 trb_buff_len = min_t(int, trb_buff_len, this_sg_len); 2462 if (trb_buff_len > urb->transfer_buffer_length) 2463 trb_buff_len = urb->transfer_buffer_length; 2464 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", 2465 trb_buff_len); 2466 2467 first_trb = true; 2468 /* Queue the first TRB, even if it's zero-length */ 2469 do { 2470 u32 field = 0; 2471 u32 length_field = 0; 2472 u32 remainder = 0; 2473 2474 /* Don't change the cycle bit of the first TRB until later */ 2475 if (first_trb) 2476 first_trb = false; 2477 else 2478 field |= ep_ring->cycle_state; 2479 2480 /* Chain all the TRBs together; clear the chain bit in the last 2481 * TRB to indicate it's the last TRB in the chain. 2482 */ 2483 if (num_trbs > 1) { 2484 field |= TRB_CHAIN; 2485 } else { 2486 /* FIXME - add check for ZERO_PACKET flag before this */ 2487 td->last_trb = ep_ring->enqueue; 2488 field |= TRB_IOC; 2489 } 2490 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " 2491 "64KB boundary at %#x, end dma = %#x\n", 2492 (unsigned int) addr, trb_buff_len, trb_buff_len, 2493 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), 2494 (unsigned int) addr + trb_buff_len); 2495 if (TRB_MAX_BUFF_SIZE - 2496 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { 2497 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); 2498 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", 2499 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), 2500 (unsigned int) addr + trb_buff_len); 2501 } 2502 remainder = xhci_td_remainder(urb->transfer_buffer_length - 2503 running_total) ; 2504 length_field = TRB_LEN(trb_buff_len) | 2505 remainder | 2506 TRB_INTR_TARGET(0); 2507 if (num_trbs > 1) 2508 more_trbs_coming = true; 2509 else 2510 more_trbs_coming = false; 2511 queue_trb(xhci, ep_ring, false, more_trbs_coming, 2512 lower_32_bits(addr), 2513 upper_32_bits(addr), 2514 length_field, 2515 /* We always want to know if the TRB was short, 2516 * or we won't get an event when it completes. 2517 * (Unless we use event data TRBs, which are a 2518 * waste of space and HC resources.) 2519 */ 2520 field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); 2521 --num_trbs; 2522 running_total += trb_buff_len; 2523 2524 /* Calculate length for next transfer -- 2525 * Are we done queueing all the TRBs for this sg entry? 2526 */ 2527 this_sg_len -= trb_buff_len; 2528 if (this_sg_len == 0) { 2529 --num_sgs; 2530 if (num_sgs == 0) 2531 break; 2532 sg = sg_next(sg); 2533 addr = (u64) sg_dma_address(sg); 2534 this_sg_len = sg_dma_len(sg); 2535 } else { 2536 addr += trb_buff_len; 2537 } 2538 2539 trb_buff_len = TRB_MAX_BUFF_SIZE - 2540 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2541 trb_buff_len = min_t(int, trb_buff_len, this_sg_len); 2542 if (running_total + trb_buff_len > urb->transfer_buffer_length) 2543 trb_buff_len = 2544 urb->transfer_buffer_length - running_total; 2545 } while (running_total < urb->transfer_buffer_length); 2546 2547 check_trb_math(urb, num_trbs, running_total); 2548 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 2549 start_cycle, start_trb, td); 2550 return 0; 2551 } 2552 2553 /* This is very similar to what ehci-q.c qtd_fill() does */ 2554 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 2555 struct urb *urb, int slot_id, unsigned int ep_index) 2556 { 2557 struct xhci_ring *ep_ring; 2558 struct urb_priv *urb_priv; 2559 struct xhci_td *td; 2560 int num_trbs; 2561 struct xhci_generic_trb *start_trb; 2562 bool first_trb; 2563 bool more_trbs_coming; 2564 int start_cycle; 2565 u32 field, length_field; 2566 2567 int running_total, trb_buff_len, ret; 2568 u64 addr; 2569 2570 if (urb->num_sgs) 2571 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); 2572 2573 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 2574 if (!ep_ring) 2575 return -EINVAL; 2576 2577 num_trbs = 0; 2578 /* How much data is (potentially) left before the 64KB boundary? */ 2579 running_total = TRB_MAX_BUFF_SIZE - 2580 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2581 2582 /* If there's some data on this 64KB chunk, or we have to send a 2583 * zero-length transfer, we need at least one TRB 2584 */ 2585 if (running_total != 0 || urb->transfer_buffer_length == 0) 2586 num_trbs++; 2587 /* How many more 64KB chunks to transfer, how many more TRBs? */ 2588 while (running_total < urb->transfer_buffer_length) { 2589 num_trbs++; 2590 running_total += TRB_MAX_BUFF_SIZE; 2591 } 2592 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ 2593 2594 if (!in_interrupt()) 2595 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", 2596 urb->ep->desc.bEndpointAddress, 2597 urb->transfer_buffer_length, 2598 urb->transfer_buffer_length, 2599 (unsigned long long)urb->transfer_dma, 2600 num_trbs); 2601 2602 ret = prepare_transfer(xhci, xhci->devs[slot_id], 2603 ep_index, urb->stream_id, 2604 num_trbs, urb, 0, mem_flags); 2605 if (ret < 0) 2606 return ret; 2607 2608 urb_priv = urb->hcpriv; 2609 td = urb_priv->td[0]; 2610 2611 /* 2612 * Don't give the first TRB to the hardware (by toggling the cycle bit) 2613 * until we've finished creating all the other TRBs. The ring's cycle 2614 * state may change as we enqueue the other TRBs, so save it too. 2615 */ 2616 start_trb = &ep_ring->enqueue->generic; 2617 start_cycle = ep_ring->cycle_state; 2618 2619 running_total = 0; 2620 /* How much data is in the first TRB? */ 2621 addr = (u64) urb->transfer_dma; 2622 trb_buff_len = TRB_MAX_BUFF_SIZE - 2623 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2624 if (urb->transfer_buffer_length < trb_buff_len) 2625 trb_buff_len = urb->transfer_buffer_length; 2626 2627 first_trb = true; 2628 2629 /* Queue the first TRB, even if it's zero-length */ 2630 do { 2631 u32 remainder = 0; 2632 field = 0; 2633 2634 /* Don't change the cycle bit of the first TRB until later */ 2635 if (first_trb) 2636 first_trb = false; 2637 else 2638 field |= ep_ring->cycle_state; 2639 2640 /* Chain all the TRBs together; clear the chain bit in the last 2641 * TRB to indicate it's the last TRB in the chain. 2642 */ 2643 if (num_trbs > 1) { 2644 field |= TRB_CHAIN; 2645 } else { 2646 /* FIXME - add check for ZERO_PACKET flag before this */ 2647 td->last_trb = ep_ring->enqueue; 2648 field |= TRB_IOC; 2649 } 2650 remainder = xhci_td_remainder(urb->transfer_buffer_length - 2651 running_total); 2652 length_field = TRB_LEN(trb_buff_len) | 2653 remainder | 2654 TRB_INTR_TARGET(0); 2655 if (num_trbs > 1) 2656 more_trbs_coming = true; 2657 else 2658 more_trbs_coming = false; 2659 queue_trb(xhci, ep_ring, false, more_trbs_coming, 2660 lower_32_bits(addr), 2661 upper_32_bits(addr), 2662 length_field, 2663 /* We always want to know if the TRB was short, 2664 * or we won't get an event when it completes. 2665 * (Unless we use event data TRBs, which are a 2666 * waste of space and HC resources.) 2667 */ 2668 field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); 2669 --num_trbs; 2670 running_total += trb_buff_len; 2671 2672 /* Calculate length for next transfer */ 2673 addr += trb_buff_len; 2674 trb_buff_len = urb->transfer_buffer_length - running_total; 2675 if (trb_buff_len > TRB_MAX_BUFF_SIZE) 2676 trb_buff_len = TRB_MAX_BUFF_SIZE; 2677 } while (running_total < urb->transfer_buffer_length); 2678 2679 check_trb_math(urb, num_trbs, running_total); 2680 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 2681 start_cycle, start_trb, td); 2682 return 0; 2683 } 2684 2685 /* Caller must have locked xhci->lock */ 2686 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 2687 struct urb *urb, int slot_id, unsigned int ep_index) 2688 { 2689 struct xhci_ring *ep_ring; 2690 int num_trbs; 2691 int ret; 2692 struct usb_ctrlrequest *setup; 2693 struct xhci_generic_trb *start_trb; 2694 int start_cycle; 2695 u32 field, length_field; 2696 struct urb_priv *urb_priv; 2697 struct xhci_td *td; 2698 2699 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 2700 if (!ep_ring) 2701 return -EINVAL; 2702 2703 /* 2704 * Need to copy setup packet into setup TRB, so we can't use the setup 2705 * DMA address. 2706 */ 2707 if (!urb->setup_packet) 2708 return -EINVAL; 2709 2710 if (!in_interrupt()) 2711 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", 2712 slot_id, ep_index); 2713 /* 1 TRB for setup, 1 for status */ 2714 num_trbs = 2; 2715 /* 2716 * Don't need to check if we need additional event data and normal TRBs, 2717 * since data in control transfers will never get bigger than 16MB 2718 * XXX: can we get a buffer that crosses 64KB boundaries? 2719 */ 2720 if (urb->transfer_buffer_length > 0) 2721 num_trbs++; 2722 ret = prepare_transfer(xhci, xhci->devs[slot_id], 2723 ep_index, urb->stream_id, 2724 num_trbs, urb, 0, mem_flags); 2725 if (ret < 0) 2726 return ret; 2727 2728 urb_priv = urb->hcpriv; 2729 td = urb_priv->td[0]; 2730 2731 /* 2732 * Don't give the first TRB to the hardware (by toggling the cycle bit) 2733 * until we've finished creating all the other TRBs. The ring's cycle 2734 * state may change as we enqueue the other TRBs, so save it too. 2735 */ 2736 start_trb = &ep_ring->enqueue->generic; 2737 start_cycle = ep_ring->cycle_state; 2738 2739 /* Queue setup TRB - see section 6.4.1.2.1 */ 2740 /* FIXME better way to translate setup_packet into two u32 fields? */ 2741 setup = (struct usb_ctrlrequest *) urb->setup_packet; 2742 queue_trb(xhci, ep_ring, false, true, 2743 /* FIXME endianness is probably going to bite my ass here. */ 2744 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, 2745 setup->wIndex | setup->wLength << 16, 2746 TRB_LEN(8) | TRB_INTR_TARGET(0), 2747 /* Immediate data in pointer */ 2748 TRB_IDT | TRB_TYPE(TRB_SETUP)); 2749 2750 /* If there's data, queue data TRBs */ 2751 field = 0; 2752 length_field = TRB_LEN(urb->transfer_buffer_length) | 2753 xhci_td_remainder(urb->transfer_buffer_length) | 2754 TRB_INTR_TARGET(0); 2755 if (urb->transfer_buffer_length > 0) { 2756 if (setup->bRequestType & USB_DIR_IN) 2757 field |= TRB_DIR_IN; 2758 queue_trb(xhci, ep_ring, false, true, 2759 lower_32_bits(urb->transfer_dma), 2760 upper_32_bits(urb->transfer_dma), 2761 length_field, 2762 /* Event on short tx */ 2763 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); 2764 } 2765 2766 /* Save the DMA address of the last TRB in the TD */ 2767 td->last_trb = ep_ring->enqueue; 2768 2769 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 2770 /* If the device sent data, the status stage is an OUT transfer */ 2771 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 2772 field = 0; 2773 else 2774 field = TRB_DIR_IN; 2775 queue_trb(xhci, ep_ring, false, false, 2776 0, 2777 0, 2778 TRB_INTR_TARGET(0), 2779 /* Event on completion */ 2780 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 2781 2782 giveback_first_trb(xhci, slot_id, ep_index, 0, 2783 start_cycle, start_trb, td); 2784 return 0; 2785 } 2786 2787 static int count_isoc_trbs_needed(struct xhci_hcd *xhci, 2788 struct urb *urb, int i) 2789 { 2790 int num_trbs = 0; 2791 u64 addr, td_len, running_total; 2792 2793 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 2794 td_len = urb->iso_frame_desc[i].length; 2795 2796 running_total = TRB_MAX_BUFF_SIZE - 2797 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2798 if (running_total != 0) 2799 num_trbs++; 2800 2801 while (running_total < td_len) { 2802 num_trbs++; 2803 running_total += TRB_MAX_BUFF_SIZE; 2804 } 2805 2806 return num_trbs; 2807 } 2808 2809 /* This is for isoc transfer */ 2810 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 2811 struct urb *urb, int slot_id, unsigned int ep_index) 2812 { 2813 struct xhci_ring *ep_ring; 2814 struct urb_priv *urb_priv; 2815 struct xhci_td *td; 2816 int num_tds, trbs_per_td; 2817 struct xhci_generic_trb *start_trb; 2818 bool first_trb; 2819 int start_cycle; 2820 u32 field, length_field; 2821 int running_total, trb_buff_len, td_len, td_remain_len, ret; 2822 u64 start_addr, addr; 2823 int i, j; 2824 2825 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 2826 2827 num_tds = urb->number_of_packets; 2828 if (num_tds < 1) { 2829 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 2830 return -EINVAL; 2831 } 2832 2833 if (!in_interrupt()) 2834 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d)," 2835 " addr = %#llx, num_tds = %d\n", 2836 urb->ep->desc.bEndpointAddress, 2837 urb->transfer_buffer_length, 2838 urb->transfer_buffer_length, 2839 (unsigned long long)urb->transfer_dma, 2840 num_tds); 2841 2842 start_addr = (u64) urb->transfer_dma; 2843 start_trb = &ep_ring->enqueue->generic; 2844 start_cycle = ep_ring->cycle_state; 2845 2846 /* Queue the first TRB, even if it's zero-length */ 2847 for (i = 0; i < num_tds; i++) { 2848 first_trb = true; 2849 2850 running_total = 0; 2851 addr = start_addr + urb->iso_frame_desc[i].offset; 2852 td_len = urb->iso_frame_desc[i].length; 2853 td_remain_len = td_len; 2854 2855 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); 2856 2857 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 2858 urb->stream_id, trbs_per_td, urb, i, mem_flags); 2859 if (ret < 0) 2860 return ret; 2861 2862 urb_priv = urb->hcpriv; 2863 td = urb_priv->td[i]; 2864 2865 for (j = 0; j < trbs_per_td; j++) { 2866 u32 remainder = 0; 2867 field = 0; 2868 2869 if (first_trb) { 2870 /* Queue the isoc TRB */ 2871 field |= TRB_TYPE(TRB_ISOC); 2872 /* Assume URB_ISO_ASAP is set */ 2873 field |= TRB_SIA; 2874 if (i > 0) 2875 field |= ep_ring->cycle_state; 2876 first_trb = false; 2877 } else { 2878 /* Queue other normal TRBs */ 2879 field |= TRB_TYPE(TRB_NORMAL); 2880 field |= ep_ring->cycle_state; 2881 } 2882 2883 /* Chain all the TRBs together; clear the chain bit in 2884 * the last TRB to indicate it's the last TRB in the 2885 * chain. 2886 */ 2887 if (j < trbs_per_td - 1) { 2888 field |= TRB_CHAIN; 2889 } else { 2890 td->last_trb = ep_ring->enqueue; 2891 field |= TRB_IOC; 2892 } 2893 2894 /* Calculate TRB length */ 2895 trb_buff_len = TRB_MAX_BUFF_SIZE - 2896 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 2897 if (trb_buff_len > td_remain_len) 2898 trb_buff_len = td_remain_len; 2899 2900 remainder = xhci_td_remainder(td_len - running_total); 2901 length_field = TRB_LEN(trb_buff_len) | 2902 remainder | 2903 TRB_INTR_TARGET(0); 2904 queue_trb(xhci, ep_ring, false, false, 2905 lower_32_bits(addr), 2906 upper_32_bits(addr), 2907 length_field, 2908 /* We always want to know if the TRB was short, 2909 * or we won't get an event when it completes. 2910 * (Unless we use event data TRBs, which are a 2911 * waste of space and HC resources.) 2912 */ 2913 field | TRB_ISP); 2914 running_total += trb_buff_len; 2915 2916 addr += trb_buff_len; 2917 td_remain_len -= trb_buff_len; 2918 } 2919 2920 /* Check TD length */ 2921 if (running_total != td_len) { 2922 xhci_err(xhci, "ISOC TD length unmatch\n"); 2923 return -EINVAL; 2924 } 2925 } 2926 2927 wmb(); 2928 start_trb->field[3] |= start_cycle; 2929 2930 ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id); 2931 return 0; 2932 } 2933 2934 /* 2935 * Check transfer ring to guarantee there is enough room for the urb. 2936 * Update ISO URB start_frame and interval. 2937 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to 2938 * update the urb->start_frame by now. 2939 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. 2940 */ 2941 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2942 struct urb *urb, int slot_id, unsigned int ep_index) 2943 { 2944 struct xhci_virt_device *xdev; 2945 struct xhci_ring *ep_ring; 2946 struct xhci_ep_ctx *ep_ctx; 2947 int start_frame; 2948 int xhci_interval; 2949 int ep_interval; 2950 int num_tds, num_trbs, i; 2951 int ret; 2952 2953 xdev = xhci->devs[slot_id]; 2954 ep_ring = xdev->eps[ep_index].ring; 2955 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2956 2957 num_trbs = 0; 2958 num_tds = urb->number_of_packets; 2959 for (i = 0; i < num_tds; i++) 2960 num_trbs += count_isoc_trbs_needed(xhci, urb, i); 2961 2962 /* Check the ring to guarantee there is enough room for the whole urb. 2963 * Do not insert any td of the urb to the ring if the check failed. 2964 */ 2965 ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK, 2966 num_trbs, mem_flags); 2967 if (ret) 2968 return ret; 2969 2970 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); 2971 start_frame &= 0x3fff; 2972 2973 urb->start_frame = start_frame; 2974 if (urb->dev->speed == USB_SPEED_LOW || 2975 urb->dev->speed == USB_SPEED_FULL) 2976 urb->start_frame >>= 3; 2977 2978 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); 2979 ep_interval = urb->interval; 2980 /* Convert to microframes */ 2981 if (urb->dev->speed == USB_SPEED_LOW || 2982 urb->dev->speed == USB_SPEED_FULL) 2983 ep_interval *= 8; 2984 /* FIXME change this to a warning and a suggestion to use the new API 2985 * to set the polling interval (once the API is added). 2986 */ 2987 if (xhci_interval != ep_interval) { 2988 if (!printk_ratelimit()) 2989 dev_dbg(&urb->dev->dev, "Driver uses different interval" 2990 " (%d microframe%s) than xHCI " 2991 "(%d microframe%s)\n", 2992 ep_interval, 2993 ep_interval == 1 ? "" : "s", 2994 xhci_interval, 2995 xhci_interval == 1 ? "" : "s"); 2996 urb->interval = xhci_interval; 2997 /* Convert back to frames for LS/FS devices */ 2998 if (urb->dev->speed == USB_SPEED_LOW || 2999 urb->dev->speed == USB_SPEED_FULL) 3000 urb->interval /= 8; 3001 } 3002 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); 3003 } 3004 3005 /**** Command Ring Operations ****/ 3006 3007 /* Generic function for queueing a command TRB on the command ring. 3008 * Check to make sure there's room on the command ring for one command TRB. 3009 * Also check that there's room reserved for commands that must not fail. 3010 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 3011 * then only check for the number of reserved spots. 3012 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 3013 * because the command event handler may want to resubmit a failed command. 3014 */ 3015 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, 3016 u32 field3, u32 field4, bool command_must_succeed) 3017 { 3018 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 3019 int ret; 3020 3021 if (!command_must_succeed) 3022 reserved_trbs++; 3023 3024 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 3025 reserved_trbs, GFP_ATOMIC); 3026 if (ret < 0) { 3027 xhci_err(xhci, "ERR: No room for command on command ring\n"); 3028 if (command_must_succeed) 3029 xhci_err(xhci, "ERR: Reserved TRB counting for " 3030 "unfailable commands failed.\n"); 3031 return ret; 3032 } 3033 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3, 3034 field4 | xhci->cmd_ring->cycle_state); 3035 return 0; 3036 } 3037 3038 /* Queue a no-op command on the command ring */ 3039 static int queue_cmd_noop(struct xhci_hcd *xhci) 3040 { 3041 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); 3042 } 3043 3044 /* 3045 * Place a no-op command on the command ring to test the command and 3046 * event ring. 3047 */ 3048 void *xhci_setup_one_noop(struct xhci_hcd *xhci) 3049 { 3050 if (queue_cmd_noop(xhci) < 0) 3051 return NULL; 3052 xhci->noops_submitted++; 3053 return xhci_ring_cmd_db; 3054 } 3055 3056 /* Queue a slot enable or disable request on the command ring */ 3057 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) 3058 { 3059 return queue_command(xhci, 0, 0, 0, 3060 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 3061 } 3062 3063 /* Queue an address device command TRB */ 3064 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3065 u32 slot_id) 3066 { 3067 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3068 upper_32_bits(in_ctx_ptr), 0, 3069 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), 3070 false); 3071 } 3072 3073 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 3074 u32 field1, u32 field2, u32 field3, u32 field4) 3075 { 3076 return queue_command(xhci, field1, field2, field3, field4, false); 3077 } 3078 3079 /* Queue a reset device command TRB */ 3080 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) 3081 { 3082 return queue_command(xhci, 0, 0, 0, 3083 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 3084 false); 3085 } 3086 3087 /* Queue a configure endpoint command TRB */ 3088 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3089 u32 slot_id, bool command_must_succeed) 3090 { 3091 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3092 upper_32_bits(in_ctx_ptr), 0, 3093 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 3094 command_must_succeed); 3095 } 3096 3097 /* Queue an evaluate context command TRB */ 3098 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3099 u32 slot_id) 3100 { 3101 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3102 upper_32_bits(in_ctx_ptr), 0, 3103 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 3104 false); 3105 } 3106 3107 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 3108 unsigned int ep_index) 3109 { 3110 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3111 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3112 u32 type = TRB_TYPE(TRB_STOP_RING); 3113 3114 return queue_command(xhci, 0, 0, 0, 3115 trb_slot_id | trb_ep_index | type, false); 3116 } 3117 3118 /* Set Transfer Ring Dequeue Pointer command. 3119 * This should not be used for endpoints that have streams enabled. 3120 */ 3121 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, 3122 unsigned int ep_index, unsigned int stream_id, 3123 struct xhci_segment *deq_seg, 3124 union xhci_trb *deq_ptr, u32 cycle_state) 3125 { 3126 dma_addr_t addr; 3127 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3128 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3129 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); 3130 u32 type = TRB_TYPE(TRB_SET_DEQ); 3131 3132 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); 3133 if (addr == 0) { 3134 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 3135 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", 3136 deq_seg, deq_ptr); 3137 return 0; 3138 } 3139 return queue_command(xhci, lower_32_bits(addr) | cycle_state, 3140 upper_32_bits(addr), trb_stream_id, 3141 trb_slot_id | trb_ep_index | type, false); 3142 } 3143 3144 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 3145 unsigned int ep_index) 3146 { 3147 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3148 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3149 u32 type = TRB_TYPE(TRB_RESET_EP); 3150 3151 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, 3152 false); 3153 } 3154