1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 * Ring initialization rules: 25 * 1. Each segment is initialized to zero, except for link TRBs. 26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 27 * Consumer Cycle State (CCS), depending on ring function. 28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 29 * 30 * Ring behavior rules: 31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 32 * least one free TRB in the ring. This is useful if you want to turn that 33 * into a link TRB and expand the ring. 34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 35 * link TRB, then load the pointer with the address in the link TRB. If the 36 * link TRB had its toggle bit set, you may need to update the ring cycle 37 * state (see cycle bit rules). You may have to do this multiple times 38 * until you reach a non-link TRB. 39 * 3. A ring is full if enqueue++ (for the definition of increment above) 40 * equals the dequeue pointer. 41 * 42 * Cycle bit rules: 43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 44 * in a link TRB, it must toggle the ring cycle state. 45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 46 * in a link TRB, it must toggle the ring cycle state. 47 * 48 * Producer rules: 49 * 1. Check if ring is full before you enqueue. 50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 51 * Update enqueue pointer between each write (which may update the ring 52 * cycle state). 53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 54 * and endpoint rings. If HC is the producer for the event ring, 55 * and it generates an interrupt according to interrupt modulation rules. 56 * 57 * Consumer rules: 58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 59 * the TRB is owned by the consumer. 60 * 2. Update dequeue pointer (which may update the ring cycle state) and 61 * continue processing TRBs until you reach a TRB which is not owned by you. 62 * 3. Notify the producer. SW is the consumer for the event ring, and it 63 * updates event ring dequeue pointer. HC is the consumer for the command and 64 * endpoint rings; it generates events on the event ring for these. 65 */ 66 67 #include <linux/scatterlist.h> 68 #include <linux/slab.h> 69 #include <linux/dma-mapping.h> 70 #include "xhci.h" 71 #include "xhci-trace.h" 72 #include "xhci-mtk.h" 73 74 /* 75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 76 * address of the TRB. 77 */ 78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 79 union xhci_trb *trb) 80 { 81 unsigned long segment_offset; 82 83 if (!seg || !trb || trb < seg->trbs) 84 return 0; 85 /* offset in TRBs */ 86 segment_offset = trb - seg->trbs; 87 if (segment_offset >= TRBS_PER_SEGMENT) 88 return 0; 89 return seg->dma + (segment_offset * sizeof(*trb)); 90 } 91 92 static bool trb_is_link(union xhci_trb *trb) 93 { 94 return TRB_TYPE_LINK_LE32(trb->link.control); 95 } 96 97 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) 98 { 99 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; 100 } 101 102 static bool last_trb_on_ring(struct xhci_ring *ring, 103 struct xhci_segment *seg, union xhci_trb *trb) 104 { 105 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); 106 } 107 108 static bool link_trb_toggles_cycle(union xhci_trb *trb) 109 { 110 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 111 } 112 113 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 114 * TRB is in a new segment. This does not skip over link TRBs, and it does not 115 * effect the ring dequeue or enqueue pointers. 116 */ 117 static void next_trb(struct xhci_hcd *xhci, 118 struct xhci_ring *ring, 119 struct xhci_segment **seg, 120 union xhci_trb **trb) 121 { 122 if (trb_is_link(*trb)) { 123 *seg = (*seg)->next; 124 *trb = ((*seg)->trbs); 125 } else { 126 (*trb)++; 127 } 128 } 129 130 /* 131 * See Cycle bit rules. SW is the consumer for the event ring only. 132 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 133 */ 134 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 135 { 136 ring->deq_updates++; 137 138 /* event ring doesn't have link trbs, check for last trb */ 139 if (ring->type == TYPE_EVENT) { 140 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 141 ring->dequeue++; 142 return; 143 } 144 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) 145 ring->cycle_state ^= 1; 146 ring->deq_seg = ring->deq_seg->next; 147 ring->dequeue = ring->deq_seg->trbs; 148 return; 149 } 150 151 /* All other rings have link trbs */ 152 if (!trb_is_link(ring->dequeue)) { 153 ring->dequeue++; 154 ring->num_trbs_free++; 155 } 156 while (trb_is_link(ring->dequeue)) { 157 ring->deq_seg = ring->deq_seg->next; 158 ring->dequeue = ring->deq_seg->trbs; 159 } 160 return; 161 } 162 163 /* 164 * See Cycle bit rules. SW is the consumer for the event ring only. 165 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 166 * 167 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 168 * chain bit is set), then set the chain bit in all the following link TRBs. 169 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 170 * have their chain bit cleared (so that each Link TRB is a separate TD). 171 * 172 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 173 * set, but other sections talk about dealing with the chain bit set. This was 174 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 175 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 176 * 177 * @more_trbs_coming: Will you enqueue more TRBs before calling 178 * prepare_transfer()? 179 */ 180 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 181 bool more_trbs_coming) 182 { 183 u32 chain; 184 union xhci_trb *next; 185 186 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 187 /* If this is not event ring, there is one less usable TRB */ 188 if (!trb_is_link(ring->enqueue)) 189 ring->num_trbs_free--; 190 next = ++(ring->enqueue); 191 192 ring->enq_updates++; 193 /* Update the dequeue pointer further if that was a link TRB */ 194 while (trb_is_link(next)) { 195 196 /* 197 * If the caller doesn't plan on enqueueing more TDs before 198 * ringing the doorbell, then we don't want to give the link TRB 199 * to the hardware just yet. We'll give the link TRB back in 200 * prepare_ring() just before we enqueue the TD at the top of 201 * the ring. 202 */ 203 if (!chain && !more_trbs_coming) 204 break; 205 206 /* If we're not dealing with 0.95 hardware or isoc rings on 207 * AMD 0.96 host, carry over the chain bit of the previous TRB 208 * (which may mean the chain bit is cleared). 209 */ 210 if (!(ring->type == TYPE_ISOC && 211 (xhci->quirks & XHCI_AMD_0x96_HOST)) && 212 !xhci_link_trb_quirk(xhci)) { 213 next->link.control &= cpu_to_le32(~TRB_CHAIN); 214 next->link.control |= cpu_to_le32(chain); 215 } 216 /* Give this link TRB to the hardware */ 217 wmb(); 218 next->link.control ^= cpu_to_le32(TRB_CYCLE); 219 220 /* Toggle the cycle bit after the last ring segment. */ 221 if (link_trb_toggles_cycle(next)) 222 ring->cycle_state ^= 1; 223 224 ring->enq_seg = ring->enq_seg->next; 225 ring->enqueue = ring->enq_seg->trbs; 226 next = ring->enqueue; 227 } 228 } 229 230 /* 231 * Check to see if there's room to enqueue num_trbs on the ring and make sure 232 * enqueue pointer will not advance into dequeue segment. See rules above. 233 */ 234 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 235 unsigned int num_trbs) 236 { 237 int num_trbs_in_deq_seg; 238 239 if (ring->num_trbs_free < num_trbs) 240 return 0; 241 242 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { 243 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; 244 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) 245 return 0; 246 } 247 248 return 1; 249 } 250 251 /* Ring the host controller doorbell after placing a command on the ring */ 252 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 253 { 254 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 255 return; 256 257 xhci_dbg(xhci, "// Ding dong!\n"); 258 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); 259 /* Flush PCI posted writes */ 260 readl(&xhci->dba->doorbell[0]); 261 } 262 263 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) 264 { 265 u64 temp_64; 266 int ret; 267 268 xhci_dbg(xhci, "Abort command ring\n"); 269 270 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 271 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 272 273 /* 274 * Writing the CMD_RING_ABORT bit should cause a cmd completion event, 275 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared 276 * but the completion event in never sent. Use the cmd timeout timer to 277 * handle those cases. Use twice the time to cover the bit polling retry 278 */ 279 mod_timer(&xhci->cmd_timer, jiffies + (2 * XHCI_CMD_DEFAULT_TIMEOUT)); 280 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, 281 &xhci->op_regs->cmd_ring); 282 283 /* Section 4.6.1.2 of xHCI 1.0 spec says software should 284 * time the completion od all xHCI commands, including 285 * the Command Abort operation. If software doesn't see 286 * CRR negated in a timely manner (e.g. longer than 5 287 * seconds), then it should assume that the there are 288 * larger problems with the xHC and assert HCRST. 289 */ 290 ret = xhci_handshake(&xhci->op_regs->cmd_ring, 291 CMD_RING_RUNNING, 0, 5 * 1000 * 1000); 292 if (ret < 0) { 293 /* we are about to kill xhci, give it one more chance */ 294 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, 295 &xhci->op_regs->cmd_ring); 296 udelay(1000); 297 ret = xhci_handshake(&xhci->op_regs->cmd_ring, 298 CMD_RING_RUNNING, 0, 3 * 1000 * 1000); 299 if (ret == 0) 300 return 0; 301 302 xhci_err(xhci, "Stopped the command ring failed, " 303 "maybe the host is dead\n"); 304 del_timer(&xhci->cmd_timer); 305 xhci->xhc_state |= XHCI_STATE_DYING; 306 xhci_quiesce(xhci); 307 xhci_halt(xhci); 308 return -ESHUTDOWN; 309 } 310 311 return 0; 312 } 313 314 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 315 unsigned int slot_id, 316 unsigned int ep_index, 317 unsigned int stream_id) 318 { 319 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 320 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 321 unsigned int ep_state = ep->ep_state; 322 323 /* Don't ring the doorbell for this endpoint if there are pending 324 * cancellations because we don't want to interrupt processing. 325 * We don't want to restart any stream rings if there's a set dequeue 326 * pointer command pending because the device can choose to start any 327 * stream once the endpoint is on the HW schedule. 328 */ 329 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || 330 (ep_state & EP_HALTED)) 331 return; 332 writel(DB_VALUE(ep_index, stream_id), db_addr); 333 /* The CPU has better things to do at this point than wait for a 334 * write-posting flush. It'll get there soon enough. 335 */ 336 } 337 338 /* Ring the doorbell for any rings with pending URBs */ 339 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 340 unsigned int slot_id, 341 unsigned int ep_index) 342 { 343 unsigned int stream_id; 344 struct xhci_virt_ep *ep; 345 346 ep = &xhci->devs[slot_id]->eps[ep_index]; 347 348 /* A ring has pending URBs if its TD list is not empty */ 349 if (!(ep->ep_state & EP_HAS_STREAMS)) { 350 if (ep->ring && !(list_empty(&ep->ring->td_list))) 351 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 352 return; 353 } 354 355 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 356 stream_id++) { 357 struct xhci_stream_info *stream_info = ep->stream_info; 358 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 359 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 360 stream_id); 361 } 362 } 363 364 /* Get the right ring for the given slot_id, ep_index and stream_id. 365 * If the endpoint supports streams, boundary check the URB's stream ID. 366 * If the endpoint doesn't support streams, return the singular endpoint ring. 367 */ 368 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 369 unsigned int slot_id, unsigned int ep_index, 370 unsigned int stream_id) 371 { 372 struct xhci_virt_ep *ep; 373 374 ep = &xhci->devs[slot_id]->eps[ep_index]; 375 /* Common case: no streams */ 376 if (!(ep->ep_state & EP_HAS_STREAMS)) 377 return ep->ring; 378 379 if (stream_id == 0) { 380 xhci_warn(xhci, 381 "WARN: Slot ID %u, ep index %u has streams, " 382 "but URB has no stream ID.\n", 383 slot_id, ep_index); 384 return NULL; 385 } 386 387 if (stream_id < ep->stream_info->num_streams) 388 return ep->stream_info->stream_rings[stream_id]; 389 390 xhci_warn(xhci, 391 "WARN: Slot ID %u, ep index %u has " 392 "stream IDs 1 to %u allocated, " 393 "but stream ID %u is requested.\n", 394 slot_id, ep_index, 395 ep->stream_info->num_streams - 1, 396 stream_id); 397 return NULL; 398 } 399 400 /* 401 * Move the xHC's endpoint ring dequeue pointer past cur_td. 402 * Record the new state of the xHC's endpoint ring dequeue segment, 403 * dequeue pointer, and new consumer cycle state in state. 404 * Update our internal representation of the ring's dequeue pointer. 405 * 406 * We do this in three jumps: 407 * - First we update our new ring state to be the same as when the xHC stopped. 408 * - Then we traverse the ring to find the segment that contains 409 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass 410 * any link TRBs with the toggle cycle bit set. 411 * - Finally we move the dequeue state one TRB further, toggling the cycle bit 412 * if we've moved it past a link TRB with the toggle cycle bit set. 413 * 414 * Some of the uses of xhci_generic_trb are grotty, but if they're done 415 * with correct __le32 accesses they should work fine. Only users of this are 416 * in here. 417 */ 418 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 419 unsigned int slot_id, unsigned int ep_index, 420 unsigned int stream_id, struct xhci_td *cur_td, 421 struct xhci_dequeue_state *state) 422 { 423 struct xhci_virt_device *dev = xhci->devs[slot_id]; 424 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 425 struct xhci_ring *ep_ring; 426 struct xhci_segment *new_seg; 427 union xhci_trb *new_deq; 428 dma_addr_t addr; 429 u64 hw_dequeue; 430 bool cycle_found = false; 431 bool td_last_trb_found = false; 432 433 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 434 ep_index, stream_id); 435 if (!ep_ring) { 436 xhci_warn(xhci, "WARN can't find new dequeue state " 437 "for invalid stream ID %u.\n", 438 stream_id); 439 return; 440 } 441 442 /* Dig out the cycle state saved by the xHC during the stop ep cmd */ 443 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 444 "Finding endpoint context"); 445 /* 4.6.9 the css flag is written to the stream context for streams */ 446 if (ep->ep_state & EP_HAS_STREAMS) { 447 struct xhci_stream_ctx *ctx = 448 &ep->stream_info->stream_ctx_array[stream_id]; 449 hw_dequeue = le64_to_cpu(ctx->stream_ring); 450 } else { 451 struct xhci_ep_ctx *ep_ctx 452 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 453 hw_dequeue = le64_to_cpu(ep_ctx->deq); 454 } 455 456 new_seg = ep_ring->deq_seg; 457 new_deq = ep_ring->dequeue; 458 state->new_cycle_state = hw_dequeue & 0x1; 459 460 /* 461 * We want to find the pointer, segment and cycle state of the new trb 462 * (the one after current TD's last_trb). We know the cycle state at 463 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are 464 * found. 465 */ 466 do { 467 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) 468 == (dma_addr_t)(hw_dequeue & ~0xf)) { 469 cycle_found = true; 470 if (td_last_trb_found) 471 break; 472 } 473 if (new_deq == cur_td->last_trb) 474 td_last_trb_found = true; 475 476 if (cycle_found && 477 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) && 478 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE)) 479 state->new_cycle_state ^= 0x1; 480 481 next_trb(xhci, ep_ring, &new_seg, &new_deq); 482 483 /* Search wrapped around, bail out */ 484 if (new_deq == ep->ring->dequeue) { 485 xhci_err(xhci, "Error: Failed finding new dequeue state\n"); 486 state->new_deq_seg = NULL; 487 state->new_deq_ptr = NULL; 488 return; 489 } 490 491 } while (!cycle_found || !td_last_trb_found); 492 493 state->new_deq_seg = new_seg; 494 state->new_deq_ptr = new_deq; 495 496 /* Don't update the ring cycle state for the producer (us). */ 497 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 498 "Cycle state = 0x%x", state->new_cycle_state); 499 500 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 501 "New dequeue segment = %p (virtual)", 502 state->new_deq_seg); 503 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 504 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 505 "New dequeue pointer = 0x%llx (DMA)", 506 (unsigned long long) addr); 507 } 508 509 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 510 * (The last TRB actually points to the ring enqueue pointer, which is not part 511 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 512 */ 513 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 514 struct xhci_td *cur_td, bool flip_cycle) 515 { 516 struct xhci_segment *cur_seg; 517 union xhci_trb *cur_trb; 518 519 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; 520 true; 521 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 522 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { 523 /* Unchain any chained Link TRBs, but 524 * leave the pointers intact. 525 */ 526 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); 527 /* Flip the cycle bit (link TRBs can't be the first 528 * or last TRB). 529 */ 530 if (flip_cycle) 531 cur_trb->generic.field[3] ^= 532 cpu_to_le32(TRB_CYCLE); 533 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 534 "Cancel (unchain) link TRB"); 535 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 536 "Address = %p (0x%llx dma); " 537 "in seg %p (0x%llx dma)", 538 cur_trb, 539 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), 540 cur_seg, 541 (unsigned long long)cur_seg->dma); 542 } else { 543 cur_trb->generic.field[0] = 0; 544 cur_trb->generic.field[1] = 0; 545 cur_trb->generic.field[2] = 0; 546 /* Preserve only the cycle bit of this TRB */ 547 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 548 /* Flip the cycle bit except on the first or last TRB */ 549 if (flip_cycle && cur_trb != cur_td->first_trb && 550 cur_trb != cur_td->last_trb) 551 cur_trb->generic.field[3] ^= 552 cpu_to_le32(TRB_CYCLE); 553 cur_trb->generic.field[3] |= cpu_to_le32( 554 TRB_TYPE(TRB_TR_NOOP)); 555 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 556 "TRB to noop at offset 0x%llx", 557 (unsigned long long) 558 xhci_trb_virt_to_dma(cur_seg, cur_trb)); 559 } 560 if (cur_trb == cur_td->last_trb) 561 break; 562 } 563 } 564 565 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, 566 struct xhci_virt_ep *ep) 567 { 568 ep->ep_state &= ~EP_HALT_PENDING; 569 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the 570 * timer is running on another CPU, we don't decrement stop_cmds_pending 571 * (since we didn't successfully stop the watchdog timer). 572 */ 573 if (del_timer(&ep->stop_cmd_timer)) 574 ep->stop_cmds_pending--; 575 } 576 577 /* Must be called with xhci->lock held in interrupt context */ 578 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 579 struct xhci_td *cur_td, int status) 580 { 581 struct usb_hcd *hcd; 582 struct urb *urb; 583 struct urb_priv *urb_priv; 584 585 urb = cur_td->urb; 586 urb_priv = urb->hcpriv; 587 urb_priv->td_cnt++; 588 hcd = bus_to_hcd(urb->dev->bus); 589 590 /* Only giveback urb when this is the last td in urb */ 591 if (urb_priv->td_cnt == urb_priv->length) { 592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 595 if (xhci->quirks & XHCI_AMD_PLL_FIX) 596 usb_amd_quirk_pll_enable(); 597 } 598 } 599 usb_hcd_unlink_urb_from_ep(hcd, urb); 600 601 spin_unlock(&xhci->lock); 602 usb_hcd_giveback_urb(hcd, urb, status); 603 xhci_urb_free_priv(urb_priv); 604 spin_lock(&xhci->lock); 605 } 606 } 607 608 void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring, 609 struct xhci_td *td) 610 { 611 struct device *dev = xhci_to_hcd(xhci)->self.controller; 612 struct xhci_segment *seg = td->bounce_seg; 613 struct urb *urb = td->urb; 614 615 if (!seg || !urb) 616 return; 617 618 if (usb_urb_dir_out(urb)) { 619 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 620 DMA_TO_DEVICE); 621 return; 622 } 623 624 /* for in tranfers we need to copy the data from bounce to sg */ 625 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, 626 seg->bounce_len, seg->bounce_offs); 627 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 628 DMA_FROM_DEVICE); 629 seg->bounce_len = 0; 630 seg->bounce_offs = 0; 631 } 632 633 /* 634 * When we get a command completion for a Stop Endpoint Command, we need to 635 * unlink any cancelled TDs from the ring. There are two ways to do that: 636 * 637 * 1. If the HW was in the middle of processing the TD that needs to be 638 * cancelled, then we must move the ring's dequeue pointer past the last TRB 639 * in the TD with a Set Dequeue Pointer Command. 640 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 641 * bit cleared) so that the HW will skip over them. 642 */ 643 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, 644 union xhci_trb *trb, struct xhci_event_cmd *event) 645 { 646 unsigned int ep_index; 647 struct xhci_ring *ep_ring; 648 struct xhci_virt_ep *ep; 649 struct list_head *entry; 650 struct xhci_td *cur_td = NULL; 651 struct xhci_td *last_unlinked_td; 652 653 struct xhci_dequeue_state deq_state; 654 655 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { 656 if (!xhci->devs[slot_id]) 657 xhci_warn(xhci, "Stop endpoint command " 658 "completion for disabled slot %u\n", 659 slot_id); 660 return; 661 } 662 663 memset(&deq_state, 0, sizeof(deq_state)); 664 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 665 ep = &xhci->devs[slot_id]->eps[ep_index]; 666 667 if (list_empty(&ep->cancelled_td_list)) { 668 xhci_stop_watchdog_timer_in_irq(xhci, ep); 669 ep->stopped_td = NULL; 670 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 671 return; 672 } 673 674 /* Fix up the ep ring first, so HW stops executing cancelled TDs. 675 * We have the xHCI lock, so nothing can modify this list until we drop 676 * it. We're also in the event handler, so we can't get re-interrupted 677 * if another Stop Endpoint command completes 678 */ 679 list_for_each(entry, &ep->cancelled_td_list) { 680 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); 681 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 682 "Removing canceled TD starting at 0x%llx (dma).", 683 (unsigned long long)xhci_trb_virt_to_dma( 684 cur_td->start_seg, cur_td->first_trb)); 685 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 686 if (!ep_ring) { 687 /* This shouldn't happen unless a driver is mucking 688 * with the stream ID after submission. This will 689 * leave the TD on the hardware ring, and the hardware 690 * will try to execute it, and may access a buffer 691 * that has already been freed. In the best case, the 692 * hardware will execute it, and the event handler will 693 * ignore the completion event for that TD, since it was 694 * removed from the td_list for that endpoint. In 695 * short, don't muck with the stream ID after 696 * submission. 697 */ 698 xhci_warn(xhci, "WARN Cancelled URB %p " 699 "has invalid stream ID %u.\n", 700 cur_td->urb, 701 cur_td->urb->stream_id); 702 goto remove_finished_td; 703 } 704 /* 705 * If we stopped on the TD we need to cancel, then we have to 706 * move the xHC endpoint ring dequeue pointer past this TD. 707 */ 708 if (cur_td == ep->stopped_td) 709 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, 710 cur_td->urb->stream_id, 711 cur_td, &deq_state); 712 else 713 td_to_noop(xhci, ep_ring, cur_td, false); 714 remove_finished_td: 715 /* 716 * The event handler won't see a completion for this TD anymore, 717 * so remove it from the endpoint ring's TD list. Keep it in 718 * the cancelled TD list for URB completion later. 719 */ 720 list_del_init(&cur_td->td_list); 721 } 722 last_unlinked_td = cur_td; 723 xhci_stop_watchdog_timer_in_irq(xhci, ep); 724 725 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ 726 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { 727 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, 728 ep->stopped_td->urb->stream_id, &deq_state); 729 xhci_ring_cmd_db(xhci); 730 } else { 731 /* Otherwise ring the doorbell(s) to restart queued transfers */ 732 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 733 } 734 735 ep->stopped_td = NULL; 736 737 /* 738 * Drop the lock and complete the URBs in the cancelled TD list. 739 * New TDs to be cancelled might be added to the end of the list before 740 * we can complete all the URBs for the TDs we already unlinked. 741 * So stop when we've completed the URB for the last TD we unlinked. 742 */ 743 do { 744 cur_td = list_entry(ep->cancelled_td_list.next, 745 struct xhci_td, cancelled_td_list); 746 list_del_init(&cur_td->cancelled_td_list); 747 748 /* Clean up the cancelled URB */ 749 /* Doesn't matter what we pass for status, since the core will 750 * just overwrite it (because the URB has been unlinked). 751 */ 752 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 753 if (ep_ring && cur_td->bounce_seg) 754 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); 755 xhci_giveback_urb_in_irq(xhci, cur_td, 0); 756 757 /* Stop processing the cancelled list if the watchdog timer is 758 * running. 759 */ 760 if (xhci->xhc_state & XHCI_STATE_DYING) 761 return; 762 } while (cur_td != last_unlinked_td); 763 764 /* Return to the event handler with xhci->lock re-acquired */ 765 } 766 767 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) 768 { 769 struct xhci_td *cur_td; 770 771 while (!list_empty(&ring->td_list)) { 772 cur_td = list_first_entry(&ring->td_list, 773 struct xhci_td, td_list); 774 list_del_init(&cur_td->td_list); 775 if (!list_empty(&cur_td->cancelled_td_list)) 776 list_del_init(&cur_td->cancelled_td_list); 777 778 if (cur_td->bounce_seg) 779 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); 780 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 781 } 782 } 783 784 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, 785 int slot_id, int ep_index) 786 { 787 struct xhci_td *cur_td; 788 struct xhci_virt_ep *ep; 789 struct xhci_ring *ring; 790 791 ep = &xhci->devs[slot_id]->eps[ep_index]; 792 if ((ep->ep_state & EP_HAS_STREAMS) || 793 (ep->ep_state & EP_GETTING_NO_STREAMS)) { 794 int stream_id; 795 796 for (stream_id = 0; stream_id < ep->stream_info->num_streams; 797 stream_id++) { 798 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 799 "Killing URBs for slot ID %u, ep index %u, stream %u", 800 slot_id, ep_index, stream_id + 1); 801 xhci_kill_ring_urbs(xhci, 802 ep->stream_info->stream_rings[stream_id]); 803 } 804 } else { 805 ring = ep->ring; 806 if (!ring) 807 return; 808 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 809 "Killing URBs for slot ID %u, ep index %u", 810 slot_id, ep_index); 811 xhci_kill_ring_urbs(xhci, ring); 812 } 813 while (!list_empty(&ep->cancelled_td_list)) { 814 cur_td = list_first_entry(&ep->cancelled_td_list, 815 struct xhci_td, cancelled_td_list); 816 list_del_init(&cur_td->cancelled_td_list); 817 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 818 } 819 } 820 821 /* Watchdog timer function for when a stop endpoint command fails to complete. 822 * In this case, we assume the host controller is broken or dying or dead. The 823 * host may still be completing some other events, so we have to be careful to 824 * let the event ring handler and the URB dequeueing/enqueueing functions know 825 * through xhci->state. 826 * 827 * The timer may also fire if the host takes a very long time to respond to the 828 * command, and the stop endpoint command completion handler cannot delete the 829 * timer before the timer function is called. Another endpoint cancellation may 830 * sneak in before the timer function can grab the lock, and that may queue 831 * another stop endpoint command and add the timer back. So we cannot use a 832 * simple flag to say whether there is a pending stop endpoint command for a 833 * particular endpoint. 834 * 835 * Instead we use a combination of that flag and a counter for the number of 836 * pending stop endpoint commands. If the timer is the tail end of the last 837 * stop endpoint command, and the endpoint's command is still pending, we assume 838 * the host is dying. 839 */ 840 void xhci_stop_endpoint_command_watchdog(unsigned long arg) 841 { 842 struct xhci_hcd *xhci; 843 struct xhci_virt_ep *ep; 844 int ret, i, j; 845 unsigned long flags; 846 847 ep = (struct xhci_virt_ep *) arg; 848 xhci = ep->xhci; 849 850 spin_lock_irqsave(&xhci->lock, flags); 851 852 ep->stop_cmds_pending--; 853 if (xhci->xhc_state & XHCI_STATE_REMOVING) { 854 spin_unlock_irqrestore(&xhci->lock, flags); 855 return; 856 } 857 if (xhci->xhc_state & XHCI_STATE_DYING) { 858 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 859 "Stop EP timer ran, but another timer marked " 860 "xHCI as DYING, exiting."); 861 spin_unlock_irqrestore(&xhci->lock, flags); 862 return; 863 } 864 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { 865 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 866 "Stop EP timer ran, but no command pending, " 867 "exiting."); 868 spin_unlock_irqrestore(&xhci->lock, flags); 869 return; 870 } 871 872 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); 873 xhci_warn(xhci, "Assuming host is dying, halting host.\n"); 874 /* Oops, HC is dead or dying or at least not responding to the stop 875 * endpoint command. 876 */ 877 xhci->xhc_state |= XHCI_STATE_DYING; 878 /* Disable interrupts from the host controller and start halting it */ 879 xhci_quiesce(xhci); 880 spin_unlock_irqrestore(&xhci->lock, flags); 881 882 ret = xhci_halt(xhci); 883 884 spin_lock_irqsave(&xhci->lock, flags); 885 if (ret < 0) { 886 /* This is bad; the host is not responding to commands and it's 887 * not allowing itself to be halted. At least interrupts are 888 * disabled. If we call usb_hc_died(), it will attempt to 889 * disconnect all device drivers under this host. Those 890 * disconnect() methods will wait for all URBs to be unlinked, 891 * so we must complete them. 892 */ 893 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); 894 xhci_warn(xhci, "Completing active URBs anyway.\n"); 895 /* We could turn all TDs on the rings to no-ops. This won't 896 * help if the host has cached part of the ring, and is slow if 897 * we want to preserve the cycle bit. Skip it and hope the host 898 * doesn't touch the memory. 899 */ 900 } 901 for (i = 0; i < MAX_HC_SLOTS; i++) { 902 if (!xhci->devs[i]) 903 continue; 904 for (j = 0; j < 31; j++) 905 xhci_kill_endpoint_urbs(xhci, i, j); 906 } 907 spin_unlock_irqrestore(&xhci->lock, flags); 908 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 909 "Calling usb_hc_died()"); 910 usb_hc_died(xhci_to_hcd(xhci)); 911 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 912 "xHCI host controller is dead."); 913 } 914 915 916 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 917 struct xhci_virt_device *dev, 918 struct xhci_ring *ep_ring, 919 unsigned int ep_index) 920 { 921 union xhci_trb *dequeue_temp; 922 int num_trbs_free_temp; 923 bool revert = false; 924 925 num_trbs_free_temp = ep_ring->num_trbs_free; 926 dequeue_temp = ep_ring->dequeue; 927 928 /* If we get two back-to-back stalls, and the first stalled transfer 929 * ends just before a link TRB, the dequeue pointer will be left on 930 * the link TRB by the code in the while loop. So we have to update 931 * the dequeue pointer one segment further, or we'll jump off 932 * the segment into la-la-land. 933 */ 934 if (trb_is_link(ep_ring->dequeue)) { 935 ep_ring->deq_seg = ep_ring->deq_seg->next; 936 ep_ring->dequeue = ep_ring->deq_seg->trbs; 937 } 938 939 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 940 /* We have more usable TRBs */ 941 ep_ring->num_trbs_free++; 942 ep_ring->dequeue++; 943 if (trb_is_link(ep_ring->dequeue)) { 944 if (ep_ring->dequeue == 945 dev->eps[ep_index].queued_deq_ptr) 946 break; 947 ep_ring->deq_seg = ep_ring->deq_seg->next; 948 ep_ring->dequeue = ep_ring->deq_seg->trbs; 949 } 950 if (ep_ring->dequeue == dequeue_temp) { 951 revert = true; 952 break; 953 } 954 } 955 956 if (revert) { 957 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 958 ep_ring->num_trbs_free = num_trbs_free_temp; 959 } 960 } 961 962 /* 963 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 964 * we need to clear the set deq pending flag in the endpoint ring state, so that 965 * the TD queueing code can ring the doorbell again. We also need to ring the 966 * endpoint doorbell to restart the ring, but only if there aren't more 967 * cancellations pending. 968 */ 969 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, 970 union xhci_trb *trb, u32 cmd_comp_code) 971 { 972 unsigned int ep_index; 973 unsigned int stream_id; 974 struct xhci_ring *ep_ring; 975 struct xhci_virt_device *dev; 976 struct xhci_virt_ep *ep; 977 struct xhci_ep_ctx *ep_ctx; 978 struct xhci_slot_ctx *slot_ctx; 979 980 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 981 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 982 dev = xhci->devs[slot_id]; 983 ep = &dev->eps[ep_index]; 984 985 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); 986 if (!ep_ring) { 987 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", 988 stream_id); 989 /* XXX: Harmless??? */ 990 goto cleanup; 991 } 992 993 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 994 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); 995 996 if (cmd_comp_code != COMP_SUCCESS) { 997 unsigned int ep_state; 998 unsigned int slot_state; 999 1000 switch (cmd_comp_code) { 1001 case COMP_TRB_ERR: 1002 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); 1003 break; 1004 case COMP_CTX_STATE: 1005 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); 1006 ep_state = le32_to_cpu(ep_ctx->ep_info); 1007 ep_state &= EP_STATE_MASK; 1008 slot_state = le32_to_cpu(slot_ctx->dev_state); 1009 slot_state = GET_SLOT_STATE(slot_state); 1010 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1011 "Slot state = %u, EP state = %u", 1012 slot_state, ep_state); 1013 break; 1014 case COMP_EBADSLT: 1015 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", 1016 slot_id); 1017 break; 1018 default: 1019 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", 1020 cmd_comp_code); 1021 break; 1022 } 1023 /* OK what do we do now? The endpoint state is hosed, and we 1024 * should never get to this point if the synchronization between 1025 * queueing, and endpoint state are correct. This might happen 1026 * if the device gets disconnected after we've finished 1027 * cancelling URBs, which might not be an error... 1028 */ 1029 } else { 1030 u64 deq; 1031 /* 4.6.10 deq ptr is written to the stream ctx for streams */ 1032 if (ep->ep_state & EP_HAS_STREAMS) { 1033 struct xhci_stream_ctx *ctx = 1034 &ep->stream_info->stream_ctx_array[stream_id]; 1035 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; 1036 } else { 1037 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; 1038 } 1039 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1040 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); 1041 if (xhci_trb_virt_to_dma(ep->queued_deq_seg, 1042 ep->queued_deq_ptr) == deq) { 1043 /* Update the ring's dequeue segment and dequeue pointer 1044 * to reflect the new position. 1045 */ 1046 update_ring_for_set_deq_completion(xhci, dev, 1047 ep_ring, ep_index); 1048 } else { 1049 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); 1050 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1051 ep->queued_deq_seg, ep->queued_deq_ptr); 1052 } 1053 } 1054 1055 cleanup: 1056 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 1057 dev->eps[ep_index].queued_deq_seg = NULL; 1058 dev->eps[ep_index].queued_deq_ptr = NULL; 1059 /* Restart any rings with pending URBs */ 1060 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1061 } 1062 1063 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, 1064 union xhci_trb *trb, u32 cmd_comp_code) 1065 { 1066 unsigned int ep_index; 1067 1068 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1069 /* This command will only fail if the endpoint wasn't halted, 1070 * but we don't care. 1071 */ 1072 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, 1073 "Ignoring reset ep completion code of %u", cmd_comp_code); 1074 1075 /* HW with the reset endpoint quirk needs to have a configure endpoint 1076 * command complete before the endpoint can be used. Queue that here 1077 * because the HW can't handle two commands being queued in a row. 1078 */ 1079 if (xhci->quirks & XHCI_RESET_EP_QUIRK) { 1080 struct xhci_command *command; 1081 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 1082 if (!command) { 1083 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); 1084 return; 1085 } 1086 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1087 "Queueing configure endpoint command"); 1088 xhci_queue_configure_endpoint(xhci, command, 1089 xhci->devs[slot_id]->in_ctx->dma, slot_id, 1090 false); 1091 xhci_ring_cmd_db(xhci); 1092 } else { 1093 /* Clear our internal halted state */ 1094 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; 1095 } 1096 } 1097 1098 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, 1099 u32 cmd_comp_code) 1100 { 1101 if (cmd_comp_code == COMP_SUCCESS) 1102 xhci->slot_id = slot_id; 1103 else 1104 xhci->slot_id = 0; 1105 } 1106 1107 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) 1108 { 1109 struct xhci_virt_device *virt_dev; 1110 1111 virt_dev = xhci->devs[slot_id]; 1112 if (!virt_dev) 1113 return; 1114 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1115 /* Delete default control endpoint resources */ 1116 xhci_free_device_endpoint_resources(xhci, virt_dev, true); 1117 xhci_free_virt_device(xhci, slot_id); 1118 } 1119 1120 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, 1121 struct xhci_event_cmd *event, u32 cmd_comp_code) 1122 { 1123 struct xhci_virt_device *virt_dev; 1124 struct xhci_input_control_ctx *ctrl_ctx; 1125 unsigned int ep_index; 1126 unsigned int ep_state; 1127 u32 add_flags, drop_flags; 1128 1129 /* 1130 * Configure endpoint commands can come from the USB core 1131 * configuration or alt setting changes, or because the HW 1132 * needed an extra configure endpoint command after a reset 1133 * endpoint command or streams were being configured. 1134 * If the command was for a halted endpoint, the xHCI driver 1135 * is not waiting on the configure endpoint command. 1136 */ 1137 virt_dev = xhci->devs[slot_id]; 1138 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 1139 if (!ctrl_ctx) { 1140 xhci_warn(xhci, "Could not get input context, bad type.\n"); 1141 return; 1142 } 1143 1144 add_flags = le32_to_cpu(ctrl_ctx->add_flags); 1145 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); 1146 /* Input ctx add_flags are the endpoint index plus one */ 1147 ep_index = xhci_last_valid_endpoint(add_flags) - 1; 1148 1149 /* A usb_set_interface() call directly after clearing a halted 1150 * condition may race on this quirky hardware. Not worth 1151 * worrying about, since this is prototype hardware. Not sure 1152 * if this will work for streams, but streams support was 1153 * untested on this prototype. 1154 */ 1155 if (xhci->quirks & XHCI_RESET_EP_QUIRK && 1156 ep_index != (unsigned int) -1 && 1157 add_flags - SLOT_FLAG == drop_flags) { 1158 ep_state = virt_dev->eps[ep_index].ep_state; 1159 if (!(ep_state & EP_HALTED)) 1160 return; 1161 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1162 "Completed config ep cmd - " 1163 "last ep index = %d, state = %d", 1164 ep_index, ep_state); 1165 /* Clear internal halted state and restart ring(s) */ 1166 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; 1167 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1168 return; 1169 } 1170 return; 1171 } 1172 1173 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, 1174 struct xhci_event_cmd *event) 1175 { 1176 xhci_dbg(xhci, "Completed reset device command.\n"); 1177 if (!xhci->devs[slot_id]) 1178 xhci_warn(xhci, "Reset device command completion " 1179 "for disabled slot %u\n", slot_id); 1180 } 1181 1182 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, 1183 struct xhci_event_cmd *event) 1184 { 1185 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1186 xhci->error_bitmask |= 1 << 6; 1187 return; 1188 } 1189 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1190 "NEC firmware version %2x.%02x", 1191 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1192 NEC_FW_MINOR(le32_to_cpu(event->status))); 1193 } 1194 1195 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) 1196 { 1197 list_del(&cmd->cmd_list); 1198 1199 if (cmd->completion) { 1200 cmd->status = status; 1201 complete(cmd->completion); 1202 } else { 1203 kfree(cmd); 1204 } 1205 } 1206 1207 void xhci_cleanup_command_queue(struct xhci_hcd *xhci) 1208 { 1209 struct xhci_command *cur_cmd, *tmp_cmd; 1210 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) 1211 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); 1212 } 1213 1214 /* 1215 * Turn all commands on command ring with status set to "aborted" to no-op trbs. 1216 * If there are other commands waiting then restart the ring and kick the timer. 1217 * This must be called with command ring stopped and xhci->lock held. 1218 */ 1219 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, 1220 struct xhci_command *cur_cmd) 1221 { 1222 struct xhci_command *i_cmd, *tmp_cmd; 1223 u32 cycle_state; 1224 1225 /* Turn all aborted commands in list to no-ops, then restart */ 1226 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list, 1227 cmd_list) { 1228 1229 if (i_cmd->status != COMP_CMD_ABORT) 1230 continue; 1231 1232 i_cmd->status = COMP_CMD_STOP; 1233 1234 xhci_dbg(xhci, "Turn aborted command %p to no-op\n", 1235 i_cmd->command_trb); 1236 /* get cycle state from the original cmd trb */ 1237 cycle_state = le32_to_cpu( 1238 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; 1239 /* modify the command trb to no-op command */ 1240 i_cmd->command_trb->generic.field[0] = 0; 1241 i_cmd->command_trb->generic.field[1] = 0; 1242 i_cmd->command_trb->generic.field[2] = 0; 1243 i_cmd->command_trb->generic.field[3] = cpu_to_le32( 1244 TRB_TYPE(TRB_CMD_NOOP) | cycle_state); 1245 1246 /* 1247 * caller waiting for completion is called when command 1248 * completion event is received for these no-op commands 1249 */ 1250 } 1251 1252 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 1253 1254 /* ring command ring doorbell to restart the command ring */ 1255 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && 1256 !(xhci->xhc_state & XHCI_STATE_DYING)) { 1257 xhci->current_cmd = cur_cmd; 1258 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); 1259 xhci_ring_cmd_db(xhci); 1260 } 1261 return; 1262 } 1263 1264 1265 void xhci_handle_command_timeout(unsigned long data) 1266 { 1267 struct xhci_hcd *xhci; 1268 int ret; 1269 unsigned long flags; 1270 u64 hw_ring_state; 1271 bool second_timeout = false; 1272 xhci = (struct xhci_hcd *) data; 1273 1274 /* mark this command to be cancelled */ 1275 spin_lock_irqsave(&xhci->lock, flags); 1276 if (xhci->current_cmd) { 1277 if (xhci->current_cmd->status == COMP_CMD_ABORT) 1278 second_timeout = true; 1279 xhci->current_cmd->status = COMP_CMD_ABORT; 1280 } 1281 1282 /* Make sure command ring is running before aborting it */ 1283 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1284 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && 1285 (hw_ring_state & CMD_RING_RUNNING)) { 1286 spin_unlock_irqrestore(&xhci->lock, flags); 1287 xhci_dbg(xhci, "Command timeout\n"); 1288 ret = xhci_abort_cmd_ring(xhci); 1289 if (unlikely(ret == -ESHUTDOWN)) { 1290 xhci_err(xhci, "Abort command ring failed\n"); 1291 xhci_cleanup_command_queue(xhci); 1292 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); 1293 xhci_dbg(xhci, "xHCI host controller is dead.\n"); 1294 } 1295 return; 1296 } 1297 1298 /* command ring failed to restart, or host removed. Bail out */ 1299 if (second_timeout || xhci->xhc_state & XHCI_STATE_REMOVING) { 1300 spin_unlock_irqrestore(&xhci->lock, flags); 1301 xhci_dbg(xhci, "command timed out twice, ring start fail?\n"); 1302 xhci_cleanup_command_queue(xhci); 1303 return; 1304 } 1305 1306 /* command timeout on stopped ring, ring can't be aborted */ 1307 xhci_dbg(xhci, "Command timeout on stopped ring\n"); 1308 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); 1309 spin_unlock_irqrestore(&xhci->lock, flags); 1310 return; 1311 } 1312 1313 static void handle_cmd_completion(struct xhci_hcd *xhci, 1314 struct xhci_event_cmd *event) 1315 { 1316 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1317 u64 cmd_dma; 1318 dma_addr_t cmd_dequeue_dma; 1319 u32 cmd_comp_code; 1320 union xhci_trb *cmd_trb; 1321 struct xhci_command *cmd; 1322 u32 cmd_type; 1323 1324 cmd_dma = le64_to_cpu(event->cmd_trb); 1325 cmd_trb = xhci->cmd_ring->dequeue; 1326 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1327 cmd_trb); 1328 /* Is the command ring deq ptr out of sync with the deq seg ptr? */ 1329 if (cmd_dequeue_dma == 0) { 1330 xhci->error_bitmask |= 1 << 4; 1331 return; 1332 } 1333 /* Does the DMA address match our internal dequeue pointer address? */ 1334 if (cmd_dma != (u64) cmd_dequeue_dma) { 1335 xhci->error_bitmask |= 1 << 5; 1336 return; 1337 } 1338 1339 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); 1340 1341 del_timer(&xhci->cmd_timer); 1342 1343 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); 1344 1345 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); 1346 1347 /* If CMD ring stopped we own the trbs between enqueue and dequeue */ 1348 if (cmd_comp_code == COMP_CMD_STOP) { 1349 xhci_handle_stopped_cmd_ring(xhci, cmd); 1350 return; 1351 } 1352 1353 if (cmd->command_trb != xhci->cmd_ring->dequeue) { 1354 xhci_err(xhci, 1355 "Command completion event does not match command\n"); 1356 return; 1357 } 1358 1359 /* 1360 * Host aborted the command ring, check if the current command was 1361 * supposed to be aborted, otherwise continue normally. 1362 * The command ring is stopped now, but the xHC will issue a Command 1363 * Ring Stopped event which will cause us to restart it. 1364 */ 1365 if (cmd_comp_code == COMP_CMD_ABORT) { 1366 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1367 if (cmd->status == COMP_CMD_ABORT) 1368 goto event_handled; 1369 } 1370 1371 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); 1372 switch (cmd_type) { 1373 case TRB_ENABLE_SLOT: 1374 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); 1375 break; 1376 case TRB_DISABLE_SLOT: 1377 xhci_handle_cmd_disable_slot(xhci, slot_id); 1378 break; 1379 case TRB_CONFIG_EP: 1380 if (!cmd->completion) 1381 xhci_handle_cmd_config_ep(xhci, slot_id, event, 1382 cmd_comp_code); 1383 break; 1384 case TRB_EVAL_CONTEXT: 1385 break; 1386 case TRB_ADDR_DEV: 1387 break; 1388 case TRB_STOP_RING: 1389 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1390 le32_to_cpu(cmd_trb->generic.field[3]))); 1391 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); 1392 break; 1393 case TRB_SET_DEQ: 1394 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1395 le32_to_cpu(cmd_trb->generic.field[3]))); 1396 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); 1397 break; 1398 case TRB_CMD_NOOP: 1399 /* Is this an aborted command turned to NO-OP? */ 1400 if (cmd->status == COMP_CMD_STOP) 1401 cmd_comp_code = COMP_CMD_STOP; 1402 break; 1403 case TRB_RESET_EP: 1404 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1405 le32_to_cpu(cmd_trb->generic.field[3]))); 1406 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); 1407 break; 1408 case TRB_RESET_DEV: 1409 /* SLOT_ID field in reset device cmd completion event TRB is 0. 1410 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) 1411 */ 1412 slot_id = TRB_TO_SLOT_ID( 1413 le32_to_cpu(cmd_trb->generic.field[3])); 1414 xhci_handle_cmd_reset_dev(xhci, slot_id, event); 1415 break; 1416 case TRB_NEC_GET_FW: 1417 xhci_handle_cmd_nec_get_fw(xhci, event); 1418 break; 1419 default: 1420 /* Skip over unknown commands on the event ring */ 1421 xhci->error_bitmask |= 1 << 6; 1422 break; 1423 } 1424 1425 /* restart timer if this wasn't the last command */ 1426 if (cmd->cmd_list.next != &xhci->cmd_list) { 1427 xhci->current_cmd = list_entry(cmd->cmd_list.next, 1428 struct xhci_command, cmd_list); 1429 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); 1430 } 1431 1432 event_handled: 1433 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); 1434 1435 inc_deq(xhci, xhci->cmd_ring); 1436 } 1437 1438 static void handle_vendor_event(struct xhci_hcd *xhci, 1439 union xhci_trb *event) 1440 { 1441 u32 trb_type; 1442 1443 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); 1444 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1445 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1446 handle_cmd_completion(xhci, &event->event_cmd); 1447 } 1448 1449 /* @port_id: the one-based port ID from the hardware (indexed from array of all 1450 * port registers -- USB 3.0 and USB 2.0). 1451 * 1452 * Returns a zero-based port number, which is suitable for indexing into each of 1453 * the split roothubs' port arrays and bus state arrays. 1454 * Add one to it in order to call xhci_find_slot_id_by_port. 1455 */ 1456 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, 1457 struct xhci_hcd *xhci, u32 port_id) 1458 { 1459 unsigned int i; 1460 unsigned int num_similar_speed_ports = 0; 1461 1462 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], 1463 * and usb2_ports are 0-based indexes. Count the number of similar 1464 * speed ports, up to 1 port before this port. 1465 */ 1466 for (i = 0; i < (port_id - 1); i++) { 1467 u8 port_speed = xhci->port_array[i]; 1468 1469 /* 1470 * Skip ports that don't have known speeds, or have duplicate 1471 * Extended Capabilities port speed entries. 1472 */ 1473 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) 1474 continue; 1475 1476 /* 1477 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and 1478 * 1.1 ports are under the USB 2.0 hub. If the port speed 1479 * matches the device speed, it's a similar speed port. 1480 */ 1481 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) 1482 num_similar_speed_ports++; 1483 } 1484 return num_similar_speed_ports; 1485 } 1486 1487 static void handle_device_notification(struct xhci_hcd *xhci, 1488 union xhci_trb *event) 1489 { 1490 u32 slot_id; 1491 struct usb_device *udev; 1492 1493 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); 1494 if (!xhci->devs[slot_id]) { 1495 xhci_warn(xhci, "Device Notification event for " 1496 "unused slot %u\n", slot_id); 1497 return; 1498 } 1499 1500 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1501 slot_id); 1502 udev = xhci->devs[slot_id]->udev; 1503 if (udev && udev->parent) 1504 usb_wakeup_notification(udev->parent, udev->portnum); 1505 } 1506 1507 static void handle_port_status(struct xhci_hcd *xhci, 1508 union xhci_trb *event) 1509 { 1510 struct usb_hcd *hcd; 1511 u32 port_id; 1512 u32 temp, temp1; 1513 int max_ports; 1514 int slot_id; 1515 unsigned int faked_port_index; 1516 u8 major_revision; 1517 struct xhci_bus_state *bus_state; 1518 __le32 __iomem **port_array; 1519 bool bogus_port_status = false; 1520 1521 /* Port status change events always have a successful completion code */ 1522 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { 1523 xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); 1524 xhci->error_bitmask |= 1 << 8; 1525 } 1526 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1527 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); 1528 1529 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1530 if ((port_id <= 0) || (port_id > max_ports)) { 1531 xhci_warn(xhci, "Invalid port id %d\n", port_id); 1532 inc_deq(xhci, xhci->event_ring); 1533 return; 1534 } 1535 1536 /* Figure out which usb_hcd this port is attached to: 1537 * is it a USB 3.0 port or a USB 2.0/1.1 port? 1538 */ 1539 major_revision = xhci->port_array[port_id - 1]; 1540 1541 /* Find the right roothub. */ 1542 hcd = xhci_to_hcd(xhci); 1543 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) 1544 hcd = xhci->shared_hcd; 1545 1546 if (major_revision == 0) { 1547 xhci_warn(xhci, "Event for port %u not in " 1548 "Extended Capabilities, ignoring.\n", 1549 port_id); 1550 bogus_port_status = true; 1551 goto cleanup; 1552 } 1553 if (major_revision == DUPLICATE_ENTRY) { 1554 xhci_warn(xhci, "Event for port %u duplicated in" 1555 "Extended Capabilities, ignoring.\n", 1556 port_id); 1557 bogus_port_status = true; 1558 goto cleanup; 1559 } 1560 1561 /* 1562 * Hardware port IDs reported by a Port Status Change Event include USB 1563 * 3.0 and USB 2.0 ports. We want to check if the port has reported a 1564 * resume event, but we first need to translate the hardware port ID 1565 * into the index into the ports on the correct split roothub, and the 1566 * correct bus_state structure. 1567 */ 1568 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1569 if (hcd->speed >= HCD_USB3) 1570 port_array = xhci->usb3_ports; 1571 else 1572 port_array = xhci->usb2_ports; 1573 /* Find the faked port hub number */ 1574 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, 1575 port_id); 1576 1577 temp = readl(port_array[faked_port_index]); 1578 if (hcd->state == HC_STATE_SUSPENDED) { 1579 xhci_dbg(xhci, "resume root hub\n"); 1580 usb_hcd_resume_root_hub(hcd); 1581 } 1582 1583 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) 1584 bus_state->port_remote_wakeup &= ~(1 << faked_port_index); 1585 1586 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { 1587 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1588 1589 temp1 = readl(&xhci->op_regs->command); 1590 if (!(temp1 & CMD_RUN)) { 1591 xhci_warn(xhci, "xHC is not running.\n"); 1592 goto cleanup; 1593 } 1594 1595 if (DEV_SUPERSPEED_ANY(temp)) { 1596 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1597 /* Set a flag to say the port signaled remote wakeup, 1598 * so we can tell the difference between the end of 1599 * device and host initiated resume. 1600 */ 1601 bus_state->port_remote_wakeup |= 1 << faked_port_index; 1602 xhci_test_and_clear_bit(xhci, port_array, 1603 faked_port_index, PORT_PLC); 1604 xhci_set_link_state(xhci, port_array, faked_port_index, 1605 XDEV_U0); 1606 /* Need to wait until the next link state change 1607 * indicates the device is actually in U0. 1608 */ 1609 bogus_port_status = true; 1610 goto cleanup; 1611 } else if (!test_bit(faked_port_index, 1612 &bus_state->resuming_ports)) { 1613 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1614 bus_state->resume_done[faked_port_index] = jiffies + 1615 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1616 set_bit(faked_port_index, &bus_state->resuming_ports); 1617 mod_timer(&hcd->rh_timer, 1618 bus_state->resume_done[faked_port_index]); 1619 /* Do the rest in GetPortStatus */ 1620 } 1621 } 1622 1623 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && 1624 DEV_SUPERSPEED_ANY(temp)) { 1625 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1626 /* We've just brought the device into U0 through either the 1627 * Resume state after a device remote wakeup, or through the 1628 * U3Exit state after a host-initiated resume. If it's a device 1629 * initiated remote wake, don't pass up the link state change, 1630 * so the roothub behavior is consistent with external 1631 * USB 3.0 hub behavior. 1632 */ 1633 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1634 faked_port_index + 1); 1635 if (slot_id && xhci->devs[slot_id]) 1636 xhci_ring_device(xhci, slot_id); 1637 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { 1638 bus_state->port_remote_wakeup &= 1639 ~(1 << faked_port_index); 1640 xhci_test_and_clear_bit(xhci, port_array, 1641 faked_port_index, PORT_PLC); 1642 usb_wakeup_notification(hcd->self.root_hub, 1643 faked_port_index + 1); 1644 bogus_port_status = true; 1645 goto cleanup; 1646 } 1647 } 1648 1649 /* 1650 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or 1651 * RExit to a disconnect state). If so, let the the driver know it's 1652 * out of the RExit state. 1653 */ 1654 if (!DEV_SUPERSPEED_ANY(temp) && 1655 test_and_clear_bit(faked_port_index, 1656 &bus_state->rexit_ports)) { 1657 complete(&bus_state->rexit_done[faked_port_index]); 1658 bogus_port_status = true; 1659 goto cleanup; 1660 } 1661 1662 if (hcd->speed < HCD_USB3) 1663 xhci_test_and_clear_bit(xhci, port_array, faked_port_index, 1664 PORT_PLC); 1665 1666 cleanup: 1667 /* Update event ring dequeue pointer before dropping the lock */ 1668 inc_deq(xhci, xhci->event_ring); 1669 1670 /* Don't make the USB core poll the roothub if we got a bad port status 1671 * change event. Besides, at that point we can't tell which roothub 1672 * (USB 2.0 or USB 3.0) to kick. 1673 */ 1674 if (bogus_port_status) 1675 return; 1676 1677 /* 1678 * xHCI port-status-change events occur when the "or" of all the 1679 * status-change bits in the portsc register changes from 0 to 1. 1680 * New status changes won't cause an event if any other change 1681 * bits are still set. When an event occurs, switch over to 1682 * polling to avoid losing status changes. 1683 */ 1684 xhci_dbg(xhci, "%s: starting port polling.\n", __func__); 1685 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1686 spin_unlock(&xhci->lock); 1687 /* Pass this up to the core */ 1688 usb_hcd_poll_rh_status(hcd); 1689 spin_lock(&xhci->lock); 1690 } 1691 1692 /* 1693 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 1694 * at end_trb, which may be in another segment. If the suspect DMA address is a 1695 * TRB in this TD, this function returns that TRB's segment. Otherwise it 1696 * returns 0. 1697 */ 1698 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1699 struct xhci_segment *start_seg, 1700 union xhci_trb *start_trb, 1701 union xhci_trb *end_trb, 1702 dma_addr_t suspect_dma, 1703 bool debug) 1704 { 1705 dma_addr_t start_dma; 1706 dma_addr_t end_seg_dma; 1707 dma_addr_t end_trb_dma; 1708 struct xhci_segment *cur_seg; 1709 1710 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 1711 cur_seg = start_seg; 1712 1713 do { 1714 if (start_dma == 0) 1715 return NULL; 1716 /* We may get an event for a Link TRB in the middle of a TD */ 1717 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 1718 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 1719 /* If the end TRB isn't in this segment, this is set to 0 */ 1720 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 1721 1722 if (debug) 1723 xhci_warn(xhci, 1724 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", 1725 (unsigned long long)suspect_dma, 1726 (unsigned long long)start_dma, 1727 (unsigned long long)end_trb_dma, 1728 (unsigned long long)cur_seg->dma, 1729 (unsigned long long)end_seg_dma); 1730 1731 if (end_trb_dma > 0) { 1732 /* The end TRB is in this segment, so suspect should be here */ 1733 if (start_dma <= end_trb_dma) { 1734 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 1735 return cur_seg; 1736 } else { 1737 /* Case for one segment with 1738 * a TD wrapped around to the top 1739 */ 1740 if ((suspect_dma >= start_dma && 1741 suspect_dma <= end_seg_dma) || 1742 (suspect_dma >= cur_seg->dma && 1743 suspect_dma <= end_trb_dma)) 1744 return cur_seg; 1745 } 1746 return NULL; 1747 } else { 1748 /* Might still be somewhere in this segment */ 1749 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 1750 return cur_seg; 1751 } 1752 cur_seg = cur_seg->next; 1753 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 1754 } while (cur_seg != start_seg); 1755 1756 return NULL; 1757 } 1758 1759 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, 1760 unsigned int slot_id, unsigned int ep_index, 1761 unsigned int stream_id, 1762 struct xhci_td *td, union xhci_trb *event_trb) 1763 { 1764 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 1765 struct xhci_command *command; 1766 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 1767 if (!command) 1768 return; 1769 1770 ep->ep_state |= EP_HALTED; 1771 ep->stopped_stream = stream_id; 1772 1773 xhci_queue_reset_ep(xhci, command, slot_id, ep_index); 1774 xhci_cleanup_stalled_ring(xhci, ep_index, td); 1775 1776 ep->stopped_stream = 0; 1777 1778 xhci_ring_cmd_db(xhci); 1779 } 1780 1781 /* Check if an error has halted the endpoint ring. The class driver will 1782 * cleanup the halt for a non-default control endpoint if we indicate a stall. 1783 * However, a babble and other errors also halt the endpoint ring, and the class 1784 * driver won't clear the halt in that case, so we need to issue a Set Transfer 1785 * Ring Dequeue Pointer command manually. 1786 */ 1787 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 1788 struct xhci_ep_ctx *ep_ctx, 1789 unsigned int trb_comp_code) 1790 { 1791 /* TRB completion codes that may require a manual halt cleanup */ 1792 if (trb_comp_code == COMP_TX_ERR || 1793 trb_comp_code == COMP_BABBLE || 1794 trb_comp_code == COMP_SPLIT_ERR) 1795 /* The 0.95 spec says a babbling control endpoint 1796 * is not halted. The 0.96 spec says it is. Some HW 1797 * claims to be 0.95 compliant, but it halts the control 1798 * endpoint anyway. Check if a babble halted the 1799 * endpoint. 1800 */ 1801 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == 1802 cpu_to_le32(EP_STATE_HALTED)) 1803 return 1; 1804 1805 return 0; 1806 } 1807 1808 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 1809 { 1810 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 1811 /* Vendor defined "informational" completion code, 1812 * treat as not-an-error. 1813 */ 1814 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 1815 trb_comp_code); 1816 xhci_dbg(xhci, "Treating code as success.\n"); 1817 return 1; 1818 } 1819 return 0; 1820 } 1821 1822 /* 1823 * Finish the td processing, remove the td from td list; 1824 * Return 1 if the urb can be given back. 1825 */ 1826 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, 1827 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1828 struct xhci_virt_ep *ep, int *status, bool skip) 1829 { 1830 struct xhci_virt_device *xdev; 1831 struct xhci_ring *ep_ring; 1832 unsigned int slot_id; 1833 int ep_index; 1834 struct urb *urb = NULL; 1835 struct xhci_ep_ctx *ep_ctx; 1836 int ret = 0; 1837 struct urb_priv *urb_priv; 1838 u32 trb_comp_code; 1839 1840 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1841 xdev = xhci->devs[slot_id]; 1842 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1843 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1844 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1845 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1846 1847 if (skip) 1848 goto td_cleanup; 1849 1850 if (trb_comp_code == COMP_STOP_INVAL || 1851 trb_comp_code == COMP_STOP || 1852 trb_comp_code == COMP_STOP_SHORT) { 1853 /* The Endpoint Stop Command completion will take care of any 1854 * stopped TDs. A stopped TD may be restarted, so don't update 1855 * the ring dequeue pointer or take this TD off any lists yet. 1856 */ 1857 ep->stopped_td = td; 1858 return 0; 1859 } 1860 if (trb_comp_code == COMP_STALL || 1861 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 1862 trb_comp_code)) { 1863 /* Issue a reset endpoint command to clear the host side 1864 * halt, followed by a set dequeue command to move the 1865 * dequeue pointer past the TD. 1866 * The class driver clears the device side halt later. 1867 */ 1868 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 1869 ep_ring->stream_id, td, event_trb); 1870 } else { 1871 /* Update ring dequeue pointer */ 1872 while (ep_ring->dequeue != td->last_trb) 1873 inc_deq(xhci, ep_ring); 1874 inc_deq(xhci, ep_ring); 1875 } 1876 1877 td_cleanup: 1878 /* Clean up the endpoint's TD list */ 1879 urb = td->urb; 1880 urb_priv = urb->hcpriv; 1881 1882 /* if a bounce buffer was used to align this td then unmap it */ 1883 if (td->bounce_seg) 1884 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); 1885 1886 /* Do one last check of the actual transfer length. 1887 * If the host controller said we transferred more data than the buffer 1888 * length, urb->actual_length will be a very big number (since it's 1889 * unsigned). Play it safe and say we didn't transfer anything. 1890 */ 1891 if (urb->actual_length > urb->transfer_buffer_length) { 1892 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n", 1893 urb->transfer_buffer_length, 1894 urb->actual_length); 1895 urb->actual_length = 0; 1896 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1897 *status = -EREMOTEIO; 1898 else 1899 *status = 0; 1900 } 1901 list_del_init(&td->td_list); 1902 /* Was this TD slated to be cancelled but completed anyway? */ 1903 if (!list_empty(&td->cancelled_td_list)) 1904 list_del_init(&td->cancelled_td_list); 1905 1906 urb_priv->td_cnt++; 1907 /* Giveback the urb when all the tds are completed */ 1908 if (urb_priv->td_cnt == urb_priv->length) { 1909 ret = 1; 1910 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 1911 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 1912 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 1913 if (xhci->quirks & XHCI_AMD_PLL_FIX) 1914 usb_amd_quirk_pll_enable(); 1915 } 1916 } 1917 } 1918 1919 return ret; 1920 } 1921 1922 /* 1923 * Process control tds, update urb status and actual_length. 1924 */ 1925 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, 1926 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1927 struct xhci_virt_ep *ep, int *status) 1928 { 1929 struct xhci_virt_device *xdev; 1930 struct xhci_ring *ep_ring; 1931 unsigned int slot_id; 1932 int ep_index; 1933 struct xhci_ep_ctx *ep_ctx; 1934 u32 trb_comp_code; 1935 1936 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1937 xdev = xhci->devs[slot_id]; 1938 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1939 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1940 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1941 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1942 1943 switch (trb_comp_code) { 1944 case COMP_SUCCESS: 1945 if (event_trb == ep_ring->dequeue) { 1946 xhci_warn(xhci, "WARN: Success on ctrl setup TRB " 1947 "without IOC set??\n"); 1948 *status = -ESHUTDOWN; 1949 } else if (event_trb != td->last_trb) { 1950 xhci_warn(xhci, "WARN: Success on ctrl data TRB " 1951 "without IOC set??\n"); 1952 *status = -ESHUTDOWN; 1953 } else { 1954 *status = 0; 1955 } 1956 break; 1957 case COMP_SHORT_TX: 1958 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1959 *status = -EREMOTEIO; 1960 else 1961 *status = 0; 1962 break; 1963 case COMP_STOP_SHORT: 1964 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb) 1965 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); 1966 else 1967 td->urb->actual_length = 1968 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 1969 1970 return finish_td(xhci, td, event_trb, event, ep, status, false); 1971 case COMP_STOP: 1972 /* Did we stop at data stage? */ 1973 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb) 1974 td->urb->actual_length = 1975 td->urb->transfer_buffer_length - 1976 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 1977 /* fall through */ 1978 case COMP_STOP_INVAL: 1979 return finish_td(xhci, td, event_trb, event, ep, status, false); 1980 default: 1981 if (!xhci_requires_manual_halt_cleanup(xhci, 1982 ep_ctx, trb_comp_code)) 1983 break; 1984 xhci_dbg(xhci, "TRB error code %u, " 1985 "halted endpoint index = %u\n", 1986 trb_comp_code, ep_index); 1987 /* else fall through */ 1988 case COMP_STALL: 1989 /* Did we transfer part of the data (middle) phase? */ 1990 if (event_trb != ep_ring->dequeue && 1991 event_trb != td->last_trb) 1992 td->urb->actual_length = 1993 td->urb->transfer_buffer_length - 1994 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 1995 else if (!td->urb_length_set) 1996 td->urb->actual_length = 0; 1997 1998 return finish_td(xhci, td, event_trb, event, ep, status, false); 1999 } 2000 /* 2001 * Did we transfer any data, despite the errors that might have 2002 * happened? I.e. did we get past the setup stage? 2003 */ 2004 if (event_trb != ep_ring->dequeue) { 2005 /* The event was for the status stage */ 2006 if (event_trb == td->last_trb) { 2007 if (td->urb_length_set) { 2008 /* Don't overwrite a previously set error code 2009 */ 2010 if ((*status == -EINPROGRESS || *status == 0) && 2011 (td->urb->transfer_flags 2012 & URB_SHORT_NOT_OK)) 2013 /* Did we already see a short data 2014 * stage? */ 2015 *status = -EREMOTEIO; 2016 } else { 2017 td->urb->actual_length = 2018 td->urb->transfer_buffer_length; 2019 } 2020 } else { 2021 /* 2022 * Maybe the event was for the data stage? If so, update 2023 * already the actual_length of the URB and flag it as 2024 * set, so that it is not overwritten in the event for 2025 * the last TRB. 2026 */ 2027 td->urb_length_set = true; 2028 td->urb->actual_length = 2029 td->urb->transfer_buffer_length - 2030 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2031 xhci_dbg(xhci, "Waiting for status " 2032 "stage event\n"); 2033 return 0; 2034 } 2035 } 2036 2037 return finish_td(xhci, td, event_trb, event, ep, status, false); 2038 } 2039 2040 /* 2041 * Process isochronous tds, update urb packet status and actual_length. 2042 */ 2043 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2044 union xhci_trb *event_trb, struct xhci_transfer_event *event, 2045 struct xhci_virt_ep *ep, int *status) 2046 { 2047 struct xhci_ring *ep_ring; 2048 struct urb_priv *urb_priv; 2049 int idx; 2050 int len = 0; 2051 union xhci_trb *cur_trb; 2052 struct xhci_segment *cur_seg; 2053 struct usb_iso_packet_descriptor *frame; 2054 u32 trb_comp_code; 2055 bool skip_td = false; 2056 2057 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2058 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2059 urb_priv = td->urb->hcpriv; 2060 idx = urb_priv->td_cnt; 2061 frame = &td->urb->iso_frame_desc[idx]; 2062 2063 /* handle completion code */ 2064 switch (trb_comp_code) { 2065 case COMP_SUCCESS: 2066 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { 2067 frame->status = 0; 2068 break; 2069 } 2070 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) 2071 trb_comp_code = COMP_SHORT_TX; 2072 /* fallthrough */ 2073 case COMP_STOP_SHORT: 2074 case COMP_SHORT_TX: 2075 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2076 -EREMOTEIO : 0; 2077 break; 2078 case COMP_BW_OVER: 2079 frame->status = -ECOMM; 2080 skip_td = true; 2081 break; 2082 case COMP_BUFF_OVER: 2083 case COMP_BABBLE: 2084 frame->status = -EOVERFLOW; 2085 skip_td = true; 2086 break; 2087 case COMP_DEV_ERR: 2088 case COMP_STALL: 2089 frame->status = -EPROTO; 2090 skip_td = true; 2091 break; 2092 case COMP_TX_ERR: 2093 frame->status = -EPROTO; 2094 if (event_trb != td->last_trb) 2095 return 0; 2096 skip_td = true; 2097 break; 2098 case COMP_STOP: 2099 case COMP_STOP_INVAL: 2100 break; 2101 default: 2102 frame->status = -1; 2103 break; 2104 } 2105 2106 if (trb_comp_code == COMP_SUCCESS || skip_td) { 2107 frame->actual_length = frame->length; 2108 td->urb->actual_length += frame->length; 2109 } else if (trb_comp_code == COMP_STOP_SHORT) { 2110 frame->actual_length = 2111 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2112 td->urb->actual_length += frame->actual_length; 2113 } else { 2114 for (cur_trb = ep_ring->dequeue, 2115 cur_seg = ep_ring->deq_seg; cur_trb != event_trb; 2116 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 2117 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && 2118 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) 2119 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); 2120 } 2121 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - 2122 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2123 2124 if (trb_comp_code != COMP_STOP_INVAL) { 2125 frame->actual_length = len; 2126 td->urb->actual_length += len; 2127 } 2128 } 2129 2130 return finish_td(xhci, td, event_trb, event, ep, status, false); 2131 } 2132 2133 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2134 struct xhci_transfer_event *event, 2135 struct xhci_virt_ep *ep, int *status) 2136 { 2137 struct xhci_ring *ep_ring; 2138 struct urb_priv *urb_priv; 2139 struct usb_iso_packet_descriptor *frame; 2140 int idx; 2141 2142 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2143 urb_priv = td->urb->hcpriv; 2144 idx = urb_priv->td_cnt; 2145 frame = &td->urb->iso_frame_desc[idx]; 2146 2147 /* The transfer is partly done. */ 2148 frame->status = -EXDEV; 2149 2150 /* calc actual length */ 2151 frame->actual_length = 0; 2152 2153 /* Update ring dequeue pointer */ 2154 while (ep_ring->dequeue != td->last_trb) 2155 inc_deq(xhci, ep_ring); 2156 inc_deq(xhci, ep_ring); 2157 2158 return finish_td(xhci, td, NULL, event, ep, status, true); 2159 } 2160 2161 /* 2162 * Process bulk and interrupt tds, update urb status and actual_length. 2163 */ 2164 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, 2165 union xhci_trb *event_trb, struct xhci_transfer_event *event, 2166 struct xhci_virt_ep *ep, int *status) 2167 { 2168 struct xhci_ring *ep_ring; 2169 union xhci_trb *cur_trb; 2170 struct xhci_segment *cur_seg; 2171 u32 trb_comp_code; 2172 2173 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2174 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2175 2176 switch (trb_comp_code) { 2177 case COMP_SUCCESS: 2178 /* Double check that the HW transferred everything. */ 2179 if (event_trb != td->last_trb || 2180 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { 2181 xhci_warn(xhci, "WARN Successful completion " 2182 "on short TX\n"); 2183 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2184 *status = -EREMOTEIO; 2185 else 2186 *status = 0; 2187 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) 2188 trb_comp_code = COMP_SHORT_TX; 2189 } else { 2190 *status = 0; 2191 } 2192 break; 2193 case COMP_STOP_SHORT: 2194 case COMP_SHORT_TX: 2195 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2196 *status = -EREMOTEIO; 2197 else 2198 *status = 0; 2199 break; 2200 default: 2201 /* Others already handled above */ 2202 break; 2203 } 2204 if (trb_comp_code == COMP_SHORT_TX) 2205 xhci_dbg(xhci, "ep %#x - asked for %d bytes, " 2206 "%d bytes untransferred\n", 2207 td->urb->ep->desc.bEndpointAddress, 2208 td->urb->transfer_buffer_length, 2209 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); 2210 /* Stopped - short packet completion */ 2211 if (trb_comp_code == COMP_STOP_SHORT) { 2212 td->urb->actual_length = 2213 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2214 2215 if (td->urb->transfer_buffer_length < 2216 td->urb->actual_length) { 2217 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n", 2218 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); 2219 td->urb->actual_length = 0; 2220 /* status will be set by usb core for canceled urbs */ 2221 } 2222 /* Fast path - was this the last TRB in the TD for this URB? */ 2223 } else if (event_trb == td->last_trb) { 2224 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { 2225 td->urb->actual_length = 2226 td->urb->transfer_buffer_length - 2227 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2228 if (td->urb->transfer_buffer_length < 2229 td->urb->actual_length) { 2230 xhci_warn(xhci, "HC gave bad length " 2231 "of %d bytes left\n", 2232 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); 2233 td->urb->actual_length = 0; 2234 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2235 *status = -EREMOTEIO; 2236 else 2237 *status = 0; 2238 } 2239 /* Don't overwrite a previously set error code */ 2240 if (*status == -EINPROGRESS) { 2241 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2242 *status = -EREMOTEIO; 2243 else 2244 *status = 0; 2245 } 2246 } else { 2247 td->urb->actual_length = 2248 td->urb->transfer_buffer_length; 2249 /* Ignore a short packet completion if the 2250 * untransferred length was zero. 2251 */ 2252 if (*status == -EREMOTEIO) 2253 *status = 0; 2254 } 2255 } else { 2256 /* Slow path - walk the list, starting from the dequeue 2257 * pointer, to get the actual length transferred. 2258 */ 2259 td->urb->actual_length = 0; 2260 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; 2261 cur_trb != event_trb; 2262 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 2263 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && 2264 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) 2265 td->urb->actual_length += 2266 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); 2267 } 2268 /* If the ring didn't stop on a Link or No-op TRB, add 2269 * in the actual bytes transferred from the Normal TRB 2270 */ 2271 if (trb_comp_code != COMP_STOP_INVAL) 2272 td->urb->actual_length += 2273 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - 2274 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2275 } 2276 2277 return finish_td(xhci, td, event_trb, event, ep, status, false); 2278 } 2279 2280 /* 2281 * If this function returns an error condition, it means it got a Transfer 2282 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2283 * At this point, the host controller is probably hosed and should be reset. 2284 */ 2285 static int handle_tx_event(struct xhci_hcd *xhci, 2286 struct xhci_transfer_event *event) 2287 __releases(&xhci->lock) 2288 __acquires(&xhci->lock) 2289 { 2290 struct xhci_virt_device *xdev; 2291 struct xhci_virt_ep *ep; 2292 struct xhci_ring *ep_ring; 2293 unsigned int slot_id; 2294 int ep_index; 2295 struct xhci_td *td = NULL; 2296 dma_addr_t event_dma; 2297 struct xhci_segment *event_seg; 2298 union xhci_trb *event_trb; 2299 struct urb *urb = NULL; 2300 int status = -EINPROGRESS; 2301 struct urb_priv *urb_priv; 2302 struct xhci_ep_ctx *ep_ctx; 2303 struct list_head *tmp; 2304 u32 trb_comp_code; 2305 int ret = 0; 2306 int td_num = 0; 2307 bool handling_skipped_tds = false; 2308 2309 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2310 xdev = xhci->devs[slot_id]; 2311 if (!xdev) { 2312 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); 2313 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2314 (unsigned long long) xhci_trb_virt_to_dma( 2315 xhci->event_ring->deq_seg, 2316 xhci->event_ring->dequeue), 2317 lower_32_bits(le64_to_cpu(event->buffer)), 2318 upper_32_bits(le64_to_cpu(event->buffer)), 2319 le32_to_cpu(event->transfer_len), 2320 le32_to_cpu(event->flags)); 2321 xhci_dbg(xhci, "Event ring:\n"); 2322 xhci_debug_segment(xhci, xhci->event_ring->deq_seg); 2323 return -ENODEV; 2324 } 2325 2326 /* Endpoint ID is 1 based, our index is zero based */ 2327 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2328 ep = &xdev->eps[ep_index]; 2329 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2330 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2331 if (!ep_ring || 2332 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == 2333 EP_STATE_DISABLED) { 2334 xhci_err(xhci, "ERROR Transfer event for disabled endpoint " 2335 "or incorrect stream ring\n"); 2336 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2337 (unsigned long long) xhci_trb_virt_to_dma( 2338 xhci->event_ring->deq_seg, 2339 xhci->event_ring->dequeue), 2340 lower_32_bits(le64_to_cpu(event->buffer)), 2341 upper_32_bits(le64_to_cpu(event->buffer)), 2342 le32_to_cpu(event->transfer_len), 2343 le32_to_cpu(event->flags)); 2344 xhci_dbg(xhci, "Event ring:\n"); 2345 xhci_debug_segment(xhci, xhci->event_ring->deq_seg); 2346 return -ENODEV; 2347 } 2348 2349 /* Count current td numbers if ep->skip is set */ 2350 if (ep->skip) { 2351 list_for_each(tmp, &ep_ring->td_list) 2352 td_num++; 2353 } 2354 2355 event_dma = le64_to_cpu(event->buffer); 2356 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2357 /* Look for common error cases */ 2358 switch (trb_comp_code) { 2359 /* Skip codes that require special handling depending on 2360 * transfer type 2361 */ 2362 case COMP_SUCCESS: 2363 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) 2364 break; 2365 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2366 trb_comp_code = COMP_SHORT_TX; 2367 else 2368 xhci_warn_ratelimited(xhci, 2369 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); 2370 case COMP_SHORT_TX: 2371 break; 2372 case COMP_STOP: 2373 xhci_dbg(xhci, "Stopped on Transfer TRB\n"); 2374 break; 2375 case COMP_STOP_INVAL: 2376 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); 2377 break; 2378 case COMP_STOP_SHORT: 2379 xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); 2380 break; 2381 case COMP_STALL: 2382 xhci_dbg(xhci, "Stalled endpoint\n"); 2383 ep->ep_state |= EP_HALTED; 2384 status = -EPIPE; 2385 break; 2386 case COMP_TRB_ERR: 2387 xhci_warn(xhci, "WARN: TRB error on endpoint\n"); 2388 status = -EILSEQ; 2389 break; 2390 case COMP_SPLIT_ERR: 2391 case COMP_TX_ERR: 2392 xhci_dbg(xhci, "Transfer error on endpoint\n"); 2393 status = -EPROTO; 2394 break; 2395 case COMP_BABBLE: 2396 xhci_dbg(xhci, "Babble error on endpoint\n"); 2397 status = -EOVERFLOW; 2398 break; 2399 case COMP_DB_ERR: 2400 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); 2401 status = -ENOSR; 2402 break; 2403 case COMP_BW_OVER: 2404 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); 2405 break; 2406 case COMP_BUFF_OVER: 2407 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); 2408 break; 2409 case COMP_UNDERRUN: 2410 /* 2411 * When the Isoch ring is empty, the xHC will generate 2412 * a Ring Overrun Event for IN Isoch endpoint or Ring 2413 * Underrun Event for OUT Isoch endpoint. 2414 */ 2415 xhci_dbg(xhci, "underrun event on endpoint\n"); 2416 if (!list_empty(&ep_ring->td_list)) 2417 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 2418 "still with TDs queued?\n", 2419 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2420 ep_index); 2421 goto cleanup; 2422 case COMP_OVERRUN: 2423 xhci_dbg(xhci, "overrun event on endpoint\n"); 2424 if (!list_empty(&ep_ring->td_list)) 2425 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 2426 "still with TDs queued?\n", 2427 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2428 ep_index); 2429 goto cleanup; 2430 case COMP_DEV_ERR: 2431 xhci_warn(xhci, "WARN: detect an incompatible device"); 2432 status = -EPROTO; 2433 break; 2434 case COMP_MISSED_INT: 2435 /* 2436 * When encounter missed service error, one or more isoc tds 2437 * may be missed by xHC. 2438 * Set skip flag of the ep_ring; Complete the missed tds as 2439 * short transfer when process the ep_ring next time. 2440 */ 2441 ep->skip = true; 2442 xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); 2443 goto cleanup; 2444 case COMP_PING_ERR: 2445 ep->skip = true; 2446 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); 2447 goto cleanup; 2448 default: 2449 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2450 status = 0; 2451 break; 2452 } 2453 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", 2454 trb_comp_code); 2455 goto cleanup; 2456 } 2457 2458 do { 2459 /* This TRB should be in the TD at the head of this ring's 2460 * TD list. 2461 */ 2462 if (list_empty(&ep_ring->td_list)) { 2463 /* 2464 * A stopped endpoint may generate an extra completion 2465 * event if the device was suspended. Don't print 2466 * warnings. 2467 */ 2468 if (!(trb_comp_code == COMP_STOP || 2469 trb_comp_code == COMP_STOP_INVAL)) { 2470 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", 2471 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2472 ep_index); 2473 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", 2474 (le32_to_cpu(event->flags) & 2475 TRB_TYPE_BITMASK)>>10); 2476 xhci_print_trb_offsets(xhci, (union xhci_trb *) event); 2477 } 2478 if (ep->skip) { 2479 ep->skip = false; 2480 xhci_dbg(xhci, "td_list is empty while skip " 2481 "flag set. Clear skip flag.\n"); 2482 } 2483 ret = 0; 2484 goto cleanup; 2485 } 2486 2487 /* We've skipped all the TDs on the ep ring when ep->skip set */ 2488 if (ep->skip && td_num == 0) { 2489 ep->skip = false; 2490 xhci_dbg(xhci, "All tds on the ep_ring skipped. " 2491 "Clear skip flag.\n"); 2492 ret = 0; 2493 goto cleanup; 2494 } 2495 2496 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); 2497 if (ep->skip) 2498 td_num--; 2499 2500 /* Is this a TRB in the currently executing TD? */ 2501 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, 2502 td->last_trb, event_dma, false); 2503 2504 /* 2505 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE 2506 * is not in the current TD pointed by ep_ring->dequeue because 2507 * that the hardware dequeue pointer still at the previous TRB 2508 * of the current TD. The previous TRB maybe a Link TD or the 2509 * last TRB of the previous TD. The command completion handle 2510 * will take care the rest. 2511 */ 2512 if (!event_seg && (trb_comp_code == COMP_STOP || 2513 trb_comp_code == COMP_STOP_INVAL)) { 2514 ret = 0; 2515 goto cleanup; 2516 } 2517 2518 if (!event_seg) { 2519 if (!ep->skip || 2520 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2521 /* Some host controllers give a spurious 2522 * successful event after a short transfer. 2523 * Ignore it. 2524 */ 2525 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2526 ep_ring->last_td_was_short) { 2527 ep_ring->last_td_was_short = false; 2528 ret = 0; 2529 goto cleanup; 2530 } 2531 /* HC is busted, give up! */ 2532 xhci_err(xhci, 2533 "ERROR Transfer event TRB DMA ptr not " 2534 "part of current TD ep_index %d " 2535 "comp_code %u\n", ep_index, 2536 trb_comp_code); 2537 trb_in_td(xhci, ep_ring->deq_seg, 2538 ep_ring->dequeue, td->last_trb, 2539 event_dma, true); 2540 return -ESHUTDOWN; 2541 } 2542 2543 ret = skip_isoc_td(xhci, td, event, ep, &status); 2544 goto cleanup; 2545 } 2546 if (trb_comp_code == COMP_SHORT_TX) 2547 ep_ring->last_td_was_short = true; 2548 else 2549 ep_ring->last_td_was_short = false; 2550 2551 if (ep->skip) { 2552 xhci_dbg(xhci, "Found td. Clear skip flag.\n"); 2553 ep->skip = false; 2554 } 2555 2556 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / 2557 sizeof(*event_trb)]; 2558 /* 2559 * No-op TRB should not trigger interrupts. 2560 * If event_trb is a no-op TRB, it means the 2561 * corresponding TD has been cancelled. Just ignore 2562 * the TD. 2563 */ 2564 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { 2565 xhci_dbg(xhci, 2566 "event_trb is a no-op TRB. Skip it\n"); 2567 goto cleanup; 2568 } 2569 2570 /* Now update the urb's actual_length and give back to 2571 * the core 2572 */ 2573 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2574 ret = process_ctrl_td(xhci, td, event_trb, event, ep, 2575 &status); 2576 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2577 ret = process_isoc_td(xhci, td, event_trb, event, ep, 2578 &status); 2579 else 2580 ret = process_bulk_intr_td(xhci, td, event_trb, event, 2581 ep, &status); 2582 2583 cleanup: 2584 2585 2586 handling_skipped_tds = ep->skip && 2587 trb_comp_code != COMP_MISSED_INT && 2588 trb_comp_code != COMP_PING_ERR; 2589 2590 /* 2591 * Do not update event ring dequeue pointer if we're in a loop 2592 * processing missed tds. 2593 */ 2594 if (!handling_skipped_tds) 2595 inc_deq(xhci, xhci->event_ring); 2596 2597 if (ret) { 2598 urb = td->urb; 2599 urb_priv = urb->hcpriv; 2600 2601 xhci_urb_free_priv(urb_priv); 2602 2603 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 2604 if ((urb->actual_length != urb->transfer_buffer_length && 2605 (urb->transfer_flags & 2606 URB_SHORT_NOT_OK)) || 2607 (status != 0 && 2608 !usb_endpoint_xfer_isoc(&urb->ep->desc))) 2609 xhci_dbg(xhci, "Giveback URB %p, len = %d, " 2610 "expected = %d, status = %d\n", 2611 urb, urb->actual_length, 2612 urb->transfer_buffer_length, 2613 status); 2614 spin_unlock(&xhci->lock); 2615 /* EHCI, UHCI, and OHCI always unconditionally set the 2616 * urb->status of an isochronous endpoint to 0. 2617 */ 2618 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2619 status = 0; 2620 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); 2621 spin_lock(&xhci->lock); 2622 } 2623 2624 /* 2625 * If ep->skip is set, it means there are missed tds on the 2626 * endpoint ring need to take care of. 2627 * Process them as short transfer until reach the td pointed by 2628 * the event. 2629 */ 2630 } while (handling_skipped_tds); 2631 2632 return 0; 2633 } 2634 2635 /* 2636 * This function handles all OS-owned events on the event ring. It may drop 2637 * xhci->lock between event processing (e.g. to pass up port status changes). 2638 * Returns >0 for "possibly more events to process" (caller should call again), 2639 * otherwise 0 if done. In future, <0 returns should indicate error code. 2640 */ 2641 static int xhci_handle_event(struct xhci_hcd *xhci) 2642 { 2643 union xhci_trb *event; 2644 int update_ptrs = 1; 2645 int ret; 2646 2647 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 2648 xhci->error_bitmask |= 1 << 1; 2649 return 0; 2650 } 2651 2652 event = xhci->event_ring->dequeue; 2653 /* Does the HC or OS own the TRB? */ 2654 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != 2655 xhci->event_ring->cycle_state) { 2656 xhci->error_bitmask |= 1 << 2; 2657 return 0; 2658 } 2659 2660 /* 2661 * Barrier between reading the TRB_CYCLE (valid) flag above and any 2662 * speculative reads of the event's flags/data below. 2663 */ 2664 rmb(); 2665 /* FIXME: Handle more event types. */ 2666 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { 2667 case TRB_TYPE(TRB_COMPLETION): 2668 handle_cmd_completion(xhci, &event->event_cmd); 2669 break; 2670 case TRB_TYPE(TRB_PORT_STATUS): 2671 handle_port_status(xhci, event); 2672 update_ptrs = 0; 2673 break; 2674 case TRB_TYPE(TRB_TRANSFER): 2675 ret = handle_tx_event(xhci, &event->trans_event); 2676 if (ret < 0) 2677 xhci->error_bitmask |= 1 << 9; 2678 else 2679 update_ptrs = 0; 2680 break; 2681 case TRB_TYPE(TRB_DEV_NOTE): 2682 handle_device_notification(xhci, event); 2683 break; 2684 default: 2685 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= 2686 TRB_TYPE(48)) 2687 handle_vendor_event(xhci, event); 2688 else 2689 xhci->error_bitmask |= 1 << 3; 2690 } 2691 /* Any of the above functions may drop and re-acquire the lock, so check 2692 * to make sure a watchdog timer didn't mark the host as non-responsive. 2693 */ 2694 if (xhci->xhc_state & XHCI_STATE_DYING) { 2695 xhci_dbg(xhci, "xHCI host dying, returning from " 2696 "event handler.\n"); 2697 return 0; 2698 } 2699 2700 if (update_ptrs) 2701 /* Update SW event ring dequeue pointer */ 2702 inc_deq(xhci, xhci->event_ring); 2703 2704 /* Are there more items on the event ring? Caller will call us again to 2705 * check. 2706 */ 2707 return 1; 2708 } 2709 2710 /* 2711 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 2712 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 2713 * indicators of an event TRB error, but we check the status *first* to be safe. 2714 */ 2715 irqreturn_t xhci_irq(struct usb_hcd *hcd) 2716 { 2717 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2718 u32 status; 2719 u64 temp_64; 2720 union xhci_trb *event_ring_deq; 2721 dma_addr_t deq; 2722 2723 spin_lock(&xhci->lock); 2724 /* Check if the xHC generated the interrupt, or the irq is shared */ 2725 status = readl(&xhci->op_regs->status); 2726 if (status == 0xffffffff) 2727 goto hw_died; 2728 2729 if (!(status & STS_EINT)) { 2730 spin_unlock(&xhci->lock); 2731 return IRQ_NONE; 2732 } 2733 if (status & STS_FATAL) { 2734 xhci_warn(xhci, "WARNING: Host System Error\n"); 2735 xhci_halt(xhci); 2736 hw_died: 2737 spin_unlock(&xhci->lock); 2738 return IRQ_HANDLED; 2739 } 2740 2741 /* 2742 * Clear the op reg interrupt status first, 2743 * so we can receive interrupts from other MSI-X interrupters. 2744 * Write 1 to clear the interrupt status. 2745 */ 2746 status |= STS_EINT; 2747 writel(status, &xhci->op_regs->status); 2748 /* FIXME when MSI-X is supported and there are multiple vectors */ 2749 /* Clear the MSI-X event interrupt status */ 2750 2751 if (hcd->irq) { 2752 u32 irq_pending; 2753 /* Acknowledge the PCI interrupt */ 2754 irq_pending = readl(&xhci->ir_set->irq_pending); 2755 irq_pending |= IMAN_IP; 2756 writel(irq_pending, &xhci->ir_set->irq_pending); 2757 } 2758 2759 if (xhci->xhc_state & XHCI_STATE_DYING || 2760 xhci->xhc_state & XHCI_STATE_HALTED) { 2761 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 2762 "Shouldn't IRQs be disabled?\n"); 2763 /* Clear the event handler busy flag (RW1C); 2764 * the event ring should be empty. 2765 */ 2766 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2767 xhci_write_64(xhci, temp_64 | ERST_EHB, 2768 &xhci->ir_set->erst_dequeue); 2769 spin_unlock(&xhci->lock); 2770 2771 return IRQ_HANDLED; 2772 } 2773 2774 event_ring_deq = xhci->event_ring->dequeue; 2775 /* FIXME this should be a delayed service routine 2776 * that clears the EHB. 2777 */ 2778 while (xhci_handle_event(xhci) > 0) {} 2779 2780 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2781 /* If necessary, update the HW's version of the event ring deq ptr. */ 2782 if (event_ring_deq != xhci->event_ring->dequeue) { 2783 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2784 xhci->event_ring->dequeue); 2785 if (deq == 0) 2786 xhci_warn(xhci, "WARN something wrong with SW event " 2787 "ring dequeue ptr.\n"); 2788 /* Update HC event ring dequeue pointer */ 2789 temp_64 &= ERST_PTR_MASK; 2790 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 2791 } 2792 2793 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2794 temp_64 |= ERST_EHB; 2795 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); 2796 2797 spin_unlock(&xhci->lock); 2798 2799 return IRQ_HANDLED; 2800 } 2801 2802 irqreturn_t xhci_msi_irq(int irq, void *hcd) 2803 { 2804 return xhci_irq(hcd); 2805 } 2806 2807 /**** Endpoint Ring Operations ****/ 2808 2809 /* 2810 * Generic function for queueing a TRB on a ring. 2811 * The caller must have checked to make sure there's room on the ring. 2812 * 2813 * @more_trbs_coming: Will you enqueue more TRBs before calling 2814 * prepare_transfer()? 2815 */ 2816 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 2817 bool more_trbs_coming, 2818 u32 field1, u32 field2, u32 field3, u32 field4) 2819 { 2820 struct xhci_generic_trb *trb; 2821 2822 trb = &ring->enqueue->generic; 2823 trb->field[0] = cpu_to_le32(field1); 2824 trb->field[1] = cpu_to_le32(field2); 2825 trb->field[2] = cpu_to_le32(field3); 2826 trb->field[3] = cpu_to_le32(field4); 2827 inc_enq(xhci, ring, more_trbs_coming); 2828 } 2829 2830 /* 2831 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 2832 * FIXME allocate segments if the ring is full. 2833 */ 2834 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 2835 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2836 { 2837 unsigned int num_trbs_needed; 2838 2839 /* Make sure the endpoint has been added to xHC schedule */ 2840 switch (ep_state) { 2841 case EP_STATE_DISABLED: 2842 /* 2843 * USB core changed config/interfaces without notifying us, 2844 * or hardware is reporting the wrong state. 2845 */ 2846 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 2847 return -ENOENT; 2848 case EP_STATE_ERROR: 2849 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 2850 /* FIXME event handling code for error needs to clear it */ 2851 /* XXX not sure if this should be -ENOENT or not */ 2852 return -EINVAL; 2853 case EP_STATE_HALTED: 2854 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 2855 case EP_STATE_STOPPED: 2856 case EP_STATE_RUNNING: 2857 break; 2858 default: 2859 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 2860 /* 2861 * FIXME issue Configure Endpoint command to try to get the HC 2862 * back into a known state. 2863 */ 2864 return -EINVAL; 2865 } 2866 2867 while (1) { 2868 if (room_on_ring(xhci, ep_ring, num_trbs)) 2869 break; 2870 2871 if (ep_ring == xhci->cmd_ring) { 2872 xhci_err(xhci, "Do not support expand command ring\n"); 2873 return -ENOMEM; 2874 } 2875 2876 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 2877 "ERROR no room on ep ring, try ring expansion"); 2878 num_trbs_needed = num_trbs - ep_ring->num_trbs_free; 2879 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, 2880 mem_flags)) { 2881 xhci_err(xhci, "Ring expansion failed\n"); 2882 return -ENOMEM; 2883 } 2884 } 2885 2886 while (trb_is_link(ep_ring->enqueue)) { 2887 /* If we're not dealing with 0.95 hardware or isoc rings 2888 * on AMD 0.96 host, clear the chain bit. 2889 */ 2890 if (!xhci_link_trb_quirk(xhci) && 2891 !(ep_ring->type == TYPE_ISOC && 2892 (xhci->quirks & XHCI_AMD_0x96_HOST))) 2893 ep_ring->enqueue->link.control &= 2894 cpu_to_le32(~TRB_CHAIN); 2895 else 2896 ep_ring->enqueue->link.control |= 2897 cpu_to_le32(TRB_CHAIN); 2898 2899 wmb(); 2900 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); 2901 2902 /* Toggle the cycle bit after the last ring segment. */ 2903 if (link_trb_toggles_cycle(ep_ring->enqueue)) 2904 ep_ring->cycle_state ^= 1; 2905 2906 ep_ring->enq_seg = ep_ring->enq_seg->next; 2907 ep_ring->enqueue = ep_ring->enq_seg->trbs; 2908 } 2909 return 0; 2910 } 2911 2912 static int prepare_transfer(struct xhci_hcd *xhci, 2913 struct xhci_virt_device *xdev, 2914 unsigned int ep_index, 2915 unsigned int stream_id, 2916 unsigned int num_trbs, 2917 struct urb *urb, 2918 unsigned int td_index, 2919 gfp_t mem_flags) 2920 { 2921 int ret; 2922 struct urb_priv *urb_priv; 2923 struct xhci_td *td; 2924 struct xhci_ring *ep_ring; 2925 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2926 2927 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); 2928 if (!ep_ring) { 2929 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 2930 stream_id); 2931 return -EINVAL; 2932 } 2933 2934 ret = prepare_ring(xhci, ep_ring, 2935 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, 2936 num_trbs, mem_flags); 2937 if (ret) 2938 return ret; 2939 2940 urb_priv = urb->hcpriv; 2941 td = urb_priv->td[td_index]; 2942 2943 INIT_LIST_HEAD(&td->td_list); 2944 INIT_LIST_HEAD(&td->cancelled_td_list); 2945 2946 if (td_index == 0) { 2947 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 2948 if (unlikely(ret)) 2949 return ret; 2950 } 2951 2952 td->urb = urb; 2953 /* Add this TD to the tail of the endpoint ring's TD list */ 2954 list_add_tail(&td->td_list, &ep_ring->td_list); 2955 td->start_seg = ep_ring->enq_seg; 2956 td->first_trb = ep_ring->enqueue; 2957 2958 urb_priv->td[td_index] = td; 2959 2960 return 0; 2961 } 2962 2963 static unsigned int count_trbs(u64 addr, u64 len) 2964 { 2965 unsigned int num_trbs; 2966 2967 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 2968 TRB_MAX_BUFF_SIZE); 2969 if (num_trbs == 0) 2970 num_trbs++; 2971 2972 return num_trbs; 2973 } 2974 2975 static inline unsigned int count_trbs_needed(struct urb *urb) 2976 { 2977 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); 2978 } 2979 2980 static unsigned int count_sg_trbs_needed(struct urb *urb) 2981 { 2982 struct scatterlist *sg; 2983 unsigned int i, len, full_len, num_trbs = 0; 2984 2985 full_len = urb->transfer_buffer_length; 2986 2987 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { 2988 len = sg_dma_len(sg); 2989 num_trbs += count_trbs(sg_dma_address(sg), len); 2990 len = min_t(unsigned int, len, full_len); 2991 full_len -= len; 2992 if (full_len == 0) 2993 break; 2994 } 2995 2996 return num_trbs; 2997 } 2998 2999 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) 3000 { 3001 u64 addr, len; 3002 3003 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3004 len = urb->iso_frame_desc[i].length; 3005 3006 return count_trbs(addr, len); 3007 } 3008 3009 static void check_trb_math(struct urb *urb, int running_total) 3010 { 3011 if (unlikely(running_total != urb->transfer_buffer_length)) 3012 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 3013 "queued %#x (%d), asked for %#x (%d)\n", 3014 __func__, 3015 urb->ep->desc.bEndpointAddress, 3016 running_total, running_total, 3017 urb->transfer_buffer_length, 3018 urb->transfer_buffer_length); 3019 } 3020 3021 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 3022 unsigned int ep_index, unsigned int stream_id, int start_cycle, 3023 struct xhci_generic_trb *start_trb) 3024 { 3025 /* 3026 * Pass all the TRBs to the hardware at once and make sure this write 3027 * isn't reordered. 3028 */ 3029 wmb(); 3030 if (start_cycle) 3031 start_trb->field[3] |= cpu_to_le32(start_cycle); 3032 else 3033 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3034 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3035 } 3036 3037 static void check_interval(struct xhci_hcd *xhci, struct urb *urb, 3038 struct xhci_ep_ctx *ep_ctx) 3039 { 3040 int xhci_interval; 3041 int ep_interval; 3042 3043 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3044 ep_interval = urb->interval; 3045 3046 /* Convert to microframes */ 3047 if (urb->dev->speed == USB_SPEED_LOW || 3048 urb->dev->speed == USB_SPEED_FULL) 3049 ep_interval *= 8; 3050 3051 /* FIXME change this to a warning and a suggestion to use the new API 3052 * to set the polling interval (once the API is added). 3053 */ 3054 if (xhci_interval != ep_interval) { 3055 dev_dbg_ratelimited(&urb->dev->dev, 3056 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", 3057 ep_interval, ep_interval == 1 ? "" : "s", 3058 xhci_interval, xhci_interval == 1 ? "" : "s"); 3059 urb->interval = xhci_interval; 3060 /* Convert back to frames for LS/FS devices */ 3061 if (urb->dev->speed == USB_SPEED_LOW || 3062 urb->dev->speed == USB_SPEED_FULL) 3063 urb->interval /= 8; 3064 } 3065 } 3066 3067 /* 3068 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3069 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3070 * (comprised of sg list entries) can take several service intervals to 3071 * transmit. 3072 */ 3073 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3074 struct urb *urb, int slot_id, unsigned int ep_index) 3075 { 3076 struct xhci_ep_ctx *ep_ctx; 3077 3078 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); 3079 check_interval(xhci, urb, ep_ctx); 3080 3081 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3082 } 3083 3084 /* 3085 * For xHCI 1.0 host controllers, TD size is the number of max packet sized 3086 * packets remaining in the TD (*not* including this TRB). 3087 * 3088 * Total TD packet count = total_packet_count = 3089 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) 3090 * 3091 * Packets transferred up to and including this TRB = packets_transferred = 3092 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3093 * 3094 * TD size = total_packet_count - packets_transferred 3095 * 3096 * For xHCI 0.96 and older, TD size field should be the remaining bytes 3097 * including this TRB, right shifted by 10 3098 * 3099 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. 3100 * This is taken care of in the TRB_TD_SIZE() macro 3101 * 3102 * The last TRB in a TD must have the TD size set to zero. 3103 */ 3104 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, 3105 int trb_buff_len, unsigned int td_total_len, 3106 struct urb *urb, bool more_trbs_coming) 3107 { 3108 u32 maxp, total_packet_count; 3109 3110 /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ 3111 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) 3112 return ((td_total_len - transferred) >> 10); 3113 3114 /* One TRB with a zero-length data packet. */ 3115 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || 3116 trb_buff_len == td_total_len) 3117 return 0; 3118 3119 /* for MTK xHCI, TD size doesn't include this TRB */ 3120 if (xhci->quirks & XHCI_MTK_HOST) 3121 trb_buff_len = 0; 3122 3123 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); 3124 total_packet_count = DIV_ROUND_UP(td_total_len, maxp); 3125 3126 /* Queueing functions don't count the current TRB into transferred */ 3127 return (total_packet_count - ((transferred + trb_buff_len) / maxp)); 3128 } 3129 3130 3131 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, 3132 u32 *trb_buff_len, struct xhci_segment *seg) 3133 { 3134 struct device *dev = xhci_to_hcd(xhci)->self.controller; 3135 unsigned int unalign; 3136 unsigned int max_pkt; 3137 u32 new_buff_len; 3138 3139 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); 3140 unalign = (enqd_len + *trb_buff_len) % max_pkt; 3141 3142 /* we got lucky, last normal TRB data on segment is packet aligned */ 3143 if (unalign == 0) 3144 return 0; 3145 3146 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", 3147 unalign, *trb_buff_len); 3148 3149 /* is the last nornal TRB alignable by splitting it */ 3150 if (*trb_buff_len > unalign) { 3151 *trb_buff_len -= unalign; 3152 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); 3153 return 0; 3154 } 3155 3156 /* 3157 * We want enqd_len + trb_buff_len to sum up to a number aligned to 3158 * number which is divisible by the endpoint's wMaxPacketSize. IOW: 3159 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. 3160 */ 3161 new_buff_len = max_pkt - (enqd_len % max_pkt); 3162 3163 if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) 3164 new_buff_len = (urb->transfer_buffer_length - enqd_len); 3165 3166 /* create a max max_pkt sized bounce buffer pointed to by last trb */ 3167 if (usb_urb_dir_out(urb)) { 3168 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, 3169 seg->bounce_buf, new_buff_len, enqd_len); 3170 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3171 max_pkt, DMA_TO_DEVICE); 3172 } else { 3173 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3174 max_pkt, DMA_FROM_DEVICE); 3175 } 3176 3177 if (dma_mapping_error(dev, seg->bounce_dma)) { 3178 /* try without aligning. Some host controllers survive */ 3179 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); 3180 return 0; 3181 } 3182 *trb_buff_len = new_buff_len; 3183 seg->bounce_len = new_buff_len; 3184 seg->bounce_offs = enqd_len; 3185 3186 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); 3187 3188 return 1; 3189 } 3190 3191 /* This is very similar to what ehci-q.c qtd_fill() does */ 3192 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3193 struct urb *urb, int slot_id, unsigned int ep_index) 3194 { 3195 struct xhci_ring *ring; 3196 struct urb_priv *urb_priv; 3197 struct xhci_td *td; 3198 struct xhci_generic_trb *start_trb; 3199 struct scatterlist *sg = NULL; 3200 bool more_trbs_coming = true; 3201 bool need_zero_pkt = false; 3202 bool first_trb = true; 3203 unsigned int num_trbs; 3204 unsigned int start_cycle, num_sgs = 0; 3205 unsigned int enqd_len, block_len, trb_buff_len, full_len; 3206 int sent_len, ret; 3207 u32 field, length_field, remainder; 3208 u64 addr, send_addr; 3209 3210 ring = xhci_urb_to_transfer_ring(xhci, urb); 3211 if (!ring) 3212 return -EINVAL; 3213 3214 full_len = urb->transfer_buffer_length; 3215 /* If we have scatter/gather list, we use it. */ 3216 if (urb->num_sgs) { 3217 num_sgs = urb->num_mapped_sgs; 3218 sg = urb->sg; 3219 addr = (u64) sg_dma_address(sg); 3220 block_len = sg_dma_len(sg); 3221 num_trbs = count_sg_trbs_needed(urb); 3222 } else { 3223 num_trbs = count_trbs_needed(urb); 3224 addr = (u64) urb->transfer_dma; 3225 block_len = full_len; 3226 } 3227 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3228 ep_index, urb->stream_id, 3229 num_trbs, urb, 0, mem_flags); 3230 if (unlikely(ret < 0)) 3231 return ret; 3232 3233 urb_priv = urb->hcpriv; 3234 3235 /* Deal with URB_ZERO_PACKET - need one more td/trb */ 3236 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1) 3237 need_zero_pkt = true; 3238 3239 td = urb_priv->td[0]; 3240 3241 /* 3242 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3243 * until we've finished creating all the other TRBs. The ring's cycle 3244 * state may change as we enqueue the other TRBs, so save it too. 3245 */ 3246 start_trb = &ring->enqueue->generic; 3247 start_cycle = ring->cycle_state; 3248 send_addr = addr; 3249 3250 /* Queue the TRBs, even if they are zero-length */ 3251 for (enqd_len = 0; first_trb || enqd_len < full_len; 3252 enqd_len += trb_buff_len) { 3253 field = TRB_TYPE(TRB_NORMAL); 3254 3255 /* TRB buffer should not cross 64KB boundaries */ 3256 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3257 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); 3258 3259 if (enqd_len + trb_buff_len > full_len) 3260 trb_buff_len = full_len - enqd_len; 3261 3262 /* Don't change the cycle bit of the first TRB until later */ 3263 if (first_trb) { 3264 first_trb = false; 3265 if (start_cycle == 0) 3266 field |= TRB_CYCLE; 3267 } else 3268 field |= ring->cycle_state; 3269 3270 /* Chain all the TRBs together; clear the chain bit in the last 3271 * TRB to indicate it's the last TRB in the chain. 3272 */ 3273 if (enqd_len + trb_buff_len < full_len) { 3274 field |= TRB_CHAIN; 3275 if (trb_is_link(ring->enqueue + 1)) { 3276 if (xhci_align_td(xhci, urb, enqd_len, 3277 &trb_buff_len, 3278 ring->enq_seg)) { 3279 send_addr = ring->enq_seg->bounce_dma; 3280 /* assuming TD won't span 2 segs */ 3281 td->bounce_seg = ring->enq_seg; 3282 } 3283 } 3284 } 3285 if (enqd_len + trb_buff_len >= full_len) { 3286 field &= ~TRB_CHAIN; 3287 field |= TRB_IOC; 3288 more_trbs_coming = false; 3289 td->last_trb = ring->enqueue; 3290 } 3291 3292 /* Only set interrupt on short packet for IN endpoints */ 3293 if (usb_urb_dir_in(urb)) 3294 field |= TRB_ISP; 3295 3296 /* Set the TRB length, TD size, and interrupter fields. */ 3297 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, 3298 full_len, urb, more_trbs_coming); 3299 3300 length_field = TRB_LEN(trb_buff_len) | 3301 TRB_TD_SIZE(remainder) | 3302 TRB_INTR_TARGET(0); 3303 3304 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, 3305 lower_32_bits(send_addr), 3306 upper_32_bits(send_addr), 3307 length_field, 3308 field); 3309 3310 addr += trb_buff_len; 3311 sent_len = trb_buff_len; 3312 3313 while (sg && sent_len >= block_len) { 3314 /* New sg entry */ 3315 --num_sgs; 3316 sent_len -= block_len; 3317 if (num_sgs != 0) { 3318 sg = sg_next(sg); 3319 block_len = sg_dma_len(sg); 3320 addr = (u64) sg_dma_address(sg); 3321 addr += sent_len; 3322 } 3323 } 3324 block_len -= sent_len; 3325 send_addr = addr; 3326 } 3327 3328 if (need_zero_pkt) { 3329 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3330 ep_index, urb->stream_id, 3331 1, urb, 1, mem_flags); 3332 urb_priv->td[1]->last_trb = ring->enqueue; 3333 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; 3334 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); 3335 } 3336 3337 check_trb_math(urb, enqd_len); 3338 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3339 start_cycle, start_trb); 3340 return 0; 3341 } 3342 3343 /* Caller must have locked xhci->lock */ 3344 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3345 struct urb *urb, int slot_id, unsigned int ep_index) 3346 { 3347 struct xhci_ring *ep_ring; 3348 int num_trbs; 3349 int ret; 3350 struct usb_ctrlrequest *setup; 3351 struct xhci_generic_trb *start_trb; 3352 int start_cycle; 3353 u32 field, length_field, remainder; 3354 struct urb_priv *urb_priv; 3355 struct xhci_td *td; 3356 3357 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3358 if (!ep_ring) 3359 return -EINVAL; 3360 3361 /* 3362 * Need to copy setup packet into setup TRB, so we can't use the setup 3363 * DMA address. 3364 */ 3365 if (!urb->setup_packet) 3366 return -EINVAL; 3367 3368 /* 1 TRB for setup, 1 for status */ 3369 num_trbs = 2; 3370 /* 3371 * Don't need to check if we need additional event data and normal TRBs, 3372 * since data in control transfers will never get bigger than 16MB 3373 * XXX: can we get a buffer that crosses 64KB boundaries? 3374 */ 3375 if (urb->transfer_buffer_length > 0) 3376 num_trbs++; 3377 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3378 ep_index, urb->stream_id, 3379 num_trbs, urb, 0, mem_flags); 3380 if (ret < 0) 3381 return ret; 3382 3383 urb_priv = urb->hcpriv; 3384 td = urb_priv->td[0]; 3385 3386 /* 3387 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3388 * until we've finished creating all the other TRBs. The ring's cycle 3389 * state may change as we enqueue the other TRBs, so save it too. 3390 */ 3391 start_trb = &ep_ring->enqueue->generic; 3392 start_cycle = ep_ring->cycle_state; 3393 3394 /* Queue setup TRB - see section 6.4.1.2.1 */ 3395 /* FIXME better way to translate setup_packet into two u32 fields? */ 3396 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3397 field = 0; 3398 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3399 if (start_cycle == 0) 3400 field |= 0x1; 3401 3402 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ 3403 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { 3404 if (urb->transfer_buffer_length > 0) { 3405 if (setup->bRequestType & USB_DIR_IN) 3406 field |= TRB_TX_TYPE(TRB_DATA_IN); 3407 else 3408 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3409 } 3410 } 3411 3412 queue_trb(xhci, ep_ring, true, 3413 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3414 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3415 TRB_LEN(8) | TRB_INTR_TARGET(0), 3416 /* Immediate data in pointer */ 3417 field); 3418 3419 /* If there's data, queue data TRBs */ 3420 /* Only set interrupt on short packet for IN endpoints */ 3421 if (usb_urb_dir_in(urb)) 3422 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3423 else 3424 field = TRB_TYPE(TRB_DATA); 3425 3426 remainder = xhci_td_remainder(xhci, 0, 3427 urb->transfer_buffer_length, 3428 urb->transfer_buffer_length, 3429 urb, 1); 3430 3431 length_field = TRB_LEN(urb->transfer_buffer_length) | 3432 TRB_TD_SIZE(remainder) | 3433 TRB_INTR_TARGET(0); 3434 3435 if (urb->transfer_buffer_length > 0) { 3436 if (setup->bRequestType & USB_DIR_IN) 3437 field |= TRB_DIR_IN; 3438 queue_trb(xhci, ep_ring, true, 3439 lower_32_bits(urb->transfer_dma), 3440 upper_32_bits(urb->transfer_dma), 3441 length_field, 3442 field | ep_ring->cycle_state); 3443 } 3444 3445 /* Save the DMA address of the last TRB in the TD */ 3446 td->last_trb = ep_ring->enqueue; 3447 3448 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3449 /* If the device sent data, the status stage is an OUT transfer */ 3450 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3451 field = 0; 3452 else 3453 field = TRB_DIR_IN; 3454 queue_trb(xhci, ep_ring, false, 3455 0, 3456 0, 3457 TRB_INTR_TARGET(0), 3458 /* Event on completion */ 3459 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3460 3461 giveback_first_trb(xhci, slot_id, ep_index, 0, 3462 start_cycle, start_trb); 3463 return 0; 3464 } 3465 3466 /* 3467 * The transfer burst count field of the isochronous TRB defines the number of 3468 * bursts that are required to move all packets in this TD. Only SuperSpeed 3469 * devices can burst up to bMaxBurst number of packets per service interval. 3470 * This field is zero based, meaning a value of zero in the field means one 3471 * burst. Basically, for everything but SuperSpeed devices, this field will be 3472 * zero. Only xHCI 1.0 host controllers support this field. 3473 */ 3474 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3475 struct urb *urb, unsigned int total_packet_count) 3476 { 3477 unsigned int max_burst; 3478 3479 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) 3480 return 0; 3481 3482 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3483 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; 3484 } 3485 3486 /* 3487 * Returns the number of packets in the last "burst" of packets. This field is 3488 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3489 * the last burst packet count is equal to the total number of packets in the 3490 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3491 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3492 * contain 1 to (bMaxBurst + 1) packets. 3493 */ 3494 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3495 struct urb *urb, unsigned int total_packet_count) 3496 { 3497 unsigned int max_burst; 3498 unsigned int residue; 3499 3500 if (xhci->hci_version < 0x100) 3501 return 0; 3502 3503 if (urb->dev->speed >= USB_SPEED_SUPER) { 3504 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3505 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3506 residue = total_packet_count % (max_burst + 1); 3507 /* If residue is zero, the last burst contains (max_burst + 1) 3508 * number of packets, but the TLBPC field is zero-based. 3509 */ 3510 if (residue == 0) 3511 return max_burst; 3512 return residue - 1; 3513 } 3514 if (total_packet_count == 0) 3515 return 0; 3516 return total_packet_count - 1; 3517 } 3518 3519 /* 3520 * Calculates Frame ID field of the isochronous TRB identifies the 3521 * target frame that the Interval associated with this Isochronous 3522 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. 3523 * 3524 * Returns actual frame id on success, negative value on error. 3525 */ 3526 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, 3527 struct urb *urb, int index) 3528 { 3529 int start_frame, ist, ret = 0; 3530 int start_frame_id, end_frame_id, current_frame_id; 3531 3532 if (urb->dev->speed == USB_SPEED_LOW || 3533 urb->dev->speed == USB_SPEED_FULL) 3534 start_frame = urb->start_frame + index * urb->interval; 3535 else 3536 start_frame = (urb->start_frame + index * urb->interval) >> 3; 3537 3538 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): 3539 * 3540 * If bit [3] of IST is cleared to '0', software can add a TRB no 3541 * later than IST[2:0] Microframes before that TRB is scheduled to 3542 * be executed. 3543 * If bit [3] of IST is set to '1', software can add a TRB no later 3544 * than IST[2:0] Frames before that TRB is scheduled to be executed. 3545 */ 3546 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3547 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3548 ist <<= 3; 3549 3550 /* Software shall not schedule an Isoch TD with a Frame ID value that 3551 * is less than the Start Frame ID or greater than the End Frame ID, 3552 * where: 3553 * 3554 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 3555 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 3556 * 3557 * Both the End Frame ID and Start Frame ID values are calculated 3558 * in microframes. When software determines the valid Frame ID value; 3559 * The End Frame ID value should be rounded down to the nearest Frame 3560 * boundary, and the Start Frame ID value should be rounded up to the 3561 * nearest Frame boundary. 3562 */ 3563 current_frame_id = readl(&xhci->run_regs->microframe_index); 3564 start_frame_id = roundup(current_frame_id + ist + 1, 8); 3565 end_frame_id = rounddown(current_frame_id + 895 * 8, 8); 3566 3567 start_frame &= 0x7ff; 3568 start_frame_id = (start_frame_id >> 3) & 0x7ff; 3569 end_frame_id = (end_frame_id >> 3) & 0x7ff; 3570 3571 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", 3572 __func__, index, readl(&xhci->run_regs->microframe_index), 3573 start_frame_id, end_frame_id, start_frame); 3574 3575 if (start_frame_id < end_frame_id) { 3576 if (start_frame > end_frame_id || 3577 start_frame < start_frame_id) 3578 ret = -EINVAL; 3579 } else if (start_frame_id > end_frame_id) { 3580 if ((start_frame > end_frame_id && 3581 start_frame < start_frame_id)) 3582 ret = -EINVAL; 3583 } else { 3584 ret = -EINVAL; 3585 } 3586 3587 if (index == 0) { 3588 if (ret == -EINVAL || start_frame == start_frame_id) { 3589 start_frame = start_frame_id + 1; 3590 if (urb->dev->speed == USB_SPEED_LOW || 3591 urb->dev->speed == USB_SPEED_FULL) 3592 urb->start_frame = start_frame; 3593 else 3594 urb->start_frame = start_frame << 3; 3595 ret = 0; 3596 } 3597 } 3598 3599 if (ret) { 3600 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", 3601 start_frame, current_frame_id, index, 3602 start_frame_id, end_frame_id); 3603 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); 3604 return ret; 3605 } 3606 3607 return start_frame; 3608 } 3609 3610 /* This is for isoc transfer */ 3611 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3612 struct urb *urb, int slot_id, unsigned int ep_index) 3613 { 3614 struct xhci_ring *ep_ring; 3615 struct urb_priv *urb_priv; 3616 struct xhci_td *td; 3617 int num_tds, trbs_per_td; 3618 struct xhci_generic_trb *start_trb; 3619 bool first_trb; 3620 int start_cycle; 3621 u32 field, length_field; 3622 int running_total, trb_buff_len, td_len, td_remain_len, ret; 3623 u64 start_addr, addr; 3624 int i, j; 3625 bool more_trbs_coming; 3626 struct xhci_virt_ep *xep; 3627 int frame_id; 3628 3629 xep = &xhci->devs[slot_id]->eps[ep_index]; 3630 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 3631 3632 num_tds = urb->number_of_packets; 3633 if (num_tds < 1) { 3634 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 3635 return -EINVAL; 3636 } 3637 start_addr = (u64) urb->transfer_dma; 3638 start_trb = &ep_ring->enqueue->generic; 3639 start_cycle = ep_ring->cycle_state; 3640 3641 urb_priv = urb->hcpriv; 3642 /* Queue the TRBs for each TD, even if they are zero-length */ 3643 for (i = 0; i < num_tds; i++) { 3644 unsigned int total_pkt_count, max_pkt; 3645 unsigned int burst_count, last_burst_pkt_count; 3646 u32 sia_frame_id; 3647 3648 first_trb = true; 3649 running_total = 0; 3650 addr = start_addr + urb->iso_frame_desc[i].offset; 3651 td_len = urb->iso_frame_desc[i].length; 3652 td_remain_len = td_len; 3653 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); 3654 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); 3655 3656 /* A zero-length transfer still involves at least one packet. */ 3657 if (total_pkt_count == 0) 3658 total_pkt_count++; 3659 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); 3660 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, 3661 urb, total_pkt_count); 3662 3663 trbs_per_td = count_isoc_trbs_needed(urb, i); 3664 3665 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 3666 urb->stream_id, trbs_per_td, urb, i, mem_flags); 3667 if (ret < 0) { 3668 if (i == 0) 3669 return ret; 3670 goto cleanup; 3671 } 3672 td = urb_priv->td[i]; 3673 3674 /* use SIA as default, if frame id is used overwrite it */ 3675 sia_frame_id = TRB_SIA; 3676 if (!(urb->transfer_flags & URB_ISO_ASAP) && 3677 HCC_CFC(xhci->hcc_params)) { 3678 frame_id = xhci_get_isoc_frame_id(xhci, urb, i); 3679 if (frame_id >= 0) 3680 sia_frame_id = TRB_FRAME_ID(frame_id); 3681 } 3682 /* 3683 * Set isoc specific data for the first TRB in a TD. 3684 * Prevent HW from getting the TRBs by keeping the cycle state 3685 * inverted in the first TDs isoc TRB. 3686 */ 3687 field = TRB_TYPE(TRB_ISOC) | 3688 TRB_TLBPC(last_burst_pkt_count) | 3689 sia_frame_id | 3690 (i ? ep_ring->cycle_state : !start_cycle); 3691 3692 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ 3693 if (!xep->use_extended_tbc) 3694 field |= TRB_TBC(burst_count); 3695 3696 /* fill the rest of the TRB fields, and remaining normal TRBs */ 3697 for (j = 0; j < trbs_per_td; j++) { 3698 u32 remainder = 0; 3699 3700 /* only first TRB is isoc, overwrite otherwise */ 3701 if (!first_trb) 3702 field = TRB_TYPE(TRB_NORMAL) | 3703 ep_ring->cycle_state; 3704 3705 /* Only set interrupt on short packet for IN EPs */ 3706 if (usb_urb_dir_in(urb)) 3707 field |= TRB_ISP; 3708 3709 /* Set the chain bit for all except the last TRB */ 3710 if (j < trbs_per_td - 1) { 3711 more_trbs_coming = true; 3712 field |= TRB_CHAIN; 3713 } else { 3714 more_trbs_coming = false; 3715 td->last_trb = ep_ring->enqueue; 3716 field |= TRB_IOC; 3717 /* set BEI, except for the last TD */ 3718 if (xhci->hci_version >= 0x100 && 3719 !(xhci->quirks & XHCI_AVOID_BEI) && 3720 i < num_tds - 1) 3721 field |= TRB_BEI; 3722 } 3723 /* Calculate TRB length */ 3724 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3725 if (trb_buff_len > td_remain_len) 3726 trb_buff_len = td_remain_len; 3727 3728 /* Set the TRB length, TD size, & interrupter fields. */ 3729 remainder = xhci_td_remainder(xhci, running_total, 3730 trb_buff_len, td_len, 3731 urb, more_trbs_coming); 3732 3733 length_field = TRB_LEN(trb_buff_len) | 3734 TRB_INTR_TARGET(0); 3735 3736 /* xhci 1.1 with ETE uses TD Size field for TBC */ 3737 if (first_trb && xep->use_extended_tbc) 3738 length_field |= TRB_TD_SIZE_TBC(burst_count); 3739 else 3740 length_field |= TRB_TD_SIZE(remainder); 3741 first_trb = false; 3742 3743 queue_trb(xhci, ep_ring, more_trbs_coming, 3744 lower_32_bits(addr), 3745 upper_32_bits(addr), 3746 length_field, 3747 field); 3748 running_total += trb_buff_len; 3749 3750 addr += trb_buff_len; 3751 td_remain_len -= trb_buff_len; 3752 } 3753 3754 /* Check TD length */ 3755 if (running_total != td_len) { 3756 xhci_err(xhci, "ISOC TD length unmatch\n"); 3757 ret = -EINVAL; 3758 goto cleanup; 3759 } 3760 } 3761 3762 /* store the next frame id */ 3763 if (HCC_CFC(xhci->hcc_params)) 3764 xep->next_frame_id = urb->start_frame + num_tds * urb->interval; 3765 3766 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 3767 if (xhci->quirks & XHCI_AMD_PLL_FIX) 3768 usb_amd_quirk_pll_disable(); 3769 } 3770 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 3771 3772 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3773 start_cycle, start_trb); 3774 return 0; 3775 cleanup: 3776 /* Clean up a partially enqueued isoc transfer. */ 3777 3778 for (i--; i >= 0; i--) 3779 list_del_init(&urb_priv->td[i]->td_list); 3780 3781 /* Use the first TD as a temporary variable to turn the TDs we've queued 3782 * into No-ops with a software-owned cycle bit. That way the hardware 3783 * won't accidentally start executing bogus TDs when we partially 3784 * overwrite them. td->first_trb and td->start_seg are already set. 3785 */ 3786 urb_priv->td[0]->last_trb = ep_ring->enqueue; 3787 /* Every TRB except the first & last will have its cycle bit flipped. */ 3788 td_to_noop(xhci, ep_ring, urb_priv->td[0], true); 3789 3790 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 3791 ep_ring->enqueue = urb_priv->td[0]->first_trb; 3792 ep_ring->enq_seg = urb_priv->td[0]->start_seg; 3793 ep_ring->cycle_state = start_cycle; 3794 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; 3795 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 3796 return ret; 3797 } 3798 3799 /* 3800 * Check transfer ring to guarantee there is enough room for the urb. 3801 * Update ISO URB start_frame and interval. 3802 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to 3803 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or 3804 * Contiguous Frame ID is not supported by HC. 3805 */ 3806 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 3807 struct urb *urb, int slot_id, unsigned int ep_index) 3808 { 3809 struct xhci_virt_device *xdev; 3810 struct xhci_ring *ep_ring; 3811 struct xhci_ep_ctx *ep_ctx; 3812 int start_frame; 3813 int num_tds, num_trbs, i; 3814 int ret; 3815 struct xhci_virt_ep *xep; 3816 int ist; 3817 3818 xdev = xhci->devs[slot_id]; 3819 xep = &xhci->devs[slot_id]->eps[ep_index]; 3820 ep_ring = xdev->eps[ep_index].ring; 3821 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3822 3823 num_trbs = 0; 3824 num_tds = urb->number_of_packets; 3825 for (i = 0; i < num_tds; i++) 3826 num_trbs += count_isoc_trbs_needed(urb, i); 3827 3828 /* Check the ring to guarantee there is enough room for the whole urb. 3829 * Do not insert any td of the urb to the ring if the check failed. 3830 */ 3831 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, 3832 num_trbs, mem_flags); 3833 if (ret) 3834 return ret; 3835 3836 /* 3837 * Check interval value. This should be done before we start to 3838 * calculate the start frame value. 3839 */ 3840 check_interval(xhci, urb, ep_ctx); 3841 3842 /* Calculate the start frame and put it in urb->start_frame. */ 3843 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { 3844 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == 3845 EP_STATE_RUNNING) { 3846 urb->start_frame = xep->next_frame_id; 3847 goto skip_start_over; 3848 } 3849 } 3850 3851 start_frame = readl(&xhci->run_regs->microframe_index); 3852 start_frame &= 0x3fff; 3853 /* 3854 * Round up to the next frame and consider the time before trb really 3855 * gets scheduled by hardare. 3856 */ 3857 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3858 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3859 ist <<= 3; 3860 start_frame += ist + XHCI_CFC_DELAY; 3861 start_frame = roundup(start_frame, 8); 3862 3863 /* 3864 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT 3865 * is greate than 8 microframes. 3866 */ 3867 if (urb->dev->speed == USB_SPEED_LOW || 3868 urb->dev->speed == USB_SPEED_FULL) { 3869 start_frame = roundup(start_frame, urb->interval << 3); 3870 urb->start_frame = start_frame >> 3; 3871 } else { 3872 start_frame = roundup(start_frame, urb->interval); 3873 urb->start_frame = start_frame; 3874 } 3875 3876 skip_start_over: 3877 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; 3878 3879 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 3880 } 3881 3882 /**** Command Ring Operations ****/ 3883 3884 /* Generic function for queueing a command TRB on the command ring. 3885 * Check to make sure there's room on the command ring for one command TRB. 3886 * Also check that there's room reserved for commands that must not fail. 3887 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 3888 * then only check for the number of reserved spots. 3889 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 3890 * because the command event handler may want to resubmit a failed command. 3891 */ 3892 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3893 u32 field1, u32 field2, 3894 u32 field3, u32 field4, bool command_must_succeed) 3895 { 3896 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 3897 int ret; 3898 3899 if ((xhci->xhc_state & XHCI_STATE_DYING) || 3900 (xhci->xhc_state & XHCI_STATE_HALTED)) { 3901 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); 3902 return -ESHUTDOWN; 3903 } 3904 3905 if (!command_must_succeed) 3906 reserved_trbs++; 3907 3908 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 3909 reserved_trbs, GFP_ATOMIC); 3910 if (ret < 0) { 3911 xhci_err(xhci, "ERR: No room for command on command ring\n"); 3912 if (command_must_succeed) 3913 xhci_err(xhci, "ERR: Reserved TRB counting for " 3914 "unfailable commands failed.\n"); 3915 return ret; 3916 } 3917 3918 cmd->command_trb = xhci->cmd_ring->enqueue; 3919 list_add_tail(&cmd->cmd_list, &xhci->cmd_list); 3920 3921 /* if there are no other commands queued we start the timeout timer */ 3922 if (xhci->cmd_list.next == &cmd->cmd_list && 3923 !timer_pending(&xhci->cmd_timer)) { 3924 xhci->current_cmd = cmd; 3925 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); 3926 } 3927 3928 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 3929 field4 | xhci->cmd_ring->cycle_state); 3930 return 0; 3931 } 3932 3933 /* Queue a slot enable or disable request on the command ring */ 3934 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 3935 u32 trb_type, u32 slot_id) 3936 { 3937 return queue_command(xhci, cmd, 0, 0, 0, 3938 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 3939 } 3940 3941 /* Queue an address device command TRB */ 3942 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3943 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) 3944 { 3945 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3946 upper_32_bits(in_ctx_ptr), 0, 3947 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) 3948 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); 3949 } 3950 3951 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3952 u32 field1, u32 field2, u32 field3, u32 field4) 3953 { 3954 return queue_command(xhci, cmd, field1, field2, field3, field4, false); 3955 } 3956 3957 /* Queue a reset device command TRB */ 3958 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3959 u32 slot_id) 3960 { 3961 return queue_command(xhci, cmd, 0, 0, 0, 3962 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 3963 false); 3964 } 3965 3966 /* Queue a configure endpoint command TRB */ 3967 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 3968 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 3969 u32 slot_id, bool command_must_succeed) 3970 { 3971 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3972 upper_32_bits(in_ctx_ptr), 0, 3973 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 3974 command_must_succeed); 3975 } 3976 3977 /* Queue an evaluate context command TRB */ 3978 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 3979 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) 3980 { 3981 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3982 upper_32_bits(in_ctx_ptr), 0, 3983 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 3984 command_must_succeed); 3985 } 3986 3987 /* 3988 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 3989 * activity on an endpoint that is about to be suspended. 3990 */ 3991 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 3992 int slot_id, unsigned int ep_index, int suspend) 3993 { 3994 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3995 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3996 u32 type = TRB_TYPE(TRB_STOP_RING); 3997 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 3998 3999 return queue_command(xhci, cmd, 0, 0, 0, 4000 trb_slot_id | trb_ep_index | type | trb_suspend, false); 4001 } 4002 4003 /* Set Transfer Ring Dequeue Pointer command */ 4004 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 4005 unsigned int slot_id, unsigned int ep_index, 4006 unsigned int stream_id, 4007 struct xhci_dequeue_state *deq_state) 4008 { 4009 dma_addr_t addr; 4010 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4011 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4012 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); 4013 u32 trb_sct = 0; 4014 u32 type = TRB_TYPE(TRB_SET_DEQ); 4015 struct xhci_virt_ep *ep; 4016 struct xhci_command *cmd; 4017 int ret; 4018 4019 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 4020 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", 4021 deq_state->new_deq_seg, 4022 (unsigned long long)deq_state->new_deq_seg->dma, 4023 deq_state->new_deq_ptr, 4024 (unsigned long long)xhci_trb_virt_to_dma( 4025 deq_state->new_deq_seg, deq_state->new_deq_ptr), 4026 deq_state->new_cycle_state); 4027 4028 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, 4029 deq_state->new_deq_ptr); 4030 if (addr == 0) { 4031 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4032 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", 4033 deq_state->new_deq_seg, deq_state->new_deq_ptr); 4034 return; 4035 } 4036 ep = &xhci->devs[slot_id]->eps[ep_index]; 4037 if ((ep->ep_state & SET_DEQ_PENDING)) { 4038 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4039 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); 4040 return; 4041 } 4042 4043 /* This function gets called from contexts where it cannot sleep */ 4044 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 4045 if (!cmd) { 4046 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); 4047 return; 4048 } 4049 4050 ep->queued_deq_seg = deq_state->new_deq_seg; 4051 ep->queued_deq_ptr = deq_state->new_deq_ptr; 4052 if (stream_id) 4053 trb_sct = SCT_FOR_TRB(SCT_PRI_TR); 4054 ret = queue_command(xhci, cmd, 4055 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, 4056 upper_32_bits(addr), trb_stream_id, 4057 trb_slot_id | trb_ep_index | type, false); 4058 if (ret < 0) { 4059 xhci_free_command(xhci, cmd); 4060 return; 4061 } 4062 4063 /* Stop the TD queueing code from ringing the doorbell until 4064 * this command completes. The HC won't set the dequeue pointer 4065 * if the ring is running, and ringing the doorbell starts the 4066 * ring running. 4067 */ 4068 ep->ep_state |= SET_DEQ_PENDING; 4069 } 4070 4071 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 4072 int slot_id, unsigned int ep_index) 4073 { 4074 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4075 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4076 u32 type = TRB_TYPE(TRB_RESET_EP); 4077 4078 return queue_command(xhci, cmd, 0, 0, 0, 4079 trb_slot_id | trb_ep_index | type, false); 4080 } 4081