1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 /* 12 * Ring initialization rules: 13 * 1. Each segment is initialized to zero, except for link TRBs. 14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 15 * Consumer Cycle State (CCS), depending on ring function. 16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 17 * 18 * Ring behavior rules: 19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 20 * least one free TRB in the ring. This is useful if you want to turn that 21 * into a link TRB and expand the ring. 22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 23 * link TRB, then load the pointer with the address in the link TRB. If the 24 * link TRB had its toggle bit set, you may need to update the ring cycle 25 * state (see cycle bit rules). You may have to do this multiple times 26 * until you reach a non-link TRB. 27 * 3. A ring is full if enqueue++ (for the definition of increment above) 28 * equals the dequeue pointer. 29 * 30 * Cycle bit rules: 31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 32 * in a link TRB, it must toggle the ring cycle state. 33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 34 * in a link TRB, it must toggle the ring cycle state. 35 * 36 * Producer rules: 37 * 1. Check if ring is full before you enqueue. 38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 39 * Update enqueue pointer between each write (which may update the ring 40 * cycle state). 41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 42 * and endpoint rings. If HC is the producer for the event ring, 43 * and it generates an interrupt according to interrupt modulation rules. 44 * 45 * Consumer rules: 46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 47 * the TRB is owned by the consumer. 48 * 2. Update dequeue pointer (which may update the ring cycle state) and 49 * continue processing TRBs until you reach a TRB which is not owned by you. 50 * 3. Notify the producer. SW is the consumer for the event ring, and it 51 * updates event ring dequeue pointer. HC is the consumer for the command and 52 * endpoint rings; it generates events on the event ring for these. 53 */ 54 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/dma-mapping.h> 58 #include "xhci.h" 59 #include "xhci-trace.h" 60 61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 62 u32 field1, u32 field2, 63 u32 field3, u32 field4, bool command_must_succeed); 64 65 /* 66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 67 * address of the TRB. 68 */ 69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 70 union xhci_trb *trb) 71 { 72 unsigned long segment_offset; 73 74 if (!seg || !trb || trb < seg->trbs) 75 return 0; 76 /* offset in TRBs */ 77 segment_offset = trb - seg->trbs; 78 if (segment_offset >= TRBS_PER_SEGMENT) 79 return 0; 80 return seg->dma + (segment_offset * sizeof(*trb)); 81 } 82 83 static bool trb_is_noop(union xhci_trb *trb) 84 { 85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); 86 } 87 88 static bool trb_is_link(union xhci_trb *trb) 89 { 90 return TRB_TYPE_LINK_LE32(trb->link.control); 91 } 92 93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) 94 { 95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; 96 } 97 98 static bool last_trb_on_ring(struct xhci_ring *ring, 99 struct xhci_segment *seg, union xhci_trb *trb) 100 { 101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); 102 } 103 104 static bool link_trb_toggles_cycle(union xhci_trb *trb) 105 { 106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 107 } 108 109 static bool last_td_in_urb(struct xhci_td *td) 110 { 111 struct urb_priv *urb_priv = td->urb->hcpriv; 112 113 return urb_priv->num_tds_done == urb_priv->num_tds; 114 } 115 116 static bool unhandled_event_trb(struct xhci_ring *ring) 117 { 118 return ((le32_to_cpu(ring->dequeue->event_cmd.flags) & TRB_CYCLE) == 119 ring->cycle_state); 120 } 121 122 static void inc_td_cnt(struct urb *urb) 123 { 124 struct urb_priv *urb_priv = urb->hcpriv; 125 126 urb_priv->num_tds_done++; 127 } 128 129 static void trb_to_noop(union xhci_trb *trb, u32 noop_type) 130 { 131 if (trb_is_link(trb)) { 132 /* unchain chained link TRBs */ 133 trb->link.control &= cpu_to_le32(~TRB_CHAIN); 134 } else { 135 trb->generic.field[0] = 0; 136 trb->generic.field[1] = 0; 137 trb->generic.field[2] = 0; 138 /* Preserve only the cycle bit of this TRB */ 139 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 140 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); 141 } 142 } 143 144 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 145 * TRB is in a new segment. This does not skip over link TRBs, and it does not 146 * effect the ring dequeue or enqueue pointers. 147 */ 148 static void next_trb(struct xhci_hcd *xhci, 149 struct xhci_ring *ring, 150 struct xhci_segment **seg, 151 union xhci_trb **trb) 152 { 153 if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) { 154 *seg = (*seg)->next; 155 *trb = ((*seg)->trbs); 156 } else { 157 (*trb)++; 158 } 159 } 160 161 /* 162 * See Cycle bit rules. SW is the consumer for the event ring only. 163 */ 164 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 165 { 166 unsigned int link_trb_count = 0; 167 168 /* event ring doesn't have link trbs, check for last trb */ 169 if (ring->type == TYPE_EVENT) { 170 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 171 ring->dequeue++; 172 goto out; 173 } 174 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) 175 ring->cycle_state ^= 1; 176 ring->deq_seg = ring->deq_seg->next; 177 ring->dequeue = ring->deq_seg->trbs; 178 goto out; 179 } 180 181 /* All other rings have link trbs */ 182 if (!trb_is_link(ring->dequeue)) { 183 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) 184 xhci_warn(xhci, "Missing link TRB at end of segment\n"); 185 else 186 ring->dequeue++; 187 } 188 189 while (trb_is_link(ring->dequeue)) { 190 ring->deq_seg = ring->deq_seg->next; 191 ring->dequeue = ring->deq_seg->trbs; 192 193 if (link_trb_count++ > ring->num_segs) { 194 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); 195 break; 196 } 197 } 198 out: 199 trace_xhci_inc_deq(ring); 200 201 return; 202 } 203 204 /* 205 * See Cycle bit rules. SW is the consumer for the event ring only. 206 * 207 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 208 * chain bit is set), then set the chain bit in all the following link TRBs. 209 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 210 * have their chain bit cleared (so that each Link TRB is a separate TD). 211 * 212 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 213 * set, but other sections talk about dealing with the chain bit set. This was 214 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 215 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 216 * 217 * @more_trbs_coming: Will you enqueue more TRBs before calling 218 * prepare_transfer()? 219 */ 220 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 221 bool more_trbs_coming) 222 { 223 u32 chain; 224 union xhci_trb *next; 225 unsigned int link_trb_count = 0; 226 227 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 228 229 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) { 230 xhci_err(xhci, "Tried to move enqueue past ring segment\n"); 231 return; 232 } 233 234 next = ++(ring->enqueue); 235 236 /* Update the dequeue pointer further if that was a link TRB */ 237 while (trb_is_link(next)) { 238 239 /* 240 * If the caller doesn't plan on enqueueing more TDs before 241 * ringing the doorbell, then we don't want to give the link TRB 242 * to the hardware just yet. We'll give the link TRB back in 243 * prepare_ring() just before we enqueue the TD at the top of 244 * the ring. 245 */ 246 if (!chain && !more_trbs_coming) 247 break; 248 249 /* If we're not dealing with 0.95 hardware or isoc rings on 250 * AMD 0.96 host, carry over the chain bit of the previous TRB 251 * (which may mean the chain bit is cleared). 252 */ 253 if (!xhci_link_chain_quirk(xhci, ring->type)) { 254 next->link.control &= cpu_to_le32(~TRB_CHAIN); 255 next->link.control |= cpu_to_le32(chain); 256 } 257 /* Give this link TRB to the hardware */ 258 wmb(); 259 next->link.control ^= cpu_to_le32(TRB_CYCLE); 260 261 /* Toggle the cycle bit after the last ring segment. */ 262 if (link_trb_toggles_cycle(next)) 263 ring->cycle_state ^= 1; 264 265 ring->enq_seg = ring->enq_seg->next; 266 ring->enqueue = ring->enq_seg->trbs; 267 next = ring->enqueue; 268 269 if (link_trb_count++ > ring->num_segs) { 270 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__); 271 break; 272 } 273 } 274 275 trace_xhci_inc_enq(ring); 276 } 277 278 /* 279 * Return number of free normal TRBs from enqueue to dequeue pointer on ring. 280 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment. 281 * Only for transfer and command rings where driver is the producer, not for 282 * event rings. 283 */ 284 static unsigned int xhci_num_trbs_free(struct xhci_ring *ring) 285 { 286 struct xhci_segment *enq_seg = ring->enq_seg; 287 union xhci_trb *enq = ring->enqueue; 288 union xhci_trb *last_on_seg; 289 unsigned int free = 0; 290 int i = 0; 291 292 /* Ring might be empty even if enq != deq if enq is left on a link trb */ 293 if (trb_is_link(enq)) { 294 enq_seg = enq_seg->next; 295 enq = enq_seg->trbs; 296 } 297 298 /* Empty ring, common case, don't walk the segments */ 299 if (enq == ring->dequeue) 300 return ring->num_segs * (TRBS_PER_SEGMENT - 1); 301 302 do { 303 if (ring->deq_seg == enq_seg && ring->dequeue >= enq) 304 return free + (ring->dequeue - enq); 305 last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1]; 306 free += last_on_seg - enq; 307 enq_seg = enq_seg->next; 308 enq = enq_seg->trbs; 309 } while (i++ < ring->num_segs); 310 311 return free; 312 } 313 314 /* 315 * Check to see if there's room to enqueue num_trbs on the ring and make sure 316 * enqueue pointer will not advance into dequeue segment. See rules above. 317 * return number of new segments needed to ensure this. 318 */ 319 320 static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring, 321 unsigned int num_trbs) 322 { 323 struct xhci_segment *seg; 324 int trbs_past_seg; 325 int enq_used; 326 int new_segs; 327 328 enq_used = ring->enqueue - ring->enq_seg->trbs; 329 330 /* how many trbs will be queued past the enqueue segment? */ 331 trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1); 332 333 /* 334 * Consider expanding the ring already if num_trbs fills the current 335 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into 336 * the next segment. Avoids confusing full ring with special empty ring 337 * case below 338 */ 339 if (trbs_past_seg < 0) 340 return 0; 341 342 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */ 343 if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue) 344 return 0; 345 346 new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1)); 347 seg = ring->enq_seg; 348 349 while (new_segs > 0) { 350 seg = seg->next; 351 if (seg == ring->deq_seg) { 352 xhci_dbg(xhci, "Adding %d trbs requires expanding ring by %d segments\n", 353 num_trbs, new_segs); 354 return new_segs; 355 } 356 new_segs--; 357 } 358 359 return 0; 360 } 361 362 /* Ring the host controller doorbell after placing a command on the ring */ 363 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 364 { 365 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 366 return; 367 368 xhci_dbg(xhci, "// Ding dong!\n"); 369 370 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST); 371 372 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); 373 /* Flush PCI posted writes */ 374 readl(&xhci->dba->doorbell[0]); 375 } 376 377 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci) 378 { 379 return mod_delayed_work(system_wq, &xhci->cmd_timer, 380 msecs_to_jiffies(xhci->current_cmd->timeout_ms)); 381 } 382 383 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) 384 { 385 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, 386 cmd_list); 387 } 388 389 /* 390 * Turn all commands on command ring with status set to "aborted" to no-op trbs. 391 * If there are other commands waiting then restart the ring and kick the timer. 392 * This must be called with command ring stopped and xhci->lock held. 393 */ 394 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, 395 struct xhci_command *cur_cmd) 396 { 397 struct xhci_command *i_cmd; 398 399 /* Turn all aborted commands in list to no-ops, then restart */ 400 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { 401 402 if (i_cmd->status != COMP_COMMAND_ABORTED) 403 continue; 404 405 i_cmd->status = COMP_COMMAND_RING_STOPPED; 406 407 xhci_dbg(xhci, "Turn aborted command %p to no-op\n", 408 i_cmd->command_trb); 409 410 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); 411 412 /* 413 * caller waiting for completion is called when command 414 * completion event is received for these no-op commands 415 */ 416 } 417 418 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 419 420 /* ring command ring doorbell to restart the command ring */ 421 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && 422 !(xhci->xhc_state & XHCI_STATE_DYING)) { 423 xhci->current_cmd = cur_cmd; 424 xhci_mod_cmd_timer(xhci); 425 xhci_ring_cmd_db(xhci); 426 } 427 } 428 429 /* Must be called with xhci->lock held, releases and aquires lock back */ 430 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) 431 { 432 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg; 433 union xhci_trb *new_deq = xhci->cmd_ring->dequeue; 434 u64 crcr; 435 int ret; 436 437 xhci_dbg(xhci, "Abort command ring\n"); 438 439 reinit_completion(&xhci->cmd_ring_stop_completion); 440 441 /* 442 * The control bits like command stop, abort are located in lower 443 * dword of the command ring control register. 444 * Some controllers require all 64 bits to be written to abort the ring. 445 * Make sure the upper dword is valid, pointing to the next command, 446 * avoiding corrupting the command ring pointer in case the command ring 447 * is stopped by the time the upper dword is written. 448 */ 449 next_trb(xhci, NULL, &new_seg, &new_deq); 450 if (trb_is_link(new_deq)) 451 next_trb(xhci, NULL, &new_seg, &new_deq); 452 453 crcr = xhci_trb_virt_to_dma(new_seg, new_deq); 454 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring); 455 456 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the 457 * completion of the Command Abort operation. If CRR is not negated in 5 458 * seconds then driver handles it as if host died (-ENODEV). 459 * In the future we should distinguish between -ENODEV and -ETIMEDOUT 460 * and try to recover a -ETIMEDOUT with a host controller reset. 461 */ 462 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring, 463 CMD_RING_RUNNING, 0, 5 * 1000 * 1000, 464 XHCI_STATE_REMOVING); 465 if (ret < 0) { 466 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); 467 xhci_halt(xhci); 468 xhci_hc_died(xhci); 469 return ret; 470 } 471 /* 472 * Writing the CMD_RING_ABORT bit should cause a cmd completion event, 473 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared 474 * but the completion event in never sent. Wait 2 secs (arbitrary 475 * number) to handle those cases after negation of CMD_RING_RUNNING. 476 */ 477 spin_unlock_irqrestore(&xhci->lock, flags); 478 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, 479 msecs_to_jiffies(2000)); 480 spin_lock_irqsave(&xhci->lock, flags); 481 if (!ret) { 482 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); 483 xhci_cleanup_command_queue(xhci); 484 } else { 485 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); 486 } 487 return 0; 488 } 489 490 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 491 unsigned int slot_id, 492 unsigned int ep_index, 493 unsigned int stream_id) 494 { 495 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 496 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 497 unsigned int ep_state = ep->ep_state; 498 499 /* Don't ring the doorbell for this endpoint if there are pending 500 * cancellations because we don't want to interrupt processing. 501 * We don't want to restart any stream rings if there's a set dequeue 502 * pointer command pending because the device can choose to start any 503 * stream once the endpoint is on the HW schedule. 504 */ 505 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || 506 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT)) 507 return; 508 509 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id)); 510 511 writel(DB_VALUE(ep_index, stream_id), db_addr); 512 /* flush the write */ 513 readl(db_addr); 514 } 515 516 /* Ring the doorbell for any rings with pending URBs */ 517 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 518 unsigned int slot_id, 519 unsigned int ep_index) 520 { 521 unsigned int stream_id; 522 struct xhci_virt_ep *ep; 523 524 ep = &xhci->devs[slot_id]->eps[ep_index]; 525 526 /* A ring has pending URBs if its TD list is not empty */ 527 if (!(ep->ep_state & EP_HAS_STREAMS)) { 528 if (ep->ring && !(list_empty(&ep->ring->td_list))) 529 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 530 return; 531 } 532 533 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 534 stream_id++) { 535 struct xhci_stream_info *stream_info = ep->stream_info; 536 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 537 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 538 stream_id); 539 } 540 } 541 542 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 543 unsigned int slot_id, 544 unsigned int ep_index) 545 { 546 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 547 } 548 549 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci, 550 unsigned int slot_id, 551 unsigned int ep_index) 552 { 553 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) { 554 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); 555 return NULL; 556 } 557 if (ep_index >= EP_CTX_PER_DEV) { 558 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index); 559 return NULL; 560 } 561 if (!xhci->devs[slot_id]) { 562 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id); 563 return NULL; 564 } 565 566 return &xhci->devs[slot_id]->eps[ep_index]; 567 } 568 569 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci, 570 struct xhci_virt_ep *ep, 571 unsigned int stream_id) 572 { 573 /* common case, no streams */ 574 if (!(ep->ep_state & EP_HAS_STREAMS)) 575 return ep->ring; 576 577 if (!ep->stream_info) 578 return NULL; 579 580 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) { 581 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n", 582 stream_id, ep->vdev->slot_id, ep->ep_index); 583 return NULL; 584 } 585 586 return ep->stream_info->stream_rings[stream_id]; 587 } 588 589 /* Get the right ring for the given slot_id, ep_index and stream_id. 590 * If the endpoint supports streams, boundary check the URB's stream ID. 591 * If the endpoint doesn't support streams, return the singular endpoint ring. 592 */ 593 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 594 unsigned int slot_id, unsigned int ep_index, 595 unsigned int stream_id) 596 { 597 struct xhci_virt_ep *ep; 598 599 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 600 if (!ep) 601 return NULL; 602 603 return xhci_virt_ep_to_ring(xhci, ep, stream_id); 604 } 605 606 607 /* 608 * Get the hw dequeue pointer xHC stopped on, either directly from the 609 * endpoint context, or if streams are in use from the stream context. 610 * The returned hw_dequeue contains the lowest four bits with cycle state 611 * and possbile stream context type. 612 */ 613 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, 614 unsigned int ep_index, unsigned int stream_id) 615 { 616 struct xhci_ep_ctx *ep_ctx; 617 struct xhci_stream_ctx *st_ctx; 618 struct xhci_virt_ep *ep; 619 620 ep = &vdev->eps[ep_index]; 621 622 if (ep->ep_state & EP_HAS_STREAMS) { 623 st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; 624 return le64_to_cpu(st_ctx->stream_ring); 625 } 626 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 627 return le64_to_cpu(ep_ctx->deq); 628 } 629 630 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci, 631 unsigned int slot_id, unsigned int ep_index, 632 unsigned int stream_id, struct xhci_td *td) 633 { 634 struct xhci_virt_device *dev = xhci->devs[slot_id]; 635 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 636 struct xhci_ring *ep_ring; 637 struct xhci_command *cmd; 638 struct xhci_segment *new_seg; 639 union xhci_trb *new_deq; 640 int new_cycle; 641 dma_addr_t addr; 642 u64 hw_dequeue; 643 bool cycle_found = false; 644 bool td_last_trb_found = false; 645 u32 trb_sct = 0; 646 int ret; 647 648 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 649 ep_index, stream_id); 650 if (!ep_ring) { 651 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n", 652 stream_id); 653 return -ENODEV; 654 } 655 656 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); 657 new_seg = ep_ring->deq_seg; 658 new_deq = ep_ring->dequeue; 659 new_cycle = hw_dequeue & 0x1; 660 661 /* 662 * We want to find the pointer, segment and cycle state of the new trb 663 * (the one after current TD's last_trb). We know the cycle state at 664 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are 665 * found. 666 */ 667 do { 668 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) 669 == (dma_addr_t)(hw_dequeue & ~0xf)) { 670 cycle_found = true; 671 if (td_last_trb_found) 672 break; 673 } 674 if (new_deq == td->last_trb) 675 td_last_trb_found = true; 676 677 if (cycle_found && trb_is_link(new_deq) && 678 link_trb_toggles_cycle(new_deq)) 679 new_cycle ^= 0x1; 680 681 next_trb(xhci, ep_ring, &new_seg, &new_deq); 682 683 /* Search wrapped around, bail out */ 684 if (new_deq == ep->ring->dequeue) { 685 xhci_err(xhci, "Error: Failed finding new dequeue state\n"); 686 return -EINVAL; 687 } 688 689 } while (!cycle_found || !td_last_trb_found); 690 691 /* Don't update the ring cycle state for the producer (us). */ 692 addr = xhci_trb_virt_to_dma(new_seg, new_deq); 693 if (addr == 0) { 694 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n"); 695 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq); 696 return -EINVAL; 697 } 698 699 if ((ep->ep_state & SET_DEQ_PENDING)) { 700 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n", 701 &addr); 702 return -EBUSY; 703 } 704 705 /* This function gets called from contexts where it cannot sleep */ 706 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); 707 if (!cmd) { 708 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr); 709 return -ENOMEM; 710 } 711 712 if (stream_id) 713 trb_sct = SCT_FOR_TRB(SCT_PRI_TR); 714 ret = queue_command(xhci, cmd, 715 lower_32_bits(addr) | trb_sct | new_cycle, 716 upper_32_bits(addr), 717 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) | 718 EP_INDEX_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false); 719 if (ret < 0) { 720 xhci_free_command(xhci, cmd); 721 return ret; 722 } 723 ep->queued_deq_seg = new_seg; 724 ep->queued_deq_ptr = new_deq; 725 726 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 727 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle); 728 729 /* Stop the TD queueing code from ringing the doorbell until 730 * this command completes. The HC won't set the dequeue pointer 731 * if the ring is running, and ringing the doorbell starts the 732 * ring running. 733 */ 734 ep->ep_state |= SET_DEQ_PENDING; 735 xhci_ring_cmd_db(xhci); 736 return 0; 737 } 738 739 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 740 * (The last TRB actually points to the ring enqueue pointer, which is not part 741 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 742 */ 743 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 744 struct xhci_td *td, bool flip_cycle) 745 { 746 struct xhci_segment *seg = td->start_seg; 747 union xhci_trb *trb = td->first_trb; 748 749 while (1) { 750 trb_to_noop(trb, TRB_TR_NOOP); 751 752 /* flip cycle if asked to */ 753 if (flip_cycle && trb != td->first_trb && trb != td->last_trb) 754 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); 755 756 if (trb == td->last_trb) 757 break; 758 759 next_trb(xhci, ep_ring, &seg, &trb); 760 } 761 } 762 763 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 764 struct xhci_td *cur_td, int status) 765 { 766 struct urb *urb = cur_td->urb; 767 struct urb_priv *urb_priv = urb->hcpriv; 768 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); 769 770 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 771 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 772 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 773 if (xhci->quirks & XHCI_AMD_PLL_FIX) 774 usb_amd_quirk_pll_enable(); 775 } 776 } 777 xhci_urb_free_priv(urb_priv); 778 usb_hcd_unlink_urb_from_ep(hcd, urb); 779 trace_xhci_urb_giveback(urb); 780 usb_hcd_giveback_urb(hcd, urb, status); 781 } 782 783 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, 784 struct xhci_ring *ring, struct xhci_td *td) 785 { 786 struct device *dev = xhci_to_hcd(xhci)->self.sysdev; 787 struct xhci_segment *seg = td->bounce_seg; 788 struct urb *urb = td->urb; 789 size_t len; 790 791 if (!ring || !seg || !urb) 792 return; 793 794 if (usb_urb_dir_out(urb)) { 795 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 796 DMA_TO_DEVICE); 797 return; 798 } 799 800 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 801 DMA_FROM_DEVICE); 802 /* for in tranfers we need to copy the data from bounce to sg */ 803 if (urb->num_sgs) { 804 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, 805 seg->bounce_len, seg->bounce_offs); 806 if (len != seg->bounce_len) 807 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n", 808 len, seg->bounce_len); 809 } else { 810 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf, 811 seg->bounce_len); 812 } 813 seg->bounce_len = 0; 814 seg->bounce_offs = 0; 815 } 816 817 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, 818 struct xhci_ring *ep_ring, int status) 819 { 820 struct urb *urb = NULL; 821 822 /* Clean up the endpoint's TD list */ 823 urb = td->urb; 824 825 /* if a bounce buffer was used to align this td then unmap it */ 826 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); 827 828 /* Do one last check of the actual transfer length. 829 * If the host controller said we transferred more data than the buffer 830 * length, urb->actual_length will be a very big number (since it's 831 * unsigned). Play it safe and say we didn't transfer anything. 832 */ 833 if (urb->actual_length > urb->transfer_buffer_length) { 834 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", 835 urb->transfer_buffer_length, urb->actual_length); 836 urb->actual_length = 0; 837 status = 0; 838 } 839 /* TD might be removed from td_list if we are giving back a cancelled URB */ 840 if (!list_empty(&td->td_list)) 841 list_del_init(&td->td_list); 842 /* Giving back a cancelled URB, or if a slated TD completed anyway */ 843 if (!list_empty(&td->cancelled_td_list)) 844 list_del_init(&td->cancelled_td_list); 845 846 inc_td_cnt(urb); 847 /* Giveback the urb when all the tds are completed */ 848 if (last_td_in_urb(td)) { 849 if ((urb->actual_length != urb->transfer_buffer_length && 850 (urb->transfer_flags & URB_SHORT_NOT_OK)) || 851 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) 852 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", 853 urb, urb->actual_length, 854 urb->transfer_buffer_length, status); 855 856 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ 857 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 858 status = 0; 859 xhci_giveback_urb_in_irq(xhci, td, status); 860 } 861 862 return 0; 863 } 864 865 866 /* Complete the cancelled URBs we unlinked from td_list. */ 867 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep) 868 { 869 struct xhci_ring *ring; 870 struct xhci_td *td, *tmp_td; 871 872 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, 873 cancelled_td_list) { 874 875 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); 876 877 if (td->cancel_status == TD_CLEARED) { 878 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", 879 __func__, td->urb); 880 xhci_td_cleanup(ep->xhci, td, ring, td->status); 881 } else { 882 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", 883 __func__, td->urb, td->cancel_status); 884 } 885 if (ep->xhci->xhc_state & XHCI_STATE_DYING) 886 return; 887 } 888 } 889 890 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id, 891 unsigned int ep_index, enum xhci_ep_reset_type reset_type) 892 { 893 struct xhci_command *command; 894 int ret = 0; 895 896 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 897 if (!command) { 898 ret = -ENOMEM; 899 goto done; 900 } 901 902 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n", 903 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft", 904 ep_index, slot_id); 905 906 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); 907 done: 908 if (ret) 909 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n", 910 slot_id, ep_index, ret); 911 return ret; 912 } 913 914 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci, 915 struct xhci_virt_ep *ep, 916 struct xhci_td *td, 917 enum xhci_ep_reset_type reset_type) 918 { 919 unsigned int slot_id = ep->vdev->slot_id; 920 int err; 921 922 /* 923 * Avoid resetting endpoint if link is inactive. Can cause host hang. 924 * Device will be reset soon to recover the link so don't do anything 925 */ 926 if (ep->vdev->flags & VDEV_PORT_ERROR) 927 return -ENODEV; 928 929 /* add td to cancelled list and let reset ep handler take care of it */ 930 if (reset_type == EP_HARD_RESET) { 931 ep->ep_state |= EP_HARD_CLEAR_TOGGLE; 932 if (td && list_empty(&td->cancelled_td_list)) { 933 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); 934 td->cancel_status = TD_HALTED; 935 } 936 } 937 938 if (ep->ep_state & EP_HALTED) { 939 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n", 940 ep->ep_index); 941 return 0; 942 } 943 944 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type); 945 if (err) 946 return err; 947 948 ep->ep_state |= EP_HALTED; 949 950 xhci_ring_cmd_db(xhci); 951 952 return 0; 953 } 954 955 /* 956 * Fix up the ep ring first, so HW stops executing cancelled TDs. 957 * We have the xHCI lock, so nothing can modify this list until we drop it. 958 * We're also in the event handler, so we can't get re-interrupted if another 959 * Stop Endpoint command completes. 960 * 961 * only call this when ring is not in a running state 962 */ 963 964 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep) 965 { 966 struct xhci_hcd *xhci; 967 struct xhci_td *td = NULL; 968 struct xhci_td *tmp_td = NULL; 969 struct xhci_td *cached_td = NULL; 970 struct xhci_ring *ring; 971 u64 hw_deq; 972 unsigned int slot_id = ep->vdev->slot_id; 973 int err; 974 975 xhci = ep->xhci; 976 977 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { 978 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 979 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p", 980 (unsigned long long)xhci_trb_virt_to_dma( 981 td->start_seg, td->first_trb), 982 td->urb->stream_id, td->urb); 983 list_del_init(&td->td_list); 984 ring = xhci_urb_to_transfer_ring(xhci, td->urb); 985 if (!ring) { 986 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n", 987 td->urb, td->urb->stream_id); 988 continue; 989 } 990 /* 991 * If a ring stopped on the TD we need to cancel then we have to 992 * move the xHC endpoint ring dequeue pointer past this TD. 993 * Rings halted due to STALL may show hw_deq is past the stalled 994 * TD, but still require a set TR Deq command to flush xHC cache. 995 */ 996 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index, 997 td->urb->stream_id); 998 hw_deq &= ~0xf; 999 1000 if (td->cancel_status == TD_HALTED || trb_in_td(xhci, td, hw_deq, false)) { 1001 switch (td->cancel_status) { 1002 case TD_CLEARED: /* TD is already no-op */ 1003 case TD_CLEARING_CACHE: /* set TR deq command already queued */ 1004 break; 1005 case TD_DIRTY: /* TD is cached, clear it */ 1006 case TD_HALTED: 1007 case TD_CLEARING_CACHE_DEFERRED: 1008 if (cached_td) { 1009 if (cached_td->urb->stream_id != td->urb->stream_id) { 1010 /* Multiple streams case, defer move dq */ 1011 xhci_dbg(xhci, 1012 "Move dq deferred: stream %u URB %p\n", 1013 td->urb->stream_id, td->urb); 1014 td->cancel_status = TD_CLEARING_CACHE_DEFERRED; 1015 break; 1016 } 1017 1018 /* Should never happen, but clear the TD if it does */ 1019 xhci_warn(xhci, 1020 "Found multiple active URBs %p and %p in stream %u?\n", 1021 td->urb, cached_td->urb, 1022 td->urb->stream_id); 1023 td_to_noop(xhci, ring, cached_td, false); 1024 cached_td->cancel_status = TD_CLEARED; 1025 } 1026 1027 td->cancel_status = TD_CLEARING_CACHE; 1028 cached_td = td; 1029 break; 1030 } 1031 } else { 1032 td_to_noop(xhci, ring, td, false); 1033 td->cancel_status = TD_CLEARED; 1034 } 1035 } 1036 1037 /* If there's no need to move the dequeue pointer then we're done */ 1038 if (!cached_td) 1039 return 0; 1040 1041 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index, 1042 cached_td->urb->stream_id, 1043 cached_td); 1044 if (err) { 1045 /* Failed to move past cached td, just set cached TDs to no-op */ 1046 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { 1047 /* 1048 * Deferred TDs need to have the deq pointer set after the above command 1049 * completes, so if that failed we just give up on all of them (and 1050 * complain loudly since this could cause issues due to caching). 1051 */ 1052 if (td->cancel_status != TD_CLEARING_CACHE && 1053 td->cancel_status != TD_CLEARING_CACHE_DEFERRED) 1054 continue; 1055 xhci_warn(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n", 1056 td->urb); 1057 td_to_noop(xhci, ring, td, false); 1058 td->cancel_status = TD_CLEARED; 1059 } 1060 } 1061 return 0; 1062 } 1063 1064 /* 1065 * Returns the TD the endpoint ring halted on. 1066 * Only call for non-running rings without streams. 1067 */ 1068 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep) 1069 { 1070 struct xhci_td *td; 1071 u64 hw_deq; 1072 1073 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */ 1074 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0); 1075 hw_deq &= ~0xf; 1076 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list); 1077 if (trb_in_td(ep->xhci, td, hw_deq, false)) 1078 return td; 1079 } 1080 return NULL; 1081 } 1082 1083 /* 1084 * When we get a command completion for a Stop Endpoint Command, we need to 1085 * unlink any cancelled TDs from the ring. There are two ways to do that: 1086 * 1087 * 1. If the HW was in the middle of processing the TD that needs to be 1088 * cancelled, then we must move the ring's dequeue pointer past the last TRB 1089 * in the TD with a Set Dequeue Pointer Command. 1090 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 1091 * bit cleared) so that the HW will skip over them. 1092 */ 1093 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, 1094 union xhci_trb *trb, u32 comp_code) 1095 { 1096 unsigned int ep_index; 1097 struct xhci_virt_ep *ep; 1098 struct xhci_ep_ctx *ep_ctx; 1099 struct xhci_td *td = NULL; 1100 enum xhci_ep_reset_type reset_type; 1101 struct xhci_command *command; 1102 int err; 1103 1104 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { 1105 if (!xhci->devs[slot_id]) 1106 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n", 1107 slot_id); 1108 return; 1109 } 1110 1111 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1112 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1113 if (!ep) 1114 return; 1115 1116 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1117 1118 trace_xhci_handle_cmd_stop_ep(ep_ctx); 1119 1120 if (comp_code == COMP_CONTEXT_STATE_ERROR) { 1121 /* 1122 * If stop endpoint command raced with a halting endpoint we need to 1123 * reset the host side endpoint first. 1124 * If the TD we halted on isn't cancelled the TD should be given back 1125 * with a proper error code, and the ring dequeue moved past the TD. 1126 * If streams case we can't find hw_deq, or the TD we halted on so do a 1127 * soft reset. 1128 * 1129 * Proper error code is unknown here, it would be -EPIPE if device side 1130 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error) 1131 * We use -EPROTO, if device is stalled it should return a stall error on 1132 * next transfer, which then will return -EPIPE, and device side stall is 1133 * noted and cleared by class driver. 1134 */ 1135 switch (GET_EP_CTX_STATE(ep_ctx)) { 1136 case EP_STATE_HALTED: 1137 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n"); 1138 if (ep->ep_state & EP_HAS_STREAMS) { 1139 reset_type = EP_SOFT_RESET; 1140 } else { 1141 reset_type = EP_HARD_RESET; 1142 td = find_halted_td(ep); 1143 if (td) 1144 td->status = -EPROTO; 1145 } 1146 /* reset ep, reset handler cleans up cancelled tds */ 1147 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type); 1148 if (err) 1149 break; 1150 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1151 return; 1152 case EP_STATE_STOPPED: 1153 /* 1154 * NEC uPD720200 sometimes sets this state and fails with 1155 * Context Error while continuing to process TRBs. 1156 * Be conservative and trust EP_CTX_STATE on other chips. 1157 */ 1158 if (!(xhci->quirks & XHCI_NEC_HOST)) 1159 break; 1160 fallthrough; 1161 case EP_STATE_RUNNING: 1162 /* Race, HW handled stop ep cmd before ep was running */ 1163 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n"); 1164 1165 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 1166 if (!command) { 1167 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1168 return; 1169 } 1170 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0); 1171 xhci_ring_cmd_db(xhci); 1172 1173 return; 1174 default: 1175 break; 1176 } 1177 } 1178 1179 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */ 1180 xhci_invalidate_cancelled_tds(ep); 1181 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1182 1183 /* Otherwise ring the doorbell(s) to restart queued transfers */ 1184 xhci_giveback_invalidated_tds(ep); 1185 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1186 } 1187 1188 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) 1189 { 1190 struct xhci_td *cur_td; 1191 struct xhci_td *tmp; 1192 1193 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { 1194 list_del_init(&cur_td->td_list); 1195 1196 if (!list_empty(&cur_td->cancelled_td_list)) 1197 list_del_init(&cur_td->cancelled_td_list); 1198 1199 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); 1200 1201 inc_td_cnt(cur_td->urb); 1202 if (last_td_in_urb(cur_td)) 1203 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 1204 } 1205 } 1206 1207 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, 1208 int slot_id, int ep_index) 1209 { 1210 struct xhci_td *cur_td; 1211 struct xhci_td *tmp; 1212 struct xhci_virt_ep *ep; 1213 struct xhci_ring *ring; 1214 1215 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1216 if (!ep) 1217 return; 1218 1219 if ((ep->ep_state & EP_HAS_STREAMS) || 1220 (ep->ep_state & EP_GETTING_NO_STREAMS)) { 1221 int stream_id; 1222 1223 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 1224 stream_id++) { 1225 ring = ep->stream_info->stream_rings[stream_id]; 1226 if (!ring) 1227 continue; 1228 1229 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1230 "Killing URBs for slot ID %u, ep index %u, stream %u", 1231 slot_id, ep_index, stream_id); 1232 xhci_kill_ring_urbs(xhci, ring); 1233 } 1234 } else { 1235 ring = ep->ring; 1236 if (!ring) 1237 return; 1238 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1239 "Killing URBs for slot ID %u, ep index %u", 1240 slot_id, ep_index); 1241 xhci_kill_ring_urbs(xhci, ring); 1242 } 1243 1244 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, 1245 cancelled_td_list) { 1246 list_del_init(&cur_td->cancelled_td_list); 1247 inc_td_cnt(cur_td->urb); 1248 1249 if (last_td_in_urb(cur_td)) 1250 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 1251 } 1252 } 1253 1254 /* 1255 * host controller died, register read returns 0xffffffff 1256 * Complete pending commands, mark them ABORTED. 1257 * URBs need to be given back as usb core might be waiting with device locks 1258 * held for the URBs to finish during device disconnect, blocking host remove. 1259 * 1260 * Call with xhci->lock held. 1261 * lock is relased and re-acquired while giving back urb. 1262 */ 1263 void xhci_hc_died(struct xhci_hcd *xhci) 1264 { 1265 int i, j; 1266 1267 if (xhci->xhc_state & XHCI_STATE_DYING) 1268 return; 1269 1270 xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); 1271 xhci->xhc_state |= XHCI_STATE_DYING; 1272 1273 xhci_cleanup_command_queue(xhci); 1274 1275 /* return any pending urbs, remove may be waiting for them */ 1276 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 1277 if (!xhci->devs[i]) 1278 continue; 1279 for (j = 0; j < 31; j++) 1280 xhci_kill_endpoint_urbs(xhci, i, j); 1281 } 1282 1283 /* inform usb core hc died if PCI remove isn't already handling it */ 1284 if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) 1285 usb_hc_died(xhci_to_hcd(xhci)); 1286 } 1287 1288 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 1289 struct xhci_virt_device *dev, 1290 struct xhci_ring *ep_ring, 1291 unsigned int ep_index) 1292 { 1293 union xhci_trb *dequeue_temp; 1294 1295 dequeue_temp = ep_ring->dequeue; 1296 1297 /* If we get two back-to-back stalls, and the first stalled transfer 1298 * ends just before a link TRB, the dequeue pointer will be left on 1299 * the link TRB by the code in the while loop. So we have to update 1300 * the dequeue pointer one segment further, or we'll jump off 1301 * the segment into la-la-land. 1302 */ 1303 if (trb_is_link(ep_ring->dequeue)) { 1304 ep_ring->deq_seg = ep_ring->deq_seg->next; 1305 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1306 } 1307 1308 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 1309 /* We have more usable TRBs */ 1310 ep_ring->dequeue++; 1311 if (trb_is_link(ep_ring->dequeue)) { 1312 if (ep_ring->dequeue == 1313 dev->eps[ep_index].queued_deq_ptr) 1314 break; 1315 ep_ring->deq_seg = ep_ring->deq_seg->next; 1316 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1317 } 1318 if (ep_ring->dequeue == dequeue_temp) { 1319 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 1320 break; 1321 } 1322 } 1323 } 1324 1325 /* 1326 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 1327 * we need to clear the set deq pending flag in the endpoint ring state, so that 1328 * the TD queueing code can ring the doorbell again. We also need to ring the 1329 * endpoint doorbell to restart the ring, but only if there aren't more 1330 * cancellations pending. 1331 */ 1332 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, 1333 union xhci_trb *trb, u32 cmd_comp_code) 1334 { 1335 unsigned int ep_index; 1336 unsigned int stream_id; 1337 struct xhci_ring *ep_ring; 1338 struct xhci_virt_ep *ep; 1339 struct xhci_ep_ctx *ep_ctx; 1340 struct xhci_slot_ctx *slot_ctx; 1341 struct xhci_td *td, *tmp_td; 1342 bool deferred = false; 1343 1344 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1345 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 1346 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1347 if (!ep) 1348 return; 1349 1350 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id); 1351 if (!ep_ring) { 1352 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", 1353 stream_id); 1354 /* XXX: Harmless??? */ 1355 goto cleanup; 1356 } 1357 1358 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1359 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); 1360 trace_xhci_handle_cmd_set_deq(slot_ctx); 1361 trace_xhci_handle_cmd_set_deq_ep(ep_ctx); 1362 1363 if (cmd_comp_code != COMP_SUCCESS) { 1364 unsigned int ep_state; 1365 unsigned int slot_state; 1366 1367 switch (cmd_comp_code) { 1368 case COMP_TRB_ERROR: 1369 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); 1370 break; 1371 case COMP_CONTEXT_STATE_ERROR: 1372 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); 1373 ep_state = GET_EP_CTX_STATE(ep_ctx); 1374 slot_state = le32_to_cpu(slot_ctx->dev_state); 1375 slot_state = GET_SLOT_STATE(slot_state); 1376 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1377 "Slot state = %u, EP state = %u", 1378 slot_state, ep_state); 1379 break; 1380 case COMP_SLOT_NOT_ENABLED_ERROR: 1381 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", 1382 slot_id); 1383 break; 1384 default: 1385 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", 1386 cmd_comp_code); 1387 break; 1388 } 1389 /* OK what do we do now? The endpoint state is hosed, and we 1390 * should never get to this point if the synchronization between 1391 * queueing, and endpoint state are correct. This might happen 1392 * if the device gets disconnected after we've finished 1393 * cancelling URBs, which might not be an error... 1394 */ 1395 } else { 1396 u64 deq; 1397 /* 4.6.10 deq ptr is written to the stream ctx for streams */ 1398 if (ep->ep_state & EP_HAS_STREAMS) { 1399 struct xhci_stream_ctx *ctx = 1400 &ep->stream_info->stream_ctx_array[stream_id]; 1401 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; 1402 1403 /* 1404 * Cadence xHCI controllers store some endpoint state 1405 * information within Rsvd0 fields of Stream Endpoint 1406 * context. This field is not cleared during Set TR 1407 * Dequeue Pointer command which causes XDMA to skip 1408 * over transfer ring and leads to data loss on stream 1409 * pipe. 1410 * To fix this issue driver must clear Rsvd0 field. 1411 */ 1412 if (xhci->quirks & XHCI_CDNS_SCTX_QUIRK) { 1413 ctx->reserved[0] = 0; 1414 ctx->reserved[1] = 0; 1415 } 1416 } else { 1417 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; 1418 } 1419 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1420 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); 1421 if (xhci_trb_virt_to_dma(ep->queued_deq_seg, 1422 ep->queued_deq_ptr) == deq) { 1423 /* Update the ring's dequeue segment and dequeue pointer 1424 * to reflect the new position. 1425 */ 1426 update_ring_for_set_deq_completion(xhci, ep->vdev, 1427 ep_ring, ep_index); 1428 } else { 1429 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); 1430 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1431 ep->queued_deq_seg, ep->queued_deq_ptr); 1432 } 1433 } 1434 /* HW cached TDs cleared from cache, give them back */ 1435 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, 1436 cancelled_td_list) { 1437 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); 1438 if (td->cancel_status == TD_CLEARING_CACHE) { 1439 td->cancel_status = TD_CLEARED; 1440 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", 1441 __func__, td->urb); 1442 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status); 1443 } else if (td->cancel_status == TD_CLEARING_CACHE_DEFERRED) { 1444 deferred = true; 1445 } else { 1446 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", 1447 __func__, td->urb, td->cancel_status); 1448 } 1449 } 1450 cleanup: 1451 ep->ep_state &= ~SET_DEQ_PENDING; 1452 ep->queued_deq_seg = NULL; 1453 ep->queued_deq_ptr = NULL; 1454 1455 if (deferred) { 1456 /* We have more streams to clear */ 1457 xhci_dbg(ep->xhci, "%s: Pending TDs to clear, continuing with invalidation\n", 1458 __func__); 1459 xhci_invalidate_cancelled_tds(ep); 1460 } else { 1461 /* Restart any rings with pending URBs */ 1462 xhci_dbg(ep->xhci, "%s: All TDs cleared, ring doorbell\n", __func__); 1463 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1464 } 1465 } 1466 1467 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, 1468 union xhci_trb *trb, u32 cmd_comp_code) 1469 { 1470 struct xhci_virt_ep *ep; 1471 struct xhci_ep_ctx *ep_ctx; 1472 unsigned int ep_index; 1473 1474 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1475 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1476 if (!ep) 1477 return; 1478 1479 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1480 trace_xhci_handle_cmd_reset_ep(ep_ctx); 1481 1482 /* This command will only fail if the endpoint wasn't halted, 1483 * but we don't care. 1484 */ 1485 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, 1486 "Ignoring reset ep completion code of %u", cmd_comp_code); 1487 1488 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */ 1489 xhci_invalidate_cancelled_tds(ep); 1490 1491 /* Clear our internal halted state */ 1492 ep->ep_state &= ~EP_HALTED; 1493 1494 xhci_giveback_invalidated_tds(ep); 1495 1496 /* if this was a soft reset, then restart */ 1497 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) 1498 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1499 } 1500 1501 static void xhci_handle_cmd_enable_slot(int slot_id, struct xhci_command *command, 1502 u32 cmd_comp_code) 1503 { 1504 if (cmd_comp_code == COMP_SUCCESS) 1505 command->slot_id = slot_id; 1506 else 1507 command->slot_id = 0; 1508 } 1509 1510 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) 1511 { 1512 struct xhci_virt_device *virt_dev; 1513 struct xhci_slot_ctx *slot_ctx; 1514 1515 virt_dev = xhci->devs[slot_id]; 1516 if (!virt_dev) 1517 return; 1518 1519 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); 1520 trace_xhci_handle_cmd_disable_slot(slot_ctx); 1521 1522 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1523 /* Delete default control endpoint resources */ 1524 xhci_free_device_endpoint_resources(xhci, virt_dev, true); 1525 } 1526 1527 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id) 1528 { 1529 struct xhci_virt_device *virt_dev; 1530 struct xhci_input_control_ctx *ctrl_ctx; 1531 struct xhci_ep_ctx *ep_ctx; 1532 unsigned int ep_index; 1533 u32 add_flags; 1534 1535 /* 1536 * Configure endpoint commands can come from the USB core configuration 1537 * or alt setting changes, or when streams were being configured. 1538 */ 1539 1540 virt_dev = xhci->devs[slot_id]; 1541 if (!virt_dev) 1542 return; 1543 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 1544 if (!ctrl_ctx) { 1545 xhci_warn(xhci, "Could not get input context, bad type.\n"); 1546 return; 1547 } 1548 1549 add_flags = le32_to_cpu(ctrl_ctx->add_flags); 1550 1551 /* Input ctx add_flags are the endpoint index plus one */ 1552 ep_index = xhci_last_valid_endpoint(add_flags) - 1; 1553 1554 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); 1555 trace_xhci_handle_cmd_config_ep(ep_ctx); 1556 1557 return; 1558 } 1559 1560 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) 1561 { 1562 struct xhci_virt_device *vdev; 1563 struct xhci_slot_ctx *slot_ctx; 1564 1565 vdev = xhci->devs[slot_id]; 1566 if (!vdev) 1567 return; 1568 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1569 trace_xhci_handle_cmd_addr_dev(slot_ctx); 1570 } 1571 1572 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id) 1573 { 1574 struct xhci_virt_device *vdev; 1575 struct xhci_slot_ctx *slot_ctx; 1576 1577 vdev = xhci->devs[slot_id]; 1578 if (!vdev) { 1579 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n", 1580 slot_id); 1581 return; 1582 } 1583 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1584 trace_xhci_handle_cmd_reset_dev(slot_ctx); 1585 1586 xhci_dbg(xhci, "Completed reset device command.\n"); 1587 } 1588 1589 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, 1590 struct xhci_event_cmd *event) 1591 { 1592 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1593 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); 1594 return; 1595 } 1596 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1597 "NEC firmware version %2x.%02x", 1598 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1599 NEC_FW_MINOR(le32_to_cpu(event->status))); 1600 } 1601 1602 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) 1603 { 1604 list_del(&cmd->cmd_list); 1605 1606 if (cmd->completion) { 1607 cmd->status = status; 1608 complete(cmd->completion); 1609 } else { 1610 kfree(cmd); 1611 } 1612 } 1613 1614 void xhci_cleanup_command_queue(struct xhci_hcd *xhci) 1615 { 1616 struct xhci_command *cur_cmd, *tmp_cmd; 1617 xhci->current_cmd = NULL; 1618 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) 1619 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); 1620 } 1621 1622 void xhci_handle_command_timeout(struct work_struct *work) 1623 { 1624 struct xhci_hcd *xhci; 1625 unsigned long flags; 1626 char str[XHCI_MSG_MAX]; 1627 u64 hw_ring_state; 1628 u32 cmd_field3; 1629 u32 usbsts; 1630 1631 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); 1632 1633 spin_lock_irqsave(&xhci->lock, flags); 1634 1635 /* 1636 * If timeout work is pending, or current_cmd is NULL, it means we 1637 * raced with command completion. Command is handled so just return. 1638 */ 1639 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { 1640 spin_unlock_irqrestore(&xhci->lock, flags); 1641 return; 1642 } 1643 1644 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]); 1645 usbsts = readl(&xhci->op_regs->status); 1646 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts)); 1647 1648 /* Bail out and tear down xhci if a stop endpoint command failed */ 1649 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) { 1650 struct xhci_virt_ep *ep; 1651 1652 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n"); 1653 1654 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3), 1655 TRB_TO_EP_INDEX(cmd_field3)); 1656 if (ep) 1657 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1658 1659 xhci_halt(xhci); 1660 xhci_hc_died(xhci); 1661 goto time_out_completed; 1662 } 1663 1664 /* mark this command to be cancelled */ 1665 xhci->current_cmd->status = COMP_COMMAND_ABORTED; 1666 1667 /* Make sure command ring is running before aborting it */ 1668 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1669 if (hw_ring_state == ~(u64)0) { 1670 xhci_hc_died(xhci); 1671 goto time_out_completed; 1672 } 1673 1674 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && 1675 (hw_ring_state & CMD_RING_RUNNING)) { 1676 /* Prevent new doorbell, and start command abort */ 1677 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 1678 xhci_dbg(xhci, "Command timeout\n"); 1679 xhci_abort_cmd_ring(xhci, flags); 1680 goto time_out_completed; 1681 } 1682 1683 /* host removed. Bail out */ 1684 if (xhci->xhc_state & XHCI_STATE_REMOVING) { 1685 xhci_dbg(xhci, "host removed, ring start fail?\n"); 1686 xhci_cleanup_command_queue(xhci); 1687 1688 goto time_out_completed; 1689 } 1690 1691 /* command timeout on stopped ring, ring can't be aborted */ 1692 xhci_dbg(xhci, "Command timeout on stopped ring\n"); 1693 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); 1694 1695 time_out_completed: 1696 spin_unlock_irqrestore(&xhci->lock, flags); 1697 return; 1698 } 1699 1700 static void handle_cmd_completion(struct xhci_hcd *xhci, 1701 struct xhci_event_cmd *event) 1702 { 1703 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1704 u64 cmd_dma; 1705 dma_addr_t cmd_dequeue_dma; 1706 u32 cmd_comp_code; 1707 union xhci_trb *cmd_trb; 1708 struct xhci_command *cmd; 1709 u32 cmd_type; 1710 1711 if (slot_id >= MAX_HC_SLOTS) { 1712 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); 1713 return; 1714 } 1715 1716 cmd_dma = le64_to_cpu(event->cmd_trb); 1717 cmd_trb = xhci->cmd_ring->dequeue; 1718 1719 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); 1720 1721 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1722 cmd_trb); 1723 /* 1724 * Check whether the completion event is for our internal kept 1725 * command. 1726 */ 1727 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { 1728 xhci_warn(xhci, 1729 "ERROR mismatched command completion event\n"); 1730 return; 1731 } 1732 1733 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); 1734 1735 cancel_delayed_work(&xhci->cmd_timer); 1736 1737 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); 1738 1739 /* If CMD ring stopped we own the trbs between enqueue and dequeue */ 1740 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { 1741 complete_all(&xhci->cmd_ring_stop_completion); 1742 return; 1743 } 1744 1745 if (cmd->command_trb != xhci->cmd_ring->dequeue) { 1746 xhci_err(xhci, 1747 "Command completion event does not match command\n"); 1748 return; 1749 } 1750 1751 /* 1752 * Host aborted the command ring, check if the current command was 1753 * supposed to be aborted, otherwise continue normally. 1754 * The command ring is stopped now, but the xHC will issue a Command 1755 * Ring Stopped event which will cause us to restart it. 1756 */ 1757 if (cmd_comp_code == COMP_COMMAND_ABORTED) { 1758 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1759 if (cmd->status == COMP_COMMAND_ABORTED) { 1760 if (xhci->current_cmd == cmd) 1761 xhci->current_cmd = NULL; 1762 goto event_handled; 1763 } 1764 } 1765 1766 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); 1767 switch (cmd_type) { 1768 case TRB_ENABLE_SLOT: 1769 xhci_handle_cmd_enable_slot(slot_id, cmd, cmd_comp_code); 1770 break; 1771 case TRB_DISABLE_SLOT: 1772 xhci_handle_cmd_disable_slot(xhci, slot_id); 1773 break; 1774 case TRB_CONFIG_EP: 1775 if (!cmd->completion) 1776 xhci_handle_cmd_config_ep(xhci, slot_id); 1777 break; 1778 case TRB_EVAL_CONTEXT: 1779 break; 1780 case TRB_ADDR_DEV: 1781 xhci_handle_cmd_addr_dev(xhci, slot_id); 1782 break; 1783 case TRB_STOP_RING: 1784 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1785 le32_to_cpu(cmd_trb->generic.field[3]))); 1786 if (!cmd->completion) 1787 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, 1788 cmd_comp_code); 1789 break; 1790 case TRB_SET_DEQ: 1791 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1792 le32_to_cpu(cmd_trb->generic.field[3]))); 1793 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); 1794 break; 1795 case TRB_CMD_NOOP: 1796 /* Is this an aborted command turned to NO-OP? */ 1797 if (cmd->status == COMP_COMMAND_RING_STOPPED) 1798 cmd_comp_code = COMP_COMMAND_RING_STOPPED; 1799 break; 1800 case TRB_RESET_EP: 1801 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1802 le32_to_cpu(cmd_trb->generic.field[3]))); 1803 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); 1804 break; 1805 case TRB_RESET_DEV: 1806 /* SLOT_ID field in reset device cmd completion event TRB is 0. 1807 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) 1808 */ 1809 slot_id = TRB_TO_SLOT_ID( 1810 le32_to_cpu(cmd_trb->generic.field[3])); 1811 xhci_handle_cmd_reset_dev(xhci, slot_id); 1812 break; 1813 case TRB_NEC_GET_FW: 1814 xhci_handle_cmd_nec_get_fw(xhci, event); 1815 break; 1816 default: 1817 /* Skip over unknown commands on the event ring */ 1818 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); 1819 break; 1820 } 1821 1822 /* restart timer if this wasn't the last command */ 1823 if (!list_is_singular(&xhci->cmd_list)) { 1824 xhci->current_cmd = list_first_entry(&cmd->cmd_list, 1825 struct xhci_command, cmd_list); 1826 xhci_mod_cmd_timer(xhci); 1827 } else if (xhci->current_cmd == cmd) { 1828 xhci->current_cmd = NULL; 1829 } 1830 1831 event_handled: 1832 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); 1833 1834 inc_deq(xhci, xhci->cmd_ring); 1835 } 1836 1837 static void handle_vendor_event(struct xhci_hcd *xhci, 1838 union xhci_trb *event, u32 trb_type) 1839 { 1840 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1841 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1842 handle_cmd_completion(xhci, &event->event_cmd); 1843 } 1844 1845 static void handle_device_notification(struct xhci_hcd *xhci, 1846 union xhci_trb *event) 1847 { 1848 u32 slot_id; 1849 struct usb_device *udev; 1850 1851 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); 1852 if (!xhci->devs[slot_id]) { 1853 xhci_warn(xhci, "Device Notification event for " 1854 "unused slot %u\n", slot_id); 1855 return; 1856 } 1857 1858 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1859 slot_id); 1860 udev = xhci->devs[slot_id]->udev; 1861 if (udev && udev->parent) 1862 usb_wakeup_notification(udev->parent, udev->portnum); 1863 } 1864 1865 /* 1866 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI 1867 * Controller. 1868 * As per ThunderX2errata-129 USB 2 device may come up as USB 1 1869 * If a connection to a USB 1 device is followed by another connection 1870 * to a USB 2 device. 1871 * 1872 * Reset the PHY after the USB device is disconnected if device speed 1873 * is less than HCD_USB3. 1874 * Retry the reset sequence max of 4 times checking the PLL lock status. 1875 * 1876 */ 1877 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) 1878 { 1879 struct usb_hcd *hcd = xhci_to_hcd(xhci); 1880 u32 pll_lock_check; 1881 u32 retry_count = 4; 1882 1883 do { 1884 /* Assert PHY reset */ 1885 writel(0x6F, hcd->regs + 0x1048); 1886 udelay(10); 1887 /* De-assert the PHY reset */ 1888 writel(0x7F, hcd->regs + 0x1048); 1889 udelay(200); 1890 pll_lock_check = readl(hcd->regs + 0x1070); 1891 } while (!(pll_lock_check & 0x1) && --retry_count); 1892 } 1893 1894 static void handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event) 1895 { 1896 struct usb_hcd *hcd; 1897 u32 port_id; 1898 u32 portsc, cmd_reg; 1899 int max_ports; 1900 unsigned int hcd_portnum; 1901 struct xhci_bus_state *bus_state; 1902 bool bogus_port_status = false; 1903 struct xhci_port *port; 1904 1905 /* Port status change events always have a successful completion code */ 1906 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) 1907 xhci_warn(xhci, 1908 "WARN: xHC returned failed port status event\n"); 1909 1910 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1911 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1912 1913 if ((port_id <= 0) || (port_id > max_ports)) { 1914 xhci_warn(xhci, "Port change event with invalid port ID %d\n", 1915 port_id); 1916 return; 1917 } 1918 1919 port = &xhci->hw_ports[port_id - 1]; 1920 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { 1921 xhci_warn(xhci, "Port change event, no port for port ID %u\n", 1922 port_id); 1923 bogus_port_status = true; 1924 goto cleanup; 1925 } 1926 1927 /* We might get interrupts after shared_hcd is removed */ 1928 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { 1929 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); 1930 bogus_port_status = true; 1931 goto cleanup; 1932 } 1933 1934 hcd = port->rhub->hcd; 1935 bus_state = &port->rhub->bus_state; 1936 hcd_portnum = port->hcd_portnum; 1937 portsc = readl(port->addr); 1938 1939 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", 1940 hcd->self.busnum, hcd_portnum + 1, port_id, portsc); 1941 1942 trace_xhci_handle_port_status(port, portsc); 1943 1944 if (hcd->state == HC_STATE_SUSPENDED) { 1945 xhci_dbg(xhci, "resume root hub\n"); 1946 usb_hcd_resume_root_hub(hcd); 1947 } 1948 1949 if (hcd->speed >= HCD_USB3 && 1950 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) { 1951 if (port->slot_id && xhci->devs[port->slot_id]) 1952 xhci->devs[port->slot_id]->flags |= VDEV_PORT_ERROR; 1953 } 1954 1955 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { 1956 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1957 1958 cmd_reg = readl(&xhci->op_regs->command); 1959 if (!(cmd_reg & CMD_RUN)) { 1960 xhci_warn(xhci, "xHC is not running.\n"); 1961 goto cleanup; 1962 } 1963 1964 if (DEV_SUPERSPEED_ANY(portsc)) { 1965 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1966 /* Set a flag to say the port signaled remote wakeup, 1967 * so we can tell the difference between the end of 1968 * device and host initiated resume. 1969 */ 1970 bus_state->port_remote_wakeup |= 1 << hcd_portnum; 1971 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1972 usb_hcd_start_port_resume(&hcd->self, hcd_portnum); 1973 xhci_set_link_state(xhci, port, XDEV_U0); 1974 /* Need to wait until the next link state change 1975 * indicates the device is actually in U0. 1976 */ 1977 bogus_port_status = true; 1978 goto cleanup; 1979 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { 1980 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1981 port->resume_timestamp = jiffies + 1982 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1983 set_bit(hcd_portnum, &bus_state->resuming_ports); 1984 /* Do the rest in GetPortStatus after resume time delay. 1985 * Avoid polling roothub status before that so that a 1986 * usb device auto-resume latency around ~40ms. 1987 */ 1988 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1989 mod_timer(&hcd->rh_timer, 1990 port->resume_timestamp); 1991 usb_hcd_start_port_resume(&hcd->self, hcd_portnum); 1992 bogus_port_status = true; 1993 } 1994 } 1995 1996 if ((portsc & PORT_PLC) && 1997 DEV_SUPERSPEED_ANY(portsc) && 1998 ((portsc & PORT_PLS_MASK) == XDEV_U0 || 1999 (portsc & PORT_PLS_MASK) == XDEV_U1 || 2000 (portsc & PORT_PLS_MASK) == XDEV_U2)) { 2001 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 2002 complete(&port->u3exit_done); 2003 /* We've just brought the device into U0/1/2 through either the 2004 * Resume state after a device remote wakeup, or through the 2005 * U3Exit state after a host-initiated resume. If it's a device 2006 * initiated remote wake, don't pass up the link state change, 2007 * so the roothub behavior is consistent with external 2008 * USB 3.0 hub behavior. 2009 */ 2010 if (port->slot_id && xhci->devs[port->slot_id]) 2011 xhci_ring_device(xhci, port->slot_id); 2012 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { 2013 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 2014 usb_wakeup_notification(hcd->self.root_hub, 2015 hcd_portnum + 1); 2016 bogus_port_status = true; 2017 goto cleanup; 2018 } 2019 } 2020 2021 /* 2022 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or 2023 * RExit to a disconnect state). If so, let the driver know it's 2024 * out of the RExit state. 2025 */ 2026 if (hcd->speed < HCD_USB3 && port->rexit_active) { 2027 complete(&port->rexit_done); 2028 port->rexit_active = false; 2029 bogus_port_status = true; 2030 goto cleanup; 2031 } 2032 2033 if (hcd->speed < HCD_USB3) { 2034 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 2035 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && 2036 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) 2037 xhci_cavium_reset_phy_quirk(xhci); 2038 } 2039 2040 cleanup: 2041 2042 /* Don't make the USB core poll the roothub if we got a bad port status 2043 * change event. Besides, at that point we can't tell which roothub 2044 * (USB 2.0 or USB 3.0) to kick. 2045 */ 2046 if (bogus_port_status) 2047 return; 2048 2049 /* 2050 * xHCI port-status-change events occur when the "or" of all the 2051 * status-change bits in the portsc register changes from 0 to 1. 2052 * New status changes won't cause an event if any other change 2053 * bits are still set. When an event occurs, switch over to 2054 * polling to avoid losing status changes. 2055 */ 2056 xhci_dbg(xhci, "%s: starting usb%d port polling.\n", 2057 __func__, hcd->self.busnum); 2058 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 2059 spin_unlock(&xhci->lock); 2060 /* Pass this up to the core */ 2061 usb_hcd_poll_rh_status(hcd); 2062 spin_lock(&xhci->lock); 2063 } 2064 2065 /* 2066 * If the suspect DMA address is a TRB in this TD, this function returns that 2067 * TRB's segment. Otherwise it returns 0. 2068 */ 2069 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, struct xhci_td *td, dma_addr_t suspect_dma, 2070 bool debug) 2071 { 2072 dma_addr_t start_dma; 2073 dma_addr_t end_seg_dma; 2074 dma_addr_t end_trb_dma; 2075 struct xhci_segment *cur_seg; 2076 2077 start_dma = xhci_trb_virt_to_dma(td->start_seg, td->first_trb); 2078 cur_seg = td->start_seg; 2079 2080 do { 2081 if (start_dma == 0) 2082 return NULL; 2083 /* We may get an event for a Link TRB in the middle of a TD */ 2084 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 2085 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 2086 /* If the end TRB isn't in this segment, this is set to 0 */ 2087 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, td->last_trb); 2088 2089 if (debug) 2090 xhci_warn(xhci, 2091 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", 2092 (unsigned long long)suspect_dma, 2093 (unsigned long long)start_dma, 2094 (unsigned long long)end_trb_dma, 2095 (unsigned long long)cur_seg->dma, 2096 (unsigned long long)end_seg_dma); 2097 2098 if (end_trb_dma > 0) { 2099 /* The end TRB is in this segment, so suspect should be here */ 2100 if (start_dma <= end_trb_dma) { 2101 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 2102 return cur_seg; 2103 } else { 2104 /* Case for one segment with 2105 * a TD wrapped around to the top 2106 */ 2107 if ((suspect_dma >= start_dma && 2108 suspect_dma <= end_seg_dma) || 2109 (suspect_dma >= cur_seg->dma && 2110 suspect_dma <= end_trb_dma)) 2111 return cur_seg; 2112 } 2113 return NULL; 2114 } else { 2115 /* Might still be somewhere in this segment */ 2116 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 2117 return cur_seg; 2118 } 2119 cur_seg = cur_seg->next; 2120 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 2121 } while (cur_seg != td->start_seg); 2122 2123 return NULL; 2124 } 2125 2126 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td, 2127 struct xhci_virt_ep *ep) 2128 { 2129 /* 2130 * As part of low/full-speed endpoint-halt processing 2131 * we must clear the TT buffer (USB 2.0 specification 11.17.5). 2132 */ 2133 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) && 2134 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) && 2135 !(ep->ep_state & EP_CLEARING_TT)) { 2136 ep->ep_state |= EP_CLEARING_TT; 2137 td->urb->ep->hcpriv = td->urb->dev; 2138 if (usb_hub_clear_tt_buffer(td->urb)) 2139 ep->ep_state &= ~EP_CLEARING_TT; 2140 } 2141 } 2142 2143 /* 2144 * Check if xhci internal endpoint state has gone to a "halt" state due to an 2145 * error or stall, including default control pipe protocol stall. 2146 * The internal halt needs to be cleared with a reset endpoint command. 2147 * 2148 * External device side is also halted in functional stall cases. Class driver 2149 * will clear the device halt with a CLEAR_FEATURE(ENDPOINT_HALT) request later. 2150 */ 2151 static bool xhci_halted_host_endpoint(struct xhci_ep_ctx *ep_ctx, unsigned int comp_code) 2152 { 2153 /* Stall halts both internal and device side endpoint */ 2154 if (comp_code == COMP_STALL_ERROR) 2155 return true; 2156 2157 /* TRB completion codes that may require internal halt cleanup */ 2158 if (comp_code == COMP_USB_TRANSACTION_ERROR || 2159 comp_code == COMP_BABBLE_DETECTED_ERROR || 2160 comp_code == COMP_SPLIT_TRANSACTION_ERROR) 2161 /* 2162 * The 0.95 spec says a babbling control endpoint is not halted. 2163 * The 0.96 spec says it is. Some HW claims to be 0.95 2164 * compliant, but it halts the control endpoint anyway. 2165 * Check endpoint context if endpoint is halted. 2166 */ 2167 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) 2168 return true; 2169 2170 return false; 2171 } 2172 2173 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 2174 { 2175 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 2176 /* Vendor defined "informational" completion code, 2177 * treat as not-an-error. 2178 */ 2179 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 2180 trb_comp_code); 2181 xhci_dbg(xhci, "Treating code as success.\n"); 2182 return 1; 2183 } 2184 return 0; 2185 } 2186 2187 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2188 struct xhci_ring *ep_ring, struct xhci_td *td, 2189 u32 trb_comp_code) 2190 { 2191 struct xhci_ep_ctx *ep_ctx; 2192 2193 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); 2194 2195 switch (trb_comp_code) { 2196 case COMP_STOPPED_LENGTH_INVALID: 2197 case COMP_STOPPED_SHORT_PACKET: 2198 case COMP_STOPPED: 2199 /* 2200 * The "Stop Endpoint" completion will take care of any 2201 * stopped TDs. A stopped TD may be restarted, so don't update 2202 * the ring dequeue pointer or take this TD off any lists yet. 2203 */ 2204 return 0; 2205 case COMP_USB_TRANSACTION_ERROR: 2206 case COMP_BABBLE_DETECTED_ERROR: 2207 case COMP_SPLIT_TRANSACTION_ERROR: 2208 /* 2209 * If endpoint context state is not halted we might be 2210 * racing with a reset endpoint command issued by a unsuccessful 2211 * stop endpoint completion (context error). In that case the 2212 * td should be on the cancelled list, and EP_HALTED flag set. 2213 * 2214 * Or then it's not halted due to the 0.95 spec stating that a 2215 * babbling control endpoint should not halt. The 0.96 spec 2216 * again says it should. Some HW claims to be 0.95 compliant, 2217 * but it halts the control endpoint anyway. 2218 */ 2219 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) { 2220 /* 2221 * If EP_HALTED is set and TD is on the cancelled list 2222 * the TD and dequeue pointer will be handled by reset 2223 * ep command completion 2224 */ 2225 if ((ep->ep_state & EP_HALTED) && 2226 !list_empty(&td->cancelled_td_list)) { 2227 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n", 2228 (unsigned long long)xhci_trb_virt_to_dma( 2229 td->start_seg, td->first_trb)); 2230 return 0; 2231 } 2232 /* endpoint not halted, don't reset it */ 2233 break; 2234 } 2235 /* Almost same procedure as for STALL_ERROR below */ 2236 xhci_clear_hub_tt_buffer(xhci, td, ep); 2237 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET); 2238 return 0; 2239 case COMP_STALL_ERROR: 2240 /* 2241 * xhci internal endpoint state will go to a "halt" state for 2242 * any stall, including default control pipe protocol stall. 2243 * To clear the host side halt we need to issue a reset endpoint 2244 * command, followed by a set dequeue command to move past the 2245 * TD. 2246 * Class drivers clear the device side halt from a functional 2247 * stall later. Hub TT buffer should only be cleared for FS/LS 2248 * devices behind HS hubs for functional stalls. 2249 */ 2250 if (ep->ep_index != 0) 2251 xhci_clear_hub_tt_buffer(xhci, td, ep); 2252 2253 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET); 2254 2255 return 0; /* xhci_handle_halted_endpoint marked td cancelled */ 2256 default: 2257 break; 2258 } 2259 2260 /* Update ring dequeue pointer */ 2261 ep_ring->dequeue = td->last_trb; 2262 ep_ring->deq_seg = td->last_trb_seg; 2263 inc_deq(xhci, ep_ring); 2264 2265 return xhci_td_cleanup(xhci, td, ep_ring, td->status); 2266 } 2267 2268 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ 2269 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, 2270 union xhci_trb *stop_trb) 2271 { 2272 u32 sum; 2273 union xhci_trb *trb = ring->dequeue; 2274 struct xhci_segment *seg = ring->deq_seg; 2275 2276 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { 2277 if (!trb_is_noop(trb) && !trb_is_link(trb)) 2278 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); 2279 } 2280 return sum; 2281 } 2282 2283 /* 2284 * Process control tds, update urb status and actual_length. 2285 */ 2286 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2287 struct xhci_ring *ep_ring, struct xhci_td *td, 2288 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2289 { 2290 struct xhci_ep_ctx *ep_ctx; 2291 u32 trb_comp_code; 2292 u32 remaining, requested; 2293 u32 trb_type; 2294 2295 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); 2296 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); 2297 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2298 requested = td->urb->transfer_buffer_length; 2299 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2300 2301 switch (trb_comp_code) { 2302 case COMP_SUCCESS: 2303 if (trb_type != TRB_STATUS) { 2304 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", 2305 (trb_type == TRB_DATA) ? "data" : "setup"); 2306 td->status = -ESHUTDOWN; 2307 break; 2308 } 2309 td->status = 0; 2310 break; 2311 case COMP_SHORT_PACKET: 2312 td->status = 0; 2313 break; 2314 case COMP_STOPPED_SHORT_PACKET: 2315 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2316 td->urb->actual_length = remaining; 2317 else 2318 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); 2319 goto finish_td; 2320 case COMP_STOPPED: 2321 switch (trb_type) { 2322 case TRB_SETUP: 2323 td->urb->actual_length = 0; 2324 goto finish_td; 2325 case TRB_DATA: 2326 case TRB_NORMAL: 2327 td->urb->actual_length = requested - remaining; 2328 goto finish_td; 2329 case TRB_STATUS: 2330 td->urb->actual_length = requested; 2331 goto finish_td; 2332 default: 2333 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", 2334 trb_type); 2335 goto finish_td; 2336 } 2337 case COMP_STOPPED_LENGTH_INVALID: 2338 goto finish_td; 2339 default: 2340 if (!xhci_halted_host_endpoint(ep_ctx, trb_comp_code)) 2341 break; 2342 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", 2343 trb_comp_code, ep->ep_index); 2344 fallthrough; 2345 case COMP_STALL_ERROR: 2346 /* Did we transfer part of the data (middle) phase? */ 2347 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2348 td->urb->actual_length = requested - remaining; 2349 else if (!td->urb_length_set) 2350 td->urb->actual_length = 0; 2351 goto finish_td; 2352 } 2353 2354 /* stopped at setup stage, no data transferred */ 2355 if (trb_type == TRB_SETUP) 2356 goto finish_td; 2357 2358 /* 2359 * if on data stage then update the actual_length of the URB and flag it 2360 * as set, so it won't be overwritten in the event for the last TRB. 2361 */ 2362 if (trb_type == TRB_DATA || 2363 trb_type == TRB_NORMAL) { 2364 td->urb_length_set = true; 2365 td->urb->actual_length = requested - remaining; 2366 xhci_dbg(xhci, "Waiting for status stage event\n"); 2367 return 0; 2368 } 2369 2370 /* at status stage */ 2371 if (!td->urb_length_set) 2372 td->urb->actual_length = requested; 2373 2374 finish_td: 2375 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2376 } 2377 2378 /* 2379 * Process isochronous tds, update urb packet status and actual_length. 2380 */ 2381 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2382 struct xhci_ring *ep_ring, struct xhci_td *td, 2383 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2384 { 2385 struct urb_priv *urb_priv; 2386 int idx; 2387 struct usb_iso_packet_descriptor *frame; 2388 u32 trb_comp_code; 2389 bool sum_trbs_for_length = false; 2390 u32 remaining, requested, ep_trb_len; 2391 int short_framestatus; 2392 2393 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2394 urb_priv = td->urb->hcpriv; 2395 idx = urb_priv->num_tds_done; 2396 frame = &td->urb->iso_frame_desc[idx]; 2397 requested = frame->length; 2398 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2399 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2400 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2401 -EREMOTEIO : 0; 2402 2403 /* handle completion code */ 2404 switch (trb_comp_code) { 2405 case COMP_SUCCESS: 2406 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */ 2407 if (td->error_mid_td) 2408 break; 2409 if (remaining) { 2410 frame->status = short_framestatus; 2411 sum_trbs_for_length = true; 2412 break; 2413 } 2414 frame->status = 0; 2415 break; 2416 case COMP_SHORT_PACKET: 2417 frame->status = short_framestatus; 2418 sum_trbs_for_length = true; 2419 break; 2420 case COMP_BANDWIDTH_OVERRUN_ERROR: 2421 frame->status = -ECOMM; 2422 break; 2423 case COMP_BABBLE_DETECTED_ERROR: 2424 sum_trbs_for_length = true; 2425 fallthrough; 2426 case COMP_ISOCH_BUFFER_OVERRUN: 2427 frame->status = -EOVERFLOW; 2428 if (ep_trb != td->last_trb) 2429 td->error_mid_td = true; 2430 break; 2431 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2432 case COMP_STALL_ERROR: 2433 frame->status = -EPROTO; 2434 break; 2435 case COMP_USB_TRANSACTION_ERROR: 2436 frame->status = -EPROTO; 2437 sum_trbs_for_length = true; 2438 if (ep_trb != td->last_trb) 2439 td->error_mid_td = true; 2440 break; 2441 case COMP_STOPPED: 2442 sum_trbs_for_length = true; 2443 break; 2444 case COMP_STOPPED_SHORT_PACKET: 2445 /* field normally containing residue now contains tranferred */ 2446 frame->status = short_framestatus; 2447 requested = remaining; 2448 break; 2449 case COMP_STOPPED_LENGTH_INVALID: 2450 /* exclude stopped trb with invalid length from length sum */ 2451 sum_trbs_for_length = true; 2452 ep_trb_len = 0; 2453 remaining = 0; 2454 break; 2455 default: 2456 sum_trbs_for_length = true; 2457 frame->status = -1; 2458 break; 2459 } 2460 2461 if (td->urb_length_set) 2462 goto finish_td; 2463 2464 if (sum_trbs_for_length) 2465 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) + 2466 ep_trb_len - remaining; 2467 else 2468 frame->actual_length = requested; 2469 2470 td->urb->actual_length += frame->actual_length; 2471 2472 finish_td: 2473 /* Don't give back TD yet if we encountered an error mid TD */ 2474 if (td->error_mid_td && ep_trb != td->last_trb) { 2475 xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n"); 2476 td->urb_length_set = true; 2477 return 0; 2478 } 2479 2480 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2481 } 2482 2483 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2484 struct xhci_virt_ep *ep, int status) 2485 { 2486 struct urb_priv *urb_priv; 2487 struct usb_iso_packet_descriptor *frame; 2488 int idx; 2489 2490 urb_priv = td->urb->hcpriv; 2491 idx = urb_priv->num_tds_done; 2492 frame = &td->urb->iso_frame_desc[idx]; 2493 2494 /* The transfer is partly done. */ 2495 frame->status = -EXDEV; 2496 2497 /* calc actual length */ 2498 frame->actual_length = 0; 2499 2500 /* Update ring dequeue pointer */ 2501 ep->ring->dequeue = td->last_trb; 2502 ep->ring->deq_seg = td->last_trb_seg; 2503 inc_deq(xhci, ep->ring); 2504 2505 return xhci_td_cleanup(xhci, td, ep->ring, status); 2506 } 2507 2508 /* 2509 * Process bulk and interrupt tds, update urb status and actual_length. 2510 */ 2511 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2512 struct xhci_ring *ep_ring, struct xhci_td *td, 2513 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2514 { 2515 struct xhci_slot_ctx *slot_ctx; 2516 u32 trb_comp_code; 2517 u32 remaining, requested, ep_trb_len; 2518 2519 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); 2520 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2521 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2522 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2523 requested = td->urb->transfer_buffer_length; 2524 2525 switch (trb_comp_code) { 2526 case COMP_SUCCESS: 2527 ep->err_count = 0; 2528 /* handle success with untransferred data as short packet */ 2529 if (ep_trb != td->last_trb || remaining) { 2530 xhci_warn(xhci, "WARN Successful completion on short TX\n"); 2531 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2532 td->urb->ep->desc.bEndpointAddress, 2533 requested, remaining); 2534 } 2535 td->status = 0; 2536 break; 2537 case COMP_SHORT_PACKET: 2538 td->status = 0; 2539 break; 2540 case COMP_STOPPED_SHORT_PACKET: 2541 td->urb->actual_length = remaining; 2542 goto finish_td; 2543 case COMP_STOPPED_LENGTH_INVALID: 2544 /* stopped on ep trb with invalid length, exclude it */ 2545 td->urb->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb); 2546 goto finish_td; 2547 case COMP_USB_TRANSACTION_ERROR: 2548 if (xhci->quirks & XHCI_NO_SOFT_RETRY || 2549 (ep->err_count++ > MAX_SOFT_RETRY) || 2550 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) 2551 break; 2552 2553 td->status = 0; 2554 2555 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET); 2556 return 0; 2557 default: 2558 /* do nothing */ 2559 break; 2560 } 2561 2562 if (ep_trb == td->last_trb) 2563 td->urb->actual_length = requested - remaining; 2564 else 2565 td->urb->actual_length = 2566 sum_trb_lengths(xhci, ep_ring, ep_trb) + 2567 ep_trb_len - remaining; 2568 finish_td: 2569 if (remaining > requested) { 2570 xhci_warn(xhci, "bad transfer trb length %d in event trb\n", 2571 remaining); 2572 td->urb->actual_length = 0; 2573 } 2574 2575 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2576 } 2577 2578 /* Transfer events which don't point to a transfer TRB, see xhci 4.17.4 */ 2579 static int handle_transferless_tx_event(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2580 u32 trb_comp_code) 2581 { 2582 switch (trb_comp_code) { 2583 case COMP_STALL_ERROR: 2584 case COMP_USB_TRANSACTION_ERROR: 2585 case COMP_INVALID_STREAM_TYPE_ERROR: 2586 case COMP_INVALID_STREAM_ID_ERROR: 2587 xhci_dbg(xhci, "Stream transaction error ep %u no id\n", ep->ep_index); 2588 if (ep->err_count++ > MAX_SOFT_RETRY) 2589 xhci_handle_halted_endpoint(xhci, ep, NULL, EP_HARD_RESET); 2590 else 2591 xhci_handle_halted_endpoint(xhci, ep, NULL, EP_SOFT_RESET); 2592 break; 2593 case COMP_RING_UNDERRUN: 2594 case COMP_RING_OVERRUN: 2595 case COMP_STOPPED_LENGTH_INVALID: 2596 break; 2597 default: 2598 xhci_err(xhci, "Transfer event %u for unknown stream ring slot %u ep %u\n", 2599 trb_comp_code, ep->vdev->slot_id, ep->ep_index); 2600 return -ENODEV; 2601 } 2602 return 0; 2603 } 2604 2605 /* 2606 * If this function returns an error condition, it means it got a Transfer 2607 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2608 * At this point, the host controller is probably hosed and should be reset. 2609 */ 2610 static int handle_tx_event(struct xhci_hcd *xhci, 2611 struct xhci_interrupter *ir, 2612 struct xhci_transfer_event *event) 2613 { 2614 struct xhci_virt_ep *ep; 2615 struct xhci_ring *ep_ring; 2616 unsigned int slot_id; 2617 int ep_index; 2618 struct xhci_td *td = NULL; 2619 dma_addr_t ep_trb_dma; 2620 struct xhci_segment *ep_seg; 2621 union xhci_trb *ep_trb; 2622 int status = -EINPROGRESS; 2623 struct xhci_ep_ctx *ep_ctx; 2624 u32 trb_comp_code; 2625 2626 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2627 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2628 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2629 ep_trb_dma = le64_to_cpu(event->buffer); 2630 2631 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 2632 if (!ep) { 2633 xhci_err(xhci, "ERROR Invalid Transfer event\n"); 2634 goto err_out; 2635 } 2636 2637 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); 2638 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 2639 2640 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { 2641 xhci_err(xhci, 2642 "ERROR Transfer event for disabled endpoint slot %u ep %u\n", 2643 slot_id, ep_index); 2644 goto err_out; 2645 } 2646 2647 if (!ep_ring) 2648 return handle_transferless_tx_event(xhci, ep, trb_comp_code); 2649 2650 /* Look for common error cases */ 2651 switch (trb_comp_code) { 2652 /* Skip codes that require special handling depending on 2653 * transfer type 2654 */ 2655 case COMP_SUCCESS: 2656 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { 2657 trb_comp_code = COMP_SHORT_PACKET; 2658 xhci_dbg(xhci, "Successful completion on short TX for slot %u ep %u with last td short %d\n", 2659 slot_id, ep_index, ep_ring->last_td_was_short); 2660 } 2661 break; 2662 case COMP_SHORT_PACKET: 2663 break; 2664 /* Completion codes for endpoint stopped state */ 2665 case COMP_STOPPED: 2666 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", 2667 slot_id, ep_index); 2668 break; 2669 case COMP_STOPPED_LENGTH_INVALID: 2670 xhci_dbg(xhci, 2671 "Stopped on No-op or Link TRB for slot %u ep %u\n", 2672 slot_id, ep_index); 2673 break; 2674 case COMP_STOPPED_SHORT_PACKET: 2675 xhci_dbg(xhci, 2676 "Stopped with short packet transfer detected for slot %u ep %u\n", 2677 slot_id, ep_index); 2678 break; 2679 /* Completion codes for endpoint halted state */ 2680 case COMP_STALL_ERROR: 2681 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, 2682 ep_index); 2683 status = -EPIPE; 2684 break; 2685 case COMP_SPLIT_TRANSACTION_ERROR: 2686 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n", 2687 slot_id, ep_index); 2688 status = -EPROTO; 2689 break; 2690 case COMP_USB_TRANSACTION_ERROR: 2691 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", 2692 slot_id, ep_index); 2693 status = -EPROTO; 2694 break; 2695 case COMP_BABBLE_DETECTED_ERROR: 2696 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", 2697 slot_id, ep_index); 2698 status = -EOVERFLOW; 2699 break; 2700 /* Completion codes for endpoint error state */ 2701 case COMP_TRB_ERROR: 2702 xhci_warn(xhci, 2703 "WARN: TRB error for slot %u ep %u on endpoint\n", 2704 slot_id, ep_index); 2705 status = -EILSEQ; 2706 break; 2707 /* completion codes not indicating endpoint state change */ 2708 case COMP_DATA_BUFFER_ERROR: 2709 xhci_warn(xhci, 2710 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", 2711 slot_id, ep_index); 2712 status = -ENOSR; 2713 break; 2714 case COMP_BANDWIDTH_OVERRUN_ERROR: 2715 xhci_warn(xhci, 2716 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", 2717 slot_id, ep_index); 2718 break; 2719 case COMP_ISOCH_BUFFER_OVERRUN: 2720 xhci_warn(xhci, 2721 "WARN: buffer overrun event for slot %u ep %u on endpoint", 2722 slot_id, ep_index); 2723 break; 2724 case COMP_RING_UNDERRUN: 2725 /* 2726 * When the Isoch ring is empty, the xHC will generate 2727 * a Ring Overrun Event for IN Isoch endpoint or Ring 2728 * Underrun Event for OUT Isoch endpoint. 2729 */ 2730 xhci_dbg(xhci, "Underrun event on slot %u ep %u\n", slot_id, ep_index); 2731 if (ep->skip) 2732 break; 2733 return 0; 2734 case COMP_RING_OVERRUN: 2735 xhci_dbg(xhci, "Overrun event on slot %u ep %u\n", slot_id, ep_index); 2736 if (ep->skip) 2737 break; 2738 return 0; 2739 case COMP_MISSED_SERVICE_ERROR: 2740 /* 2741 * When encounter missed service error, one or more isoc tds 2742 * may be missed by xHC. 2743 * Set skip flag of the ep_ring; Complete the missed tds as 2744 * short transfer when process the ep_ring next time. 2745 */ 2746 ep->skip = true; 2747 xhci_dbg(xhci, 2748 "Miss service interval error for slot %u ep %u, set skip flag\n", 2749 slot_id, ep_index); 2750 return 0; 2751 case COMP_NO_PING_RESPONSE_ERROR: 2752 ep->skip = true; 2753 xhci_dbg(xhci, 2754 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", 2755 slot_id, ep_index); 2756 return 0; 2757 2758 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2759 /* needs disable slot command to recover */ 2760 xhci_warn(xhci, 2761 "WARN: detect an incompatible device for slot %u ep %u", 2762 slot_id, ep_index); 2763 status = -EPROTO; 2764 break; 2765 default: 2766 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2767 status = 0; 2768 break; 2769 } 2770 xhci_warn(xhci, 2771 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", 2772 trb_comp_code, slot_id, ep_index); 2773 if (ep->skip) 2774 break; 2775 return 0; 2776 } 2777 2778 if (list_empty(&ep_ring->td_list)) { 2779 /* 2780 * Don't print wanings if ring is empty due to a stopped endpoint generating an 2781 * extra completion event if the device was suspended. Or, a event for the last TRB 2782 * of a short TD we already got a short event for. The short TD is already removed 2783 * from the TD list. 2784 */ 2785 if (trb_comp_code != COMP_STOPPED && 2786 trb_comp_code != COMP_STOPPED_LENGTH_INVALID && 2787 !ep_ring->last_td_was_short) { 2788 xhci_warn(xhci, "Event TRB for slot %u ep %u with no TDs queued\n", 2789 slot_id, ep_index); 2790 } 2791 2792 ep->skip = false; 2793 goto check_endpoint_halted; 2794 } 2795 2796 do { 2797 td = list_first_entry(&ep_ring->td_list, struct xhci_td, 2798 td_list); 2799 2800 /* Is this a TRB in the currently executing TD? */ 2801 ep_seg = trb_in_td(xhci, td, ep_trb_dma, false); 2802 2803 if (!ep_seg) { 2804 2805 if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2806 skip_isoc_td(xhci, td, ep, status); 2807 if (!list_empty(&ep_ring->td_list)) 2808 continue; 2809 2810 xhci_dbg(xhci, "All TDs skipped for slot %u ep %u. Clear skip flag.\n", 2811 slot_id, ep_index); 2812 ep->skip = false; 2813 td = NULL; 2814 goto check_endpoint_halted; 2815 } 2816 2817 /* 2818 * Skip the Force Stopped Event. The 'ep_trb' of FSE is not in the current 2819 * TD pointed by 'ep_ring->dequeue' because that the hardware dequeue 2820 * pointer still at the previous TRB of the current TD. The previous TRB 2821 * maybe a Link TD or the last TRB of the previous TD. The command 2822 * completion handle will take care the rest. 2823 */ 2824 if (trb_comp_code == COMP_STOPPED || 2825 trb_comp_code == COMP_STOPPED_LENGTH_INVALID) { 2826 return 0; 2827 } 2828 2829 /* 2830 * Some hosts give a spurious success event after a short 2831 * transfer. Ignore it. 2832 */ 2833 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2834 ep_ring->last_td_was_short) { 2835 ep_ring->last_td_was_short = false; 2836 return 0; 2837 } 2838 2839 /* 2840 * xhci 4.10.2 states isoc endpoints should continue 2841 * processing the next TD if there was an error mid TD. 2842 * So host like NEC don't generate an event for the last 2843 * isoc TRB even if the IOC flag is set. 2844 * xhci 4.9.1 states that if there are errors in mult-TRB 2845 * TDs xHC should generate an error for that TRB, and if xHC 2846 * proceeds to the next TD it should genete an event for 2847 * any TRB with IOC flag on the way. Other host follow this. 2848 * So this event might be for the next TD. 2849 */ 2850 if (td->error_mid_td && 2851 !list_is_last(&td->td_list, &ep_ring->td_list)) { 2852 struct xhci_td *td_next = list_next_entry(td, td_list); 2853 2854 ep_seg = trb_in_td(xhci, td_next, ep_trb_dma, false); 2855 if (ep_seg) { 2856 /* give back previous TD, start handling new */ 2857 xhci_dbg(xhci, "Missing TD completion event after mid TD error\n"); 2858 ep_ring->dequeue = td->last_trb; 2859 ep_ring->deq_seg = td->last_trb_seg; 2860 inc_deq(xhci, ep_ring); 2861 xhci_td_cleanup(xhci, td, ep_ring, td->status); 2862 td = td_next; 2863 } 2864 } 2865 2866 if (!ep_seg) { 2867 /* HC is busted, give up! */ 2868 xhci_err(xhci, 2869 "ERROR Transfer event TRB DMA ptr not " 2870 "part of current TD ep_index %d " 2871 "comp_code %u\n", ep_index, 2872 trb_comp_code); 2873 trb_in_td(xhci, td, ep_trb_dma, true); 2874 2875 return -ESHUTDOWN; 2876 } 2877 } 2878 2879 if (ep->skip) { 2880 xhci_dbg(xhci, 2881 "Found td. Clear skip flag for slot %u ep %u.\n", 2882 slot_id, ep_index); 2883 ep->skip = false; 2884 } 2885 2886 /* 2887 * If ep->skip is set, it means there are missed tds on the 2888 * endpoint ring need to take care of. 2889 * Process them as short transfer until reach the td pointed by 2890 * the event. 2891 */ 2892 } while (ep->skip); 2893 2894 if (trb_comp_code == COMP_SHORT_PACKET) 2895 ep_ring->last_td_was_short = true; 2896 else 2897 ep_ring->last_td_was_short = false; 2898 2899 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / sizeof(*ep_trb)]; 2900 trace_xhci_handle_transfer(ep_ring, (struct xhci_generic_trb *) ep_trb); 2901 2902 /* 2903 * No-op TRB could trigger interrupts in a case where a URB was killed 2904 * and a STALL_ERROR happens right after the endpoint ring stopped. 2905 * Reset the halted endpoint. Otherwise, the endpoint remains stalled 2906 * indefinitely. 2907 */ 2908 2909 if (trb_is_noop(ep_trb)) 2910 goto check_endpoint_halted; 2911 2912 td->status = status; 2913 2914 /* update the urb's actual_length and give back to the core */ 2915 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2916 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event); 2917 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2918 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event); 2919 else 2920 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event); 2921 return 0; 2922 2923 check_endpoint_halted: 2924 if (xhci_halted_host_endpoint(ep_ctx, trb_comp_code)) 2925 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET); 2926 2927 return 0; 2928 2929 err_out: 2930 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2931 (unsigned long long) xhci_trb_virt_to_dma( 2932 ir->event_ring->deq_seg, 2933 ir->event_ring->dequeue), 2934 lower_32_bits(le64_to_cpu(event->buffer)), 2935 upper_32_bits(le64_to_cpu(event->buffer)), 2936 le32_to_cpu(event->transfer_len), 2937 le32_to_cpu(event->flags)); 2938 return -ENODEV; 2939 } 2940 2941 /* 2942 * This function handles one OS-owned event on the event ring. It may drop 2943 * xhci->lock between event processing (e.g. to pass up port status changes). 2944 */ 2945 static int xhci_handle_event_trb(struct xhci_hcd *xhci, struct xhci_interrupter *ir, 2946 union xhci_trb *event) 2947 { 2948 u32 trb_type; 2949 2950 trace_xhci_handle_event(ir->event_ring, &event->generic); 2951 2952 /* 2953 * Barrier between reading the TRB_CYCLE (valid) flag before, and any 2954 * speculative reads of the event's flags/data below. 2955 */ 2956 rmb(); 2957 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags)); 2958 /* FIXME: Handle more event types. */ 2959 2960 switch (trb_type) { 2961 case TRB_COMPLETION: 2962 handle_cmd_completion(xhci, &event->event_cmd); 2963 break; 2964 case TRB_PORT_STATUS: 2965 handle_port_status(xhci, event); 2966 break; 2967 case TRB_TRANSFER: 2968 handle_tx_event(xhci, ir, &event->trans_event); 2969 break; 2970 case TRB_DEV_NOTE: 2971 handle_device_notification(xhci, event); 2972 break; 2973 default: 2974 if (trb_type >= TRB_VENDOR_DEFINED_LOW) 2975 handle_vendor_event(xhci, event, trb_type); 2976 else 2977 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type); 2978 } 2979 /* Any of the above functions may drop and re-acquire the lock, so check 2980 * to make sure a watchdog timer didn't mark the host as non-responsive. 2981 */ 2982 if (xhci->xhc_state & XHCI_STATE_DYING) { 2983 xhci_dbg(xhci, "xHCI host dying, returning from event handler.\n"); 2984 return -ENODEV; 2985 } 2986 2987 return 0; 2988 } 2989 2990 /* 2991 * Update Event Ring Dequeue Pointer: 2992 * - When all events have finished 2993 * - To avoid "Event Ring Full Error" condition 2994 */ 2995 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 2996 struct xhci_interrupter *ir, 2997 bool clear_ehb) 2998 { 2999 u64 temp_64; 3000 dma_addr_t deq; 3001 3002 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue); 3003 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg, 3004 ir->event_ring->dequeue); 3005 if (deq == 0) 3006 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n"); 3007 /* 3008 * Per 4.9.4, Software writes to the ERDP register shall always advance 3009 * the Event Ring Dequeue Pointer value. 3010 */ 3011 if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK) && !clear_ehb) 3012 return; 3013 3014 /* Update HC event ring dequeue pointer */ 3015 temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK; 3016 temp_64 |= deq & ERST_PTR_MASK; 3017 3018 /* Clear the event handler busy flag (RW1C) */ 3019 if (clear_ehb) 3020 temp_64 |= ERST_EHB; 3021 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue); 3022 } 3023 3024 /* Clear the interrupt pending bit for a specific interrupter. */ 3025 static void xhci_clear_interrupt_pending(struct xhci_interrupter *ir) 3026 { 3027 if (!ir->ip_autoclear) { 3028 u32 irq_pending; 3029 3030 irq_pending = readl(&ir->ir_set->irq_pending); 3031 irq_pending |= IMAN_IP; 3032 writel(irq_pending, &ir->ir_set->irq_pending); 3033 } 3034 } 3035 3036 /* 3037 * Handle all OS-owned events on an interrupter event ring. It may drop 3038 * and reaquire xhci->lock between event processing. 3039 */ 3040 static int xhci_handle_events(struct xhci_hcd *xhci, struct xhci_interrupter *ir) 3041 { 3042 int event_loop = 0; 3043 int err; 3044 u64 temp; 3045 3046 xhci_clear_interrupt_pending(ir); 3047 3048 /* Event ring hasn't been allocated yet. */ 3049 if (!ir->event_ring || !ir->event_ring->dequeue) { 3050 xhci_err(xhci, "ERROR interrupter event ring not ready\n"); 3051 return -ENOMEM; 3052 } 3053 3054 if (xhci->xhc_state & XHCI_STATE_DYING || 3055 xhci->xhc_state & XHCI_STATE_HALTED) { 3056 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?\n"); 3057 3058 /* Clear the event handler busy flag (RW1C) */ 3059 temp = xhci_read_64(xhci, &ir->ir_set->erst_dequeue); 3060 xhci_write_64(xhci, temp | ERST_EHB, &ir->ir_set->erst_dequeue); 3061 return -ENODEV; 3062 } 3063 3064 /* Process all OS owned event TRBs on this event ring */ 3065 while (unhandled_event_trb(ir->event_ring)) { 3066 err = xhci_handle_event_trb(xhci, ir, ir->event_ring->dequeue); 3067 3068 /* 3069 * If half a segment of events have been handled in one go then 3070 * update ERDP, and force isoc trbs to interrupt more often 3071 */ 3072 if (event_loop++ > TRBS_PER_SEGMENT / 2) { 3073 xhci_update_erst_dequeue(xhci, ir, false); 3074 3075 if (ir->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN) 3076 ir->isoc_bei_interval = ir->isoc_bei_interval / 2; 3077 3078 event_loop = 0; 3079 } 3080 3081 /* Update SW event ring dequeue pointer */ 3082 inc_deq(xhci, ir->event_ring); 3083 3084 if (err) 3085 break; 3086 } 3087 3088 xhci_update_erst_dequeue(xhci, ir, true); 3089 3090 return 0; 3091 } 3092 3093 /* 3094 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 3095 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 3096 * indicators of an event TRB error, but we check the status *first* to be safe. 3097 */ 3098 irqreturn_t xhci_irq(struct usb_hcd *hcd) 3099 { 3100 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 3101 irqreturn_t ret = IRQ_HANDLED; 3102 u32 status; 3103 3104 spin_lock(&xhci->lock); 3105 /* Check if the xHC generated the interrupt, or the irq is shared */ 3106 status = readl(&xhci->op_regs->status); 3107 if (status == ~(u32)0) { 3108 xhci_hc_died(xhci); 3109 goto out; 3110 } 3111 3112 if (!(status & STS_EINT)) { 3113 ret = IRQ_NONE; 3114 goto out; 3115 } 3116 3117 if (status & STS_HCE) { 3118 xhci_warn(xhci, "WARNING: Host Controller Error\n"); 3119 goto out; 3120 } 3121 3122 if (status & STS_FATAL) { 3123 xhci_warn(xhci, "WARNING: Host System Error\n"); 3124 xhci_halt(xhci); 3125 goto out; 3126 } 3127 3128 /* 3129 * Clear the op reg interrupt status first, 3130 * so we can receive interrupts from other MSI-X interrupters. 3131 * Write 1 to clear the interrupt status. 3132 */ 3133 status |= STS_EINT; 3134 writel(status, &xhci->op_regs->status); 3135 3136 /* This is the handler of the primary interrupter */ 3137 xhci_handle_events(xhci, xhci->interrupters[0]); 3138 out: 3139 spin_unlock(&xhci->lock); 3140 3141 return ret; 3142 } 3143 3144 irqreturn_t xhci_msi_irq(int irq, void *hcd) 3145 { 3146 return xhci_irq(hcd); 3147 } 3148 EXPORT_SYMBOL_GPL(xhci_msi_irq); 3149 3150 /**** Endpoint Ring Operations ****/ 3151 3152 /* 3153 * Generic function for queueing a TRB on a ring. 3154 * The caller must have checked to make sure there's room on the ring. 3155 * 3156 * @more_trbs_coming: Will you enqueue more TRBs before calling 3157 * prepare_transfer()? 3158 */ 3159 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 3160 bool more_trbs_coming, 3161 u32 field1, u32 field2, u32 field3, u32 field4) 3162 { 3163 struct xhci_generic_trb *trb; 3164 3165 trb = &ring->enqueue->generic; 3166 trb->field[0] = cpu_to_le32(field1); 3167 trb->field[1] = cpu_to_le32(field2); 3168 trb->field[2] = cpu_to_le32(field3); 3169 /* make sure TRB is fully written before giving it to the controller */ 3170 wmb(); 3171 trb->field[3] = cpu_to_le32(field4); 3172 3173 trace_xhci_queue_trb(ring, trb); 3174 3175 inc_enq(xhci, ring, more_trbs_coming); 3176 } 3177 3178 /* 3179 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 3180 * expand ring if it start to be full. 3181 */ 3182 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 3183 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 3184 { 3185 unsigned int link_trb_count = 0; 3186 unsigned int new_segs = 0; 3187 3188 /* Make sure the endpoint has been added to xHC schedule */ 3189 switch (ep_state) { 3190 case EP_STATE_DISABLED: 3191 /* 3192 * USB core changed config/interfaces without notifying us, 3193 * or hardware is reporting the wrong state. 3194 */ 3195 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 3196 return -ENOENT; 3197 case EP_STATE_ERROR: 3198 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 3199 /* FIXME event handling code for error needs to clear it */ 3200 /* XXX not sure if this should be -ENOENT or not */ 3201 return -EINVAL; 3202 case EP_STATE_HALTED: 3203 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 3204 break; 3205 case EP_STATE_STOPPED: 3206 case EP_STATE_RUNNING: 3207 break; 3208 default: 3209 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 3210 /* 3211 * FIXME issue Configure Endpoint command to try to get the HC 3212 * back into a known state. 3213 */ 3214 return -EINVAL; 3215 } 3216 3217 if (ep_ring != xhci->cmd_ring) { 3218 new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs); 3219 } else if (xhci_num_trbs_free(ep_ring) <= num_trbs) { 3220 xhci_err(xhci, "Do not support expand command ring\n"); 3221 return -ENOMEM; 3222 } 3223 3224 if (new_segs) { 3225 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 3226 "ERROR no room on ep ring, try ring expansion"); 3227 if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) { 3228 xhci_err(xhci, "Ring expansion failed\n"); 3229 return -ENOMEM; 3230 } 3231 } 3232 3233 while (trb_is_link(ep_ring->enqueue)) { 3234 /* If we're not dealing with 0.95 hardware or isoc rings 3235 * on AMD 0.96 host, clear the chain bit. 3236 */ 3237 if (!xhci_link_chain_quirk(xhci, ep_ring->type)) 3238 ep_ring->enqueue->link.control &= 3239 cpu_to_le32(~TRB_CHAIN); 3240 else 3241 ep_ring->enqueue->link.control |= 3242 cpu_to_le32(TRB_CHAIN); 3243 3244 wmb(); 3245 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); 3246 3247 /* Toggle the cycle bit after the last ring segment. */ 3248 if (link_trb_toggles_cycle(ep_ring->enqueue)) 3249 ep_ring->cycle_state ^= 1; 3250 3251 ep_ring->enq_seg = ep_ring->enq_seg->next; 3252 ep_ring->enqueue = ep_ring->enq_seg->trbs; 3253 3254 /* prevent infinite loop if all first trbs are link trbs */ 3255 if (link_trb_count++ > ep_ring->num_segs) { 3256 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); 3257 return -EINVAL; 3258 } 3259 } 3260 3261 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) { 3262 xhci_warn(xhci, "Missing link TRB at end of ring segment\n"); 3263 return -EINVAL; 3264 } 3265 3266 return 0; 3267 } 3268 3269 static int prepare_transfer(struct xhci_hcd *xhci, 3270 struct xhci_virt_device *xdev, 3271 unsigned int ep_index, 3272 unsigned int stream_id, 3273 unsigned int num_trbs, 3274 struct urb *urb, 3275 unsigned int td_index, 3276 gfp_t mem_flags) 3277 { 3278 int ret; 3279 struct urb_priv *urb_priv; 3280 struct xhci_td *td; 3281 struct xhci_ring *ep_ring; 3282 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3283 3284 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index, 3285 stream_id); 3286 if (!ep_ring) { 3287 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 3288 stream_id); 3289 return -EINVAL; 3290 } 3291 3292 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 3293 num_trbs, mem_flags); 3294 if (ret) 3295 return ret; 3296 3297 urb_priv = urb->hcpriv; 3298 td = &urb_priv->td[td_index]; 3299 3300 INIT_LIST_HEAD(&td->td_list); 3301 INIT_LIST_HEAD(&td->cancelled_td_list); 3302 3303 if (td_index == 0) { 3304 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 3305 if (unlikely(ret)) 3306 return ret; 3307 } 3308 3309 td->urb = urb; 3310 /* Add this TD to the tail of the endpoint ring's TD list */ 3311 list_add_tail(&td->td_list, &ep_ring->td_list); 3312 td->start_seg = ep_ring->enq_seg; 3313 td->first_trb = ep_ring->enqueue; 3314 3315 return 0; 3316 } 3317 3318 unsigned int count_trbs(u64 addr, u64 len) 3319 { 3320 unsigned int num_trbs; 3321 3322 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 3323 TRB_MAX_BUFF_SIZE); 3324 if (num_trbs == 0) 3325 num_trbs++; 3326 3327 return num_trbs; 3328 } 3329 3330 static inline unsigned int count_trbs_needed(struct urb *urb) 3331 { 3332 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); 3333 } 3334 3335 static unsigned int count_sg_trbs_needed(struct urb *urb) 3336 { 3337 struct scatterlist *sg; 3338 unsigned int i, len, full_len, num_trbs = 0; 3339 3340 full_len = urb->transfer_buffer_length; 3341 3342 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { 3343 len = sg_dma_len(sg); 3344 num_trbs += count_trbs(sg_dma_address(sg), len); 3345 len = min_t(unsigned int, len, full_len); 3346 full_len -= len; 3347 if (full_len == 0) 3348 break; 3349 } 3350 3351 return num_trbs; 3352 } 3353 3354 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) 3355 { 3356 u64 addr, len; 3357 3358 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3359 len = urb->iso_frame_desc[i].length; 3360 3361 return count_trbs(addr, len); 3362 } 3363 3364 static void check_trb_math(struct urb *urb, int running_total) 3365 { 3366 if (unlikely(running_total != urb->transfer_buffer_length)) 3367 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 3368 "queued %#x (%d), asked for %#x (%d)\n", 3369 __func__, 3370 urb->ep->desc.bEndpointAddress, 3371 running_total, running_total, 3372 urb->transfer_buffer_length, 3373 urb->transfer_buffer_length); 3374 } 3375 3376 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 3377 unsigned int ep_index, unsigned int stream_id, int start_cycle, 3378 struct xhci_generic_trb *start_trb) 3379 { 3380 /* 3381 * Pass all the TRBs to the hardware at once and make sure this write 3382 * isn't reordered. 3383 */ 3384 wmb(); 3385 if (start_cycle) 3386 start_trb->field[3] |= cpu_to_le32(start_cycle); 3387 else 3388 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3389 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3390 } 3391 3392 static void check_interval(struct urb *urb, struct xhci_ep_ctx *ep_ctx) 3393 { 3394 int xhci_interval; 3395 int ep_interval; 3396 3397 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3398 ep_interval = urb->interval; 3399 3400 /* Convert to microframes */ 3401 if (urb->dev->speed == USB_SPEED_LOW || 3402 urb->dev->speed == USB_SPEED_FULL) 3403 ep_interval *= 8; 3404 3405 /* FIXME change this to a warning and a suggestion to use the new API 3406 * to set the polling interval (once the API is added). 3407 */ 3408 if (xhci_interval != ep_interval) { 3409 dev_dbg_ratelimited(&urb->dev->dev, 3410 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", 3411 ep_interval, ep_interval == 1 ? "" : "s", 3412 xhci_interval, xhci_interval == 1 ? "" : "s"); 3413 urb->interval = xhci_interval; 3414 /* Convert back to frames for LS/FS devices */ 3415 if (urb->dev->speed == USB_SPEED_LOW || 3416 urb->dev->speed == USB_SPEED_FULL) 3417 urb->interval /= 8; 3418 } 3419 } 3420 3421 /* 3422 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3423 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3424 * (comprised of sg list entries) can take several service intervals to 3425 * transmit. 3426 */ 3427 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3428 struct urb *urb, int slot_id, unsigned int ep_index) 3429 { 3430 struct xhci_ep_ctx *ep_ctx; 3431 3432 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); 3433 check_interval(urb, ep_ctx); 3434 3435 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3436 } 3437 3438 /* 3439 * For xHCI 1.0 host controllers, TD size is the number of max packet sized 3440 * packets remaining in the TD (*not* including this TRB). 3441 * 3442 * Total TD packet count = total_packet_count = 3443 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) 3444 * 3445 * Packets transferred up to and including this TRB = packets_transferred = 3446 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3447 * 3448 * TD size = total_packet_count - packets_transferred 3449 * 3450 * For xHCI 0.96 and older, TD size field should be the remaining bytes 3451 * including this TRB, right shifted by 10 3452 * 3453 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. 3454 * This is taken care of in the TRB_TD_SIZE() macro 3455 * 3456 * The last TRB in a TD must have the TD size set to zero. 3457 */ 3458 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, 3459 int trb_buff_len, unsigned int td_total_len, 3460 struct urb *urb, bool more_trbs_coming) 3461 { 3462 u32 maxp, total_packet_count; 3463 3464 /* MTK xHCI 0.96 contains some features from 1.0 */ 3465 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) 3466 return ((td_total_len - transferred) >> 10); 3467 3468 /* One TRB with a zero-length data packet. */ 3469 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || 3470 trb_buff_len == td_total_len) 3471 return 0; 3472 3473 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ 3474 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) 3475 trb_buff_len = 0; 3476 3477 maxp = usb_endpoint_maxp(&urb->ep->desc); 3478 total_packet_count = DIV_ROUND_UP(td_total_len, maxp); 3479 3480 /* Queueing functions don't count the current TRB into transferred */ 3481 return (total_packet_count - ((transferred + trb_buff_len) / maxp)); 3482 } 3483 3484 3485 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, 3486 u32 *trb_buff_len, struct xhci_segment *seg) 3487 { 3488 struct device *dev = xhci_to_hcd(xhci)->self.sysdev; 3489 unsigned int unalign; 3490 unsigned int max_pkt; 3491 u32 new_buff_len; 3492 size_t len; 3493 3494 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3495 unalign = (enqd_len + *trb_buff_len) % max_pkt; 3496 3497 /* we got lucky, last normal TRB data on segment is packet aligned */ 3498 if (unalign == 0) 3499 return 0; 3500 3501 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", 3502 unalign, *trb_buff_len); 3503 3504 /* is the last nornal TRB alignable by splitting it */ 3505 if (*trb_buff_len > unalign) { 3506 *trb_buff_len -= unalign; 3507 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); 3508 return 0; 3509 } 3510 3511 /* 3512 * We want enqd_len + trb_buff_len to sum up to a number aligned to 3513 * number which is divisible by the endpoint's wMaxPacketSize. IOW: 3514 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. 3515 */ 3516 new_buff_len = max_pkt - (enqd_len % max_pkt); 3517 3518 if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) 3519 new_buff_len = (urb->transfer_buffer_length - enqd_len); 3520 3521 /* create a max max_pkt sized bounce buffer pointed to by last trb */ 3522 if (usb_urb_dir_out(urb)) { 3523 if (urb->num_sgs) { 3524 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, 3525 seg->bounce_buf, new_buff_len, enqd_len); 3526 if (len != new_buff_len) 3527 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n", 3528 len, new_buff_len); 3529 } else { 3530 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len); 3531 } 3532 3533 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3534 max_pkt, DMA_TO_DEVICE); 3535 } else { 3536 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3537 max_pkt, DMA_FROM_DEVICE); 3538 } 3539 3540 if (dma_mapping_error(dev, seg->bounce_dma)) { 3541 /* try without aligning. Some host controllers survive */ 3542 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); 3543 return 0; 3544 } 3545 *trb_buff_len = new_buff_len; 3546 seg->bounce_len = new_buff_len; 3547 seg->bounce_offs = enqd_len; 3548 3549 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); 3550 3551 return 1; 3552 } 3553 3554 /* This is very similar to what ehci-q.c qtd_fill() does */ 3555 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3556 struct urb *urb, int slot_id, unsigned int ep_index) 3557 { 3558 struct xhci_ring *ring; 3559 struct urb_priv *urb_priv; 3560 struct xhci_td *td; 3561 struct xhci_generic_trb *start_trb; 3562 struct scatterlist *sg = NULL; 3563 bool more_trbs_coming = true; 3564 bool need_zero_pkt = false; 3565 bool first_trb = true; 3566 unsigned int num_trbs; 3567 unsigned int start_cycle, num_sgs = 0; 3568 unsigned int enqd_len, block_len, trb_buff_len, full_len; 3569 int sent_len, ret; 3570 u32 field, length_field, remainder; 3571 u64 addr, send_addr; 3572 3573 ring = xhci_urb_to_transfer_ring(xhci, urb); 3574 if (!ring) 3575 return -EINVAL; 3576 3577 full_len = urb->transfer_buffer_length; 3578 /* If we have scatter/gather list, we use it. */ 3579 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { 3580 num_sgs = urb->num_mapped_sgs; 3581 sg = urb->sg; 3582 addr = (u64) sg_dma_address(sg); 3583 block_len = sg_dma_len(sg); 3584 num_trbs = count_sg_trbs_needed(urb); 3585 } else { 3586 num_trbs = count_trbs_needed(urb); 3587 addr = (u64) urb->transfer_dma; 3588 block_len = full_len; 3589 } 3590 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3591 ep_index, urb->stream_id, 3592 num_trbs, urb, 0, mem_flags); 3593 if (unlikely(ret < 0)) 3594 return ret; 3595 3596 urb_priv = urb->hcpriv; 3597 3598 /* Deal with URB_ZERO_PACKET - need one more td/trb */ 3599 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) 3600 need_zero_pkt = true; 3601 3602 td = &urb_priv->td[0]; 3603 3604 /* 3605 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3606 * until we've finished creating all the other TRBs. The ring's cycle 3607 * state may change as we enqueue the other TRBs, so save it too. 3608 */ 3609 start_trb = &ring->enqueue->generic; 3610 start_cycle = ring->cycle_state; 3611 send_addr = addr; 3612 3613 /* Queue the TRBs, even if they are zero-length */ 3614 for (enqd_len = 0; first_trb || enqd_len < full_len; 3615 enqd_len += trb_buff_len) { 3616 field = TRB_TYPE(TRB_NORMAL); 3617 3618 /* TRB buffer should not cross 64KB boundaries */ 3619 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3620 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); 3621 3622 if (enqd_len + trb_buff_len > full_len) 3623 trb_buff_len = full_len - enqd_len; 3624 3625 /* Don't change the cycle bit of the first TRB until later */ 3626 if (first_trb) { 3627 first_trb = false; 3628 if (start_cycle == 0) 3629 field |= TRB_CYCLE; 3630 } else 3631 field |= ring->cycle_state; 3632 3633 /* Chain all the TRBs together; clear the chain bit in the last 3634 * TRB to indicate it's the last TRB in the chain. 3635 */ 3636 if (enqd_len + trb_buff_len < full_len) { 3637 field |= TRB_CHAIN; 3638 if (trb_is_link(ring->enqueue + 1)) { 3639 if (xhci_align_td(xhci, urb, enqd_len, 3640 &trb_buff_len, 3641 ring->enq_seg)) { 3642 send_addr = ring->enq_seg->bounce_dma; 3643 /* assuming TD won't span 2 segs */ 3644 td->bounce_seg = ring->enq_seg; 3645 } 3646 } 3647 } 3648 if (enqd_len + trb_buff_len >= full_len) { 3649 field &= ~TRB_CHAIN; 3650 field |= TRB_IOC; 3651 more_trbs_coming = false; 3652 td->last_trb = ring->enqueue; 3653 td->last_trb_seg = ring->enq_seg; 3654 if (xhci_urb_suitable_for_idt(urb)) { 3655 memcpy(&send_addr, urb->transfer_buffer, 3656 trb_buff_len); 3657 le64_to_cpus(&send_addr); 3658 field |= TRB_IDT; 3659 } 3660 } 3661 3662 /* Only set interrupt on short packet for IN endpoints */ 3663 if (usb_urb_dir_in(urb)) 3664 field |= TRB_ISP; 3665 3666 /* Set the TRB length, TD size, and interrupter fields. */ 3667 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, 3668 full_len, urb, more_trbs_coming); 3669 3670 length_field = TRB_LEN(trb_buff_len) | 3671 TRB_TD_SIZE(remainder) | 3672 TRB_INTR_TARGET(0); 3673 3674 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, 3675 lower_32_bits(send_addr), 3676 upper_32_bits(send_addr), 3677 length_field, 3678 field); 3679 addr += trb_buff_len; 3680 sent_len = trb_buff_len; 3681 3682 while (sg && sent_len >= block_len) { 3683 /* New sg entry */ 3684 --num_sgs; 3685 sent_len -= block_len; 3686 sg = sg_next(sg); 3687 if (num_sgs != 0 && sg) { 3688 block_len = sg_dma_len(sg); 3689 addr = (u64) sg_dma_address(sg); 3690 addr += sent_len; 3691 } 3692 } 3693 block_len -= sent_len; 3694 send_addr = addr; 3695 } 3696 3697 if (need_zero_pkt) { 3698 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3699 ep_index, urb->stream_id, 3700 1, urb, 1, mem_flags); 3701 urb_priv->td[1].last_trb = ring->enqueue; 3702 urb_priv->td[1].last_trb_seg = ring->enq_seg; 3703 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; 3704 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); 3705 } 3706 3707 check_trb_math(urb, enqd_len); 3708 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3709 start_cycle, start_trb); 3710 return 0; 3711 } 3712 3713 /* Caller must have locked xhci->lock */ 3714 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3715 struct urb *urb, int slot_id, unsigned int ep_index) 3716 { 3717 struct xhci_ring *ep_ring; 3718 int num_trbs; 3719 int ret; 3720 struct usb_ctrlrequest *setup; 3721 struct xhci_generic_trb *start_trb; 3722 int start_cycle; 3723 u32 field; 3724 struct urb_priv *urb_priv; 3725 struct xhci_td *td; 3726 3727 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3728 if (!ep_ring) 3729 return -EINVAL; 3730 3731 /* 3732 * Need to copy setup packet into setup TRB, so we can't use the setup 3733 * DMA address. 3734 */ 3735 if (!urb->setup_packet) 3736 return -EINVAL; 3737 3738 /* 1 TRB for setup, 1 for status */ 3739 num_trbs = 2; 3740 /* 3741 * Don't need to check if we need additional event data and normal TRBs, 3742 * since data in control transfers will never get bigger than 16MB 3743 * XXX: can we get a buffer that crosses 64KB boundaries? 3744 */ 3745 if (urb->transfer_buffer_length > 0) 3746 num_trbs++; 3747 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3748 ep_index, urb->stream_id, 3749 num_trbs, urb, 0, mem_flags); 3750 if (ret < 0) 3751 return ret; 3752 3753 urb_priv = urb->hcpriv; 3754 td = &urb_priv->td[0]; 3755 3756 /* 3757 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3758 * until we've finished creating all the other TRBs. The ring's cycle 3759 * state may change as we enqueue the other TRBs, so save it too. 3760 */ 3761 start_trb = &ep_ring->enqueue->generic; 3762 start_cycle = ep_ring->cycle_state; 3763 3764 /* Queue setup TRB - see section 6.4.1.2.1 */ 3765 /* FIXME better way to translate setup_packet into two u32 fields? */ 3766 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3767 field = 0; 3768 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3769 if (start_cycle == 0) 3770 field |= 0x1; 3771 3772 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ 3773 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { 3774 if (urb->transfer_buffer_length > 0) { 3775 if (setup->bRequestType & USB_DIR_IN) 3776 field |= TRB_TX_TYPE(TRB_DATA_IN); 3777 else 3778 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3779 } 3780 } 3781 3782 queue_trb(xhci, ep_ring, true, 3783 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3784 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3785 TRB_LEN(8) | TRB_INTR_TARGET(0), 3786 /* Immediate data in pointer */ 3787 field); 3788 3789 /* If there's data, queue data TRBs */ 3790 /* Only set interrupt on short packet for IN endpoints */ 3791 if (usb_urb_dir_in(urb)) 3792 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3793 else 3794 field = TRB_TYPE(TRB_DATA); 3795 3796 if (urb->transfer_buffer_length > 0) { 3797 u32 length_field, remainder; 3798 u64 addr; 3799 3800 if (xhci_urb_suitable_for_idt(urb)) { 3801 memcpy(&addr, urb->transfer_buffer, 3802 urb->transfer_buffer_length); 3803 le64_to_cpus(&addr); 3804 field |= TRB_IDT; 3805 } else { 3806 addr = (u64) urb->transfer_dma; 3807 } 3808 3809 remainder = xhci_td_remainder(xhci, 0, 3810 urb->transfer_buffer_length, 3811 urb->transfer_buffer_length, 3812 urb, 1); 3813 length_field = TRB_LEN(urb->transfer_buffer_length) | 3814 TRB_TD_SIZE(remainder) | 3815 TRB_INTR_TARGET(0); 3816 if (setup->bRequestType & USB_DIR_IN) 3817 field |= TRB_DIR_IN; 3818 queue_trb(xhci, ep_ring, true, 3819 lower_32_bits(addr), 3820 upper_32_bits(addr), 3821 length_field, 3822 field | ep_ring->cycle_state); 3823 } 3824 3825 /* Save the DMA address of the last TRB in the TD */ 3826 td->last_trb = ep_ring->enqueue; 3827 td->last_trb_seg = ep_ring->enq_seg; 3828 3829 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3830 /* If the device sent data, the status stage is an OUT transfer */ 3831 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3832 field = 0; 3833 else 3834 field = TRB_DIR_IN; 3835 queue_trb(xhci, ep_ring, false, 3836 0, 3837 0, 3838 TRB_INTR_TARGET(0), 3839 /* Event on completion */ 3840 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3841 3842 giveback_first_trb(xhci, slot_id, ep_index, 0, 3843 start_cycle, start_trb); 3844 return 0; 3845 } 3846 3847 /* 3848 * The transfer burst count field of the isochronous TRB defines the number of 3849 * bursts that are required to move all packets in this TD. Only SuperSpeed 3850 * devices can burst up to bMaxBurst number of packets per service interval. 3851 * This field is zero based, meaning a value of zero in the field means one 3852 * burst. Basically, for everything but SuperSpeed devices, this field will be 3853 * zero. Only xHCI 1.0 host controllers support this field. 3854 */ 3855 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3856 struct urb *urb, unsigned int total_packet_count) 3857 { 3858 unsigned int max_burst; 3859 3860 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) 3861 return 0; 3862 3863 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3864 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; 3865 } 3866 3867 /* 3868 * Returns the number of packets in the last "burst" of packets. This field is 3869 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3870 * the last burst packet count is equal to the total number of packets in the 3871 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3872 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3873 * contain 1 to (bMaxBurst + 1) packets. 3874 */ 3875 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3876 struct urb *urb, unsigned int total_packet_count) 3877 { 3878 unsigned int max_burst; 3879 unsigned int residue; 3880 3881 if (xhci->hci_version < 0x100) 3882 return 0; 3883 3884 if (urb->dev->speed >= USB_SPEED_SUPER) { 3885 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3886 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3887 residue = total_packet_count % (max_burst + 1); 3888 /* If residue is zero, the last burst contains (max_burst + 1) 3889 * number of packets, but the TLBPC field is zero-based. 3890 */ 3891 if (residue == 0) 3892 return max_burst; 3893 return residue - 1; 3894 } 3895 if (total_packet_count == 0) 3896 return 0; 3897 return total_packet_count - 1; 3898 } 3899 3900 /* 3901 * Calculates Frame ID field of the isochronous TRB identifies the 3902 * target frame that the Interval associated with this Isochronous 3903 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. 3904 * 3905 * Returns actual frame id on success, negative value on error. 3906 */ 3907 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, 3908 struct urb *urb, int index) 3909 { 3910 int start_frame, ist, ret = 0; 3911 int start_frame_id, end_frame_id, current_frame_id; 3912 3913 if (urb->dev->speed == USB_SPEED_LOW || 3914 urb->dev->speed == USB_SPEED_FULL) 3915 start_frame = urb->start_frame + index * urb->interval; 3916 else 3917 start_frame = (urb->start_frame + index * urb->interval) >> 3; 3918 3919 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): 3920 * 3921 * If bit [3] of IST is cleared to '0', software can add a TRB no 3922 * later than IST[2:0] Microframes before that TRB is scheduled to 3923 * be executed. 3924 * If bit [3] of IST is set to '1', software can add a TRB no later 3925 * than IST[2:0] Frames before that TRB is scheduled to be executed. 3926 */ 3927 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3928 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3929 ist <<= 3; 3930 3931 /* Software shall not schedule an Isoch TD with a Frame ID value that 3932 * is less than the Start Frame ID or greater than the End Frame ID, 3933 * where: 3934 * 3935 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 3936 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 3937 * 3938 * Both the End Frame ID and Start Frame ID values are calculated 3939 * in microframes. When software determines the valid Frame ID value; 3940 * The End Frame ID value should be rounded down to the nearest Frame 3941 * boundary, and the Start Frame ID value should be rounded up to the 3942 * nearest Frame boundary. 3943 */ 3944 current_frame_id = readl(&xhci->run_regs->microframe_index); 3945 start_frame_id = roundup(current_frame_id + ist + 1, 8); 3946 end_frame_id = rounddown(current_frame_id + 895 * 8, 8); 3947 3948 start_frame &= 0x7ff; 3949 start_frame_id = (start_frame_id >> 3) & 0x7ff; 3950 end_frame_id = (end_frame_id >> 3) & 0x7ff; 3951 3952 if (start_frame_id < end_frame_id) { 3953 if (start_frame > end_frame_id || 3954 start_frame < start_frame_id) 3955 ret = -EINVAL; 3956 } else if (start_frame_id > end_frame_id) { 3957 if ((start_frame > end_frame_id && 3958 start_frame < start_frame_id)) 3959 ret = -EINVAL; 3960 } else { 3961 ret = -EINVAL; 3962 } 3963 3964 if (index == 0) { 3965 if (ret == -EINVAL || start_frame == start_frame_id) { 3966 start_frame = start_frame_id + 1; 3967 if (urb->dev->speed == USB_SPEED_LOW || 3968 urb->dev->speed == USB_SPEED_FULL) 3969 urb->start_frame = start_frame; 3970 else 3971 urb->start_frame = start_frame << 3; 3972 ret = 0; 3973 } 3974 } 3975 3976 if (ret) { 3977 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", 3978 start_frame, current_frame_id, index, 3979 start_frame_id, end_frame_id); 3980 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); 3981 return ret; 3982 } 3983 3984 return start_frame; 3985 } 3986 3987 /* Check if we should generate event interrupt for a TD in an isoc URB */ 3988 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i, 3989 struct xhci_interrupter *ir) 3990 { 3991 if (xhci->hci_version < 0x100) 3992 return false; 3993 /* always generate an event interrupt for the last TD */ 3994 if (i == num_tds - 1) 3995 return false; 3996 /* 3997 * If AVOID_BEI is set the host handles full event rings poorly, 3998 * generate an event at least every 8th TD to clear the event ring 3999 */ 4000 if (i && ir->isoc_bei_interval && xhci->quirks & XHCI_AVOID_BEI) 4001 return !!(i % ir->isoc_bei_interval); 4002 4003 return true; 4004 } 4005 4006 /* This is for isoc transfer */ 4007 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 4008 struct urb *urb, int slot_id, unsigned int ep_index) 4009 { 4010 struct xhci_interrupter *ir; 4011 struct xhci_ring *ep_ring; 4012 struct urb_priv *urb_priv; 4013 struct xhci_td *td; 4014 int num_tds, trbs_per_td; 4015 struct xhci_generic_trb *start_trb; 4016 bool first_trb; 4017 int start_cycle; 4018 u32 field, length_field; 4019 int running_total, trb_buff_len, td_len, td_remain_len, ret; 4020 u64 start_addr, addr; 4021 int i, j; 4022 bool more_trbs_coming; 4023 struct xhci_virt_ep *xep; 4024 int frame_id; 4025 4026 xep = &xhci->devs[slot_id]->eps[ep_index]; 4027 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 4028 ir = xhci->interrupters[0]; 4029 4030 num_tds = urb->number_of_packets; 4031 if (num_tds < 1) { 4032 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 4033 return -EINVAL; 4034 } 4035 start_addr = (u64) urb->transfer_dma; 4036 start_trb = &ep_ring->enqueue->generic; 4037 start_cycle = ep_ring->cycle_state; 4038 4039 urb_priv = urb->hcpriv; 4040 /* Queue the TRBs for each TD, even if they are zero-length */ 4041 for (i = 0; i < num_tds; i++) { 4042 unsigned int total_pkt_count, max_pkt; 4043 unsigned int burst_count, last_burst_pkt_count; 4044 u32 sia_frame_id; 4045 4046 first_trb = true; 4047 running_total = 0; 4048 addr = start_addr + urb->iso_frame_desc[i].offset; 4049 td_len = urb->iso_frame_desc[i].length; 4050 td_remain_len = td_len; 4051 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 4052 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); 4053 4054 /* A zero-length transfer still involves at least one packet. */ 4055 if (total_pkt_count == 0) 4056 total_pkt_count++; 4057 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); 4058 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, 4059 urb, total_pkt_count); 4060 4061 trbs_per_td = count_isoc_trbs_needed(urb, i); 4062 4063 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 4064 urb->stream_id, trbs_per_td, urb, i, mem_flags); 4065 if (ret < 0) { 4066 if (i == 0) 4067 return ret; 4068 goto cleanup; 4069 } 4070 td = &urb_priv->td[i]; 4071 /* use SIA as default, if frame id is used overwrite it */ 4072 sia_frame_id = TRB_SIA; 4073 if (!(urb->transfer_flags & URB_ISO_ASAP) && 4074 HCC_CFC(xhci->hcc_params)) { 4075 frame_id = xhci_get_isoc_frame_id(xhci, urb, i); 4076 if (frame_id >= 0) 4077 sia_frame_id = TRB_FRAME_ID(frame_id); 4078 } 4079 /* 4080 * Set isoc specific data for the first TRB in a TD. 4081 * Prevent HW from getting the TRBs by keeping the cycle state 4082 * inverted in the first TDs isoc TRB. 4083 */ 4084 field = TRB_TYPE(TRB_ISOC) | 4085 TRB_TLBPC(last_burst_pkt_count) | 4086 sia_frame_id | 4087 (i ? ep_ring->cycle_state : !start_cycle); 4088 4089 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ 4090 if (!xep->use_extended_tbc) 4091 field |= TRB_TBC(burst_count); 4092 4093 /* fill the rest of the TRB fields, and remaining normal TRBs */ 4094 for (j = 0; j < trbs_per_td; j++) { 4095 u32 remainder = 0; 4096 4097 /* only first TRB is isoc, overwrite otherwise */ 4098 if (!first_trb) 4099 field = TRB_TYPE(TRB_NORMAL) | 4100 ep_ring->cycle_state; 4101 4102 /* Only set interrupt on short packet for IN EPs */ 4103 if (usb_urb_dir_in(urb)) 4104 field |= TRB_ISP; 4105 4106 /* Set the chain bit for all except the last TRB */ 4107 if (j < trbs_per_td - 1) { 4108 more_trbs_coming = true; 4109 field |= TRB_CHAIN; 4110 } else { 4111 more_trbs_coming = false; 4112 td->last_trb = ep_ring->enqueue; 4113 td->last_trb_seg = ep_ring->enq_seg; 4114 field |= TRB_IOC; 4115 if (trb_block_event_intr(xhci, num_tds, i, ir)) 4116 field |= TRB_BEI; 4117 } 4118 /* Calculate TRB length */ 4119 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 4120 if (trb_buff_len > td_remain_len) 4121 trb_buff_len = td_remain_len; 4122 4123 /* Set the TRB length, TD size, & interrupter fields. */ 4124 remainder = xhci_td_remainder(xhci, running_total, 4125 trb_buff_len, td_len, 4126 urb, more_trbs_coming); 4127 4128 length_field = TRB_LEN(trb_buff_len) | 4129 TRB_INTR_TARGET(0); 4130 4131 /* xhci 1.1 with ETE uses TD Size field for TBC */ 4132 if (first_trb && xep->use_extended_tbc) 4133 length_field |= TRB_TD_SIZE_TBC(burst_count); 4134 else 4135 length_field |= TRB_TD_SIZE(remainder); 4136 first_trb = false; 4137 4138 queue_trb(xhci, ep_ring, more_trbs_coming, 4139 lower_32_bits(addr), 4140 upper_32_bits(addr), 4141 length_field, 4142 field); 4143 running_total += trb_buff_len; 4144 4145 addr += trb_buff_len; 4146 td_remain_len -= trb_buff_len; 4147 } 4148 4149 /* Check TD length */ 4150 if (running_total != td_len) { 4151 xhci_err(xhci, "ISOC TD length unmatch\n"); 4152 ret = -EINVAL; 4153 goto cleanup; 4154 } 4155 } 4156 4157 /* store the next frame id */ 4158 if (HCC_CFC(xhci->hcc_params)) 4159 xep->next_frame_id = urb->start_frame + num_tds * urb->interval; 4160 4161 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 4162 if (xhci->quirks & XHCI_AMD_PLL_FIX) 4163 usb_amd_quirk_pll_disable(); 4164 } 4165 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 4166 4167 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 4168 start_cycle, start_trb); 4169 return 0; 4170 cleanup: 4171 /* Clean up a partially enqueued isoc transfer. */ 4172 4173 for (i--; i >= 0; i--) 4174 list_del_init(&urb_priv->td[i].td_list); 4175 4176 /* Use the first TD as a temporary variable to turn the TDs we've queued 4177 * into No-ops with a software-owned cycle bit. That way the hardware 4178 * won't accidentally start executing bogus TDs when we partially 4179 * overwrite them. td->first_trb and td->start_seg are already set. 4180 */ 4181 urb_priv->td[0].last_trb = ep_ring->enqueue; 4182 /* Every TRB except the first & last will have its cycle bit flipped. */ 4183 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); 4184 4185 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 4186 ep_ring->enqueue = urb_priv->td[0].first_trb; 4187 ep_ring->enq_seg = urb_priv->td[0].start_seg; 4188 ep_ring->cycle_state = start_cycle; 4189 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 4190 return ret; 4191 } 4192 4193 /* 4194 * Check transfer ring to guarantee there is enough room for the urb. 4195 * Update ISO URB start_frame and interval. 4196 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to 4197 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or 4198 * Contiguous Frame ID is not supported by HC. 4199 */ 4200 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 4201 struct urb *urb, int slot_id, unsigned int ep_index) 4202 { 4203 struct xhci_virt_device *xdev; 4204 struct xhci_ring *ep_ring; 4205 struct xhci_ep_ctx *ep_ctx; 4206 int start_frame; 4207 int num_tds, num_trbs, i; 4208 int ret; 4209 struct xhci_virt_ep *xep; 4210 int ist; 4211 4212 xdev = xhci->devs[slot_id]; 4213 xep = &xhci->devs[slot_id]->eps[ep_index]; 4214 ep_ring = xdev->eps[ep_index].ring; 4215 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 4216 4217 num_trbs = 0; 4218 num_tds = urb->number_of_packets; 4219 for (i = 0; i < num_tds; i++) 4220 num_trbs += count_isoc_trbs_needed(urb, i); 4221 4222 /* Check the ring to guarantee there is enough room for the whole urb. 4223 * Do not insert any td of the urb to the ring if the check failed. 4224 */ 4225 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 4226 num_trbs, mem_flags); 4227 if (ret) 4228 return ret; 4229 4230 /* 4231 * Check interval value. This should be done before we start to 4232 * calculate the start frame value. 4233 */ 4234 check_interval(urb, ep_ctx); 4235 4236 /* Calculate the start frame and put it in urb->start_frame. */ 4237 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { 4238 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { 4239 urb->start_frame = xep->next_frame_id; 4240 goto skip_start_over; 4241 } 4242 } 4243 4244 start_frame = readl(&xhci->run_regs->microframe_index); 4245 start_frame &= 0x3fff; 4246 /* 4247 * Round up to the next frame and consider the time before trb really 4248 * gets scheduled by hardare. 4249 */ 4250 ist = HCS_IST(xhci->hcs_params2) & 0x7; 4251 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 4252 ist <<= 3; 4253 start_frame += ist + XHCI_CFC_DELAY; 4254 start_frame = roundup(start_frame, 8); 4255 4256 /* 4257 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT 4258 * is greate than 8 microframes. 4259 */ 4260 if (urb->dev->speed == USB_SPEED_LOW || 4261 urb->dev->speed == USB_SPEED_FULL) { 4262 start_frame = roundup(start_frame, urb->interval << 3); 4263 urb->start_frame = start_frame >> 3; 4264 } else { 4265 start_frame = roundup(start_frame, urb->interval); 4266 urb->start_frame = start_frame; 4267 } 4268 4269 skip_start_over: 4270 4271 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 4272 } 4273 4274 /**** Command Ring Operations ****/ 4275 4276 /* Generic function for queueing a command TRB on the command ring. 4277 * Check to make sure there's room on the command ring for one command TRB. 4278 * Also check that there's room reserved for commands that must not fail. 4279 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 4280 * then only check for the number of reserved spots. 4281 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 4282 * because the command event handler may want to resubmit a failed command. 4283 */ 4284 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 4285 u32 field1, u32 field2, 4286 u32 field3, u32 field4, bool command_must_succeed) 4287 { 4288 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 4289 int ret; 4290 4291 if ((xhci->xhc_state & XHCI_STATE_DYING) || 4292 (xhci->xhc_state & XHCI_STATE_HALTED)) { 4293 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); 4294 return -ESHUTDOWN; 4295 } 4296 4297 if (!command_must_succeed) 4298 reserved_trbs++; 4299 4300 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 4301 reserved_trbs, GFP_ATOMIC); 4302 if (ret < 0) { 4303 xhci_err(xhci, "ERR: No room for command on command ring\n"); 4304 if (command_must_succeed) 4305 xhci_err(xhci, "ERR: Reserved TRB counting for " 4306 "unfailable commands failed.\n"); 4307 return ret; 4308 } 4309 4310 cmd->command_trb = xhci->cmd_ring->enqueue; 4311 4312 /* if there are no other commands queued we start the timeout timer */ 4313 if (list_empty(&xhci->cmd_list)) { 4314 xhci->current_cmd = cmd; 4315 xhci_mod_cmd_timer(xhci); 4316 } 4317 4318 list_add_tail(&cmd->cmd_list, &xhci->cmd_list); 4319 4320 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 4321 field4 | xhci->cmd_ring->cycle_state); 4322 return 0; 4323 } 4324 4325 /* Queue a slot enable or disable request on the command ring */ 4326 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 4327 u32 trb_type, u32 slot_id) 4328 { 4329 return queue_command(xhci, cmd, 0, 0, 0, 4330 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 4331 } 4332 4333 /* Queue an address device command TRB */ 4334 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 4335 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) 4336 { 4337 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4338 upper_32_bits(in_ctx_ptr), 0, 4339 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) 4340 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); 4341 } 4342 4343 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 4344 u32 field1, u32 field2, u32 field3, u32 field4) 4345 { 4346 return queue_command(xhci, cmd, field1, field2, field3, field4, false); 4347 } 4348 4349 /* Queue a reset device command TRB */ 4350 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 4351 u32 slot_id) 4352 { 4353 return queue_command(xhci, cmd, 0, 0, 0, 4354 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 4355 false); 4356 } 4357 4358 /* Queue a configure endpoint command TRB */ 4359 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 4360 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 4361 u32 slot_id, bool command_must_succeed) 4362 { 4363 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4364 upper_32_bits(in_ctx_ptr), 0, 4365 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 4366 command_must_succeed); 4367 } 4368 4369 /* Queue an evaluate context command TRB */ 4370 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 4371 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) 4372 { 4373 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4374 upper_32_bits(in_ctx_ptr), 0, 4375 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 4376 command_must_succeed); 4377 } 4378 4379 /* 4380 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 4381 * activity on an endpoint that is about to be suspended. 4382 */ 4383 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 4384 int slot_id, unsigned int ep_index, int suspend) 4385 { 4386 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4387 u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index); 4388 u32 type = TRB_TYPE(TRB_STOP_RING); 4389 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 4390 4391 return queue_command(xhci, cmd, 0, 0, 0, 4392 trb_slot_id | trb_ep_index | type | trb_suspend, false); 4393 } 4394 4395 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 4396 int slot_id, unsigned int ep_index, 4397 enum xhci_ep_reset_type reset_type) 4398 { 4399 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4400 u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index); 4401 u32 type = TRB_TYPE(TRB_RESET_EP); 4402 4403 if (reset_type == EP_SOFT_RESET) 4404 type |= TRB_TSP; 4405 4406 return queue_command(xhci, cmd, 0, 0, 0, 4407 trb_slot_id | trb_ep_index | type, false); 4408 } 4409