1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 * Ring initialization rules: 25 * 1. Each segment is initialized to zero, except for link TRBs. 26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 27 * Consumer Cycle State (CCS), depending on ring function. 28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 29 * 30 * Ring behavior rules: 31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 32 * least one free TRB in the ring. This is useful if you want to turn that 33 * into a link TRB and expand the ring. 34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 35 * link TRB, then load the pointer with the address in the link TRB. If the 36 * link TRB had its toggle bit set, you may need to update the ring cycle 37 * state (see cycle bit rules). You may have to do this multiple times 38 * until you reach a non-link TRB. 39 * 3. A ring is full if enqueue++ (for the definition of increment above) 40 * equals the dequeue pointer. 41 * 42 * Cycle bit rules: 43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 44 * in a link TRB, it must toggle the ring cycle state. 45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 46 * in a link TRB, it must toggle the ring cycle state. 47 * 48 * Producer rules: 49 * 1. Check if ring is full before you enqueue. 50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 51 * Update enqueue pointer between each write (which may update the ring 52 * cycle state). 53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 54 * and endpoint rings. If HC is the producer for the event ring, 55 * and it generates an interrupt according to interrupt modulation rules. 56 * 57 * Consumer rules: 58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 59 * the TRB is owned by the consumer. 60 * 2. Update dequeue pointer (which may update the ring cycle state) and 61 * continue processing TRBs until you reach a TRB which is not owned by you. 62 * 3. Notify the producer. SW is the consumer for the event ring, and it 63 * updates event ring dequeue pointer. HC is the consumer for the command and 64 * endpoint rings; it generates events on the event ring for these. 65 */ 66 67 #include <linux/scatterlist.h> 68 #include <linux/slab.h> 69 #include "xhci.h" 70 71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, 72 struct xhci_virt_device *virt_dev, 73 struct xhci_event_cmd *event); 74 75 /* 76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 77 * address of the TRB. 78 */ 79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 80 union xhci_trb *trb) 81 { 82 unsigned long segment_offset; 83 84 if (!seg || !trb || trb < seg->trbs) 85 return 0; 86 /* offset in TRBs */ 87 segment_offset = trb - seg->trbs; 88 if (segment_offset > TRBS_PER_SEGMENT) 89 return 0; 90 return seg->dma + (segment_offset * sizeof(*trb)); 91 } 92 93 /* Does this link TRB point to the first segment in a ring, 94 * or was the previous TRB the last TRB on the last segment in the ERST? 95 */ 96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, 97 struct xhci_segment *seg, union xhci_trb *trb) 98 { 99 if (ring == xhci->event_ring) 100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && 101 (seg->next == xhci->event_ring->first_seg); 102 else 103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 104 } 105 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring 107 * segment? I.e. would the updated event TRB pointer step off the end of the 108 * event seg? 109 */ 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 111 struct xhci_segment *seg, union xhci_trb *trb) 112 { 113 if (ring == xhci->event_ring) 114 return trb == &seg->trbs[TRBS_PER_SEGMENT]; 115 else 116 return TRB_TYPE_LINK_LE32(trb->link.control); 117 } 118 119 static int enqueue_is_link_trb(struct xhci_ring *ring) 120 { 121 struct xhci_link_trb *link = &ring->enqueue->link; 122 return TRB_TYPE_LINK_LE32(link->control); 123 } 124 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 126 * TRB is in a new segment. This does not skip over link TRBs, and it does not 127 * effect the ring dequeue or enqueue pointers. 128 */ 129 static void next_trb(struct xhci_hcd *xhci, 130 struct xhci_ring *ring, 131 struct xhci_segment **seg, 132 union xhci_trb **trb) 133 { 134 if (last_trb(xhci, ring, *seg, *trb)) { 135 *seg = (*seg)->next; 136 *trb = ((*seg)->trbs); 137 } else { 138 (*trb)++; 139 } 140 } 141 142 /* 143 * See Cycle bit rules. SW is the consumer for the event ring only. 144 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 145 */ 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 147 { 148 unsigned long long addr; 149 150 ring->deq_updates++; 151 152 /* 153 * If this is not event ring, and the dequeue pointer 154 * is not on a link TRB, there is one more usable TRB 155 */ 156 if (ring->type != TYPE_EVENT && 157 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) 158 ring->num_trbs_free++; 159 160 do { 161 /* 162 * Update the dequeue pointer further if that was a link TRB or 163 * we're at the end of an event ring segment (which doesn't have 164 * link TRBS) 165 */ 166 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { 167 if (ring->type == TYPE_EVENT && 168 last_trb_on_last_seg(xhci, ring, 169 ring->deq_seg, ring->dequeue)) { 170 ring->cycle_state = (ring->cycle_state ? 0 : 1); 171 } 172 ring->deq_seg = ring->deq_seg->next; 173 ring->dequeue = ring->deq_seg->trbs; 174 } else { 175 ring->dequeue++; 176 } 177 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); 178 179 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); 180 } 181 182 /* 183 * See Cycle bit rules. SW is the consumer for the event ring only. 184 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 185 * 186 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 187 * chain bit is set), then set the chain bit in all the following link TRBs. 188 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 189 * have their chain bit cleared (so that each Link TRB is a separate TD). 190 * 191 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 192 * set, but other sections talk about dealing with the chain bit set. This was 193 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 194 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 195 * 196 * @more_trbs_coming: Will you enqueue more TRBs before calling 197 * prepare_transfer()? 198 */ 199 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 200 bool more_trbs_coming) 201 { 202 u32 chain; 203 union xhci_trb *next; 204 unsigned long long addr; 205 206 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 207 /* If this is not event ring, there is one less usable TRB */ 208 if (ring->type != TYPE_EVENT && 209 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) 210 ring->num_trbs_free--; 211 next = ++(ring->enqueue); 212 213 ring->enq_updates++; 214 /* Update the dequeue pointer further if that was a link TRB or we're at 215 * the end of an event ring segment (which doesn't have link TRBS) 216 */ 217 while (last_trb(xhci, ring, ring->enq_seg, next)) { 218 if (ring->type != TYPE_EVENT) { 219 /* 220 * If the caller doesn't plan on enqueueing more 221 * TDs before ringing the doorbell, then we 222 * don't want to give the link TRB to the 223 * hardware just yet. We'll give the link TRB 224 * back in prepare_ring() just before we enqueue 225 * the TD at the top of the ring. 226 */ 227 if (!chain && !more_trbs_coming) 228 break; 229 230 /* If we're not dealing with 0.95 hardware or 231 * isoc rings on AMD 0.96 host, 232 * carry over the chain bit of the previous TRB 233 * (which may mean the chain bit is cleared). 234 */ 235 if (!(ring->type == TYPE_ISOC && 236 (xhci->quirks & XHCI_AMD_0x96_HOST)) 237 && !xhci_link_trb_quirk(xhci)) { 238 next->link.control &= 239 cpu_to_le32(~TRB_CHAIN); 240 next->link.control |= 241 cpu_to_le32(chain); 242 } 243 /* Give this link TRB to the hardware */ 244 wmb(); 245 next->link.control ^= cpu_to_le32(TRB_CYCLE); 246 247 /* Toggle the cycle bit after the last ring segment. */ 248 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { 249 ring->cycle_state = (ring->cycle_state ? 0 : 1); 250 } 251 } 252 ring->enq_seg = ring->enq_seg->next; 253 ring->enqueue = ring->enq_seg->trbs; 254 next = ring->enqueue; 255 } 256 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); 257 } 258 259 /* 260 * Check to see if there's room to enqueue num_trbs on the ring and make sure 261 * enqueue pointer will not advance into dequeue segment. See rules above. 262 */ 263 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 264 unsigned int num_trbs) 265 { 266 int num_trbs_in_deq_seg; 267 268 if (ring->num_trbs_free < num_trbs) 269 return 0; 270 271 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { 272 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; 273 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) 274 return 0; 275 } 276 277 return 1; 278 } 279 280 /* Ring the host controller doorbell after placing a command on the ring */ 281 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 282 { 283 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 284 return; 285 286 xhci_dbg(xhci, "// Ding dong!\n"); 287 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); 288 /* Flush PCI posted writes */ 289 xhci_readl(xhci, &xhci->dba->doorbell[0]); 290 } 291 292 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) 293 { 294 u64 temp_64; 295 int ret; 296 297 xhci_dbg(xhci, "Abort command ring\n"); 298 299 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) { 300 xhci_dbg(xhci, "The command ring isn't running, " 301 "Have the command ring been stopped?\n"); 302 return 0; 303 } 304 305 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 306 if (!(temp_64 & CMD_RING_RUNNING)) { 307 xhci_dbg(xhci, "Command ring had been stopped\n"); 308 return 0; 309 } 310 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 311 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, 312 &xhci->op_regs->cmd_ring); 313 314 /* Section 4.6.1.2 of xHCI 1.0 spec says software should 315 * time the completion od all xHCI commands, including 316 * the Command Abort operation. If software doesn't see 317 * CRR negated in a timely manner (e.g. longer than 5 318 * seconds), then it should assume that the there are 319 * larger problems with the xHC and assert HCRST. 320 */ 321 ret = handshake(xhci, &xhci->op_regs->cmd_ring, 322 CMD_RING_RUNNING, 0, 5 * 1000 * 1000); 323 if (ret < 0) { 324 xhci_err(xhci, "Stopped the command ring failed, " 325 "maybe the host is dead\n"); 326 xhci->xhc_state |= XHCI_STATE_DYING; 327 xhci_quiesce(xhci); 328 xhci_halt(xhci); 329 return -ESHUTDOWN; 330 } 331 332 return 0; 333 } 334 335 static int xhci_queue_cd(struct xhci_hcd *xhci, 336 struct xhci_command *command, 337 union xhci_trb *cmd_trb) 338 { 339 struct xhci_cd *cd; 340 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC); 341 if (!cd) 342 return -ENOMEM; 343 INIT_LIST_HEAD(&cd->cancel_cmd_list); 344 345 cd->command = command; 346 cd->cmd_trb = cmd_trb; 347 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list); 348 349 return 0; 350 } 351 352 /* 353 * Cancel the command which has issue. 354 * 355 * Some commands may hang due to waiting for acknowledgement from 356 * usb device. It is outside of the xHC's ability to control and 357 * will cause the command ring is blocked. When it occurs software 358 * should intervene to recover the command ring. 359 * See Section 4.6.1.1 and 4.6.1.2 360 */ 361 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command, 362 union xhci_trb *cmd_trb) 363 { 364 int retval = 0; 365 unsigned long flags; 366 367 spin_lock_irqsave(&xhci->lock, flags); 368 369 if (xhci->xhc_state & XHCI_STATE_DYING) { 370 xhci_warn(xhci, "Abort the command ring," 371 " but the xHCI is dead.\n"); 372 retval = -ESHUTDOWN; 373 goto fail; 374 } 375 376 /* queue the cmd desriptor to cancel_cmd_list */ 377 retval = xhci_queue_cd(xhci, command, cmd_trb); 378 if (retval) { 379 xhci_warn(xhci, "Queuing command descriptor failed.\n"); 380 goto fail; 381 } 382 383 /* abort command ring */ 384 retval = xhci_abort_cmd_ring(xhci); 385 if (retval) { 386 xhci_err(xhci, "Abort command ring failed\n"); 387 if (unlikely(retval == -ESHUTDOWN)) { 388 spin_unlock_irqrestore(&xhci->lock, flags); 389 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); 390 xhci_dbg(xhci, "xHCI host controller is dead.\n"); 391 return retval; 392 } 393 } 394 395 fail: 396 spin_unlock_irqrestore(&xhci->lock, flags); 397 return retval; 398 } 399 400 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 401 unsigned int slot_id, 402 unsigned int ep_index, 403 unsigned int stream_id) 404 { 405 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 406 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 407 unsigned int ep_state = ep->ep_state; 408 409 /* Don't ring the doorbell for this endpoint if there are pending 410 * cancellations because we don't want to interrupt processing. 411 * We don't want to restart any stream rings if there's a set dequeue 412 * pointer command pending because the device can choose to start any 413 * stream once the endpoint is on the HW schedule. 414 * FIXME - check all the stream rings for pending cancellations. 415 */ 416 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || 417 (ep_state & EP_HALTED)) 418 return; 419 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); 420 /* The CPU has better things to do at this point than wait for a 421 * write-posting flush. It'll get there soon enough. 422 */ 423 } 424 425 /* Ring the doorbell for any rings with pending URBs */ 426 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 427 unsigned int slot_id, 428 unsigned int ep_index) 429 { 430 unsigned int stream_id; 431 struct xhci_virt_ep *ep; 432 433 ep = &xhci->devs[slot_id]->eps[ep_index]; 434 435 /* A ring has pending URBs if its TD list is not empty */ 436 if (!(ep->ep_state & EP_HAS_STREAMS)) { 437 if (!(list_empty(&ep->ring->td_list))) 438 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 439 return; 440 } 441 442 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 443 stream_id++) { 444 struct xhci_stream_info *stream_info = ep->stream_info; 445 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 446 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 447 stream_id); 448 } 449 } 450 451 /* 452 * Find the segment that trb is in. Start searching in start_seg. 453 * If we must move past a segment that has a link TRB with a toggle cycle state 454 * bit set, then we will toggle the value pointed at by cycle_state. 455 */ 456 static struct xhci_segment *find_trb_seg( 457 struct xhci_segment *start_seg, 458 union xhci_trb *trb, int *cycle_state) 459 { 460 struct xhci_segment *cur_seg = start_seg; 461 struct xhci_generic_trb *generic_trb; 462 463 while (cur_seg->trbs > trb || 464 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { 465 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; 466 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE)) 467 *cycle_state ^= 0x1; 468 cur_seg = cur_seg->next; 469 if (cur_seg == start_seg) 470 /* Looped over the entire list. Oops! */ 471 return NULL; 472 } 473 return cur_seg; 474 } 475 476 477 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 478 unsigned int slot_id, unsigned int ep_index, 479 unsigned int stream_id) 480 { 481 struct xhci_virt_ep *ep; 482 483 ep = &xhci->devs[slot_id]->eps[ep_index]; 484 /* Common case: no streams */ 485 if (!(ep->ep_state & EP_HAS_STREAMS)) 486 return ep->ring; 487 488 if (stream_id == 0) { 489 xhci_warn(xhci, 490 "WARN: Slot ID %u, ep index %u has streams, " 491 "but URB has no stream ID.\n", 492 slot_id, ep_index); 493 return NULL; 494 } 495 496 if (stream_id < ep->stream_info->num_streams) 497 return ep->stream_info->stream_rings[stream_id]; 498 499 xhci_warn(xhci, 500 "WARN: Slot ID %u, ep index %u has " 501 "stream IDs 1 to %u allocated, " 502 "but stream ID %u is requested.\n", 503 slot_id, ep_index, 504 ep->stream_info->num_streams - 1, 505 stream_id); 506 return NULL; 507 } 508 509 /* Get the right ring for the given URB. 510 * If the endpoint supports streams, boundary check the URB's stream ID. 511 * If the endpoint doesn't support streams, return the singular endpoint ring. 512 */ 513 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 514 struct urb *urb) 515 { 516 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 517 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); 518 } 519 520 /* 521 * Move the xHC's endpoint ring dequeue pointer past cur_td. 522 * Record the new state of the xHC's endpoint ring dequeue segment, 523 * dequeue pointer, and new consumer cycle state in state. 524 * Update our internal representation of the ring's dequeue pointer. 525 * 526 * We do this in three jumps: 527 * - First we update our new ring state to be the same as when the xHC stopped. 528 * - Then we traverse the ring to find the segment that contains 529 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass 530 * any link TRBs with the toggle cycle bit set. 531 * - Finally we move the dequeue state one TRB further, toggling the cycle bit 532 * if we've moved it past a link TRB with the toggle cycle bit set. 533 * 534 * Some of the uses of xhci_generic_trb are grotty, but if they're done 535 * with correct __le32 accesses they should work fine. Only users of this are 536 * in here. 537 */ 538 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 539 unsigned int slot_id, unsigned int ep_index, 540 unsigned int stream_id, struct xhci_td *cur_td, 541 struct xhci_dequeue_state *state) 542 { 543 struct xhci_virt_device *dev = xhci->devs[slot_id]; 544 struct xhci_ring *ep_ring; 545 struct xhci_generic_trb *trb; 546 struct xhci_ep_ctx *ep_ctx; 547 dma_addr_t addr; 548 549 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 550 ep_index, stream_id); 551 if (!ep_ring) { 552 xhci_warn(xhci, "WARN can't find new dequeue state " 553 "for invalid stream ID %u.\n", 554 stream_id); 555 return; 556 } 557 state->new_cycle_state = 0; 558 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); 559 state->new_deq_seg = find_trb_seg(cur_td->start_seg, 560 dev->eps[ep_index].stopped_trb, 561 &state->new_cycle_state); 562 if (!state->new_deq_seg) { 563 WARN_ON(1); 564 return; 565 } 566 567 /* Dig out the cycle state saved by the xHC during the stop ep cmd */ 568 xhci_dbg(xhci, "Finding endpoint context\n"); 569 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 570 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); 571 572 state->new_deq_ptr = cur_td->last_trb; 573 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); 574 state->new_deq_seg = find_trb_seg(state->new_deq_seg, 575 state->new_deq_ptr, 576 &state->new_cycle_state); 577 if (!state->new_deq_seg) { 578 WARN_ON(1); 579 return; 580 } 581 582 trb = &state->new_deq_ptr->generic; 583 if (TRB_TYPE_LINK_LE32(trb->field[3]) && 584 (trb->field[3] & cpu_to_le32(LINK_TOGGLE))) 585 state->new_cycle_state ^= 0x1; 586 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); 587 588 /* 589 * If there is only one segment in a ring, find_trb_seg()'s while loop 590 * will not run, and it will return before it has a chance to see if it 591 * needs to toggle the cycle bit. It can't tell if the stalled transfer 592 * ended just before the link TRB on a one-segment ring, or if the TD 593 * wrapped around the top of the ring, because it doesn't have the TD in 594 * question. Look for the one-segment case where stalled TRB's address 595 * is greater than the new dequeue pointer address. 596 */ 597 if (ep_ring->first_seg == ep_ring->first_seg->next && 598 state->new_deq_ptr < dev->eps[ep_index].stopped_trb) 599 state->new_cycle_state ^= 0x1; 600 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state); 601 602 /* Don't update the ring cycle state for the producer (us). */ 603 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", 604 state->new_deq_seg); 605 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 606 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", 607 (unsigned long long) addr); 608 } 609 610 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 611 * (The last TRB actually points to the ring enqueue pointer, which is not part 612 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 613 */ 614 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 615 struct xhci_td *cur_td, bool flip_cycle) 616 { 617 struct xhci_segment *cur_seg; 618 union xhci_trb *cur_trb; 619 620 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; 621 true; 622 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 623 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { 624 /* Unchain any chained Link TRBs, but 625 * leave the pointers intact. 626 */ 627 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); 628 /* Flip the cycle bit (link TRBs can't be the first 629 * or last TRB). 630 */ 631 if (flip_cycle) 632 cur_trb->generic.field[3] ^= 633 cpu_to_le32(TRB_CYCLE); 634 xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); 635 xhci_dbg(xhci, "Address = %p (0x%llx dma); " 636 "in seg %p (0x%llx dma)\n", 637 cur_trb, 638 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), 639 cur_seg, 640 (unsigned long long)cur_seg->dma); 641 } else { 642 cur_trb->generic.field[0] = 0; 643 cur_trb->generic.field[1] = 0; 644 cur_trb->generic.field[2] = 0; 645 /* Preserve only the cycle bit of this TRB */ 646 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 647 /* Flip the cycle bit except on the first or last TRB */ 648 if (flip_cycle && cur_trb != cur_td->first_trb && 649 cur_trb != cur_td->last_trb) 650 cur_trb->generic.field[3] ^= 651 cpu_to_le32(TRB_CYCLE); 652 cur_trb->generic.field[3] |= cpu_to_le32( 653 TRB_TYPE(TRB_TR_NOOP)); 654 xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n", 655 (unsigned long long) 656 xhci_trb_virt_to_dma(cur_seg, cur_trb)); 657 } 658 if (cur_trb == cur_td->last_trb) 659 break; 660 } 661 } 662 663 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, 664 unsigned int ep_index, unsigned int stream_id, 665 struct xhci_segment *deq_seg, 666 union xhci_trb *deq_ptr, u32 cycle_state); 667 668 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 669 unsigned int slot_id, unsigned int ep_index, 670 unsigned int stream_id, 671 struct xhci_dequeue_state *deq_state) 672 { 673 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 674 675 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " 676 "new deq ptr = %p (0x%llx dma), new cycle = %u\n", 677 deq_state->new_deq_seg, 678 (unsigned long long)deq_state->new_deq_seg->dma, 679 deq_state->new_deq_ptr, 680 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), 681 deq_state->new_cycle_state); 682 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, 683 deq_state->new_deq_seg, 684 deq_state->new_deq_ptr, 685 (u32) deq_state->new_cycle_state); 686 /* Stop the TD queueing code from ringing the doorbell until 687 * this command completes. The HC won't set the dequeue pointer 688 * if the ring is running, and ringing the doorbell starts the 689 * ring running. 690 */ 691 ep->ep_state |= SET_DEQ_PENDING; 692 } 693 694 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, 695 struct xhci_virt_ep *ep) 696 { 697 ep->ep_state &= ~EP_HALT_PENDING; 698 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the 699 * timer is running on another CPU, we don't decrement stop_cmds_pending 700 * (since we didn't successfully stop the watchdog timer). 701 */ 702 if (del_timer(&ep->stop_cmd_timer)) 703 ep->stop_cmds_pending--; 704 } 705 706 /* Must be called with xhci->lock held in interrupt context */ 707 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 708 struct xhci_td *cur_td, int status, char *adjective) 709 { 710 struct usb_hcd *hcd; 711 struct urb *urb; 712 struct urb_priv *urb_priv; 713 714 urb = cur_td->urb; 715 urb_priv = urb->hcpriv; 716 urb_priv->td_cnt++; 717 hcd = bus_to_hcd(urb->dev->bus); 718 719 /* Only giveback urb when this is the last td in urb */ 720 if (urb_priv->td_cnt == urb_priv->length) { 721 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 722 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 723 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 724 if (xhci->quirks & XHCI_AMD_PLL_FIX) 725 usb_amd_quirk_pll_enable(); 726 } 727 } 728 usb_hcd_unlink_urb_from_ep(hcd, urb); 729 730 spin_unlock(&xhci->lock); 731 usb_hcd_giveback_urb(hcd, urb, status); 732 xhci_urb_free_priv(xhci, urb_priv); 733 spin_lock(&xhci->lock); 734 } 735 } 736 737 /* 738 * When we get a command completion for a Stop Endpoint Command, we need to 739 * unlink any cancelled TDs from the ring. There are two ways to do that: 740 * 741 * 1. If the HW was in the middle of processing the TD that needs to be 742 * cancelled, then we must move the ring's dequeue pointer past the last TRB 743 * in the TD with a Set Dequeue Pointer Command. 744 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 745 * bit cleared) so that the HW will skip over them. 746 */ 747 static void handle_stopped_endpoint(struct xhci_hcd *xhci, 748 union xhci_trb *trb, struct xhci_event_cmd *event) 749 { 750 unsigned int slot_id; 751 unsigned int ep_index; 752 struct xhci_virt_device *virt_dev; 753 struct xhci_ring *ep_ring; 754 struct xhci_virt_ep *ep; 755 struct list_head *entry; 756 struct xhci_td *cur_td = NULL; 757 struct xhci_td *last_unlinked_td; 758 759 struct xhci_dequeue_state deq_state; 760 761 if (unlikely(TRB_TO_SUSPEND_PORT( 762 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) { 763 slot_id = TRB_TO_SLOT_ID( 764 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); 765 virt_dev = xhci->devs[slot_id]; 766 if (virt_dev) 767 handle_cmd_in_cmd_wait_list(xhci, virt_dev, 768 event); 769 else 770 xhci_warn(xhci, "Stop endpoint command " 771 "completion for disabled slot %u\n", 772 slot_id); 773 return; 774 } 775 776 memset(&deq_state, 0, sizeof(deq_state)); 777 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); 778 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 779 ep = &xhci->devs[slot_id]->eps[ep_index]; 780 781 if (list_empty(&ep->cancelled_td_list)) { 782 xhci_stop_watchdog_timer_in_irq(xhci, ep); 783 ep->stopped_td = NULL; 784 ep->stopped_trb = NULL; 785 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 786 return; 787 } 788 789 /* Fix up the ep ring first, so HW stops executing cancelled TDs. 790 * We have the xHCI lock, so nothing can modify this list until we drop 791 * it. We're also in the event handler, so we can't get re-interrupted 792 * if another Stop Endpoint command completes 793 */ 794 list_for_each(entry, &ep->cancelled_td_list) { 795 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); 796 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n", 797 (unsigned long long)xhci_trb_virt_to_dma( 798 cur_td->start_seg, cur_td->first_trb)); 799 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 800 if (!ep_ring) { 801 /* This shouldn't happen unless a driver is mucking 802 * with the stream ID after submission. This will 803 * leave the TD on the hardware ring, and the hardware 804 * will try to execute it, and may access a buffer 805 * that has already been freed. In the best case, the 806 * hardware will execute it, and the event handler will 807 * ignore the completion event for that TD, since it was 808 * removed from the td_list for that endpoint. In 809 * short, don't muck with the stream ID after 810 * submission. 811 */ 812 xhci_warn(xhci, "WARN Cancelled URB %p " 813 "has invalid stream ID %u.\n", 814 cur_td->urb, 815 cur_td->urb->stream_id); 816 goto remove_finished_td; 817 } 818 /* 819 * If we stopped on the TD we need to cancel, then we have to 820 * move the xHC endpoint ring dequeue pointer past this TD. 821 */ 822 if (cur_td == ep->stopped_td) 823 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, 824 cur_td->urb->stream_id, 825 cur_td, &deq_state); 826 else 827 td_to_noop(xhci, ep_ring, cur_td, false); 828 remove_finished_td: 829 /* 830 * The event handler won't see a completion for this TD anymore, 831 * so remove it from the endpoint ring's TD list. Keep it in 832 * the cancelled TD list for URB completion later. 833 */ 834 list_del_init(&cur_td->td_list); 835 } 836 last_unlinked_td = cur_td; 837 xhci_stop_watchdog_timer_in_irq(xhci, ep); 838 839 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ 840 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { 841 xhci_queue_new_dequeue_state(xhci, 842 slot_id, ep_index, 843 ep->stopped_td->urb->stream_id, 844 &deq_state); 845 xhci_ring_cmd_db(xhci); 846 } else { 847 /* Otherwise ring the doorbell(s) to restart queued transfers */ 848 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 849 } 850 ep->stopped_td = NULL; 851 ep->stopped_trb = NULL; 852 853 /* 854 * Drop the lock and complete the URBs in the cancelled TD list. 855 * New TDs to be cancelled might be added to the end of the list before 856 * we can complete all the URBs for the TDs we already unlinked. 857 * So stop when we've completed the URB for the last TD we unlinked. 858 */ 859 do { 860 cur_td = list_entry(ep->cancelled_td_list.next, 861 struct xhci_td, cancelled_td_list); 862 list_del_init(&cur_td->cancelled_td_list); 863 864 /* Clean up the cancelled URB */ 865 /* Doesn't matter what we pass for status, since the core will 866 * just overwrite it (because the URB has been unlinked). 867 */ 868 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); 869 870 /* Stop processing the cancelled list if the watchdog timer is 871 * running. 872 */ 873 if (xhci->xhc_state & XHCI_STATE_DYING) 874 return; 875 } while (cur_td != last_unlinked_td); 876 877 /* Return to the event handler with xhci->lock re-acquired */ 878 } 879 880 /* Watchdog timer function for when a stop endpoint command fails to complete. 881 * In this case, we assume the host controller is broken or dying or dead. The 882 * host may still be completing some other events, so we have to be careful to 883 * let the event ring handler and the URB dequeueing/enqueueing functions know 884 * through xhci->state. 885 * 886 * The timer may also fire if the host takes a very long time to respond to the 887 * command, and the stop endpoint command completion handler cannot delete the 888 * timer before the timer function is called. Another endpoint cancellation may 889 * sneak in before the timer function can grab the lock, and that may queue 890 * another stop endpoint command and add the timer back. So we cannot use a 891 * simple flag to say whether there is a pending stop endpoint command for a 892 * particular endpoint. 893 * 894 * Instead we use a combination of that flag and a counter for the number of 895 * pending stop endpoint commands. If the timer is the tail end of the last 896 * stop endpoint command, and the endpoint's command is still pending, we assume 897 * the host is dying. 898 */ 899 void xhci_stop_endpoint_command_watchdog(unsigned long arg) 900 { 901 struct xhci_hcd *xhci; 902 struct xhci_virt_ep *ep; 903 struct xhci_virt_ep *temp_ep; 904 struct xhci_ring *ring; 905 struct xhci_td *cur_td; 906 int ret, i, j; 907 unsigned long flags; 908 909 ep = (struct xhci_virt_ep *) arg; 910 xhci = ep->xhci; 911 912 spin_lock_irqsave(&xhci->lock, flags); 913 914 ep->stop_cmds_pending--; 915 if (xhci->xhc_state & XHCI_STATE_DYING) { 916 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " 917 "xHCI as DYING, exiting.\n"); 918 spin_unlock_irqrestore(&xhci->lock, flags); 919 return; 920 } 921 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { 922 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " 923 "exiting.\n"); 924 spin_unlock_irqrestore(&xhci->lock, flags); 925 return; 926 } 927 928 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); 929 xhci_warn(xhci, "Assuming host is dying, halting host.\n"); 930 /* Oops, HC is dead or dying or at least not responding to the stop 931 * endpoint command. 932 */ 933 xhci->xhc_state |= XHCI_STATE_DYING; 934 /* Disable interrupts from the host controller and start halting it */ 935 xhci_quiesce(xhci); 936 spin_unlock_irqrestore(&xhci->lock, flags); 937 938 ret = xhci_halt(xhci); 939 940 spin_lock_irqsave(&xhci->lock, flags); 941 if (ret < 0) { 942 /* This is bad; the host is not responding to commands and it's 943 * not allowing itself to be halted. At least interrupts are 944 * disabled. If we call usb_hc_died(), it will attempt to 945 * disconnect all device drivers under this host. Those 946 * disconnect() methods will wait for all URBs to be unlinked, 947 * so we must complete them. 948 */ 949 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); 950 xhci_warn(xhci, "Completing active URBs anyway.\n"); 951 /* We could turn all TDs on the rings to no-ops. This won't 952 * help if the host has cached part of the ring, and is slow if 953 * we want to preserve the cycle bit. Skip it and hope the host 954 * doesn't touch the memory. 955 */ 956 } 957 for (i = 0; i < MAX_HC_SLOTS; i++) { 958 if (!xhci->devs[i]) 959 continue; 960 for (j = 0; j < 31; j++) { 961 temp_ep = &xhci->devs[i]->eps[j]; 962 ring = temp_ep->ring; 963 if (!ring) 964 continue; 965 xhci_dbg(xhci, "Killing URBs for slot ID %u, " 966 "ep index %u\n", i, j); 967 while (!list_empty(&ring->td_list)) { 968 cur_td = list_first_entry(&ring->td_list, 969 struct xhci_td, 970 td_list); 971 list_del_init(&cur_td->td_list); 972 if (!list_empty(&cur_td->cancelled_td_list)) 973 list_del_init(&cur_td->cancelled_td_list); 974 xhci_giveback_urb_in_irq(xhci, cur_td, 975 -ESHUTDOWN, "killed"); 976 } 977 while (!list_empty(&temp_ep->cancelled_td_list)) { 978 cur_td = list_first_entry( 979 &temp_ep->cancelled_td_list, 980 struct xhci_td, 981 cancelled_td_list); 982 list_del_init(&cur_td->cancelled_td_list); 983 xhci_giveback_urb_in_irq(xhci, cur_td, 984 -ESHUTDOWN, "killed"); 985 } 986 } 987 } 988 spin_unlock_irqrestore(&xhci->lock, flags); 989 xhci_dbg(xhci, "Calling usb_hc_died()\n"); 990 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); 991 xhci_dbg(xhci, "xHCI host controller is dead.\n"); 992 } 993 994 995 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 996 struct xhci_virt_device *dev, 997 struct xhci_ring *ep_ring, 998 unsigned int ep_index) 999 { 1000 union xhci_trb *dequeue_temp; 1001 int num_trbs_free_temp; 1002 bool revert = false; 1003 1004 num_trbs_free_temp = ep_ring->num_trbs_free; 1005 dequeue_temp = ep_ring->dequeue; 1006 1007 /* If we get two back-to-back stalls, and the first stalled transfer 1008 * ends just before a link TRB, the dequeue pointer will be left on 1009 * the link TRB by the code in the while loop. So we have to update 1010 * the dequeue pointer one segment further, or we'll jump off 1011 * the segment into la-la-land. 1012 */ 1013 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { 1014 ep_ring->deq_seg = ep_ring->deq_seg->next; 1015 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1016 } 1017 1018 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 1019 /* We have more usable TRBs */ 1020 ep_ring->num_trbs_free++; 1021 ep_ring->dequeue++; 1022 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, 1023 ep_ring->dequeue)) { 1024 if (ep_ring->dequeue == 1025 dev->eps[ep_index].queued_deq_ptr) 1026 break; 1027 ep_ring->deq_seg = ep_ring->deq_seg->next; 1028 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1029 } 1030 if (ep_ring->dequeue == dequeue_temp) { 1031 revert = true; 1032 break; 1033 } 1034 } 1035 1036 if (revert) { 1037 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 1038 ep_ring->num_trbs_free = num_trbs_free_temp; 1039 } 1040 } 1041 1042 /* 1043 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 1044 * we need to clear the set deq pending flag in the endpoint ring state, so that 1045 * the TD queueing code can ring the doorbell again. We also need to ring the 1046 * endpoint doorbell to restart the ring, but only if there aren't more 1047 * cancellations pending. 1048 */ 1049 static void handle_set_deq_completion(struct xhci_hcd *xhci, 1050 struct xhci_event_cmd *event, 1051 union xhci_trb *trb) 1052 { 1053 unsigned int slot_id; 1054 unsigned int ep_index; 1055 unsigned int stream_id; 1056 struct xhci_ring *ep_ring; 1057 struct xhci_virt_device *dev; 1058 struct xhci_ep_ctx *ep_ctx; 1059 struct xhci_slot_ctx *slot_ctx; 1060 1061 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); 1062 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1063 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 1064 dev = xhci->devs[slot_id]; 1065 1066 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); 1067 if (!ep_ring) { 1068 xhci_warn(xhci, "WARN Set TR deq ptr command for " 1069 "freed stream ID %u\n", 1070 stream_id); 1071 /* XXX: Harmless??? */ 1072 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 1073 return; 1074 } 1075 1076 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 1077 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); 1078 1079 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) { 1080 unsigned int ep_state; 1081 unsigned int slot_state; 1082 1083 switch (GET_COMP_CODE(le32_to_cpu(event->status))) { 1084 case COMP_TRB_ERR: 1085 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " 1086 "of stream ID configuration\n"); 1087 break; 1088 case COMP_CTX_STATE: 1089 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " 1090 "to incorrect slot or ep state.\n"); 1091 ep_state = le32_to_cpu(ep_ctx->ep_info); 1092 ep_state &= EP_STATE_MASK; 1093 slot_state = le32_to_cpu(slot_ctx->dev_state); 1094 slot_state = GET_SLOT_STATE(slot_state); 1095 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", 1096 slot_state, ep_state); 1097 break; 1098 case COMP_EBADSLT: 1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " 1100 "slot %u was not enabled.\n", slot_id); 1101 break; 1102 default: 1103 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " 1104 "completion code of %u.\n", 1105 GET_COMP_CODE(le32_to_cpu(event->status))); 1106 break; 1107 } 1108 /* OK what do we do now? The endpoint state is hosed, and we 1109 * should never get to this point if the synchronization between 1110 * queueing, and endpoint state are correct. This might happen 1111 * if the device gets disconnected after we've finished 1112 * cancelling URBs, which might not be an error... 1113 */ 1114 } else { 1115 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", 1116 le64_to_cpu(ep_ctx->deq)); 1117 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg, 1118 dev->eps[ep_index].queued_deq_ptr) == 1119 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) { 1120 /* Update the ring's dequeue segment and dequeue pointer 1121 * to reflect the new position. 1122 */ 1123 update_ring_for_set_deq_completion(xhci, dev, 1124 ep_ring, ep_index); 1125 } else { 1126 xhci_warn(xhci, "Mismatch between completed Set TR Deq " 1127 "Ptr command & xHCI internal state.\n"); 1128 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1129 dev->eps[ep_index].queued_deq_seg, 1130 dev->eps[ep_index].queued_deq_ptr); 1131 } 1132 } 1133 1134 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 1135 dev->eps[ep_index].queued_deq_seg = NULL; 1136 dev->eps[ep_index].queued_deq_ptr = NULL; 1137 /* Restart any rings with pending URBs */ 1138 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1139 } 1140 1141 static void handle_reset_ep_completion(struct xhci_hcd *xhci, 1142 struct xhci_event_cmd *event, 1143 union xhci_trb *trb) 1144 { 1145 int slot_id; 1146 unsigned int ep_index; 1147 1148 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); 1149 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1150 /* This command will only fail if the endpoint wasn't halted, 1151 * but we don't care. 1152 */ 1153 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", 1154 GET_COMP_CODE(le32_to_cpu(event->status))); 1155 1156 /* HW with the reset endpoint quirk needs to have a configure endpoint 1157 * command complete before the endpoint can be used. Queue that here 1158 * because the HW can't handle two commands being queued in a row. 1159 */ 1160 if (xhci->quirks & XHCI_RESET_EP_QUIRK) { 1161 xhci_dbg(xhci, "Queueing configure endpoint command\n"); 1162 xhci_queue_configure_endpoint(xhci, 1163 xhci->devs[slot_id]->in_ctx->dma, slot_id, 1164 false); 1165 xhci_ring_cmd_db(xhci); 1166 } else { 1167 /* Clear our internal halted state and restart the ring(s) */ 1168 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; 1169 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1170 } 1171 } 1172 1173 /* Complete the command and detele it from the devcie's command queue. 1174 */ 1175 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, 1176 struct xhci_command *command, u32 status) 1177 { 1178 command->status = status; 1179 list_del(&command->cmd_list); 1180 if (command->completion) 1181 complete(command->completion); 1182 else 1183 xhci_free_command(xhci, command); 1184 } 1185 1186 1187 /* Check to see if a command in the device's command queue matches this one. 1188 * Signal the completion or free the command, and return 1. Return 0 if the 1189 * completed command isn't at the head of the command list. 1190 */ 1191 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, 1192 struct xhci_virt_device *virt_dev, 1193 struct xhci_event_cmd *event) 1194 { 1195 struct xhci_command *command; 1196 1197 if (list_empty(&virt_dev->cmd_list)) 1198 return 0; 1199 1200 command = list_entry(virt_dev->cmd_list.next, 1201 struct xhci_command, cmd_list); 1202 if (xhci->cmd_ring->dequeue != command->command_trb) 1203 return 0; 1204 1205 xhci_complete_cmd_in_cmd_wait_list(xhci, command, 1206 GET_COMP_CODE(le32_to_cpu(event->status))); 1207 return 1; 1208 } 1209 1210 /* 1211 * Finding the command trb need to be cancelled and modifying it to 1212 * NO OP command. And if the command is in device's command wait 1213 * list, finishing and freeing it. 1214 * 1215 * If we can't find the command trb, we think it had already been 1216 * executed. 1217 */ 1218 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd) 1219 { 1220 struct xhci_segment *cur_seg; 1221 union xhci_trb *cmd_trb; 1222 u32 cycle_state; 1223 1224 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue) 1225 return; 1226 1227 /* find the current segment of command ring */ 1228 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg, 1229 xhci->cmd_ring->dequeue, &cycle_state); 1230 1231 /* find the command trb matched by cd from command ring */ 1232 for (cmd_trb = xhci->cmd_ring->dequeue; 1233 cmd_trb != xhci->cmd_ring->enqueue; 1234 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) { 1235 /* If the trb is link trb, continue */ 1236 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3])) 1237 continue; 1238 1239 if (cur_cd->cmd_trb == cmd_trb) { 1240 1241 /* If the command in device's command list, we should 1242 * finish it and free the command structure. 1243 */ 1244 if (cur_cd->command) 1245 xhci_complete_cmd_in_cmd_wait_list(xhci, 1246 cur_cd->command, COMP_CMD_STOP); 1247 1248 /* get cycle state from the origin command trb */ 1249 cycle_state = le32_to_cpu(cmd_trb->generic.field[3]) 1250 & TRB_CYCLE; 1251 1252 /* modify the command trb to NO OP command */ 1253 cmd_trb->generic.field[0] = 0; 1254 cmd_trb->generic.field[1] = 0; 1255 cmd_trb->generic.field[2] = 0; 1256 cmd_trb->generic.field[3] = cpu_to_le32( 1257 TRB_TYPE(TRB_CMD_NOOP) | cycle_state); 1258 break; 1259 } 1260 } 1261 } 1262 1263 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci) 1264 { 1265 struct xhci_cd *cur_cd, *next_cd; 1266 1267 if (list_empty(&xhci->cancel_cmd_list)) 1268 return; 1269 1270 list_for_each_entry_safe(cur_cd, next_cd, 1271 &xhci->cancel_cmd_list, cancel_cmd_list) { 1272 xhci_cmd_to_noop(xhci, cur_cd); 1273 list_del(&cur_cd->cancel_cmd_list); 1274 kfree(cur_cd); 1275 } 1276 } 1277 1278 /* 1279 * traversing the cancel_cmd_list. If the command descriptor according 1280 * to cmd_trb is found, the function free it and return 1, otherwise 1281 * return 0. 1282 */ 1283 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci, 1284 union xhci_trb *cmd_trb) 1285 { 1286 struct xhci_cd *cur_cd, *next_cd; 1287 1288 if (list_empty(&xhci->cancel_cmd_list)) 1289 return 0; 1290 1291 list_for_each_entry_safe(cur_cd, next_cd, 1292 &xhci->cancel_cmd_list, cancel_cmd_list) { 1293 if (cur_cd->cmd_trb == cmd_trb) { 1294 if (cur_cd->command) 1295 xhci_complete_cmd_in_cmd_wait_list(xhci, 1296 cur_cd->command, COMP_CMD_STOP); 1297 list_del(&cur_cd->cancel_cmd_list); 1298 kfree(cur_cd); 1299 return 1; 1300 } 1301 } 1302 1303 return 0; 1304 } 1305 1306 /* 1307 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the 1308 * trb pointed by the command ring dequeue pointer is the trb we want to 1309 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will 1310 * traverse the cancel_cmd_list to trun the all of the commands according 1311 * to command descriptor to NO-OP trb. 1312 */ 1313 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci, 1314 int cmd_trb_comp_code) 1315 { 1316 int cur_trb_is_good = 0; 1317 1318 /* Searching the cmd trb pointed by the command ring dequeue 1319 * pointer in command descriptor list. If it is found, free it. 1320 */ 1321 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci, 1322 xhci->cmd_ring->dequeue); 1323 1324 if (cmd_trb_comp_code == COMP_CMD_ABORT) 1325 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1326 else if (cmd_trb_comp_code == COMP_CMD_STOP) { 1327 /* traversing the cancel_cmd_list and canceling 1328 * the command according to command descriptor 1329 */ 1330 xhci_cancel_cmd_in_cd_list(xhci); 1331 1332 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 1333 /* 1334 * ring command ring doorbell again to restart the 1335 * command ring 1336 */ 1337 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) 1338 xhci_ring_cmd_db(xhci); 1339 } 1340 return cur_trb_is_good; 1341 } 1342 1343 static void handle_cmd_completion(struct xhci_hcd *xhci, 1344 struct xhci_event_cmd *event) 1345 { 1346 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1347 u64 cmd_dma; 1348 dma_addr_t cmd_dequeue_dma; 1349 struct xhci_input_control_ctx *ctrl_ctx; 1350 struct xhci_virt_device *virt_dev; 1351 unsigned int ep_index; 1352 struct xhci_ring *ep_ring; 1353 unsigned int ep_state; 1354 1355 cmd_dma = le64_to_cpu(event->cmd_trb); 1356 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1357 xhci->cmd_ring->dequeue); 1358 /* Is the command ring deq ptr out of sync with the deq seg ptr? */ 1359 if (cmd_dequeue_dma == 0) { 1360 xhci->error_bitmask |= 1 << 4; 1361 return; 1362 } 1363 /* Does the DMA address match our internal dequeue pointer address? */ 1364 if (cmd_dma != (u64) cmd_dequeue_dma) { 1365 xhci->error_bitmask |= 1 << 5; 1366 return; 1367 } 1368 1369 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) || 1370 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) { 1371 /* If the return value is 0, we think the trb pointed by 1372 * command ring dequeue pointer is a good trb. The good 1373 * trb means we don't want to cancel the trb, but it have 1374 * been stopped by host. So we should handle it normally. 1375 * Otherwise, driver should invoke inc_deq() and return. 1376 */ 1377 if (handle_stopped_cmd_ring(xhci, 1378 GET_COMP_CODE(le32_to_cpu(event->status)))) { 1379 inc_deq(xhci, xhci->cmd_ring); 1380 return; 1381 } 1382 } 1383 1384 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]) 1385 & TRB_TYPE_BITMASK) { 1386 case TRB_TYPE(TRB_ENABLE_SLOT): 1387 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS) 1388 xhci->slot_id = slot_id; 1389 else 1390 xhci->slot_id = 0; 1391 complete(&xhci->addr_dev); 1392 break; 1393 case TRB_TYPE(TRB_DISABLE_SLOT): 1394 if (xhci->devs[slot_id]) { 1395 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1396 /* Delete default control endpoint resources */ 1397 xhci_free_device_endpoint_resources(xhci, 1398 xhci->devs[slot_id], true); 1399 xhci_free_virt_device(xhci, slot_id); 1400 } 1401 break; 1402 case TRB_TYPE(TRB_CONFIG_EP): 1403 virt_dev = xhci->devs[slot_id]; 1404 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) 1405 break; 1406 /* 1407 * Configure endpoint commands can come from the USB core 1408 * configuration or alt setting changes, or because the HW 1409 * needed an extra configure endpoint command after a reset 1410 * endpoint command or streams were being configured. 1411 * If the command was for a halted endpoint, the xHCI driver 1412 * is not waiting on the configure endpoint command. 1413 */ 1414 ctrl_ctx = xhci_get_input_control_ctx(xhci, 1415 virt_dev->in_ctx); 1416 /* Input ctx add_flags are the endpoint index plus one */ 1417 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1; 1418 /* A usb_set_interface() call directly after clearing a halted 1419 * condition may race on this quirky hardware. Not worth 1420 * worrying about, since this is prototype hardware. Not sure 1421 * if this will work for streams, but streams support was 1422 * untested on this prototype. 1423 */ 1424 if (xhci->quirks & XHCI_RESET_EP_QUIRK && 1425 ep_index != (unsigned int) -1 && 1426 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG == 1427 le32_to_cpu(ctrl_ctx->drop_flags)) { 1428 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 1429 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; 1430 if (!(ep_state & EP_HALTED)) 1431 goto bandwidth_change; 1432 xhci_dbg(xhci, "Completed config ep cmd - " 1433 "last ep index = %d, state = %d\n", 1434 ep_index, ep_state); 1435 /* Clear internal halted state and restart ring(s) */ 1436 xhci->devs[slot_id]->eps[ep_index].ep_state &= 1437 ~EP_HALTED; 1438 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1439 break; 1440 } 1441 bandwidth_change: 1442 xhci_dbg(xhci, "Completed config ep cmd\n"); 1443 xhci->devs[slot_id]->cmd_status = 1444 GET_COMP_CODE(le32_to_cpu(event->status)); 1445 complete(&xhci->devs[slot_id]->cmd_completion); 1446 break; 1447 case TRB_TYPE(TRB_EVAL_CONTEXT): 1448 virt_dev = xhci->devs[slot_id]; 1449 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) 1450 break; 1451 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); 1452 complete(&xhci->devs[slot_id]->cmd_completion); 1453 break; 1454 case TRB_TYPE(TRB_ADDR_DEV): 1455 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); 1456 complete(&xhci->addr_dev); 1457 break; 1458 case TRB_TYPE(TRB_STOP_RING): 1459 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); 1460 break; 1461 case TRB_TYPE(TRB_SET_DEQ): 1462 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); 1463 break; 1464 case TRB_TYPE(TRB_CMD_NOOP): 1465 break; 1466 case TRB_TYPE(TRB_RESET_EP): 1467 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); 1468 break; 1469 case TRB_TYPE(TRB_RESET_DEV): 1470 xhci_dbg(xhci, "Completed reset device command.\n"); 1471 slot_id = TRB_TO_SLOT_ID( 1472 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); 1473 virt_dev = xhci->devs[slot_id]; 1474 if (virt_dev) 1475 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); 1476 else 1477 xhci_warn(xhci, "Reset device command completion " 1478 "for disabled slot %u\n", slot_id); 1479 break; 1480 case TRB_TYPE(TRB_NEC_GET_FW): 1481 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1482 xhci->error_bitmask |= 1 << 6; 1483 break; 1484 } 1485 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", 1486 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1487 NEC_FW_MINOR(le32_to_cpu(event->status))); 1488 break; 1489 default: 1490 /* Skip over unknown commands on the event ring */ 1491 xhci->error_bitmask |= 1 << 6; 1492 break; 1493 } 1494 inc_deq(xhci, xhci->cmd_ring); 1495 } 1496 1497 static void handle_vendor_event(struct xhci_hcd *xhci, 1498 union xhci_trb *event) 1499 { 1500 u32 trb_type; 1501 1502 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); 1503 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1504 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1505 handle_cmd_completion(xhci, &event->event_cmd); 1506 } 1507 1508 /* @port_id: the one-based port ID from the hardware (indexed from array of all 1509 * port registers -- USB 3.0 and USB 2.0). 1510 * 1511 * Returns a zero-based port number, which is suitable for indexing into each of 1512 * the split roothubs' port arrays and bus state arrays. 1513 * Add one to it in order to call xhci_find_slot_id_by_port. 1514 */ 1515 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, 1516 struct xhci_hcd *xhci, u32 port_id) 1517 { 1518 unsigned int i; 1519 unsigned int num_similar_speed_ports = 0; 1520 1521 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], 1522 * and usb2_ports are 0-based indexes. Count the number of similar 1523 * speed ports, up to 1 port before this port. 1524 */ 1525 for (i = 0; i < (port_id - 1); i++) { 1526 u8 port_speed = xhci->port_array[i]; 1527 1528 /* 1529 * Skip ports that don't have known speeds, or have duplicate 1530 * Extended Capabilities port speed entries. 1531 */ 1532 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) 1533 continue; 1534 1535 /* 1536 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and 1537 * 1.1 ports are under the USB 2.0 hub. If the port speed 1538 * matches the device speed, it's a similar speed port. 1539 */ 1540 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) 1541 num_similar_speed_ports++; 1542 } 1543 return num_similar_speed_ports; 1544 } 1545 1546 static void handle_device_notification(struct xhci_hcd *xhci, 1547 union xhci_trb *event) 1548 { 1549 u32 slot_id; 1550 struct usb_device *udev; 1551 1552 slot_id = TRB_TO_SLOT_ID(event->generic.field[3]); 1553 if (!xhci->devs[slot_id]) { 1554 xhci_warn(xhci, "Device Notification event for " 1555 "unused slot %u\n", slot_id); 1556 return; 1557 } 1558 1559 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1560 slot_id); 1561 udev = xhci->devs[slot_id]->udev; 1562 if (udev && udev->parent) 1563 usb_wakeup_notification(udev->parent, udev->portnum); 1564 } 1565 1566 static void handle_port_status(struct xhci_hcd *xhci, 1567 union xhci_trb *event) 1568 { 1569 struct usb_hcd *hcd; 1570 u32 port_id; 1571 u32 temp, temp1; 1572 int max_ports; 1573 int slot_id; 1574 unsigned int faked_port_index; 1575 u8 major_revision; 1576 struct xhci_bus_state *bus_state; 1577 __le32 __iomem **port_array; 1578 bool bogus_port_status = false; 1579 1580 /* Port status change events always have a successful completion code */ 1581 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { 1582 xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); 1583 xhci->error_bitmask |= 1 << 8; 1584 } 1585 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1586 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); 1587 1588 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1589 if ((port_id <= 0) || (port_id > max_ports)) { 1590 xhci_warn(xhci, "Invalid port id %d\n", port_id); 1591 bogus_port_status = true; 1592 goto cleanup; 1593 } 1594 1595 /* Figure out which usb_hcd this port is attached to: 1596 * is it a USB 3.0 port or a USB 2.0/1.1 port? 1597 */ 1598 major_revision = xhci->port_array[port_id - 1]; 1599 if (major_revision == 0) { 1600 xhci_warn(xhci, "Event for port %u not in " 1601 "Extended Capabilities, ignoring.\n", 1602 port_id); 1603 bogus_port_status = true; 1604 goto cleanup; 1605 } 1606 if (major_revision == DUPLICATE_ENTRY) { 1607 xhci_warn(xhci, "Event for port %u duplicated in" 1608 "Extended Capabilities, ignoring.\n", 1609 port_id); 1610 bogus_port_status = true; 1611 goto cleanup; 1612 } 1613 1614 /* 1615 * Hardware port IDs reported by a Port Status Change Event include USB 1616 * 3.0 and USB 2.0 ports. We want to check if the port has reported a 1617 * resume event, but we first need to translate the hardware port ID 1618 * into the index into the ports on the correct split roothub, and the 1619 * correct bus_state structure. 1620 */ 1621 /* Find the right roothub. */ 1622 hcd = xhci_to_hcd(xhci); 1623 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) 1624 hcd = xhci->shared_hcd; 1625 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1626 if (hcd->speed == HCD_USB3) 1627 port_array = xhci->usb3_ports; 1628 else 1629 port_array = xhci->usb2_ports; 1630 /* Find the faked port hub number */ 1631 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, 1632 port_id); 1633 1634 temp = xhci_readl(xhci, port_array[faked_port_index]); 1635 if (hcd->state == HC_STATE_SUSPENDED) { 1636 xhci_dbg(xhci, "resume root hub\n"); 1637 usb_hcd_resume_root_hub(hcd); 1638 } 1639 1640 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { 1641 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1642 1643 temp1 = xhci_readl(xhci, &xhci->op_regs->command); 1644 if (!(temp1 & CMD_RUN)) { 1645 xhci_warn(xhci, "xHC is not running.\n"); 1646 goto cleanup; 1647 } 1648 1649 if (DEV_SUPERSPEED(temp)) { 1650 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1651 /* Set a flag to say the port signaled remote wakeup, 1652 * so we can tell the difference between the end of 1653 * device and host initiated resume. 1654 */ 1655 bus_state->port_remote_wakeup |= 1 << faked_port_index; 1656 xhci_test_and_clear_bit(xhci, port_array, 1657 faked_port_index, PORT_PLC); 1658 xhci_set_link_state(xhci, port_array, faked_port_index, 1659 XDEV_U0); 1660 /* Need to wait until the next link state change 1661 * indicates the device is actually in U0. 1662 */ 1663 bogus_port_status = true; 1664 goto cleanup; 1665 } else { 1666 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1667 bus_state->resume_done[faked_port_index] = jiffies + 1668 msecs_to_jiffies(20); 1669 set_bit(faked_port_index, &bus_state->resuming_ports); 1670 mod_timer(&hcd->rh_timer, 1671 bus_state->resume_done[faked_port_index]); 1672 /* Do the rest in GetPortStatus */ 1673 } 1674 } 1675 1676 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && 1677 DEV_SUPERSPEED(temp)) { 1678 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1679 /* We've just brought the device into U0 through either the 1680 * Resume state after a device remote wakeup, or through the 1681 * U3Exit state after a host-initiated resume. If it's a device 1682 * initiated remote wake, don't pass up the link state change, 1683 * so the roothub behavior is consistent with external 1684 * USB 3.0 hub behavior. 1685 */ 1686 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1687 faked_port_index + 1); 1688 if (slot_id && xhci->devs[slot_id]) 1689 xhci_ring_device(xhci, slot_id); 1690 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) { 1691 bus_state->port_remote_wakeup &= 1692 ~(1 << faked_port_index); 1693 xhci_test_and_clear_bit(xhci, port_array, 1694 faked_port_index, PORT_PLC); 1695 usb_wakeup_notification(hcd->self.root_hub, 1696 faked_port_index + 1); 1697 bogus_port_status = true; 1698 goto cleanup; 1699 } 1700 } 1701 1702 if (hcd->speed != HCD_USB3) 1703 xhci_test_and_clear_bit(xhci, port_array, faked_port_index, 1704 PORT_PLC); 1705 1706 cleanup: 1707 /* Update event ring dequeue pointer before dropping the lock */ 1708 inc_deq(xhci, xhci->event_ring); 1709 1710 /* Don't make the USB core poll the roothub if we got a bad port status 1711 * change event. Besides, at that point we can't tell which roothub 1712 * (USB 2.0 or USB 3.0) to kick. 1713 */ 1714 if (bogus_port_status) 1715 return; 1716 1717 spin_unlock(&xhci->lock); 1718 /* Pass this up to the core */ 1719 usb_hcd_poll_rh_status(hcd); 1720 spin_lock(&xhci->lock); 1721 } 1722 1723 /* 1724 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 1725 * at end_trb, which may be in another segment. If the suspect DMA address is a 1726 * TRB in this TD, this function returns that TRB's segment. Otherwise it 1727 * returns 0. 1728 */ 1729 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1730 union xhci_trb *start_trb, 1731 union xhci_trb *end_trb, 1732 dma_addr_t suspect_dma) 1733 { 1734 dma_addr_t start_dma; 1735 dma_addr_t end_seg_dma; 1736 dma_addr_t end_trb_dma; 1737 struct xhci_segment *cur_seg; 1738 1739 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 1740 cur_seg = start_seg; 1741 1742 do { 1743 if (start_dma == 0) 1744 return NULL; 1745 /* We may get an event for a Link TRB in the middle of a TD */ 1746 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 1747 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 1748 /* If the end TRB isn't in this segment, this is set to 0 */ 1749 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 1750 1751 if (end_trb_dma > 0) { 1752 /* The end TRB is in this segment, so suspect should be here */ 1753 if (start_dma <= end_trb_dma) { 1754 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 1755 return cur_seg; 1756 } else { 1757 /* Case for one segment with 1758 * a TD wrapped around to the top 1759 */ 1760 if ((suspect_dma >= start_dma && 1761 suspect_dma <= end_seg_dma) || 1762 (suspect_dma >= cur_seg->dma && 1763 suspect_dma <= end_trb_dma)) 1764 return cur_seg; 1765 } 1766 return NULL; 1767 } else { 1768 /* Might still be somewhere in this segment */ 1769 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 1770 return cur_seg; 1771 } 1772 cur_seg = cur_seg->next; 1773 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 1774 } while (cur_seg != start_seg); 1775 1776 return NULL; 1777 } 1778 1779 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, 1780 unsigned int slot_id, unsigned int ep_index, 1781 unsigned int stream_id, 1782 struct xhci_td *td, union xhci_trb *event_trb) 1783 { 1784 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 1785 ep->ep_state |= EP_HALTED; 1786 ep->stopped_td = td; 1787 ep->stopped_trb = event_trb; 1788 ep->stopped_stream = stream_id; 1789 1790 xhci_queue_reset_ep(xhci, slot_id, ep_index); 1791 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); 1792 1793 ep->stopped_td = NULL; 1794 ep->stopped_trb = NULL; 1795 ep->stopped_stream = 0; 1796 1797 xhci_ring_cmd_db(xhci); 1798 } 1799 1800 /* Check if an error has halted the endpoint ring. The class driver will 1801 * cleanup the halt for a non-default control endpoint if we indicate a stall. 1802 * However, a babble and other errors also halt the endpoint ring, and the class 1803 * driver won't clear the halt in that case, so we need to issue a Set Transfer 1804 * Ring Dequeue Pointer command manually. 1805 */ 1806 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 1807 struct xhci_ep_ctx *ep_ctx, 1808 unsigned int trb_comp_code) 1809 { 1810 /* TRB completion codes that may require a manual halt cleanup */ 1811 if (trb_comp_code == COMP_TX_ERR || 1812 trb_comp_code == COMP_BABBLE || 1813 trb_comp_code == COMP_SPLIT_ERR) 1814 /* The 0.96 spec says a babbling control endpoint 1815 * is not halted. The 0.96 spec says it is. Some HW 1816 * claims to be 0.95 compliant, but it halts the control 1817 * endpoint anyway. Check if a babble halted the 1818 * endpoint. 1819 */ 1820 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == 1821 cpu_to_le32(EP_STATE_HALTED)) 1822 return 1; 1823 1824 return 0; 1825 } 1826 1827 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 1828 { 1829 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 1830 /* Vendor defined "informational" completion code, 1831 * treat as not-an-error. 1832 */ 1833 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 1834 trb_comp_code); 1835 xhci_dbg(xhci, "Treating code as success.\n"); 1836 return 1; 1837 } 1838 return 0; 1839 } 1840 1841 /* 1842 * Finish the td processing, remove the td from td list; 1843 * Return 1 if the urb can be given back. 1844 */ 1845 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, 1846 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1847 struct xhci_virt_ep *ep, int *status, bool skip) 1848 { 1849 struct xhci_virt_device *xdev; 1850 struct xhci_ring *ep_ring; 1851 unsigned int slot_id; 1852 int ep_index; 1853 struct urb *urb = NULL; 1854 struct xhci_ep_ctx *ep_ctx; 1855 int ret = 0; 1856 struct urb_priv *urb_priv; 1857 u32 trb_comp_code; 1858 1859 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1860 xdev = xhci->devs[slot_id]; 1861 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1862 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1863 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1864 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1865 1866 if (skip) 1867 goto td_cleanup; 1868 1869 if (trb_comp_code == COMP_STOP_INVAL || 1870 trb_comp_code == COMP_STOP) { 1871 /* The Endpoint Stop Command completion will take care of any 1872 * stopped TDs. A stopped TD may be restarted, so don't update 1873 * the ring dequeue pointer or take this TD off any lists yet. 1874 */ 1875 ep->stopped_td = td; 1876 ep->stopped_trb = event_trb; 1877 return 0; 1878 } else { 1879 if (trb_comp_code == COMP_STALL) { 1880 /* The transfer is completed from the driver's 1881 * perspective, but we need to issue a set dequeue 1882 * command for this stalled endpoint to move the dequeue 1883 * pointer past the TD. We can't do that here because 1884 * the halt condition must be cleared first. Let the 1885 * USB class driver clear the stall later. 1886 */ 1887 ep->stopped_td = td; 1888 ep->stopped_trb = event_trb; 1889 ep->stopped_stream = ep_ring->stream_id; 1890 } else if (xhci_requires_manual_halt_cleanup(xhci, 1891 ep_ctx, trb_comp_code)) { 1892 /* Other types of errors halt the endpoint, but the 1893 * class driver doesn't call usb_reset_endpoint() unless 1894 * the error is -EPIPE. Clear the halted status in the 1895 * xHCI hardware manually. 1896 */ 1897 xhci_cleanup_halted_endpoint(xhci, 1898 slot_id, ep_index, ep_ring->stream_id, 1899 td, event_trb); 1900 } else { 1901 /* Update ring dequeue pointer */ 1902 while (ep_ring->dequeue != td->last_trb) 1903 inc_deq(xhci, ep_ring); 1904 inc_deq(xhci, ep_ring); 1905 } 1906 1907 td_cleanup: 1908 /* Clean up the endpoint's TD list */ 1909 urb = td->urb; 1910 urb_priv = urb->hcpriv; 1911 1912 /* Do one last check of the actual transfer length. 1913 * If the host controller said we transferred more data than 1914 * the buffer length, urb->actual_length will be a very big 1915 * number (since it's unsigned). Play it safe and say we didn't 1916 * transfer anything. 1917 */ 1918 if (urb->actual_length > urb->transfer_buffer_length) { 1919 xhci_warn(xhci, "URB transfer length is wrong, " 1920 "xHC issue? req. len = %u, " 1921 "act. len = %u\n", 1922 urb->transfer_buffer_length, 1923 urb->actual_length); 1924 urb->actual_length = 0; 1925 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1926 *status = -EREMOTEIO; 1927 else 1928 *status = 0; 1929 } 1930 list_del_init(&td->td_list); 1931 /* Was this TD slated to be cancelled but completed anyway? */ 1932 if (!list_empty(&td->cancelled_td_list)) 1933 list_del_init(&td->cancelled_td_list); 1934 1935 urb_priv->td_cnt++; 1936 /* Giveback the urb when all the tds are completed */ 1937 if (urb_priv->td_cnt == urb_priv->length) { 1938 ret = 1; 1939 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 1940 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 1941 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs 1942 == 0) { 1943 if (xhci->quirks & XHCI_AMD_PLL_FIX) 1944 usb_amd_quirk_pll_enable(); 1945 } 1946 } 1947 } 1948 } 1949 1950 return ret; 1951 } 1952 1953 /* 1954 * Process control tds, update urb status and actual_length. 1955 */ 1956 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, 1957 union xhci_trb *event_trb, struct xhci_transfer_event *event, 1958 struct xhci_virt_ep *ep, int *status) 1959 { 1960 struct xhci_virt_device *xdev; 1961 struct xhci_ring *ep_ring; 1962 unsigned int slot_id; 1963 int ep_index; 1964 struct xhci_ep_ctx *ep_ctx; 1965 u32 trb_comp_code; 1966 1967 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1968 xdev = xhci->devs[slot_id]; 1969 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1970 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1971 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1972 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1973 1974 switch (trb_comp_code) { 1975 case COMP_SUCCESS: 1976 if (event_trb == ep_ring->dequeue) { 1977 xhci_warn(xhci, "WARN: Success on ctrl setup TRB " 1978 "without IOC set??\n"); 1979 *status = -ESHUTDOWN; 1980 } else if (event_trb != td->last_trb) { 1981 xhci_warn(xhci, "WARN: Success on ctrl data TRB " 1982 "without IOC set??\n"); 1983 *status = -ESHUTDOWN; 1984 } else { 1985 *status = 0; 1986 } 1987 break; 1988 case COMP_SHORT_TX: 1989 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 1990 *status = -EREMOTEIO; 1991 else 1992 *status = 0; 1993 break; 1994 case COMP_STOP_INVAL: 1995 case COMP_STOP: 1996 return finish_td(xhci, td, event_trb, event, ep, status, false); 1997 default: 1998 if (!xhci_requires_manual_halt_cleanup(xhci, 1999 ep_ctx, trb_comp_code)) 2000 break; 2001 xhci_dbg(xhci, "TRB error code %u, " 2002 "halted endpoint index = %u\n", 2003 trb_comp_code, ep_index); 2004 /* else fall through */ 2005 case COMP_STALL: 2006 /* Did we transfer part of the data (middle) phase? */ 2007 if (event_trb != ep_ring->dequeue && 2008 event_trb != td->last_trb) 2009 td->urb->actual_length = 2010 td->urb->transfer_buffer_length 2011 - TRB_LEN(le32_to_cpu(event->transfer_len)); 2012 else 2013 td->urb->actual_length = 0; 2014 2015 xhci_cleanup_halted_endpoint(xhci, 2016 slot_id, ep_index, 0, td, event_trb); 2017 return finish_td(xhci, td, event_trb, event, ep, status, true); 2018 } 2019 /* 2020 * Did we transfer any data, despite the errors that might have 2021 * happened? I.e. did we get past the setup stage? 2022 */ 2023 if (event_trb != ep_ring->dequeue) { 2024 /* The event was for the status stage */ 2025 if (event_trb == td->last_trb) { 2026 if (td->urb->actual_length != 0) { 2027 /* Don't overwrite a previously set error code 2028 */ 2029 if ((*status == -EINPROGRESS || *status == 0) && 2030 (td->urb->transfer_flags 2031 & URB_SHORT_NOT_OK)) 2032 /* Did we already see a short data 2033 * stage? */ 2034 *status = -EREMOTEIO; 2035 } else { 2036 td->urb->actual_length = 2037 td->urb->transfer_buffer_length; 2038 } 2039 } else { 2040 /* Maybe the event was for the data stage? */ 2041 td->urb->actual_length = 2042 td->urb->transfer_buffer_length - 2043 TRB_LEN(le32_to_cpu(event->transfer_len)); 2044 xhci_dbg(xhci, "Waiting for status " 2045 "stage event\n"); 2046 return 0; 2047 } 2048 } 2049 2050 return finish_td(xhci, td, event_trb, event, ep, status, false); 2051 } 2052 2053 /* 2054 * Process isochronous tds, update urb packet status and actual_length. 2055 */ 2056 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2057 union xhci_trb *event_trb, struct xhci_transfer_event *event, 2058 struct xhci_virt_ep *ep, int *status) 2059 { 2060 struct xhci_ring *ep_ring; 2061 struct urb_priv *urb_priv; 2062 int idx; 2063 int len = 0; 2064 union xhci_trb *cur_trb; 2065 struct xhci_segment *cur_seg; 2066 struct usb_iso_packet_descriptor *frame; 2067 u32 trb_comp_code; 2068 bool skip_td = false; 2069 2070 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2071 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2072 urb_priv = td->urb->hcpriv; 2073 idx = urb_priv->td_cnt; 2074 frame = &td->urb->iso_frame_desc[idx]; 2075 2076 /* handle completion code */ 2077 switch (trb_comp_code) { 2078 case COMP_SUCCESS: 2079 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { 2080 frame->status = 0; 2081 break; 2082 } 2083 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) 2084 trb_comp_code = COMP_SHORT_TX; 2085 case COMP_SHORT_TX: 2086 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2087 -EREMOTEIO : 0; 2088 break; 2089 case COMP_BW_OVER: 2090 frame->status = -ECOMM; 2091 skip_td = true; 2092 break; 2093 case COMP_BUFF_OVER: 2094 case COMP_BABBLE: 2095 frame->status = -EOVERFLOW; 2096 skip_td = true; 2097 break; 2098 case COMP_DEV_ERR: 2099 case COMP_STALL: 2100 case COMP_TX_ERR: 2101 frame->status = -EPROTO; 2102 skip_td = true; 2103 break; 2104 case COMP_STOP: 2105 case COMP_STOP_INVAL: 2106 break; 2107 default: 2108 frame->status = -1; 2109 break; 2110 } 2111 2112 if (trb_comp_code == COMP_SUCCESS || skip_td) { 2113 frame->actual_length = frame->length; 2114 td->urb->actual_length += frame->length; 2115 } else { 2116 for (cur_trb = ep_ring->dequeue, 2117 cur_seg = ep_ring->deq_seg; cur_trb != event_trb; 2118 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 2119 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && 2120 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) 2121 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); 2122 } 2123 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - 2124 TRB_LEN(le32_to_cpu(event->transfer_len)); 2125 2126 if (trb_comp_code != COMP_STOP_INVAL) { 2127 frame->actual_length = len; 2128 td->urb->actual_length += len; 2129 } 2130 } 2131 2132 return finish_td(xhci, td, event_trb, event, ep, status, false); 2133 } 2134 2135 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2136 struct xhci_transfer_event *event, 2137 struct xhci_virt_ep *ep, int *status) 2138 { 2139 struct xhci_ring *ep_ring; 2140 struct urb_priv *urb_priv; 2141 struct usb_iso_packet_descriptor *frame; 2142 int idx; 2143 2144 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2145 urb_priv = td->urb->hcpriv; 2146 idx = urb_priv->td_cnt; 2147 frame = &td->urb->iso_frame_desc[idx]; 2148 2149 /* The transfer is partly done. */ 2150 frame->status = -EXDEV; 2151 2152 /* calc actual length */ 2153 frame->actual_length = 0; 2154 2155 /* Update ring dequeue pointer */ 2156 while (ep_ring->dequeue != td->last_trb) 2157 inc_deq(xhci, ep_ring); 2158 inc_deq(xhci, ep_ring); 2159 2160 return finish_td(xhci, td, NULL, event, ep, status, true); 2161 } 2162 2163 /* 2164 * Process bulk and interrupt tds, update urb status and actual_length. 2165 */ 2166 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, 2167 union xhci_trb *event_trb, struct xhci_transfer_event *event, 2168 struct xhci_virt_ep *ep, int *status) 2169 { 2170 struct xhci_ring *ep_ring; 2171 union xhci_trb *cur_trb; 2172 struct xhci_segment *cur_seg; 2173 u32 trb_comp_code; 2174 2175 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2176 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2177 2178 switch (trb_comp_code) { 2179 case COMP_SUCCESS: 2180 /* Double check that the HW transferred everything. */ 2181 if (event_trb != td->last_trb || 2182 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { 2183 xhci_warn(xhci, "WARN Successful completion " 2184 "on short TX\n"); 2185 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2186 *status = -EREMOTEIO; 2187 else 2188 *status = 0; 2189 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) 2190 trb_comp_code = COMP_SHORT_TX; 2191 } else { 2192 *status = 0; 2193 } 2194 break; 2195 case COMP_SHORT_TX: 2196 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2197 *status = -EREMOTEIO; 2198 else 2199 *status = 0; 2200 break; 2201 default: 2202 /* Others already handled above */ 2203 break; 2204 } 2205 if (trb_comp_code == COMP_SHORT_TX) 2206 xhci_dbg(xhci, "ep %#x - asked for %d bytes, " 2207 "%d bytes untransferred\n", 2208 td->urb->ep->desc.bEndpointAddress, 2209 td->urb->transfer_buffer_length, 2210 TRB_LEN(le32_to_cpu(event->transfer_len))); 2211 /* Fast path - was this the last TRB in the TD for this URB? */ 2212 if (event_trb == td->last_trb) { 2213 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { 2214 td->urb->actual_length = 2215 td->urb->transfer_buffer_length - 2216 TRB_LEN(le32_to_cpu(event->transfer_len)); 2217 if (td->urb->transfer_buffer_length < 2218 td->urb->actual_length) { 2219 xhci_warn(xhci, "HC gave bad length " 2220 "of %d bytes left\n", 2221 TRB_LEN(le32_to_cpu(event->transfer_len))); 2222 td->urb->actual_length = 0; 2223 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2224 *status = -EREMOTEIO; 2225 else 2226 *status = 0; 2227 } 2228 /* Don't overwrite a previously set error code */ 2229 if (*status == -EINPROGRESS) { 2230 if (td->urb->transfer_flags & URB_SHORT_NOT_OK) 2231 *status = -EREMOTEIO; 2232 else 2233 *status = 0; 2234 } 2235 } else { 2236 td->urb->actual_length = 2237 td->urb->transfer_buffer_length; 2238 /* Ignore a short packet completion if the 2239 * untransferred length was zero. 2240 */ 2241 if (*status == -EREMOTEIO) 2242 *status = 0; 2243 } 2244 } else { 2245 /* Slow path - walk the list, starting from the dequeue 2246 * pointer, to get the actual length transferred. 2247 */ 2248 td->urb->actual_length = 0; 2249 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; 2250 cur_trb != event_trb; 2251 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { 2252 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && 2253 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) 2254 td->urb->actual_length += 2255 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); 2256 } 2257 /* If the ring didn't stop on a Link or No-op TRB, add 2258 * in the actual bytes transferred from the Normal TRB 2259 */ 2260 if (trb_comp_code != COMP_STOP_INVAL) 2261 td->urb->actual_length += 2262 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - 2263 TRB_LEN(le32_to_cpu(event->transfer_len)); 2264 } 2265 2266 return finish_td(xhci, td, event_trb, event, ep, status, false); 2267 } 2268 2269 /* 2270 * If this function returns an error condition, it means it got a Transfer 2271 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2272 * At this point, the host controller is probably hosed and should be reset. 2273 */ 2274 static int handle_tx_event(struct xhci_hcd *xhci, 2275 struct xhci_transfer_event *event) 2276 __releases(&xhci->lock) 2277 __acquires(&xhci->lock) 2278 { 2279 struct xhci_virt_device *xdev; 2280 struct xhci_virt_ep *ep; 2281 struct xhci_ring *ep_ring; 2282 unsigned int slot_id; 2283 int ep_index; 2284 struct xhci_td *td = NULL; 2285 dma_addr_t event_dma; 2286 struct xhci_segment *event_seg; 2287 union xhci_trb *event_trb; 2288 struct urb *urb = NULL; 2289 int status = -EINPROGRESS; 2290 struct urb_priv *urb_priv; 2291 struct xhci_ep_ctx *ep_ctx; 2292 struct list_head *tmp; 2293 u32 trb_comp_code; 2294 int ret = 0; 2295 int td_num = 0; 2296 2297 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2298 xdev = xhci->devs[slot_id]; 2299 if (!xdev) { 2300 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); 2301 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2302 (unsigned long long) xhci_trb_virt_to_dma( 2303 xhci->event_ring->deq_seg, 2304 xhci->event_ring->dequeue), 2305 lower_32_bits(le64_to_cpu(event->buffer)), 2306 upper_32_bits(le64_to_cpu(event->buffer)), 2307 le32_to_cpu(event->transfer_len), 2308 le32_to_cpu(event->flags)); 2309 xhci_dbg(xhci, "Event ring:\n"); 2310 xhci_debug_segment(xhci, xhci->event_ring->deq_seg); 2311 return -ENODEV; 2312 } 2313 2314 /* Endpoint ID is 1 based, our index is zero based */ 2315 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2316 ep = &xdev->eps[ep_index]; 2317 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2318 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2319 if (!ep_ring || 2320 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == 2321 EP_STATE_DISABLED) { 2322 xhci_err(xhci, "ERROR Transfer event for disabled endpoint " 2323 "or incorrect stream ring\n"); 2324 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2325 (unsigned long long) xhci_trb_virt_to_dma( 2326 xhci->event_ring->deq_seg, 2327 xhci->event_ring->dequeue), 2328 lower_32_bits(le64_to_cpu(event->buffer)), 2329 upper_32_bits(le64_to_cpu(event->buffer)), 2330 le32_to_cpu(event->transfer_len), 2331 le32_to_cpu(event->flags)); 2332 xhci_dbg(xhci, "Event ring:\n"); 2333 xhci_debug_segment(xhci, xhci->event_ring->deq_seg); 2334 return -ENODEV; 2335 } 2336 2337 /* Count current td numbers if ep->skip is set */ 2338 if (ep->skip) { 2339 list_for_each(tmp, &ep_ring->td_list) 2340 td_num++; 2341 } 2342 2343 event_dma = le64_to_cpu(event->buffer); 2344 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2345 /* Look for common error cases */ 2346 switch (trb_comp_code) { 2347 /* Skip codes that require special handling depending on 2348 * transfer type 2349 */ 2350 case COMP_SUCCESS: 2351 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) 2352 break; 2353 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2354 trb_comp_code = COMP_SHORT_TX; 2355 else 2356 xhci_warn_ratelimited(xhci, 2357 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); 2358 case COMP_SHORT_TX: 2359 break; 2360 case COMP_STOP: 2361 xhci_dbg(xhci, "Stopped on Transfer TRB\n"); 2362 break; 2363 case COMP_STOP_INVAL: 2364 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); 2365 break; 2366 case COMP_STALL: 2367 xhci_dbg(xhci, "Stalled endpoint\n"); 2368 ep->ep_state |= EP_HALTED; 2369 status = -EPIPE; 2370 break; 2371 case COMP_TRB_ERR: 2372 xhci_warn(xhci, "WARN: TRB error on endpoint\n"); 2373 status = -EILSEQ; 2374 break; 2375 case COMP_SPLIT_ERR: 2376 case COMP_TX_ERR: 2377 xhci_dbg(xhci, "Transfer error on endpoint\n"); 2378 status = -EPROTO; 2379 break; 2380 case COMP_BABBLE: 2381 xhci_dbg(xhci, "Babble error on endpoint\n"); 2382 status = -EOVERFLOW; 2383 break; 2384 case COMP_DB_ERR: 2385 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); 2386 status = -ENOSR; 2387 break; 2388 case COMP_BW_OVER: 2389 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); 2390 break; 2391 case COMP_BUFF_OVER: 2392 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); 2393 break; 2394 case COMP_UNDERRUN: 2395 /* 2396 * When the Isoch ring is empty, the xHC will generate 2397 * a Ring Overrun Event for IN Isoch endpoint or Ring 2398 * Underrun Event for OUT Isoch endpoint. 2399 */ 2400 xhci_dbg(xhci, "underrun event on endpoint\n"); 2401 if (!list_empty(&ep_ring->td_list)) 2402 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 2403 "still with TDs queued?\n", 2404 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2405 ep_index); 2406 goto cleanup; 2407 case COMP_OVERRUN: 2408 xhci_dbg(xhci, "overrun event on endpoint\n"); 2409 if (!list_empty(&ep_ring->td_list)) 2410 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 2411 "still with TDs queued?\n", 2412 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2413 ep_index); 2414 goto cleanup; 2415 case COMP_DEV_ERR: 2416 xhci_warn(xhci, "WARN: detect an incompatible device"); 2417 status = -EPROTO; 2418 break; 2419 case COMP_MISSED_INT: 2420 /* 2421 * When encounter missed service error, one or more isoc tds 2422 * may be missed by xHC. 2423 * Set skip flag of the ep_ring; Complete the missed tds as 2424 * short transfer when process the ep_ring next time. 2425 */ 2426 ep->skip = true; 2427 xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); 2428 goto cleanup; 2429 default: 2430 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2431 status = 0; 2432 break; 2433 } 2434 xhci_warn(xhci, "ERROR Unknown event condition, HC probably " 2435 "busted\n"); 2436 goto cleanup; 2437 } 2438 2439 do { 2440 /* This TRB should be in the TD at the head of this ring's 2441 * TD list. 2442 */ 2443 if (list_empty(&ep_ring->td_list)) { 2444 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " 2445 "with no TDs queued?\n", 2446 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2447 ep_index); 2448 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", 2449 (le32_to_cpu(event->flags) & 2450 TRB_TYPE_BITMASK)>>10); 2451 xhci_print_trb_offsets(xhci, (union xhci_trb *) event); 2452 if (ep->skip) { 2453 ep->skip = false; 2454 xhci_dbg(xhci, "td_list is empty while skip " 2455 "flag set. Clear skip flag.\n"); 2456 } 2457 ret = 0; 2458 goto cleanup; 2459 } 2460 2461 /* We've skipped all the TDs on the ep ring when ep->skip set */ 2462 if (ep->skip && td_num == 0) { 2463 ep->skip = false; 2464 xhci_dbg(xhci, "All tds on the ep_ring skipped. " 2465 "Clear skip flag.\n"); 2466 ret = 0; 2467 goto cleanup; 2468 } 2469 2470 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); 2471 if (ep->skip) 2472 td_num--; 2473 2474 /* Is this a TRB in the currently executing TD? */ 2475 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, 2476 td->last_trb, event_dma); 2477 2478 /* 2479 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE 2480 * is not in the current TD pointed by ep_ring->dequeue because 2481 * that the hardware dequeue pointer still at the previous TRB 2482 * of the current TD. The previous TRB maybe a Link TD or the 2483 * last TRB of the previous TD. The command completion handle 2484 * will take care the rest. 2485 */ 2486 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { 2487 ret = 0; 2488 goto cleanup; 2489 } 2490 2491 if (!event_seg) { 2492 if (!ep->skip || 2493 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2494 /* Some host controllers give a spurious 2495 * successful event after a short transfer. 2496 * Ignore it. 2497 */ 2498 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2499 ep_ring->last_td_was_short) { 2500 ep_ring->last_td_was_short = false; 2501 ret = 0; 2502 goto cleanup; 2503 } 2504 /* HC is busted, give up! */ 2505 xhci_err(xhci, 2506 "ERROR Transfer event TRB DMA ptr not " 2507 "part of current TD\n"); 2508 return -ESHUTDOWN; 2509 } 2510 2511 ret = skip_isoc_td(xhci, td, event, ep, &status); 2512 goto cleanup; 2513 } 2514 if (trb_comp_code == COMP_SHORT_TX) 2515 ep_ring->last_td_was_short = true; 2516 else 2517 ep_ring->last_td_was_short = false; 2518 2519 if (ep->skip) { 2520 xhci_dbg(xhci, "Found td. Clear skip flag.\n"); 2521 ep->skip = false; 2522 } 2523 2524 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / 2525 sizeof(*event_trb)]; 2526 /* 2527 * No-op TRB should not trigger interrupts. 2528 * If event_trb is a no-op TRB, it means the 2529 * corresponding TD has been cancelled. Just ignore 2530 * the TD. 2531 */ 2532 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { 2533 xhci_dbg(xhci, 2534 "event_trb is a no-op TRB. Skip it\n"); 2535 goto cleanup; 2536 } 2537 2538 /* Now update the urb's actual_length and give back to 2539 * the core 2540 */ 2541 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2542 ret = process_ctrl_td(xhci, td, event_trb, event, ep, 2543 &status); 2544 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2545 ret = process_isoc_td(xhci, td, event_trb, event, ep, 2546 &status); 2547 else 2548 ret = process_bulk_intr_td(xhci, td, event_trb, event, 2549 ep, &status); 2550 2551 cleanup: 2552 /* 2553 * Do not update event ring dequeue pointer if ep->skip is set. 2554 * Will roll back to continue process missed tds. 2555 */ 2556 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { 2557 inc_deq(xhci, xhci->event_ring); 2558 } 2559 2560 if (ret) { 2561 urb = td->urb; 2562 urb_priv = urb->hcpriv; 2563 /* Leave the TD around for the reset endpoint function 2564 * to use(but only if it's not a control endpoint, 2565 * since we already queued the Set TR dequeue pointer 2566 * command for stalled control endpoints). 2567 */ 2568 if (usb_endpoint_xfer_control(&urb->ep->desc) || 2569 (trb_comp_code != COMP_STALL && 2570 trb_comp_code != COMP_BABBLE)) 2571 xhci_urb_free_priv(xhci, urb_priv); 2572 2573 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 2574 if ((urb->actual_length != urb->transfer_buffer_length && 2575 (urb->transfer_flags & 2576 URB_SHORT_NOT_OK)) || 2577 (status != 0 && 2578 !usb_endpoint_xfer_isoc(&urb->ep->desc))) 2579 xhci_dbg(xhci, "Giveback URB %p, len = %d, " 2580 "expected = %d, status = %d\n", 2581 urb, urb->actual_length, 2582 urb->transfer_buffer_length, 2583 status); 2584 spin_unlock(&xhci->lock); 2585 /* EHCI, UHCI, and OHCI always unconditionally set the 2586 * urb->status of an isochronous endpoint to 0. 2587 */ 2588 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2589 status = 0; 2590 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); 2591 spin_lock(&xhci->lock); 2592 } 2593 2594 /* 2595 * If ep->skip is set, it means there are missed tds on the 2596 * endpoint ring need to take care of. 2597 * Process them as short transfer until reach the td pointed by 2598 * the event. 2599 */ 2600 } while (ep->skip && trb_comp_code != COMP_MISSED_INT); 2601 2602 return 0; 2603 } 2604 2605 /* 2606 * This function handles all OS-owned events on the event ring. It may drop 2607 * xhci->lock between event processing (e.g. to pass up port status changes). 2608 * Returns >0 for "possibly more events to process" (caller should call again), 2609 * otherwise 0 if done. In future, <0 returns should indicate error code. 2610 */ 2611 static int xhci_handle_event(struct xhci_hcd *xhci) 2612 { 2613 union xhci_trb *event; 2614 int update_ptrs = 1; 2615 int ret; 2616 2617 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 2618 xhci->error_bitmask |= 1 << 1; 2619 return 0; 2620 } 2621 2622 event = xhci->event_ring->dequeue; 2623 /* Does the HC or OS own the TRB? */ 2624 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != 2625 xhci->event_ring->cycle_state) { 2626 xhci->error_bitmask |= 1 << 2; 2627 return 0; 2628 } 2629 2630 /* 2631 * Barrier between reading the TRB_CYCLE (valid) flag above and any 2632 * speculative reads of the event's flags/data below. 2633 */ 2634 rmb(); 2635 /* FIXME: Handle more event types. */ 2636 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { 2637 case TRB_TYPE(TRB_COMPLETION): 2638 handle_cmd_completion(xhci, &event->event_cmd); 2639 break; 2640 case TRB_TYPE(TRB_PORT_STATUS): 2641 handle_port_status(xhci, event); 2642 update_ptrs = 0; 2643 break; 2644 case TRB_TYPE(TRB_TRANSFER): 2645 ret = handle_tx_event(xhci, &event->trans_event); 2646 if (ret < 0) 2647 xhci->error_bitmask |= 1 << 9; 2648 else 2649 update_ptrs = 0; 2650 break; 2651 case TRB_TYPE(TRB_DEV_NOTE): 2652 handle_device_notification(xhci, event); 2653 break; 2654 default: 2655 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= 2656 TRB_TYPE(48)) 2657 handle_vendor_event(xhci, event); 2658 else 2659 xhci->error_bitmask |= 1 << 3; 2660 } 2661 /* Any of the above functions may drop and re-acquire the lock, so check 2662 * to make sure a watchdog timer didn't mark the host as non-responsive. 2663 */ 2664 if (xhci->xhc_state & XHCI_STATE_DYING) { 2665 xhci_dbg(xhci, "xHCI host dying, returning from " 2666 "event handler.\n"); 2667 return 0; 2668 } 2669 2670 if (update_ptrs) 2671 /* Update SW event ring dequeue pointer */ 2672 inc_deq(xhci, xhci->event_ring); 2673 2674 /* Are there more items on the event ring? Caller will call us again to 2675 * check. 2676 */ 2677 return 1; 2678 } 2679 2680 /* 2681 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 2682 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 2683 * indicators of an event TRB error, but we check the status *first* to be safe. 2684 */ 2685 irqreturn_t xhci_irq(struct usb_hcd *hcd) 2686 { 2687 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2688 u32 status; 2689 union xhci_trb *trb; 2690 u64 temp_64; 2691 union xhci_trb *event_ring_deq; 2692 dma_addr_t deq; 2693 2694 spin_lock(&xhci->lock); 2695 trb = xhci->event_ring->dequeue; 2696 /* Check if the xHC generated the interrupt, or the irq is shared */ 2697 status = xhci_readl(xhci, &xhci->op_regs->status); 2698 if (status == 0xffffffff) 2699 goto hw_died; 2700 2701 if (!(status & STS_EINT)) { 2702 spin_unlock(&xhci->lock); 2703 return IRQ_NONE; 2704 } 2705 if (status & STS_FATAL) { 2706 xhci_warn(xhci, "WARNING: Host System Error\n"); 2707 xhci_halt(xhci); 2708 hw_died: 2709 spin_unlock(&xhci->lock); 2710 return -ESHUTDOWN; 2711 } 2712 2713 /* 2714 * Clear the op reg interrupt status first, 2715 * so we can receive interrupts from other MSI-X interrupters. 2716 * Write 1 to clear the interrupt status. 2717 */ 2718 status |= STS_EINT; 2719 xhci_writel(xhci, status, &xhci->op_regs->status); 2720 /* FIXME when MSI-X is supported and there are multiple vectors */ 2721 /* Clear the MSI-X event interrupt status */ 2722 2723 if (hcd->irq) { 2724 u32 irq_pending; 2725 /* Acknowledge the PCI interrupt */ 2726 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); 2727 irq_pending |= IMAN_IP; 2728 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); 2729 } 2730 2731 if (xhci->xhc_state & XHCI_STATE_DYING) { 2732 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 2733 "Shouldn't IRQs be disabled?\n"); 2734 /* Clear the event handler busy flag (RW1C); 2735 * the event ring should be empty. 2736 */ 2737 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2738 xhci_write_64(xhci, temp_64 | ERST_EHB, 2739 &xhci->ir_set->erst_dequeue); 2740 spin_unlock(&xhci->lock); 2741 2742 return IRQ_HANDLED; 2743 } 2744 2745 event_ring_deq = xhci->event_ring->dequeue; 2746 /* FIXME this should be a delayed service routine 2747 * that clears the EHB. 2748 */ 2749 while (xhci_handle_event(xhci) > 0) {} 2750 2751 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2752 /* If necessary, update the HW's version of the event ring deq ptr. */ 2753 if (event_ring_deq != xhci->event_ring->dequeue) { 2754 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2755 xhci->event_ring->dequeue); 2756 if (deq == 0) 2757 xhci_warn(xhci, "WARN something wrong with SW event " 2758 "ring dequeue ptr.\n"); 2759 /* Update HC event ring dequeue pointer */ 2760 temp_64 &= ERST_PTR_MASK; 2761 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 2762 } 2763 2764 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2765 temp_64 |= ERST_EHB; 2766 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); 2767 2768 spin_unlock(&xhci->lock); 2769 2770 return IRQ_HANDLED; 2771 } 2772 2773 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) 2774 { 2775 return xhci_irq(hcd); 2776 } 2777 2778 /**** Endpoint Ring Operations ****/ 2779 2780 /* 2781 * Generic function for queueing a TRB on a ring. 2782 * The caller must have checked to make sure there's room on the ring. 2783 * 2784 * @more_trbs_coming: Will you enqueue more TRBs before calling 2785 * prepare_transfer()? 2786 */ 2787 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 2788 bool more_trbs_coming, 2789 u32 field1, u32 field2, u32 field3, u32 field4) 2790 { 2791 struct xhci_generic_trb *trb; 2792 2793 trb = &ring->enqueue->generic; 2794 trb->field[0] = cpu_to_le32(field1); 2795 trb->field[1] = cpu_to_le32(field2); 2796 trb->field[2] = cpu_to_le32(field3); 2797 trb->field[3] = cpu_to_le32(field4); 2798 inc_enq(xhci, ring, more_trbs_coming); 2799 } 2800 2801 /* 2802 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 2803 * FIXME allocate segments if the ring is full. 2804 */ 2805 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 2806 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2807 { 2808 unsigned int num_trbs_needed; 2809 2810 /* Make sure the endpoint has been added to xHC schedule */ 2811 switch (ep_state) { 2812 case EP_STATE_DISABLED: 2813 /* 2814 * USB core changed config/interfaces without notifying us, 2815 * or hardware is reporting the wrong state. 2816 */ 2817 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 2818 return -ENOENT; 2819 case EP_STATE_ERROR: 2820 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 2821 /* FIXME event handling code for error needs to clear it */ 2822 /* XXX not sure if this should be -ENOENT or not */ 2823 return -EINVAL; 2824 case EP_STATE_HALTED: 2825 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 2826 case EP_STATE_STOPPED: 2827 case EP_STATE_RUNNING: 2828 break; 2829 default: 2830 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 2831 /* 2832 * FIXME issue Configure Endpoint command to try to get the HC 2833 * back into a known state. 2834 */ 2835 return -EINVAL; 2836 } 2837 2838 while (1) { 2839 if (room_on_ring(xhci, ep_ring, num_trbs)) 2840 break; 2841 2842 if (ep_ring == xhci->cmd_ring) { 2843 xhci_err(xhci, "Do not support expand command ring\n"); 2844 return -ENOMEM; 2845 } 2846 2847 xhci_dbg(xhci, "ERROR no room on ep ring, " 2848 "try ring expansion\n"); 2849 num_trbs_needed = num_trbs - ep_ring->num_trbs_free; 2850 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, 2851 mem_flags)) { 2852 xhci_err(xhci, "Ring expansion failed\n"); 2853 return -ENOMEM; 2854 } 2855 } 2856 2857 if (enqueue_is_link_trb(ep_ring)) { 2858 struct xhci_ring *ring = ep_ring; 2859 union xhci_trb *next; 2860 2861 next = ring->enqueue; 2862 2863 while (last_trb(xhci, ring, ring->enq_seg, next)) { 2864 /* If we're not dealing with 0.95 hardware or isoc rings 2865 * on AMD 0.96 host, clear the chain bit. 2866 */ 2867 if (!xhci_link_trb_quirk(xhci) && 2868 !(ring->type == TYPE_ISOC && 2869 (xhci->quirks & XHCI_AMD_0x96_HOST))) 2870 next->link.control &= cpu_to_le32(~TRB_CHAIN); 2871 else 2872 next->link.control |= cpu_to_le32(TRB_CHAIN); 2873 2874 wmb(); 2875 next->link.control ^= cpu_to_le32(TRB_CYCLE); 2876 2877 /* Toggle the cycle bit after the last ring segment. */ 2878 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { 2879 ring->cycle_state = (ring->cycle_state ? 0 : 1); 2880 } 2881 ring->enq_seg = ring->enq_seg->next; 2882 ring->enqueue = ring->enq_seg->trbs; 2883 next = ring->enqueue; 2884 } 2885 } 2886 2887 return 0; 2888 } 2889 2890 static int prepare_transfer(struct xhci_hcd *xhci, 2891 struct xhci_virt_device *xdev, 2892 unsigned int ep_index, 2893 unsigned int stream_id, 2894 unsigned int num_trbs, 2895 struct urb *urb, 2896 unsigned int td_index, 2897 gfp_t mem_flags) 2898 { 2899 int ret; 2900 struct urb_priv *urb_priv; 2901 struct xhci_td *td; 2902 struct xhci_ring *ep_ring; 2903 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2904 2905 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); 2906 if (!ep_ring) { 2907 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 2908 stream_id); 2909 return -EINVAL; 2910 } 2911 2912 ret = prepare_ring(xhci, ep_ring, 2913 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, 2914 num_trbs, mem_flags); 2915 if (ret) 2916 return ret; 2917 2918 urb_priv = urb->hcpriv; 2919 td = urb_priv->td[td_index]; 2920 2921 INIT_LIST_HEAD(&td->td_list); 2922 INIT_LIST_HEAD(&td->cancelled_td_list); 2923 2924 if (td_index == 0) { 2925 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 2926 if (unlikely(ret)) 2927 return ret; 2928 } 2929 2930 td->urb = urb; 2931 /* Add this TD to the tail of the endpoint ring's TD list */ 2932 list_add_tail(&td->td_list, &ep_ring->td_list); 2933 td->start_seg = ep_ring->enq_seg; 2934 td->first_trb = ep_ring->enqueue; 2935 2936 urb_priv->td[td_index] = td; 2937 2938 return 0; 2939 } 2940 2941 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) 2942 { 2943 int num_sgs, num_trbs, running_total, temp, i; 2944 struct scatterlist *sg; 2945 2946 sg = NULL; 2947 num_sgs = urb->num_mapped_sgs; 2948 temp = urb->transfer_buffer_length; 2949 2950 num_trbs = 0; 2951 for_each_sg(urb->sg, sg, num_sgs, i) { 2952 unsigned int len = sg_dma_len(sg); 2953 2954 /* Scatter gather list entries may cross 64KB boundaries */ 2955 running_total = TRB_MAX_BUFF_SIZE - 2956 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); 2957 running_total &= TRB_MAX_BUFF_SIZE - 1; 2958 if (running_total != 0) 2959 num_trbs++; 2960 2961 /* How many more 64KB chunks to transfer, how many more TRBs? */ 2962 while (running_total < sg_dma_len(sg) && running_total < temp) { 2963 num_trbs++; 2964 running_total += TRB_MAX_BUFF_SIZE; 2965 } 2966 len = min_t(int, len, temp); 2967 temp -= len; 2968 if (temp == 0) 2969 break; 2970 } 2971 return num_trbs; 2972 } 2973 2974 static void check_trb_math(struct urb *urb, int num_trbs, int running_total) 2975 { 2976 if (num_trbs != 0) 2977 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " 2978 "TRBs, %d left\n", __func__, 2979 urb->ep->desc.bEndpointAddress, num_trbs); 2980 if (running_total != urb->transfer_buffer_length) 2981 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 2982 "queued %#x (%d), asked for %#x (%d)\n", 2983 __func__, 2984 urb->ep->desc.bEndpointAddress, 2985 running_total, running_total, 2986 urb->transfer_buffer_length, 2987 urb->transfer_buffer_length); 2988 } 2989 2990 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 2991 unsigned int ep_index, unsigned int stream_id, int start_cycle, 2992 struct xhci_generic_trb *start_trb) 2993 { 2994 /* 2995 * Pass all the TRBs to the hardware at once and make sure this write 2996 * isn't reordered. 2997 */ 2998 wmb(); 2999 if (start_cycle) 3000 start_trb->field[3] |= cpu_to_le32(start_cycle); 3001 else 3002 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3003 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3004 } 3005 3006 /* 3007 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3008 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3009 * (comprised of sg list entries) can take several service intervals to 3010 * transmit. 3011 */ 3012 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3013 struct urb *urb, int slot_id, unsigned int ep_index) 3014 { 3015 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, 3016 xhci->devs[slot_id]->out_ctx, ep_index); 3017 int xhci_interval; 3018 int ep_interval; 3019 3020 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3021 ep_interval = urb->interval; 3022 /* Convert to microframes */ 3023 if (urb->dev->speed == USB_SPEED_LOW || 3024 urb->dev->speed == USB_SPEED_FULL) 3025 ep_interval *= 8; 3026 /* FIXME change this to a warning and a suggestion to use the new API 3027 * to set the polling interval (once the API is added). 3028 */ 3029 if (xhci_interval != ep_interval) { 3030 if (printk_ratelimit()) 3031 dev_dbg(&urb->dev->dev, "Driver uses different interval" 3032 " (%d microframe%s) than xHCI " 3033 "(%d microframe%s)\n", 3034 ep_interval, 3035 ep_interval == 1 ? "" : "s", 3036 xhci_interval, 3037 xhci_interval == 1 ? "" : "s"); 3038 urb->interval = xhci_interval; 3039 /* Convert back to frames for LS/FS devices */ 3040 if (urb->dev->speed == USB_SPEED_LOW || 3041 urb->dev->speed == USB_SPEED_FULL) 3042 urb->interval /= 8; 3043 } 3044 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3045 } 3046 3047 /* 3048 * The TD size is the number of bytes remaining in the TD (including this TRB), 3049 * right shifted by 10. 3050 * It must fit in bits 21:17, so it can't be bigger than 31. 3051 */ 3052 static u32 xhci_td_remainder(unsigned int remainder) 3053 { 3054 u32 max = (1 << (21 - 17 + 1)) - 1; 3055 3056 if ((remainder >> 10) >= max) 3057 return max << 17; 3058 else 3059 return (remainder >> 10) << 17; 3060 } 3061 3062 /* 3063 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in 3064 * the TD (*not* including this TRB). 3065 * 3066 * Total TD packet count = total_packet_count = 3067 * roundup(TD size in bytes / wMaxPacketSize) 3068 * 3069 * Packets transferred up to and including this TRB = packets_transferred = 3070 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3071 * 3072 * TD size = total_packet_count - packets_transferred 3073 * 3074 * It must fit in bits 21:17, so it can't be bigger than 31. 3075 */ 3076 3077 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, 3078 unsigned int total_packet_count, struct urb *urb) 3079 { 3080 int packets_transferred; 3081 3082 /* One TRB with a zero-length data packet. */ 3083 if (running_total == 0 && trb_buff_len == 0) 3084 return 0; 3085 3086 /* All the TRB queueing functions don't count the current TRB in 3087 * running_total. 3088 */ 3089 packets_transferred = (running_total + trb_buff_len) / 3090 usb_endpoint_maxp(&urb->ep->desc); 3091 3092 return xhci_td_remainder(total_packet_count - packets_transferred); 3093 } 3094 3095 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3096 struct urb *urb, int slot_id, unsigned int ep_index) 3097 { 3098 struct xhci_ring *ep_ring; 3099 unsigned int num_trbs; 3100 struct urb_priv *urb_priv; 3101 struct xhci_td *td; 3102 struct scatterlist *sg; 3103 int num_sgs; 3104 int trb_buff_len, this_sg_len, running_total; 3105 unsigned int total_packet_count; 3106 bool first_trb; 3107 u64 addr; 3108 bool more_trbs_coming; 3109 3110 struct xhci_generic_trb *start_trb; 3111 int start_cycle; 3112 3113 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3114 if (!ep_ring) 3115 return -EINVAL; 3116 3117 num_trbs = count_sg_trbs_needed(xhci, urb); 3118 num_sgs = urb->num_mapped_sgs; 3119 total_packet_count = roundup(urb->transfer_buffer_length, 3120 usb_endpoint_maxp(&urb->ep->desc)); 3121 3122 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], 3123 ep_index, urb->stream_id, 3124 num_trbs, urb, 0, mem_flags); 3125 if (trb_buff_len < 0) 3126 return trb_buff_len; 3127 3128 urb_priv = urb->hcpriv; 3129 td = urb_priv->td[0]; 3130 3131 /* 3132 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3133 * until we've finished creating all the other TRBs. The ring's cycle 3134 * state may change as we enqueue the other TRBs, so save it too. 3135 */ 3136 start_trb = &ep_ring->enqueue->generic; 3137 start_cycle = ep_ring->cycle_state; 3138 3139 running_total = 0; 3140 /* 3141 * How much data is in the first TRB? 3142 * 3143 * There are three forces at work for TRB buffer pointers and lengths: 3144 * 1. We don't want to walk off the end of this sg-list entry buffer. 3145 * 2. The transfer length that the driver requested may be smaller than 3146 * the amount of memory allocated for this scatter-gather list. 3147 * 3. TRBs buffers can't cross 64KB boundaries. 3148 */ 3149 sg = urb->sg; 3150 addr = (u64) sg_dma_address(sg); 3151 this_sg_len = sg_dma_len(sg); 3152 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); 3153 trb_buff_len = min_t(int, trb_buff_len, this_sg_len); 3154 if (trb_buff_len > urb->transfer_buffer_length) 3155 trb_buff_len = urb->transfer_buffer_length; 3156 3157 first_trb = true; 3158 /* Queue the first TRB, even if it's zero-length */ 3159 do { 3160 u32 field = 0; 3161 u32 length_field = 0; 3162 u32 remainder = 0; 3163 3164 /* Don't change the cycle bit of the first TRB until later */ 3165 if (first_trb) { 3166 first_trb = false; 3167 if (start_cycle == 0) 3168 field |= 0x1; 3169 } else 3170 field |= ep_ring->cycle_state; 3171 3172 /* Chain all the TRBs together; clear the chain bit in the last 3173 * TRB to indicate it's the last TRB in the chain. 3174 */ 3175 if (num_trbs > 1) { 3176 field |= TRB_CHAIN; 3177 } else { 3178 /* FIXME - add check for ZERO_PACKET flag before this */ 3179 td->last_trb = ep_ring->enqueue; 3180 field |= TRB_IOC; 3181 } 3182 3183 /* Only set interrupt on short packet for IN endpoints */ 3184 if (usb_urb_dir_in(urb)) 3185 field |= TRB_ISP; 3186 3187 if (TRB_MAX_BUFF_SIZE - 3188 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { 3189 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); 3190 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", 3191 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), 3192 (unsigned int) addr + trb_buff_len); 3193 } 3194 3195 /* Set the TRB length, TD size, and interrupter fields. */ 3196 if (xhci->hci_version < 0x100) { 3197 remainder = xhci_td_remainder( 3198 urb->transfer_buffer_length - 3199 running_total); 3200 } else { 3201 remainder = xhci_v1_0_td_remainder(running_total, 3202 trb_buff_len, total_packet_count, urb); 3203 } 3204 length_field = TRB_LEN(trb_buff_len) | 3205 remainder | 3206 TRB_INTR_TARGET(0); 3207 3208 if (num_trbs > 1) 3209 more_trbs_coming = true; 3210 else 3211 more_trbs_coming = false; 3212 queue_trb(xhci, ep_ring, more_trbs_coming, 3213 lower_32_bits(addr), 3214 upper_32_bits(addr), 3215 length_field, 3216 field | TRB_TYPE(TRB_NORMAL)); 3217 --num_trbs; 3218 running_total += trb_buff_len; 3219 3220 /* Calculate length for next transfer -- 3221 * Are we done queueing all the TRBs for this sg entry? 3222 */ 3223 this_sg_len -= trb_buff_len; 3224 if (this_sg_len == 0) { 3225 --num_sgs; 3226 if (num_sgs == 0) 3227 break; 3228 sg = sg_next(sg); 3229 addr = (u64) sg_dma_address(sg); 3230 this_sg_len = sg_dma_len(sg); 3231 } else { 3232 addr += trb_buff_len; 3233 } 3234 3235 trb_buff_len = TRB_MAX_BUFF_SIZE - 3236 (addr & (TRB_MAX_BUFF_SIZE - 1)); 3237 trb_buff_len = min_t(int, trb_buff_len, this_sg_len); 3238 if (running_total + trb_buff_len > urb->transfer_buffer_length) 3239 trb_buff_len = 3240 urb->transfer_buffer_length - running_total; 3241 } while (running_total < urb->transfer_buffer_length); 3242 3243 check_trb_math(urb, num_trbs, running_total); 3244 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3245 start_cycle, start_trb); 3246 return 0; 3247 } 3248 3249 /* This is very similar to what ehci-q.c qtd_fill() does */ 3250 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3251 struct urb *urb, int slot_id, unsigned int ep_index) 3252 { 3253 struct xhci_ring *ep_ring; 3254 struct urb_priv *urb_priv; 3255 struct xhci_td *td; 3256 int num_trbs; 3257 struct xhci_generic_trb *start_trb; 3258 bool first_trb; 3259 bool more_trbs_coming; 3260 int start_cycle; 3261 u32 field, length_field; 3262 3263 int running_total, trb_buff_len, ret; 3264 unsigned int total_packet_count; 3265 u64 addr; 3266 3267 if (urb->num_sgs) 3268 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); 3269 3270 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3271 if (!ep_ring) 3272 return -EINVAL; 3273 3274 num_trbs = 0; 3275 /* How much data is (potentially) left before the 64KB boundary? */ 3276 running_total = TRB_MAX_BUFF_SIZE - 3277 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); 3278 running_total &= TRB_MAX_BUFF_SIZE - 1; 3279 3280 /* If there's some data on this 64KB chunk, or we have to send a 3281 * zero-length transfer, we need at least one TRB 3282 */ 3283 if (running_total != 0 || urb->transfer_buffer_length == 0) 3284 num_trbs++; 3285 /* How many more 64KB chunks to transfer, how many more TRBs? */ 3286 while (running_total < urb->transfer_buffer_length) { 3287 num_trbs++; 3288 running_total += TRB_MAX_BUFF_SIZE; 3289 } 3290 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ 3291 3292 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3293 ep_index, urb->stream_id, 3294 num_trbs, urb, 0, mem_flags); 3295 if (ret < 0) 3296 return ret; 3297 3298 urb_priv = urb->hcpriv; 3299 td = urb_priv->td[0]; 3300 3301 /* 3302 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3303 * until we've finished creating all the other TRBs. The ring's cycle 3304 * state may change as we enqueue the other TRBs, so save it too. 3305 */ 3306 start_trb = &ep_ring->enqueue->generic; 3307 start_cycle = ep_ring->cycle_state; 3308 3309 running_total = 0; 3310 total_packet_count = roundup(urb->transfer_buffer_length, 3311 usb_endpoint_maxp(&urb->ep->desc)); 3312 /* How much data is in the first TRB? */ 3313 addr = (u64) urb->transfer_dma; 3314 trb_buff_len = TRB_MAX_BUFF_SIZE - 3315 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); 3316 if (trb_buff_len > urb->transfer_buffer_length) 3317 trb_buff_len = urb->transfer_buffer_length; 3318 3319 first_trb = true; 3320 3321 /* Queue the first TRB, even if it's zero-length */ 3322 do { 3323 u32 remainder = 0; 3324 field = 0; 3325 3326 /* Don't change the cycle bit of the first TRB until later */ 3327 if (first_trb) { 3328 first_trb = false; 3329 if (start_cycle == 0) 3330 field |= 0x1; 3331 } else 3332 field |= ep_ring->cycle_state; 3333 3334 /* Chain all the TRBs together; clear the chain bit in the last 3335 * TRB to indicate it's the last TRB in the chain. 3336 */ 3337 if (num_trbs > 1) { 3338 field |= TRB_CHAIN; 3339 } else { 3340 /* FIXME - add check for ZERO_PACKET flag before this */ 3341 td->last_trb = ep_ring->enqueue; 3342 field |= TRB_IOC; 3343 } 3344 3345 /* Only set interrupt on short packet for IN endpoints */ 3346 if (usb_urb_dir_in(urb)) 3347 field |= TRB_ISP; 3348 3349 /* Set the TRB length, TD size, and interrupter fields. */ 3350 if (xhci->hci_version < 0x100) { 3351 remainder = xhci_td_remainder( 3352 urb->transfer_buffer_length - 3353 running_total); 3354 } else { 3355 remainder = xhci_v1_0_td_remainder(running_total, 3356 trb_buff_len, total_packet_count, urb); 3357 } 3358 length_field = TRB_LEN(trb_buff_len) | 3359 remainder | 3360 TRB_INTR_TARGET(0); 3361 3362 if (num_trbs > 1) 3363 more_trbs_coming = true; 3364 else 3365 more_trbs_coming = false; 3366 queue_trb(xhci, ep_ring, more_trbs_coming, 3367 lower_32_bits(addr), 3368 upper_32_bits(addr), 3369 length_field, 3370 field | TRB_TYPE(TRB_NORMAL)); 3371 --num_trbs; 3372 running_total += trb_buff_len; 3373 3374 /* Calculate length for next transfer */ 3375 addr += trb_buff_len; 3376 trb_buff_len = urb->transfer_buffer_length - running_total; 3377 if (trb_buff_len > TRB_MAX_BUFF_SIZE) 3378 trb_buff_len = TRB_MAX_BUFF_SIZE; 3379 } while (running_total < urb->transfer_buffer_length); 3380 3381 check_trb_math(urb, num_trbs, running_total); 3382 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3383 start_cycle, start_trb); 3384 return 0; 3385 } 3386 3387 /* Caller must have locked xhci->lock */ 3388 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3389 struct urb *urb, int slot_id, unsigned int ep_index) 3390 { 3391 struct xhci_ring *ep_ring; 3392 int num_trbs; 3393 int ret; 3394 struct usb_ctrlrequest *setup; 3395 struct xhci_generic_trb *start_trb; 3396 int start_cycle; 3397 u32 field, length_field; 3398 struct urb_priv *urb_priv; 3399 struct xhci_td *td; 3400 3401 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3402 if (!ep_ring) 3403 return -EINVAL; 3404 3405 /* 3406 * Need to copy setup packet into setup TRB, so we can't use the setup 3407 * DMA address. 3408 */ 3409 if (!urb->setup_packet) 3410 return -EINVAL; 3411 3412 /* 1 TRB for setup, 1 for status */ 3413 num_trbs = 2; 3414 /* 3415 * Don't need to check if we need additional event data and normal TRBs, 3416 * since data in control transfers will never get bigger than 16MB 3417 * XXX: can we get a buffer that crosses 64KB boundaries? 3418 */ 3419 if (urb->transfer_buffer_length > 0) 3420 num_trbs++; 3421 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3422 ep_index, urb->stream_id, 3423 num_trbs, urb, 0, mem_flags); 3424 if (ret < 0) 3425 return ret; 3426 3427 urb_priv = urb->hcpriv; 3428 td = urb_priv->td[0]; 3429 3430 /* 3431 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3432 * until we've finished creating all the other TRBs. The ring's cycle 3433 * state may change as we enqueue the other TRBs, so save it too. 3434 */ 3435 start_trb = &ep_ring->enqueue->generic; 3436 start_cycle = ep_ring->cycle_state; 3437 3438 /* Queue setup TRB - see section 6.4.1.2.1 */ 3439 /* FIXME better way to translate setup_packet into two u32 fields? */ 3440 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3441 field = 0; 3442 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3443 if (start_cycle == 0) 3444 field |= 0x1; 3445 3446 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ 3447 if (xhci->hci_version == 0x100) { 3448 if (urb->transfer_buffer_length > 0) { 3449 if (setup->bRequestType & USB_DIR_IN) 3450 field |= TRB_TX_TYPE(TRB_DATA_IN); 3451 else 3452 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3453 } 3454 } 3455 3456 queue_trb(xhci, ep_ring, true, 3457 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3458 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3459 TRB_LEN(8) | TRB_INTR_TARGET(0), 3460 /* Immediate data in pointer */ 3461 field); 3462 3463 /* If there's data, queue data TRBs */ 3464 /* Only set interrupt on short packet for IN endpoints */ 3465 if (usb_urb_dir_in(urb)) 3466 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3467 else 3468 field = TRB_TYPE(TRB_DATA); 3469 3470 length_field = TRB_LEN(urb->transfer_buffer_length) | 3471 xhci_td_remainder(urb->transfer_buffer_length) | 3472 TRB_INTR_TARGET(0); 3473 if (urb->transfer_buffer_length > 0) { 3474 if (setup->bRequestType & USB_DIR_IN) 3475 field |= TRB_DIR_IN; 3476 queue_trb(xhci, ep_ring, true, 3477 lower_32_bits(urb->transfer_dma), 3478 upper_32_bits(urb->transfer_dma), 3479 length_field, 3480 field | ep_ring->cycle_state); 3481 } 3482 3483 /* Save the DMA address of the last TRB in the TD */ 3484 td->last_trb = ep_ring->enqueue; 3485 3486 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3487 /* If the device sent data, the status stage is an OUT transfer */ 3488 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3489 field = 0; 3490 else 3491 field = TRB_DIR_IN; 3492 queue_trb(xhci, ep_ring, false, 3493 0, 3494 0, 3495 TRB_INTR_TARGET(0), 3496 /* Event on completion */ 3497 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3498 3499 giveback_first_trb(xhci, slot_id, ep_index, 0, 3500 start_cycle, start_trb); 3501 return 0; 3502 } 3503 3504 static int count_isoc_trbs_needed(struct xhci_hcd *xhci, 3505 struct urb *urb, int i) 3506 { 3507 int num_trbs = 0; 3508 u64 addr, td_len; 3509 3510 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3511 td_len = urb->iso_frame_desc[i].length; 3512 3513 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 3514 TRB_MAX_BUFF_SIZE); 3515 if (num_trbs == 0) 3516 num_trbs++; 3517 3518 return num_trbs; 3519 } 3520 3521 /* 3522 * The transfer burst count field of the isochronous TRB defines the number of 3523 * bursts that are required to move all packets in this TD. Only SuperSpeed 3524 * devices can burst up to bMaxBurst number of packets per service interval. 3525 * This field is zero based, meaning a value of zero in the field means one 3526 * burst. Basically, for everything but SuperSpeed devices, this field will be 3527 * zero. Only xHCI 1.0 host controllers support this field. 3528 */ 3529 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3530 struct usb_device *udev, 3531 struct urb *urb, unsigned int total_packet_count) 3532 { 3533 unsigned int max_burst; 3534 3535 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) 3536 return 0; 3537 3538 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3539 return roundup(total_packet_count, max_burst + 1) - 1; 3540 } 3541 3542 /* 3543 * Returns the number of packets in the last "burst" of packets. This field is 3544 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3545 * the last burst packet count is equal to the total number of packets in the 3546 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3547 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3548 * contain 1 to (bMaxBurst + 1) packets. 3549 */ 3550 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3551 struct usb_device *udev, 3552 struct urb *urb, unsigned int total_packet_count) 3553 { 3554 unsigned int max_burst; 3555 unsigned int residue; 3556 3557 if (xhci->hci_version < 0x100) 3558 return 0; 3559 3560 switch (udev->speed) { 3561 case USB_SPEED_SUPER: 3562 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3563 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3564 residue = total_packet_count % (max_burst + 1); 3565 /* If residue is zero, the last burst contains (max_burst + 1) 3566 * number of packets, but the TLBPC field is zero-based. 3567 */ 3568 if (residue == 0) 3569 return max_burst; 3570 return residue - 1; 3571 default: 3572 if (total_packet_count == 0) 3573 return 0; 3574 return total_packet_count - 1; 3575 } 3576 } 3577 3578 /* This is for isoc transfer */ 3579 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3580 struct urb *urb, int slot_id, unsigned int ep_index) 3581 { 3582 struct xhci_ring *ep_ring; 3583 struct urb_priv *urb_priv; 3584 struct xhci_td *td; 3585 int num_tds, trbs_per_td; 3586 struct xhci_generic_trb *start_trb; 3587 bool first_trb; 3588 int start_cycle; 3589 u32 field, length_field; 3590 int running_total, trb_buff_len, td_len, td_remain_len, ret; 3591 u64 start_addr, addr; 3592 int i, j; 3593 bool more_trbs_coming; 3594 3595 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 3596 3597 num_tds = urb->number_of_packets; 3598 if (num_tds < 1) { 3599 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 3600 return -EINVAL; 3601 } 3602 3603 start_addr = (u64) urb->transfer_dma; 3604 start_trb = &ep_ring->enqueue->generic; 3605 start_cycle = ep_ring->cycle_state; 3606 3607 urb_priv = urb->hcpriv; 3608 /* Queue the first TRB, even if it's zero-length */ 3609 for (i = 0; i < num_tds; i++) { 3610 unsigned int total_packet_count; 3611 unsigned int burst_count; 3612 unsigned int residue; 3613 3614 first_trb = true; 3615 running_total = 0; 3616 addr = start_addr + urb->iso_frame_desc[i].offset; 3617 td_len = urb->iso_frame_desc[i].length; 3618 td_remain_len = td_len; 3619 total_packet_count = roundup(td_len, 3620 usb_endpoint_maxp(&urb->ep->desc)); 3621 /* A zero-length transfer still involves at least one packet. */ 3622 if (total_packet_count == 0) 3623 total_packet_count++; 3624 burst_count = xhci_get_burst_count(xhci, urb->dev, urb, 3625 total_packet_count); 3626 residue = xhci_get_last_burst_packet_count(xhci, 3627 urb->dev, urb, total_packet_count); 3628 3629 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); 3630 3631 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 3632 urb->stream_id, trbs_per_td, urb, i, mem_flags); 3633 if (ret < 0) { 3634 if (i == 0) 3635 return ret; 3636 goto cleanup; 3637 } 3638 3639 td = urb_priv->td[i]; 3640 for (j = 0; j < trbs_per_td; j++) { 3641 u32 remainder = 0; 3642 field = TRB_TBC(burst_count) | TRB_TLBPC(residue); 3643 3644 if (first_trb) { 3645 /* Queue the isoc TRB */ 3646 field |= TRB_TYPE(TRB_ISOC); 3647 /* Assume URB_ISO_ASAP is set */ 3648 field |= TRB_SIA; 3649 if (i == 0) { 3650 if (start_cycle == 0) 3651 field |= 0x1; 3652 } else 3653 field |= ep_ring->cycle_state; 3654 first_trb = false; 3655 } else { 3656 /* Queue other normal TRBs */ 3657 field |= TRB_TYPE(TRB_NORMAL); 3658 field |= ep_ring->cycle_state; 3659 } 3660 3661 /* Only set interrupt on short packet for IN EPs */ 3662 if (usb_urb_dir_in(urb)) 3663 field |= TRB_ISP; 3664 3665 /* Chain all the TRBs together; clear the chain bit in 3666 * the last TRB to indicate it's the last TRB in the 3667 * chain. 3668 */ 3669 if (j < trbs_per_td - 1) { 3670 field |= TRB_CHAIN; 3671 more_trbs_coming = true; 3672 } else { 3673 td->last_trb = ep_ring->enqueue; 3674 field |= TRB_IOC; 3675 if (xhci->hci_version == 0x100 && 3676 !(xhci->quirks & 3677 XHCI_AVOID_BEI)) { 3678 /* Set BEI bit except for the last td */ 3679 if (i < num_tds - 1) 3680 field |= TRB_BEI; 3681 } 3682 more_trbs_coming = false; 3683 } 3684 3685 /* Calculate TRB length */ 3686 trb_buff_len = TRB_MAX_BUFF_SIZE - 3687 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); 3688 if (trb_buff_len > td_remain_len) 3689 trb_buff_len = td_remain_len; 3690 3691 /* Set the TRB length, TD size, & interrupter fields. */ 3692 if (xhci->hci_version < 0x100) { 3693 remainder = xhci_td_remainder( 3694 td_len - running_total); 3695 } else { 3696 remainder = xhci_v1_0_td_remainder( 3697 running_total, trb_buff_len, 3698 total_packet_count, urb); 3699 } 3700 length_field = TRB_LEN(trb_buff_len) | 3701 remainder | 3702 TRB_INTR_TARGET(0); 3703 3704 queue_trb(xhci, ep_ring, more_trbs_coming, 3705 lower_32_bits(addr), 3706 upper_32_bits(addr), 3707 length_field, 3708 field); 3709 running_total += trb_buff_len; 3710 3711 addr += trb_buff_len; 3712 td_remain_len -= trb_buff_len; 3713 } 3714 3715 /* Check TD length */ 3716 if (running_total != td_len) { 3717 xhci_err(xhci, "ISOC TD length unmatch\n"); 3718 ret = -EINVAL; 3719 goto cleanup; 3720 } 3721 } 3722 3723 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 3724 if (xhci->quirks & XHCI_AMD_PLL_FIX) 3725 usb_amd_quirk_pll_disable(); 3726 } 3727 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 3728 3729 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3730 start_cycle, start_trb); 3731 return 0; 3732 cleanup: 3733 /* Clean up a partially enqueued isoc transfer. */ 3734 3735 for (i--; i >= 0; i--) 3736 list_del_init(&urb_priv->td[i]->td_list); 3737 3738 /* Use the first TD as a temporary variable to turn the TDs we've queued 3739 * into No-ops with a software-owned cycle bit. That way the hardware 3740 * won't accidentally start executing bogus TDs when we partially 3741 * overwrite them. td->first_trb and td->start_seg are already set. 3742 */ 3743 urb_priv->td[0]->last_trb = ep_ring->enqueue; 3744 /* Every TRB except the first & last will have its cycle bit flipped. */ 3745 td_to_noop(xhci, ep_ring, urb_priv->td[0], true); 3746 3747 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 3748 ep_ring->enqueue = urb_priv->td[0]->first_trb; 3749 ep_ring->enq_seg = urb_priv->td[0]->start_seg; 3750 ep_ring->cycle_state = start_cycle; 3751 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; 3752 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 3753 return ret; 3754 } 3755 3756 /* 3757 * Check transfer ring to guarantee there is enough room for the urb. 3758 * Update ISO URB start_frame and interval. 3759 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to 3760 * update the urb->start_frame by now. 3761 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. 3762 */ 3763 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 3764 struct urb *urb, int slot_id, unsigned int ep_index) 3765 { 3766 struct xhci_virt_device *xdev; 3767 struct xhci_ring *ep_ring; 3768 struct xhci_ep_ctx *ep_ctx; 3769 int start_frame; 3770 int xhci_interval; 3771 int ep_interval; 3772 int num_tds, num_trbs, i; 3773 int ret; 3774 3775 xdev = xhci->devs[slot_id]; 3776 ep_ring = xdev->eps[ep_index].ring; 3777 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3778 3779 num_trbs = 0; 3780 num_tds = urb->number_of_packets; 3781 for (i = 0; i < num_tds; i++) 3782 num_trbs += count_isoc_trbs_needed(xhci, urb, i); 3783 3784 /* Check the ring to guarantee there is enough room for the whole urb. 3785 * Do not insert any td of the urb to the ring if the check failed. 3786 */ 3787 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, 3788 num_trbs, mem_flags); 3789 if (ret) 3790 return ret; 3791 3792 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); 3793 start_frame &= 0x3fff; 3794 3795 urb->start_frame = start_frame; 3796 if (urb->dev->speed == USB_SPEED_LOW || 3797 urb->dev->speed == USB_SPEED_FULL) 3798 urb->start_frame >>= 3; 3799 3800 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3801 ep_interval = urb->interval; 3802 /* Convert to microframes */ 3803 if (urb->dev->speed == USB_SPEED_LOW || 3804 urb->dev->speed == USB_SPEED_FULL) 3805 ep_interval *= 8; 3806 /* FIXME change this to a warning and a suggestion to use the new API 3807 * to set the polling interval (once the API is added). 3808 */ 3809 if (xhci_interval != ep_interval) { 3810 if (printk_ratelimit()) 3811 dev_dbg(&urb->dev->dev, "Driver uses different interval" 3812 " (%d microframe%s) than xHCI " 3813 "(%d microframe%s)\n", 3814 ep_interval, 3815 ep_interval == 1 ? "" : "s", 3816 xhci_interval, 3817 xhci_interval == 1 ? "" : "s"); 3818 urb->interval = xhci_interval; 3819 /* Convert back to frames for LS/FS devices */ 3820 if (urb->dev->speed == USB_SPEED_LOW || 3821 urb->dev->speed == USB_SPEED_FULL) 3822 urb->interval /= 8; 3823 } 3824 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; 3825 3826 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 3827 } 3828 3829 /**** Command Ring Operations ****/ 3830 3831 /* Generic function for queueing a command TRB on the command ring. 3832 * Check to make sure there's room on the command ring for one command TRB. 3833 * Also check that there's room reserved for commands that must not fail. 3834 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 3835 * then only check for the number of reserved spots. 3836 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 3837 * because the command event handler may want to resubmit a failed command. 3838 */ 3839 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, 3840 u32 field3, u32 field4, bool command_must_succeed) 3841 { 3842 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 3843 int ret; 3844 3845 if (!command_must_succeed) 3846 reserved_trbs++; 3847 3848 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 3849 reserved_trbs, GFP_ATOMIC); 3850 if (ret < 0) { 3851 xhci_err(xhci, "ERR: No room for command on command ring\n"); 3852 if (command_must_succeed) 3853 xhci_err(xhci, "ERR: Reserved TRB counting for " 3854 "unfailable commands failed.\n"); 3855 return ret; 3856 } 3857 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 3858 field4 | xhci->cmd_ring->cycle_state); 3859 return 0; 3860 } 3861 3862 /* Queue a slot enable or disable request on the command ring */ 3863 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) 3864 { 3865 return queue_command(xhci, 0, 0, 0, 3866 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 3867 } 3868 3869 /* Queue an address device command TRB */ 3870 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3871 u32 slot_id) 3872 { 3873 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3874 upper_32_bits(in_ctx_ptr), 0, 3875 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), 3876 false); 3877 } 3878 3879 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 3880 u32 field1, u32 field2, u32 field3, u32 field4) 3881 { 3882 return queue_command(xhci, field1, field2, field3, field4, false); 3883 } 3884 3885 /* Queue a reset device command TRB */ 3886 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) 3887 { 3888 return queue_command(xhci, 0, 0, 0, 3889 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 3890 false); 3891 } 3892 3893 /* Queue a configure endpoint command TRB */ 3894 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3895 u32 slot_id, bool command_must_succeed) 3896 { 3897 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3898 upper_32_bits(in_ctx_ptr), 0, 3899 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 3900 command_must_succeed); 3901 } 3902 3903 /* Queue an evaluate context command TRB */ 3904 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 3905 u32 slot_id, bool command_must_succeed) 3906 { 3907 return queue_command(xhci, lower_32_bits(in_ctx_ptr), 3908 upper_32_bits(in_ctx_ptr), 0, 3909 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 3910 command_must_succeed); 3911 } 3912 3913 /* 3914 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 3915 * activity on an endpoint that is about to be suspended. 3916 */ 3917 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 3918 unsigned int ep_index, int suspend) 3919 { 3920 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3921 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3922 u32 type = TRB_TYPE(TRB_STOP_RING); 3923 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 3924 3925 return queue_command(xhci, 0, 0, 0, 3926 trb_slot_id | trb_ep_index | type | trb_suspend, false); 3927 } 3928 3929 /* Set Transfer Ring Dequeue Pointer command. 3930 * This should not be used for endpoints that have streams enabled. 3931 */ 3932 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, 3933 unsigned int ep_index, unsigned int stream_id, 3934 struct xhci_segment *deq_seg, 3935 union xhci_trb *deq_ptr, u32 cycle_state) 3936 { 3937 dma_addr_t addr; 3938 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3939 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3940 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); 3941 u32 type = TRB_TYPE(TRB_SET_DEQ); 3942 struct xhci_virt_ep *ep; 3943 3944 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); 3945 if (addr == 0) { 3946 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 3947 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", 3948 deq_seg, deq_ptr); 3949 return 0; 3950 } 3951 ep = &xhci->devs[slot_id]->eps[ep_index]; 3952 if ((ep->ep_state & SET_DEQ_PENDING)) { 3953 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 3954 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); 3955 return 0; 3956 } 3957 ep->queued_deq_seg = deq_seg; 3958 ep->queued_deq_ptr = deq_ptr; 3959 return queue_command(xhci, lower_32_bits(addr) | cycle_state, 3960 upper_32_bits(addr), trb_stream_id, 3961 trb_slot_id | trb_ep_index | type, false); 3962 } 3963 3964 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 3965 unsigned int ep_index) 3966 { 3967 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 3968 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3969 u32 type = TRB_TYPE(TRB_RESET_EP); 3970 3971 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, 3972 false); 3973 } 3974