1 /* 2 * xHCI host controller driver for R-Car SoCs 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 */ 10 11 #include <linux/firmware.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/usb/phy.h> 16 17 #include "xhci.h" 18 #include "xhci-plat.h" 19 #include "xhci-rcar.h" 20 21 /* 22 * - The V3 firmware is for r8a7796 (with good performance). 23 * - The V2 firmware can be used on both r8a7795 (es1.x) and r8a7796. 24 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes 25 * performance degradation. So, this driver continues to use the V1 if R-Car 26 * Gen2. 27 * - The V1 firmware is impossible to use on R-Car Gen3. 28 */ 29 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1); 30 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2); 31 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3); 32 33 /*** Register Offset ***/ 34 #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */ 35 #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */ 36 #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */ 37 38 #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */ 39 #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */ 40 #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */ 41 #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */ 42 #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */ 43 #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */ 44 45 /*** Register Settings ***/ 46 /* Interrupt Enable */ 47 #define RCAR_USB3_INT_XHC_ENA 0x00000001 48 #define RCAR_USB3_INT_PME_ENA 0x00000002 49 #define RCAR_USB3_INT_HSE_ENA 0x00000004 50 #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \ 51 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA) 52 53 /* FW Download Control & Status */ 54 #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001 55 #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010 56 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100 57 58 /* LCLK Select */ 59 #define RCAR_USB3_LCLK_ENA_VAL 0x01030001 60 61 /* USB3.0 Configuration */ 62 #define RCAR_USB3_CONF1_VAL 0x00030204 63 #define RCAR_USB3_CONF2_VAL 0x00030300 64 #define RCAR_USB3_CONF3_VAL 0x13802007 65 66 /* USB3.0 Polarity */ 67 #define RCAR_USB3_RX_POL_VAL BIT(21) 68 #define RCAR_USB3_TX_POL_VAL BIT(4) 69 70 static void xhci_rcar_start_gen2(struct usb_hcd *hcd) 71 { 72 /* LCLK Select */ 73 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK); 74 /* USB3.0 Configuration */ 75 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1); 76 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2); 77 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3); 78 /* USB3.0 Polarity */ 79 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL); 80 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL); 81 } 82 83 static int xhci_rcar_is_gen2(struct device *dev) 84 { 85 struct device_node *node = dev->of_node; 86 87 return of_device_is_compatible(node, "renesas,xhci-r8a7790") || 88 of_device_is_compatible(node, "renesas,xhci-r8a7791") || 89 of_device_is_compatible(node, "renesas,xhci-r8a7793") || 90 of_device_is_compatible(node, "renensas,rcar-gen2-xhci"); 91 } 92 93 static int xhci_rcar_is_gen3(struct device *dev) 94 { 95 struct device_node *node = dev->of_node; 96 97 return of_device_is_compatible(node, "renesas,xhci-r8a7795") || 98 of_device_is_compatible(node, "renesas,xhci-r8a7796") || 99 of_device_is_compatible(node, "renesas,rcar-gen3-xhci"); 100 } 101 102 void xhci_rcar_start(struct usb_hcd *hcd) 103 { 104 u32 temp; 105 106 if (hcd->regs != NULL) { 107 /* Interrupt Enable */ 108 temp = readl(hcd->regs + RCAR_USB3_INT_ENA); 109 temp |= RCAR_USB3_INT_ENA_VAL; 110 writel(temp, hcd->regs + RCAR_USB3_INT_ENA); 111 if (xhci_rcar_is_gen2(hcd->self.controller)) 112 xhci_rcar_start_gen2(hcd); 113 } 114 } 115 116 static int xhci_rcar_download_firmware(struct usb_hcd *hcd) 117 { 118 struct device *dev = hcd->self.controller; 119 void __iomem *regs = hcd->regs; 120 struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); 121 const struct firmware *fw; 122 int retval, index, j, time; 123 int timeout = 10000; 124 u32 data, val, temp; 125 126 /* request R-Car USB3.0 firmware */ 127 retval = request_firmware(&fw, priv->firmware_name, dev); 128 if (retval) 129 return retval; 130 131 /* download R-Car USB3.0 firmware */ 132 temp = readl(regs + RCAR_USB3_DL_CTRL); 133 temp |= RCAR_USB3_DL_CTRL_ENABLE; 134 writel(temp, regs + RCAR_USB3_DL_CTRL); 135 136 for (index = 0; index < fw->size; index += 4) { 137 /* to avoid reading beyond the end of the buffer */ 138 for (data = 0, j = 3; j >= 0; j--) { 139 if ((j + index) < fw->size) 140 data |= fw->data[index + j] << (8 * j); 141 } 142 writel(data, regs + RCAR_USB3_FW_DATA0); 143 temp = readl(regs + RCAR_USB3_DL_CTRL); 144 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0; 145 writel(temp, regs + RCAR_USB3_DL_CTRL); 146 147 for (time = 0; time < timeout; time++) { 148 val = readl(regs + RCAR_USB3_DL_CTRL); 149 if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0) 150 break; 151 udelay(1); 152 } 153 if (time == timeout) { 154 retval = -ETIMEDOUT; 155 break; 156 } 157 } 158 159 temp = readl(regs + RCAR_USB3_DL_CTRL); 160 temp &= ~RCAR_USB3_DL_CTRL_ENABLE; 161 writel(temp, regs + RCAR_USB3_DL_CTRL); 162 163 for (time = 0; time < timeout; time++) { 164 val = readl(regs + RCAR_USB3_DL_CTRL); 165 if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) { 166 retval = 0; 167 break; 168 } 169 udelay(1); 170 } 171 if (time == timeout) 172 retval = -ETIMEDOUT; 173 174 release_firmware(fw); 175 176 return retval; 177 } 178 179 /* This function needs to initialize a "phy" of usb before */ 180 int xhci_rcar_init_quirk(struct usb_hcd *hcd) 181 { 182 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 183 184 /* If hcd->regs is NULL, we don't just call the following function */ 185 if (!hcd->regs) 186 return 0; 187 188 /* 189 * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set 190 * to 1. However, these SoCs don't support 64-bit address memory 191 * pointers. So, this driver clears the AC64 bit of xhci->hcc_params 192 * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in 193 * xhci_gen_setup(). 194 */ 195 if (xhci_rcar_is_gen2(hcd->self.controller) || 196 xhci_rcar_is_gen3(hcd->self.controller)) 197 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 198 199 return xhci_rcar_download_firmware(hcd); 200 } 201 202 int xhci_rcar_resume_quirk(struct usb_hcd *hcd) 203 { 204 int ret; 205 206 ret = xhci_rcar_download_firmware(hcd); 207 if (!ret) 208 xhci_rcar_start(hcd); 209 210 return ret; 211 } 212