1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 53 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed 54 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 55 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 56 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 57 58 /* Thunderbolt */ 59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 60 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 61 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 62 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 63 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 64 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 65 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 66 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 67 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 68 69 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 72 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 73 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 74 75 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 76 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 77 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 78 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 79 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 80 81 static const char hcd_name[] = "xhci_hcd"; 82 83 static struct hc_driver __read_mostly xhci_pci_hc_driver; 84 85 static int xhci_pci_setup(struct usb_hcd *hcd); 86 static int xhci_pci_run(struct usb_hcd *hcd); 87 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 88 struct usb_tt *tt, gfp_t mem_flags); 89 90 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 91 .reset = xhci_pci_setup, 92 .start = xhci_pci_run, 93 .update_hub_device = xhci_pci_update_hub_device, 94 }; 95 96 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 97 { 98 struct usb_hcd *hcd = xhci_to_hcd(xhci); 99 100 if (hcd->msix_enabled) { 101 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 102 103 /* for now, the driver only supports one primary interrupter */ 104 synchronize_irq(pci_irq_vector(pdev, 0)); 105 } 106 } 107 108 /* Free any IRQs and disable MSI-X */ 109 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 110 { 111 struct usb_hcd *hcd = xhci_to_hcd(xhci); 112 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 113 114 /* return if using legacy interrupt */ 115 if (hcd->irq > 0) 116 return; 117 118 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 119 pci_free_irq_vectors(pdev); 120 hcd->msix_enabled = 0; 121 } 122 123 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 124 static int xhci_try_enable_msi(struct usb_hcd *hcd) 125 { 126 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 127 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 128 int ret; 129 130 /* 131 * Some Fresco Logic host controllers advertise MSI, but fail to 132 * generate interrupts. Don't even try to enable MSI. 133 */ 134 if (xhci->quirks & XHCI_BROKEN_MSI) 135 goto legacy_irq; 136 137 /* unregister the legacy interrupt */ 138 if (hcd->irq) 139 free_irq(hcd->irq, hcd); 140 hcd->irq = 0; 141 142 /* 143 * calculate number of MSI-X vectors supported. 144 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 145 * with max number of interrupters based on the xhci HCSPARAMS1. 146 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 147 * Add additional 1 vector to ensure always available interrupt. 148 */ 149 xhci->nvecs = min(num_online_cpus() + 1, 150 HCS_MAX_INTRS(xhci->hcs_params1)); 151 152 /* TODO: Check with MSI Soc for sysdev */ 153 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 154 PCI_IRQ_MSIX | PCI_IRQ_MSI); 155 if (xhci->nvecs < 0) { 156 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 157 "failed to allocate IRQ vectors"); 158 goto legacy_irq; 159 } 160 161 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 162 xhci_to_hcd(xhci)); 163 if (ret) 164 goto free_irq_vectors; 165 166 hcd->msi_enabled = 1; 167 hcd->msix_enabled = pdev->msix_enabled; 168 return 0; 169 170 free_irq_vectors: 171 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 172 pdev->msix_enabled ? "MSI-X" : "MSI"); 173 pci_free_irq_vectors(pdev); 174 175 legacy_irq: 176 if (!pdev->irq) { 177 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 178 return -EINVAL; 179 } 180 181 if (!strlen(hcd->irq_descr)) 182 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 183 hcd->driver->description, hcd->self.busnum); 184 185 /* fall back to legacy interrupt */ 186 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 187 if (ret) { 188 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 189 return ret; 190 } 191 hcd->irq = pdev->irq; 192 return 0; 193 } 194 195 static int xhci_pci_run(struct usb_hcd *hcd) 196 { 197 int ret; 198 199 if (usb_hcd_is_primary_hcd(hcd)) { 200 ret = xhci_try_enable_msi(hcd); 201 if (ret) 202 return ret; 203 } 204 205 return xhci_run(hcd); 206 } 207 208 static void xhci_pci_stop(struct usb_hcd *hcd) 209 { 210 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 211 212 xhci_stop(hcd); 213 214 if (usb_hcd_is_primary_hcd(hcd)) 215 xhci_cleanup_msix(xhci); 216 } 217 218 /* called after powerup, by probe or system-pm "wakeup" */ 219 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 220 { 221 /* 222 * TODO: Implement finding debug ports later. 223 * TODO: see if there are any quirks that need to be added to handle 224 * new extended capabilities. 225 */ 226 227 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 228 if (!pci_set_mwi(pdev)) 229 xhci_dbg(xhci, "MWI active\n"); 230 231 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 232 return 0; 233 } 234 235 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 236 { 237 struct pci_dev *pdev = to_pci_dev(dev); 238 239 /* Look for vendor-specific quirks */ 240 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 241 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 242 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 243 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 244 pdev->revision == 0x0) { 245 xhci->quirks |= XHCI_RESET_EP_QUIRK; 246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 247 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 248 } 249 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 250 pdev->revision == 0x4) { 251 xhci->quirks |= XHCI_SLOW_SUSPEND; 252 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 253 "QUIRK: Fresco Logic xHC revision %u" 254 "must be suspended extra slowly", 255 pdev->revision); 256 } 257 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 258 xhci->quirks |= XHCI_BROKEN_STREAMS; 259 /* Fresco Logic confirms: all revisions of this chip do not 260 * support MSI, even though some of them claim to in their PCI 261 * capabilities. 262 */ 263 xhci->quirks |= XHCI_BROKEN_MSI; 264 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 265 "QUIRK: Fresco Logic revision %u " 266 "has broken MSI implementation", 267 pdev->revision); 268 } 269 270 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 271 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 272 xhci->quirks |= XHCI_BROKEN_STREAMS; 273 274 if (pdev->vendor == PCI_VENDOR_ID_NEC) 275 xhci->quirks |= XHCI_NEC_HOST; 276 277 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 278 xhci->quirks |= XHCI_AMD_0x96_HOST; 279 280 /* AMD PLL quirk */ 281 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 282 xhci->quirks |= XHCI_AMD_PLL_FIX; 283 284 if (pdev->vendor == PCI_VENDOR_ID_AMD && 285 (pdev->device == 0x145c || 286 pdev->device == 0x15e0 || 287 pdev->device == 0x15e1 || 288 pdev->device == 0x43bb)) 289 xhci->quirks |= XHCI_SUSPEND_DELAY; 290 291 if (pdev->vendor == PCI_VENDOR_ID_AMD && 292 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 293 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 294 295 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 296 xhci->quirks |= XHCI_DISABLE_SPARSE; 297 xhci->quirks |= XHCI_RESET_ON_RESUME; 298 } 299 300 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 301 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 302 303 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 304 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 305 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 306 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 307 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 308 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 309 310 if (pdev->vendor == PCI_VENDOR_ID_AMD && 311 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 312 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 313 314 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 315 xhci->quirks |= XHCI_LPM_SUPPORT; 316 xhci->quirks |= XHCI_INTEL_HOST; 317 xhci->quirks |= XHCI_AVOID_BEI; 318 } 319 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 320 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 321 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 322 xhci->limit_active_eps = 64; 323 xhci->quirks |= XHCI_SW_BW_CHECKING; 324 /* 325 * PPT desktop boards DH77EB and DH77DF will power back on after 326 * a few seconds of being shutdown. The fix for this is to 327 * switch the ports from xHCI to EHCI on shutdown. We can't use 328 * DMI information to find those particular boards (since each 329 * vendor will change the board name), so we have to key off all 330 * PPT chipsets. 331 */ 332 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 333 } 334 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 335 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 336 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 337 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 338 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 339 } 340 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 341 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 342 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 343 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 344 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 345 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 346 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 347 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 348 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 349 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 350 } 351 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 352 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 353 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 354 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 355 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 356 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 357 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 358 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 359 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 360 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 361 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 362 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 363 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 364 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 365 xhci->quirks |= XHCI_MISSING_CAS; 366 367 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 368 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || 369 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 370 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 371 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 372 373 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 374 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 375 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 376 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 377 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 378 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 379 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 380 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 381 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 382 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 383 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 384 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 385 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 386 387 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 388 pdev->device == PCI_DEVICE_ID_EJ168) { 389 xhci->quirks |= XHCI_RESET_ON_RESUME; 390 xhci->quirks |= XHCI_BROKEN_STREAMS; 391 } 392 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 393 pdev->device == PCI_DEVICE_ID_EJ188) { 394 xhci->quirks |= XHCI_RESET_ON_RESUME; 395 xhci->quirks |= XHCI_BROKEN_STREAMS; 396 } 397 398 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 399 pdev->device == 0x0014) { 400 xhci->quirks |= XHCI_ZERO_64B_REGS; 401 } 402 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 403 pdev->device == 0x0015) { 404 xhci->quirks |= XHCI_RESET_ON_RESUME; 405 xhci->quirks |= XHCI_ZERO_64B_REGS; 406 } 407 if (pdev->vendor == PCI_VENDOR_ID_VIA) 408 xhci->quirks |= XHCI_RESET_ON_RESUME; 409 410 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 411 if (pdev->vendor == PCI_VENDOR_ID_VIA && 412 pdev->device == 0x3432) 413 xhci->quirks |= XHCI_BROKEN_STREAMS; 414 415 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 416 xhci->quirks |= XHCI_LPM_SUPPORT; 417 418 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 419 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 420 /* 421 * try to tame the ASMedia 1042 controller which reports 0.96 422 * but appears to behave more like 1.0 423 */ 424 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 425 xhci->quirks |= XHCI_BROKEN_STREAMS; 426 } 427 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 428 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 429 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 430 } 431 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 432 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 433 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 434 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 435 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 436 437 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 438 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 439 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 440 441 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 442 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 443 444 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 445 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 446 pdev->device == 0x9026) 447 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 448 449 if (pdev->vendor == PCI_VENDOR_ID_AMD && 450 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 451 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 452 xhci->quirks |= XHCI_NO_SOFT_RETRY; 453 454 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 455 xhci->quirks |= XHCI_ZHAOXIN_HOST; 456 xhci->quirks |= XHCI_LPM_SUPPORT; 457 458 if (pdev->device == 0x9202) { 459 xhci->quirks |= XHCI_RESET_ON_RESUME; 460 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 461 } 462 463 if (pdev->device == 0x9203) 464 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 465 } 466 467 /* xHC spec requires PCI devices to support D3hot and D3cold */ 468 if (xhci->hci_version >= 0x120) 469 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 470 471 if (xhci->quirks & XHCI_RESET_ON_RESUME) 472 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 473 "QUIRK: Resetting on resume"); 474 } 475 476 #ifdef CONFIG_ACPI 477 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 478 { 479 static const guid_t intel_dsm_guid = 480 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 481 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 482 union acpi_object *obj; 483 484 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 485 NULL); 486 ACPI_FREE(obj); 487 } 488 489 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 490 { 491 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 492 struct xhci_hub *rhub = &xhci->usb3_rhub; 493 int ret; 494 int i; 495 496 /* This is not the usb3 roothub we are looking for */ 497 if (hcd != rhub->hcd) 498 return; 499 500 if (hdev->maxchild > rhub->num_ports) { 501 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 502 return; 503 } 504 505 for (i = 0; i < hdev->maxchild; i++) { 506 ret = usb_acpi_port_lpm_incapable(hdev, i); 507 508 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 509 510 if (ret >= 0) { 511 rhub->ports[i]->lpm_incapable = ret; 512 continue; 513 } 514 } 515 } 516 517 #else 518 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 519 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 520 #endif /* CONFIG_ACPI */ 521 522 /* called during probe() after chip reset completes */ 523 static int xhci_pci_setup(struct usb_hcd *hcd) 524 { 525 struct xhci_hcd *xhci; 526 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 527 int retval; 528 529 xhci = hcd_to_xhci(hcd); 530 if (!xhci->sbrn) 531 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 532 533 /* imod_interval is the interrupt moderation value in nanoseconds. */ 534 xhci->imod_interval = 40000; 535 536 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 537 if (retval) 538 return retval; 539 540 if (!usb_hcd_is_primary_hcd(hcd)) 541 return 0; 542 543 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 544 xhci_pme_acpi_rtd3_enable(pdev); 545 546 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 547 548 /* Find any debug ports */ 549 return xhci_pci_reinit(xhci, pdev); 550 } 551 552 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 553 struct usb_tt *tt, gfp_t mem_flags) 554 { 555 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 556 if (!hdev->parent) 557 xhci_find_lpm_incapable_ports(hcd, hdev); 558 559 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 560 } 561 562 /* 563 * We need to register our own PCI probe function (instead of the USB core's 564 * function) in order to create a second roothub under xHCI. 565 */ 566 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) 567 { 568 int retval; 569 struct xhci_hcd *xhci; 570 struct usb_hcd *hcd; 571 struct reset_control *reset; 572 573 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 574 if (IS_ERR(reset)) 575 return PTR_ERR(reset); 576 reset_control_reset(reset); 577 578 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 579 pm_runtime_get_noresume(&dev->dev); 580 581 /* Register the USB 2.0 roothub. 582 * FIXME: USB core must know to register the USB 2.0 roothub first. 583 * This is sort of silly, because we could just set the HCD driver flags 584 * to say USB 2.0, but I'm not sure what the implications would be in 585 * the other parts of the HCD code. 586 */ 587 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 588 589 if (retval) 590 goto put_runtime_pm; 591 592 /* USB 2.0 roothub is stored in the PCI device now. */ 593 hcd = dev_get_drvdata(&dev->dev); 594 xhci = hcd_to_xhci(hcd); 595 xhci->reset = reset; 596 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 597 pci_name(dev), hcd); 598 if (!xhci->shared_hcd) { 599 retval = -ENOMEM; 600 goto dealloc_usb2_hcd; 601 } 602 603 retval = xhci_ext_cap_init(xhci); 604 if (retval) 605 goto put_usb3_hcd; 606 607 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 608 IRQF_SHARED); 609 if (retval) 610 goto put_usb3_hcd; 611 /* Roothub already marked as USB 3.0 speed */ 612 613 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 614 HCC_MAX_PSA(xhci->hcc_params) >= 4) 615 xhci->shared_hcd->can_do_streams = 1; 616 617 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 618 pm_runtime_put_noidle(&dev->dev); 619 620 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 621 pm_runtime_forbid(&dev->dev); 622 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 623 pm_runtime_allow(&dev->dev); 624 625 dma_set_max_seg_size(&dev->dev, UINT_MAX); 626 627 return 0; 628 629 put_usb3_hcd: 630 usb_put_hcd(xhci->shared_hcd); 631 dealloc_usb2_hcd: 632 usb_hcd_pci_remove(dev); 633 put_runtime_pm: 634 pm_runtime_put_noidle(&dev->dev); 635 return retval; 636 } 637 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, xhci); 638 639 static const struct pci_device_id pci_ids_reject[] = { 640 /* handled by xhci-pci-renesas */ 641 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, 642 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, 643 { /* end: all zeroes */ } 644 }; 645 646 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 647 { 648 if (pci_match_id(pci_ids_reject, dev)) 649 return -ENODEV; 650 651 return xhci_pci_common_probe(dev, id); 652 } 653 654 void xhci_pci_remove(struct pci_dev *dev) 655 { 656 struct xhci_hcd *xhci; 657 658 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 659 660 xhci->xhc_state |= XHCI_STATE_REMOVING; 661 662 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 663 pm_runtime_forbid(&dev->dev); 664 665 if (xhci->shared_hcd) { 666 usb_remove_hcd(xhci->shared_hcd); 667 usb_put_hcd(xhci->shared_hcd); 668 xhci->shared_hcd = NULL; 669 } 670 671 /* Workaround for spurious wakeups at shutdown with HSW */ 672 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 673 pci_set_power_state(dev, PCI_D3hot); 674 675 usb_hcd_pci_remove(dev); 676 } 677 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, xhci); 678 679 /* 680 * In some Intel xHCI controllers, in order to get D3 working, 681 * through a vendor specific SSIC CONFIG register at offset 0x883c, 682 * SSIC PORT need to be marked as "unused" before putting xHCI 683 * into D3. After D3 exit, the SSIC port need to be marked as "used". 684 * Without this change, xHCI might not enter D3 state. 685 */ 686 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 687 { 688 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 689 u32 val; 690 void __iomem *reg; 691 int i; 692 693 for (i = 0; i < SSIC_PORT_NUM; i++) { 694 reg = (void __iomem *) xhci->cap_regs + 695 SSIC_PORT_CFG2 + 696 i * SSIC_PORT_CFG2_OFFSET; 697 698 /* Notify SSIC that SSIC profile programming is not done. */ 699 val = readl(reg) & ~PROG_DONE; 700 writel(val, reg); 701 702 /* Mark SSIC port as unused(suspend) or used(resume) */ 703 val = readl(reg); 704 if (suspend) 705 val |= SSIC_PORT_UNUSED; 706 else 707 val &= ~SSIC_PORT_UNUSED; 708 writel(val, reg); 709 710 /* Notify SSIC that SSIC profile programming is done */ 711 val = readl(reg) | PROG_DONE; 712 writel(val, reg); 713 readl(reg); 714 } 715 } 716 717 /* 718 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 719 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 720 */ 721 static void xhci_pme_quirk(struct usb_hcd *hcd) 722 { 723 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 724 void __iomem *reg; 725 u32 val; 726 727 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 728 val = readl(reg); 729 writel(val | BIT(28), reg); 730 readl(reg); 731 } 732 733 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 734 { 735 u32 reg; 736 737 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 738 reg &= ~BIT(SPARSE_DISABLE_BIT); 739 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 740 } 741 742 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 743 { 744 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 745 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 746 int ret; 747 748 /* 749 * Systems with the TI redriver that loses port status change events 750 * need to have the registers polled during D3, so avoid D3cold. 751 */ 752 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 753 pci_d3cold_disable(pdev); 754 755 #ifdef CONFIG_SUSPEND 756 /* d3cold is broken, but only when s2idle is used */ 757 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 758 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 759 pci_d3cold_disable(pdev); 760 #endif 761 762 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 763 xhci_pme_quirk(hcd); 764 765 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 766 xhci_ssic_port_unused_quirk(hcd, true); 767 768 if (xhci->quirks & XHCI_DISABLE_SPARSE) 769 xhci_sparse_control_quirk(hcd); 770 771 ret = xhci_suspend(xhci, do_wakeup); 772 773 /* synchronize irq when using MSI-X */ 774 xhci_msix_sync_irqs(xhci); 775 776 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 777 xhci_ssic_port_unused_quirk(hcd, false); 778 779 return ret; 780 } 781 782 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 783 { 784 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 785 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 786 int retval = 0; 787 788 reset_control_reset(xhci->reset); 789 790 /* The BIOS on systems with the Intel Panther Point chipset may or may 791 * not support xHCI natively. That means that during system resume, it 792 * may switch the ports back to EHCI so that users can use their 793 * keyboard to select a kernel from GRUB after resume from hibernate. 794 * 795 * The BIOS is supposed to remember whether the OS had xHCI ports 796 * enabled before resume, and switch the ports back to xHCI when the 797 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 798 * writers. 799 * 800 * Unconditionally switch the ports back to xHCI after a system resume. 801 * It should not matter whether the EHCI or xHCI controller is 802 * resumed first. It's enough to do the switchover in xHCI because 803 * USB core won't notice anything as the hub driver doesn't start 804 * running again until after all the devices (including both EHCI and 805 * xHCI host controllers) have been resumed. 806 */ 807 808 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 809 usb_enable_intel_xhci_ports(pdev); 810 811 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 812 xhci_ssic_port_unused_quirk(hcd, false); 813 814 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 815 xhci_pme_quirk(hcd); 816 817 retval = xhci_resume(xhci, msg); 818 return retval; 819 } 820 821 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 822 { 823 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 824 struct xhci_port *port; 825 struct usb_device *udev; 826 u32 portsc; 827 int i; 828 829 /* 830 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 831 * cause significant boot delay if usb ports are in suspended U3 state 832 * during boot. Some USB devices survive in U3 state over S4 hibernate 833 * 834 * Disable ports that are in U3 if remote wake is not enabled for either 835 * host controller or connected device 836 */ 837 838 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 839 return 0; 840 841 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 842 port = &xhci->hw_ports[i]; 843 portsc = readl(port->addr); 844 845 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 846 continue; 847 848 if (!port->slot_id || !xhci->devs[port->slot_id]) { 849 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 850 port->slot_id, port->rhub->hcd->self.busnum, 851 port->hcd_portnum + 1); 852 continue; 853 } 854 855 udev = xhci->devs[port->slot_id]->udev; 856 857 /* if wakeup is enabled then don't disable the port */ 858 if (udev->do_remote_wakeup && do_wakeup) 859 continue; 860 861 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 862 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 863 portsc = xhci_port_state_to_neutral(portsc); 864 writel(portsc | PORT_PE, port->addr); 865 } 866 867 return 0; 868 } 869 870 static void xhci_pci_shutdown(struct usb_hcd *hcd) 871 { 872 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 873 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 874 875 xhci_shutdown(hcd); 876 xhci_cleanup_msix(xhci); 877 878 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 879 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 880 pci_set_power_state(pdev, PCI_D3hot); 881 } 882 883 /*-------------------------------------------------------------------------*/ 884 885 /* PCI driver selection metadata; PCI hotplugging uses this */ 886 static const struct pci_device_id pci_ids[] = { 887 /* handle any USB 3.0 xHCI controller */ 888 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 889 }, 890 { /* end: all zeroes */ } 891 }; 892 MODULE_DEVICE_TABLE(pci, pci_ids); 893 894 /* pci driver glue; this is a "new style" PCI driver module */ 895 static struct pci_driver xhci_pci_driver = { 896 .name = hcd_name, 897 .id_table = pci_ids, 898 899 .probe = xhci_pci_probe, 900 .remove = xhci_pci_remove, 901 /* suspend and resume implemented later */ 902 903 .shutdown = usb_hcd_pci_shutdown, 904 .driver = { 905 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 906 }, 907 }; 908 909 static int __init xhci_pci_init(void) 910 { 911 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 912 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 913 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 914 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 915 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 916 xhci_pci_hc_driver.stop = xhci_pci_stop; 917 return pci_register_driver(&xhci_pci_driver); 918 } 919 module_init(xhci_pci_init); 920 921 static void __exit xhci_pci_exit(void) 922 { 923 pci_unregister_driver(&xhci_pci_driver); 924 } 925 module_exit(xhci_pci_exit); 926 927 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 928 MODULE_LICENSE("GPL"); 929