1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/acpi.h> 27 28 #include "xhci.h" 29 #include "xhci-trace.h" 30 31 #define PORT2_SSIC_CONFIG_REG2 0x883c 32 #define PROG_DONE (1 << 30) 33 #define SSIC_PORT_UNUSED (1 << 31) 34 35 /* Device for a quirk */ 36 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 37 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 38 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 39 40 #define PCI_VENDOR_ID_ETRON 0x1b6f 41 #define PCI_DEVICE_ID_EJ168 0x7023 42 43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 45 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 48 49 static const char hcd_name[] = "xhci_hcd"; 50 51 static struct hc_driver __read_mostly xhci_pci_hc_driver; 52 53 static int xhci_pci_setup(struct usb_hcd *hcd); 54 55 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 56 .extra_priv_size = sizeof(struct xhci_hcd), 57 .reset = xhci_pci_setup, 58 }; 59 60 /* called after powerup, by probe or system-pm "wakeup" */ 61 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 62 { 63 /* 64 * TODO: Implement finding debug ports later. 65 * TODO: see if there are any quirks that need to be added to handle 66 * new extended capabilities. 67 */ 68 69 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 70 if (!pci_set_mwi(pdev)) 71 xhci_dbg(xhci, "MWI active\n"); 72 73 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 74 return 0; 75 } 76 77 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 78 { 79 struct pci_dev *pdev = to_pci_dev(dev); 80 81 /* Look for vendor-specific quirks */ 82 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 83 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 84 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 85 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 86 pdev->revision == 0x0) { 87 xhci->quirks |= XHCI_RESET_EP_QUIRK; 88 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 89 "QUIRK: Fresco Logic xHC needs configure" 90 " endpoint cmd after reset endpoint"); 91 } 92 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 93 pdev->revision == 0x4) { 94 xhci->quirks |= XHCI_SLOW_SUSPEND; 95 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 96 "QUIRK: Fresco Logic xHC revision %u" 97 "must be suspended extra slowly", 98 pdev->revision); 99 } 100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 101 xhci->quirks |= XHCI_BROKEN_STREAMS; 102 /* Fresco Logic confirms: all revisions of this chip do not 103 * support MSI, even though some of them claim to in their PCI 104 * capabilities. 105 */ 106 xhci->quirks |= XHCI_BROKEN_MSI; 107 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 108 "QUIRK: Fresco Logic revision %u " 109 "has broken MSI implementation", 110 pdev->revision); 111 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 112 } 113 114 if (pdev->vendor == PCI_VENDOR_ID_NEC) 115 xhci->quirks |= XHCI_NEC_HOST; 116 117 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 118 xhci->quirks |= XHCI_AMD_0x96_HOST; 119 120 /* AMD PLL quirk */ 121 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 122 xhci->quirks |= XHCI_AMD_PLL_FIX; 123 124 if (pdev->vendor == PCI_VENDOR_ID_AMD) 125 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 126 127 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 128 xhci->quirks |= XHCI_LPM_SUPPORT; 129 xhci->quirks |= XHCI_INTEL_HOST; 130 xhci->quirks |= XHCI_AVOID_BEI; 131 } 132 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 133 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 134 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 135 xhci->limit_active_eps = 64; 136 xhci->quirks |= XHCI_SW_BW_CHECKING; 137 /* 138 * PPT desktop boards DH77EB and DH77DF will power back on after 139 * a few seconds of being shutdown. The fix for this is to 140 * switch the ports from xHCI to EHCI on shutdown. We can't use 141 * DMI information to find those particular boards (since each 142 * vendor will change the board name), so we have to key off all 143 * PPT chipsets. 144 */ 145 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 146 } 147 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 148 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { 149 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 150 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 151 } 152 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 153 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 154 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 155 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) { 156 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 157 } 158 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 159 pdev->device == PCI_DEVICE_ID_EJ168) { 160 xhci->quirks |= XHCI_RESET_ON_RESUME; 161 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 162 xhci->quirks |= XHCI_BROKEN_STREAMS; 163 } 164 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 165 pdev->device == 0x0015) 166 xhci->quirks |= XHCI_RESET_ON_RESUME; 167 if (pdev->vendor == PCI_VENDOR_ID_VIA) 168 xhci->quirks |= XHCI_RESET_ON_RESUME; 169 170 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 171 if (pdev->vendor == PCI_VENDOR_ID_VIA && 172 pdev->device == 0x3432) 173 xhci->quirks |= XHCI_BROKEN_STREAMS; 174 175 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 176 pdev->device == 0x1042) 177 xhci->quirks |= XHCI_BROKEN_STREAMS; 178 179 if (xhci->quirks & XHCI_RESET_ON_RESUME) 180 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 181 "QUIRK: Resetting on resume"); 182 } 183 184 #ifdef CONFIG_ACPI 185 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 186 { 187 static const u8 intel_dsm_uuid[] = { 188 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 189 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23, 190 }; 191 acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL); 192 } 193 #else 194 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 195 #endif /* CONFIG_ACPI */ 196 197 /* called during probe() after chip reset completes */ 198 static int xhci_pci_setup(struct usb_hcd *hcd) 199 { 200 struct xhci_hcd *xhci; 201 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 202 int retval; 203 204 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 205 if (retval) 206 return retval; 207 208 xhci = hcd_to_xhci(hcd); 209 if (!usb_hcd_is_primary_hcd(hcd)) 210 return 0; 211 212 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 213 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 214 215 /* Find any debug ports */ 216 retval = xhci_pci_reinit(xhci, pdev); 217 if (!retval) 218 return retval; 219 220 return retval; 221 } 222 223 /* 224 * We need to register our own PCI probe function (instead of the USB core's 225 * function) in order to create a second roothub under xHCI. 226 */ 227 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 228 { 229 int retval; 230 struct xhci_hcd *xhci; 231 struct hc_driver *driver; 232 struct usb_hcd *hcd; 233 234 driver = (struct hc_driver *)id->driver_data; 235 236 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 237 pm_runtime_get_noresume(&dev->dev); 238 239 /* Register the USB 2.0 roothub. 240 * FIXME: USB core must know to register the USB 2.0 roothub first. 241 * This is sort of silly, because we could just set the HCD driver flags 242 * to say USB 2.0, but I'm not sure what the implications would be in 243 * the other parts of the HCD code. 244 */ 245 retval = usb_hcd_pci_probe(dev, id); 246 247 if (retval) 248 goto put_runtime_pm; 249 250 /* USB 2.0 roothub is stored in the PCI device now. */ 251 hcd = dev_get_drvdata(&dev->dev); 252 xhci = hcd_to_xhci(hcd); 253 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 254 pci_name(dev), hcd); 255 if (!xhci->shared_hcd) { 256 retval = -ENOMEM; 257 goto dealloc_usb2_hcd; 258 } 259 260 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 261 IRQF_SHARED); 262 if (retval) 263 goto put_usb3_hcd; 264 /* Roothub already marked as USB 3.0 speed */ 265 266 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 267 HCC_MAX_PSA(xhci->hcc_params) >= 4) 268 xhci->shared_hcd->can_do_streams = 1; 269 270 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 271 xhci_pme_acpi_rtd3_enable(dev); 272 273 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 274 pm_runtime_put_noidle(&dev->dev); 275 276 return 0; 277 278 put_usb3_hcd: 279 usb_put_hcd(xhci->shared_hcd); 280 dealloc_usb2_hcd: 281 usb_hcd_pci_remove(dev); 282 put_runtime_pm: 283 pm_runtime_put_noidle(&dev->dev); 284 return retval; 285 } 286 287 static void xhci_pci_remove(struct pci_dev *dev) 288 { 289 struct xhci_hcd *xhci; 290 291 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 292 if (xhci->shared_hcd) { 293 usb_remove_hcd(xhci->shared_hcd); 294 usb_put_hcd(xhci->shared_hcd); 295 } 296 usb_hcd_pci_remove(dev); 297 298 /* Workaround for spurious wakeups at shutdown with HSW */ 299 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 300 pci_set_power_state(dev, PCI_D3hot); 301 } 302 303 #ifdef CONFIG_PM 304 /* 305 * In some Intel xHCI controllers, in order to get D3 working, 306 * through a vendor specific SSIC CONFIG register at offset 0x883c, 307 * SSIC PORT need to be marked as "unused" before putting xHCI 308 * into D3. After D3 exit, the SSIC port need to be marked as "used". 309 * Without this change, xHCI might not enter D3 state. 310 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 311 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 312 */ 313 static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend) 314 { 315 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 316 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 317 u32 val; 318 void __iomem *reg; 319 320 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 321 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 322 323 reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2; 324 325 /* Notify SSIC that SSIC profile programming is not done */ 326 val = readl(reg) & ~PROG_DONE; 327 writel(val, reg); 328 329 /* Mark SSIC port as unused(suspend) or used(resume) */ 330 val = readl(reg); 331 if (suspend) 332 val |= SSIC_PORT_UNUSED; 333 else 334 val &= ~SSIC_PORT_UNUSED; 335 writel(val, reg); 336 337 /* Notify SSIC that SSIC profile programming is done */ 338 val = readl(reg) | PROG_DONE; 339 writel(val, reg); 340 readl(reg); 341 } 342 343 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 344 val = readl(reg); 345 writel(val | BIT(28), reg); 346 readl(reg); 347 } 348 349 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 350 { 351 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 352 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 353 354 /* 355 * Systems with the TI redriver that loses port status change events 356 * need to have the registers polled during D3, so avoid D3cold. 357 */ 358 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 359 pdev->no_d3cold = true; 360 361 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 362 xhci_pme_quirk(hcd, true); 363 364 return xhci_suspend(xhci, do_wakeup); 365 } 366 367 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 368 { 369 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 370 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 371 int retval = 0; 372 373 /* The BIOS on systems with the Intel Panther Point chipset may or may 374 * not support xHCI natively. That means that during system resume, it 375 * may switch the ports back to EHCI so that users can use their 376 * keyboard to select a kernel from GRUB after resume from hibernate. 377 * 378 * The BIOS is supposed to remember whether the OS had xHCI ports 379 * enabled before resume, and switch the ports back to xHCI when the 380 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 381 * writers. 382 * 383 * Unconditionally switch the ports back to xHCI after a system resume. 384 * It should not matter whether the EHCI or xHCI controller is 385 * resumed first. It's enough to do the switchover in xHCI because 386 * USB core won't notice anything as the hub driver doesn't start 387 * running again until after all the devices (including both EHCI and 388 * xHCI host controllers) have been resumed. 389 */ 390 391 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 392 usb_enable_intel_xhci_ports(pdev); 393 394 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 395 xhci_pme_quirk(hcd, false); 396 397 retval = xhci_resume(xhci, hibernated); 398 return retval; 399 } 400 #endif /* CONFIG_PM */ 401 402 /*-------------------------------------------------------------------------*/ 403 404 /* PCI driver selection metadata; PCI hotplugging uses this */ 405 static const struct pci_device_id pci_ids[] = { { 406 /* handle any USB 3.0 xHCI controller */ 407 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 408 .driver_data = (unsigned long) &xhci_pci_hc_driver, 409 }, 410 { /* end: all zeroes */ } 411 }; 412 MODULE_DEVICE_TABLE(pci, pci_ids); 413 414 /* pci driver glue; this is a "new style" PCI driver module */ 415 static struct pci_driver xhci_pci_driver = { 416 .name = (char *) hcd_name, 417 .id_table = pci_ids, 418 419 .probe = xhci_pci_probe, 420 .remove = xhci_pci_remove, 421 /* suspend and resume implemented later */ 422 423 .shutdown = usb_hcd_pci_shutdown, 424 #ifdef CONFIG_PM 425 .driver = { 426 .pm = &usb_hcd_pci_pm_ops 427 }, 428 #endif 429 }; 430 431 static int __init xhci_pci_init(void) 432 { 433 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 434 #ifdef CONFIG_PM 435 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 436 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 437 #endif 438 return pci_register_driver(&xhci_pci_driver); 439 } 440 module_init(xhci_pci_init); 441 442 static void __exit xhci_pci_exit(void) 443 { 444 pci_unregister_driver(&xhci_pci_driver); 445 } 446 module_exit(xhci_pci_exit); 447 448 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 449 MODULE_LICENSE("GPL"); 450