1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 51 52 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 53 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 56 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 57 58 static const char hcd_name[] = "xhci_hcd"; 59 60 static struct hc_driver __read_mostly xhci_pci_hc_driver; 61 62 static int xhci_pci_setup(struct usb_hcd *hcd); 63 64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 65 .reset = xhci_pci_setup, 66 }; 67 68 /* called after powerup, by probe or system-pm "wakeup" */ 69 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 70 { 71 /* 72 * TODO: Implement finding debug ports later. 73 * TODO: see if there are any quirks that need to be added to handle 74 * new extended capabilities. 75 */ 76 77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 78 if (!pci_set_mwi(pdev)) 79 xhci_dbg(xhci, "MWI active\n"); 80 81 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 82 return 0; 83 } 84 85 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 86 { 87 struct pci_dev *pdev = to_pci_dev(dev); 88 89 /* Look for vendor-specific quirks */ 90 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 91 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 92 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 94 pdev->revision == 0x0) { 95 xhci->quirks |= XHCI_RESET_EP_QUIRK; 96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 97 "QUIRK: Fresco Logic xHC needs configure" 98 " endpoint cmd after reset endpoint"); 99 } 100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 101 pdev->revision == 0x4) { 102 xhci->quirks |= XHCI_SLOW_SUSPEND; 103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 104 "QUIRK: Fresco Logic xHC revision %u" 105 "must be suspended extra slowly", 106 pdev->revision); 107 } 108 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 109 xhci->quirks |= XHCI_BROKEN_STREAMS; 110 /* Fresco Logic confirms: all revisions of this chip do not 111 * support MSI, even though some of them claim to in their PCI 112 * capabilities. 113 */ 114 xhci->quirks |= XHCI_BROKEN_MSI; 115 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 116 "QUIRK: Fresco Logic revision %u " 117 "has broken MSI implementation", 118 pdev->revision); 119 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 120 } 121 122 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 123 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 124 xhci->quirks |= XHCI_BROKEN_STREAMS; 125 126 if (pdev->vendor == PCI_VENDOR_ID_NEC) 127 xhci->quirks |= XHCI_NEC_HOST; 128 129 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 130 xhci->quirks |= XHCI_AMD_0x96_HOST; 131 132 /* AMD PLL quirk */ 133 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 134 xhci->quirks |= XHCI_AMD_PLL_FIX; 135 136 if (pdev->vendor == PCI_VENDOR_ID_AMD && 137 (pdev->device == 0x15e0 || 138 pdev->device == 0x15e1 || 139 pdev->device == 0x43bb)) 140 xhci->quirks |= XHCI_SUSPEND_DELAY; 141 142 if (pdev->vendor == PCI_VENDOR_ID_AMD) 143 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 144 145 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 146 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 147 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 148 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 149 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 150 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 151 152 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 153 xhci->quirks |= XHCI_LPM_SUPPORT; 154 xhci->quirks |= XHCI_INTEL_HOST; 155 xhci->quirks |= XHCI_AVOID_BEI; 156 } 157 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 158 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 159 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 160 xhci->limit_active_eps = 64; 161 xhci->quirks |= XHCI_SW_BW_CHECKING; 162 /* 163 * PPT desktop boards DH77EB and DH77DF will power back on after 164 * a few seconds of being shutdown. The fix for this is to 165 * switch the ports from xHCI to EHCI on shutdown. We can't use 166 * DMI information to find those particular boards (since each 167 * vendor will change the board name), so we have to key off all 168 * PPT chipsets. 169 */ 170 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 171 } 172 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 173 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 174 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 175 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 176 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 177 } 178 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 179 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 180 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 181 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 182 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 183 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 184 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 185 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 186 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 187 } 188 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 189 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 190 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 191 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 192 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 193 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 194 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 195 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 196 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 197 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 198 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 199 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 200 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 201 xhci->quirks |= XHCI_MISSING_CAS; 202 203 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 204 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 205 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 206 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 207 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 208 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 209 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 210 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI)) 211 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 212 213 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 214 pdev->device == PCI_DEVICE_ID_EJ168) { 215 xhci->quirks |= XHCI_RESET_ON_RESUME; 216 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 217 xhci->quirks |= XHCI_BROKEN_STREAMS; 218 } 219 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 220 pdev->device == 0x0014) { 221 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 222 xhci->quirks |= XHCI_ZERO_64B_REGS; 223 } 224 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 225 pdev->device == 0x0015) { 226 xhci->quirks |= XHCI_RESET_ON_RESUME; 227 xhci->quirks |= XHCI_ZERO_64B_REGS; 228 } 229 if (pdev->vendor == PCI_VENDOR_ID_VIA) 230 xhci->quirks |= XHCI_RESET_ON_RESUME; 231 232 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 233 if (pdev->vendor == PCI_VENDOR_ID_VIA && 234 pdev->device == 0x3432) 235 xhci->quirks |= XHCI_BROKEN_STREAMS; 236 237 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 238 pdev->device == 0x1042) 239 xhci->quirks |= XHCI_BROKEN_STREAMS; 240 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 241 pdev->device == 0x1142) 242 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 243 244 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 245 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 246 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 247 248 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 249 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 250 251 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 252 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 253 pdev->device == 0x9026) 254 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 255 256 if (xhci->quirks & XHCI_RESET_ON_RESUME) 257 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 258 "QUIRK: Resetting on resume"); 259 } 260 261 #ifdef CONFIG_ACPI 262 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 263 { 264 static const guid_t intel_dsm_guid = 265 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 266 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 267 union acpi_object *obj; 268 269 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 270 NULL); 271 ACPI_FREE(obj); 272 } 273 #else 274 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 275 #endif /* CONFIG_ACPI */ 276 277 /* called during probe() after chip reset completes */ 278 static int xhci_pci_setup(struct usb_hcd *hcd) 279 { 280 struct xhci_hcd *xhci; 281 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 282 int retval; 283 284 xhci = hcd_to_xhci(hcd); 285 if (!xhci->sbrn) 286 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 287 288 /* imod_interval is the interrupt moderation value in nanoseconds. */ 289 xhci->imod_interval = 40000; 290 291 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 292 if (retval) 293 return retval; 294 295 if (!usb_hcd_is_primary_hcd(hcd)) 296 return 0; 297 298 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 299 300 /* Find any debug ports */ 301 return xhci_pci_reinit(xhci, pdev); 302 } 303 304 /* 305 * We need to register our own PCI probe function (instead of the USB core's 306 * function) in order to create a second roothub under xHCI. 307 */ 308 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 309 { 310 int retval; 311 struct xhci_hcd *xhci; 312 struct hc_driver *driver; 313 struct usb_hcd *hcd; 314 315 driver = (struct hc_driver *)id->driver_data; 316 317 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 318 pm_runtime_get_noresume(&dev->dev); 319 320 /* Register the USB 2.0 roothub. 321 * FIXME: USB core must know to register the USB 2.0 roothub first. 322 * This is sort of silly, because we could just set the HCD driver flags 323 * to say USB 2.0, but I'm not sure what the implications would be in 324 * the other parts of the HCD code. 325 */ 326 retval = usb_hcd_pci_probe(dev, id); 327 328 if (retval) 329 goto put_runtime_pm; 330 331 /* USB 2.0 roothub is stored in the PCI device now. */ 332 hcd = dev_get_drvdata(&dev->dev); 333 xhci = hcd_to_xhci(hcd); 334 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 335 pci_name(dev), hcd); 336 if (!xhci->shared_hcd) { 337 retval = -ENOMEM; 338 goto dealloc_usb2_hcd; 339 } 340 341 retval = xhci_ext_cap_init(xhci); 342 if (retval) 343 goto put_usb3_hcd; 344 345 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 346 IRQF_SHARED); 347 if (retval) 348 goto put_usb3_hcd; 349 /* Roothub already marked as USB 3.0 speed */ 350 351 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 352 HCC_MAX_PSA(xhci->hcc_params) >= 4) 353 xhci->shared_hcd->can_do_streams = 1; 354 355 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 356 xhci_pme_acpi_rtd3_enable(dev); 357 358 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 359 pm_runtime_put_noidle(&dev->dev); 360 361 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 362 pm_runtime_allow(&dev->dev); 363 364 return 0; 365 366 put_usb3_hcd: 367 usb_put_hcd(xhci->shared_hcd); 368 dealloc_usb2_hcd: 369 usb_hcd_pci_remove(dev); 370 put_runtime_pm: 371 pm_runtime_put_noidle(&dev->dev); 372 return retval; 373 } 374 375 static void xhci_pci_remove(struct pci_dev *dev) 376 { 377 struct xhci_hcd *xhci; 378 379 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 380 xhci->xhc_state |= XHCI_STATE_REMOVING; 381 382 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 383 pm_runtime_forbid(&dev->dev); 384 385 if (xhci->shared_hcd) { 386 usb_remove_hcd(xhci->shared_hcd); 387 usb_put_hcd(xhci->shared_hcd); 388 xhci->shared_hcd = NULL; 389 } 390 391 /* Workaround for spurious wakeups at shutdown with HSW */ 392 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 393 pci_set_power_state(dev, PCI_D3hot); 394 395 usb_hcd_pci_remove(dev); 396 } 397 398 #ifdef CONFIG_PM 399 /* 400 * In some Intel xHCI controllers, in order to get D3 working, 401 * through a vendor specific SSIC CONFIG register at offset 0x883c, 402 * SSIC PORT need to be marked as "unused" before putting xHCI 403 * into D3. After D3 exit, the SSIC port need to be marked as "used". 404 * Without this change, xHCI might not enter D3 state. 405 */ 406 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 407 { 408 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 409 u32 val; 410 void __iomem *reg; 411 int i; 412 413 for (i = 0; i < SSIC_PORT_NUM; i++) { 414 reg = (void __iomem *) xhci->cap_regs + 415 SSIC_PORT_CFG2 + 416 i * SSIC_PORT_CFG2_OFFSET; 417 418 /* Notify SSIC that SSIC profile programming is not done. */ 419 val = readl(reg) & ~PROG_DONE; 420 writel(val, reg); 421 422 /* Mark SSIC port as unused(suspend) or used(resume) */ 423 val = readl(reg); 424 if (suspend) 425 val |= SSIC_PORT_UNUSED; 426 else 427 val &= ~SSIC_PORT_UNUSED; 428 writel(val, reg); 429 430 /* Notify SSIC that SSIC profile programming is done */ 431 val = readl(reg) | PROG_DONE; 432 writel(val, reg); 433 readl(reg); 434 } 435 } 436 437 /* 438 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 439 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 440 */ 441 static void xhci_pme_quirk(struct usb_hcd *hcd) 442 { 443 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 444 void __iomem *reg; 445 u32 val; 446 447 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 448 val = readl(reg); 449 writel(val | BIT(28), reg); 450 readl(reg); 451 } 452 453 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 454 { 455 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 456 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 457 int ret; 458 459 /* 460 * Systems with the TI redriver that loses port status change events 461 * need to have the registers polled during D3, so avoid D3cold. 462 */ 463 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 464 pci_d3cold_disable(pdev); 465 466 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 467 xhci_pme_quirk(hcd); 468 469 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 470 xhci_ssic_port_unused_quirk(hcd, true); 471 472 ret = xhci_suspend(xhci, do_wakeup); 473 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 474 xhci_ssic_port_unused_quirk(hcd, false); 475 476 return ret; 477 } 478 479 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 480 { 481 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 482 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 483 int retval = 0; 484 485 /* The BIOS on systems with the Intel Panther Point chipset may or may 486 * not support xHCI natively. That means that during system resume, it 487 * may switch the ports back to EHCI so that users can use their 488 * keyboard to select a kernel from GRUB after resume from hibernate. 489 * 490 * The BIOS is supposed to remember whether the OS had xHCI ports 491 * enabled before resume, and switch the ports back to xHCI when the 492 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 493 * writers. 494 * 495 * Unconditionally switch the ports back to xHCI after a system resume. 496 * It should not matter whether the EHCI or xHCI controller is 497 * resumed first. It's enough to do the switchover in xHCI because 498 * USB core won't notice anything as the hub driver doesn't start 499 * running again until after all the devices (including both EHCI and 500 * xHCI host controllers) have been resumed. 501 */ 502 503 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 504 usb_enable_intel_xhci_ports(pdev); 505 506 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 507 xhci_ssic_port_unused_quirk(hcd, false); 508 509 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 510 xhci_pme_quirk(hcd); 511 512 retval = xhci_resume(xhci, hibernated); 513 return retval; 514 } 515 #endif /* CONFIG_PM */ 516 517 /*-------------------------------------------------------------------------*/ 518 519 /* PCI driver selection metadata; PCI hotplugging uses this */ 520 static const struct pci_device_id pci_ids[] = { { 521 /* handle any USB 3.0 xHCI controller */ 522 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 523 .driver_data = (unsigned long) &xhci_pci_hc_driver, 524 }, 525 { /* end: all zeroes */ } 526 }; 527 MODULE_DEVICE_TABLE(pci, pci_ids); 528 529 /* pci driver glue; this is a "new style" PCI driver module */ 530 static struct pci_driver xhci_pci_driver = { 531 .name = (char *) hcd_name, 532 .id_table = pci_ids, 533 534 .probe = xhci_pci_probe, 535 .remove = xhci_pci_remove, 536 /* suspend and resume implemented later */ 537 538 .shutdown = usb_hcd_pci_shutdown, 539 #ifdef CONFIG_PM 540 .driver = { 541 .pm = &usb_hcd_pci_pm_ops 542 }, 543 #endif 544 }; 545 546 static int __init xhci_pci_init(void) 547 { 548 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 549 #ifdef CONFIG_PM 550 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 551 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 552 #endif 553 return pci_register_driver(&xhci_pci_driver); 554 } 555 module_init(xhci_pci_init); 556 557 static void __exit xhci_pci_exit(void) 558 { 559 pci_unregister_driver(&xhci_pci_driver); 560 } 561 module_exit(xhci_pci_exit); 562 563 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 564 MODULE_LICENSE("GPL"); 565