1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 53 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed 54 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 55 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 56 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 57 58 #define PCI_VENDOR_ID_PHYTIUM 0x1db7 59 #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27 60 61 /* Thunderbolt */ 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 64 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 65 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 66 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 67 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 68 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 69 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 70 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 71 72 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 73 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 74 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 75 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 76 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 77 78 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 79 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 80 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 81 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 82 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 83 84 #define PCI_DEVICE_ID_CADENCE 0x17CD 85 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200 86 87 static const char hcd_name[] = "xhci_hcd"; 88 89 static struct hc_driver __read_mostly xhci_pci_hc_driver; 90 91 static int xhci_pci_setup(struct usb_hcd *hcd); 92 static int xhci_pci_run(struct usb_hcd *hcd); 93 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 94 struct usb_tt *tt, gfp_t mem_flags); 95 96 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 97 .reset = xhci_pci_setup, 98 .start = xhci_pci_run, 99 .update_hub_device = xhci_pci_update_hub_device, 100 }; 101 102 /* 103 * Primary Legacy and MSI IRQ are synced in suspend_common(). 104 * All MSI-X IRQs and secondary MSI IRQs should be synced here. 105 */ 106 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 107 { 108 struct usb_hcd *hcd = xhci_to_hcd(xhci); 109 110 if (hcd->msix_enabled) { 111 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 112 113 /* for now, the driver only supports one primary interrupter */ 114 synchronize_irq(pci_irq_vector(pdev, 0)); 115 } 116 } 117 118 /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */ 119 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 120 { 121 struct usb_hcd *hcd = xhci_to_hcd(xhci); 122 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 123 124 if (hcd->irq > 0) 125 return; 126 127 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 128 pci_free_irq_vectors(pdev); 129 hcd->msix_enabled = 0; 130 } 131 132 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 133 static int xhci_try_enable_msi(struct usb_hcd *hcd) 134 { 135 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 136 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 137 int ret; 138 139 /* 140 * Some Fresco Logic host controllers advertise MSI, but fail to 141 * generate interrupts. Don't even try to enable MSI. 142 */ 143 if (xhci->quirks & XHCI_BROKEN_MSI) 144 goto legacy_irq; 145 146 /* unregister the legacy interrupt */ 147 if (hcd->irq) 148 free_irq(hcd->irq, hcd); 149 hcd->irq = 0; 150 151 /* 152 * calculate number of MSI-X vectors supported. 153 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 154 * with max number of interrupters based on the xhci HCSPARAMS1. 155 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 156 * Add additional 1 vector to ensure always available interrupt. 157 */ 158 xhci->nvecs = min(num_online_cpus() + 1, 159 HCS_MAX_INTRS(xhci->hcs_params1)); 160 161 /* TODO: Check with MSI Soc for sysdev */ 162 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 163 PCI_IRQ_MSIX | PCI_IRQ_MSI); 164 if (xhci->nvecs < 0) { 165 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 166 "failed to allocate IRQ vectors"); 167 goto legacy_irq; 168 } 169 170 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 171 xhci_to_hcd(xhci)); 172 if (ret) 173 goto free_irq_vectors; 174 175 hcd->msi_enabled = 1; 176 hcd->msix_enabled = pdev->msix_enabled; 177 return 0; 178 179 free_irq_vectors: 180 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 181 pdev->msix_enabled ? "MSI-X" : "MSI"); 182 pci_free_irq_vectors(pdev); 183 184 legacy_irq: 185 if (!pdev->irq) { 186 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 187 return -EINVAL; 188 } 189 190 if (!strlen(hcd->irq_descr)) 191 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 192 hcd->driver->description, hcd->self.busnum); 193 194 /* fall back to legacy interrupt */ 195 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 196 if (ret) { 197 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 198 return ret; 199 } 200 hcd->irq = pdev->irq; 201 return 0; 202 } 203 204 static int xhci_pci_run(struct usb_hcd *hcd) 205 { 206 int ret; 207 208 if (usb_hcd_is_primary_hcd(hcd)) { 209 ret = xhci_try_enable_msi(hcd); 210 if (ret) 211 return ret; 212 } 213 214 return xhci_run(hcd); 215 } 216 217 static void xhci_pci_stop(struct usb_hcd *hcd) 218 { 219 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 220 221 xhci_stop(hcd); 222 223 if (usb_hcd_is_primary_hcd(hcd)) 224 xhci_cleanup_msix(xhci); 225 } 226 227 /* called after powerup, by probe or system-pm "wakeup" */ 228 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 229 { 230 /* 231 * TODO: Implement finding debug ports later. 232 * TODO: see if there are any quirks that need to be added to handle 233 * new extended capabilities. 234 */ 235 236 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 237 if (!pci_set_mwi(pdev)) 238 xhci_dbg(xhci, "MWI active\n"); 239 240 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 241 return 0; 242 } 243 244 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 245 { 246 struct pci_dev *pdev = to_pci_dev(dev); 247 248 /* Look for vendor-specific quirks */ 249 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 250 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 251 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 252 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 253 pdev->revision == 0x0) { 254 xhci->quirks |= XHCI_RESET_EP_QUIRK; 255 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 256 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 257 } 258 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 259 pdev->revision == 0x4) { 260 xhci->quirks |= XHCI_SLOW_SUSPEND; 261 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 262 "QUIRK: Fresco Logic xHC revision %u" 263 "must be suspended extra slowly", 264 pdev->revision); 265 } 266 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 267 xhci->quirks |= XHCI_BROKEN_STREAMS; 268 /* Fresco Logic confirms: all revisions of this chip do not 269 * support MSI, even though some of them claim to in their PCI 270 * capabilities. 271 */ 272 xhci->quirks |= XHCI_BROKEN_MSI; 273 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 274 "QUIRK: Fresco Logic revision %u " 275 "has broken MSI implementation", 276 pdev->revision); 277 } 278 279 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 280 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 281 xhci->quirks |= XHCI_BROKEN_STREAMS; 282 283 if (pdev->vendor == PCI_VENDOR_ID_NEC) 284 xhci->quirks |= XHCI_NEC_HOST; 285 286 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 287 xhci->quirks |= XHCI_AMD_0x96_HOST; 288 289 /* AMD PLL quirk */ 290 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 291 xhci->quirks |= XHCI_AMD_PLL_FIX; 292 293 if (pdev->vendor == PCI_VENDOR_ID_AMD && 294 (pdev->device == 0x145c || 295 pdev->device == 0x15e0 || 296 pdev->device == 0x15e1 || 297 pdev->device == 0x43bb)) 298 xhci->quirks |= XHCI_SUSPEND_DELAY; 299 300 if (pdev->vendor == PCI_VENDOR_ID_AMD && 301 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 302 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 303 304 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 305 xhci->quirks |= XHCI_DISABLE_SPARSE; 306 xhci->quirks |= XHCI_RESET_ON_RESUME; 307 } 308 309 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 310 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 311 312 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 313 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 314 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 315 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 316 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 317 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 318 319 if (pdev->vendor == PCI_VENDOR_ID_AMD && 320 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 321 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 322 323 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 324 xhci->quirks |= XHCI_LPM_SUPPORT; 325 xhci->quirks |= XHCI_INTEL_HOST; 326 xhci->quirks |= XHCI_AVOID_BEI; 327 } 328 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 329 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 330 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 331 xhci->limit_active_eps = 64; 332 xhci->quirks |= XHCI_SW_BW_CHECKING; 333 /* 334 * PPT desktop boards DH77EB and DH77DF will power back on after 335 * a few seconds of being shutdown. The fix for this is to 336 * switch the ports from xHCI to EHCI on shutdown. We can't use 337 * DMI information to find those particular boards (since each 338 * vendor will change the board name), so we have to key off all 339 * PPT chipsets. 340 */ 341 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 342 } 343 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 344 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 345 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 346 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 347 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 348 } 349 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 350 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 351 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 352 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 353 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 354 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 355 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 356 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 357 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 358 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 359 } 360 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 361 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 362 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 363 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 364 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 365 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 366 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 367 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 368 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 369 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 370 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 371 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 372 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 373 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 374 xhci->quirks |= XHCI_MISSING_CAS; 375 376 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 377 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || 378 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 379 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 380 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 381 382 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 383 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 384 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 385 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 386 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 389 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 390 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 391 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 392 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 393 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 394 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 395 396 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 397 pdev->device == PCI_DEVICE_ID_EJ168) { 398 xhci->quirks |= XHCI_RESET_ON_RESUME; 399 xhci->quirks |= XHCI_BROKEN_STREAMS; 400 } 401 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 402 pdev->device == PCI_DEVICE_ID_EJ188) { 403 xhci->quirks |= XHCI_RESET_ON_RESUME; 404 xhci->quirks |= XHCI_BROKEN_STREAMS; 405 } 406 407 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 408 pdev->device == 0x0014) { 409 xhci->quirks |= XHCI_ZERO_64B_REGS; 410 } 411 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 412 pdev->device == 0x0015) { 413 xhci->quirks |= XHCI_RESET_ON_RESUME; 414 xhci->quirks |= XHCI_ZERO_64B_REGS; 415 } 416 if (pdev->vendor == PCI_VENDOR_ID_VIA) 417 xhci->quirks |= XHCI_RESET_ON_RESUME; 418 419 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM && 420 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) 421 xhci->quirks |= XHCI_RESET_ON_RESUME; 422 423 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 424 if (pdev->vendor == PCI_VENDOR_ID_VIA && 425 pdev->device == 0x3432) 426 xhci->quirks |= XHCI_BROKEN_STREAMS; 427 428 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 429 xhci->quirks |= XHCI_LPM_SUPPORT; 430 431 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 432 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 433 /* 434 * try to tame the ASMedia 1042 controller which reports 0.96 435 * but appears to behave more like 1.0 436 */ 437 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 438 xhci->quirks |= XHCI_BROKEN_STREAMS; 439 } 440 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 441 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 442 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 443 } 444 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 445 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 446 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 447 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 448 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 449 450 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 451 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 452 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 453 454 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 455 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 456 457 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 458 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 459 pdev->device == 0x9026) 460 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 461 462 if (pdev->vendor == PCI_VENDOR_ID_AMD && 463 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 464 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 465 xhci->quirks |= XHCI_NO_SOFT_RETRY; 466 467 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 468 xhci->quirks |= XHCI_ZHAOXIN_HOST; 469 xhci->quirks |= XHCI_LPM_SUPPORT; 470 471 if (pdev->device == 0x9202) { 472 xhci->quirks |= XHCI_RESET_ON_RESUME; 473 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 474 } 475 476 if (pdev->device == 0x9203) 477 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 478 } 479 480 if (pdev->vendor == PCI_DEVICE_ID_CADENCE && 481 pdev->device == PCI_DEVICE_ID_CADENCE_SSP) 482 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 483 484 /* xHC spec requires PCI devices to support D3hot and D3cold */ 485 if (xhci->hci_version >= 0x120) 486 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 487 488 if (xhci->quirks & XHCI_RESET_ON_RESUME) 489 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 490 "QUIRK: Resetting on resume"); 491 } 492 493 #ifdef CONFIG_ACPI 494 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 495 { 496 static const guid_t intel_dsm_guid = 497 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 498 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 499 union acpi_object *obj; 500 501 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 502 NULL); 503 ACPI_FREE(obj); 504 } 505 506 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 507 { 508 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 509 struct xhci_hub *rhub = &xhci->usb3_rhub; 510 int ret; 511 int i; 512 513 /* This is not the usb3 roothub we are looking for */ 514 if (hcd != rhub->hcd) 515 return; 516 517 if (hdev->maxchild > rhub->num_ports) { 518 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 519 return; 520 } 521 522 for (i = 0; i < hdev->maxchild; i++) { 523 ret = usb_acpi_port_lpm_incapable(hdev, i); 524 525 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 526 527 if (ret >= 0) { 528 rhub->ports[i]->lpm_incapable = ret; 529 continue; 530 } 531 } 532 } 533 534 #else 535 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 536 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 537 #endif /* CONFIG_ACPI */ 538 539 /* called during probe() after chip reset completes */ 540 static int xhci_pci_setup(struct usb_hcd *hcd) 541 { 542 struct xhci_hcd *xhci; 543 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 544 int retval; 545 u8 sbrn; 546 547 xhci = hcd_to_xhci(hcd); 548 549 /* imod_interval is the interrupt moderation value in nanoseconds. */ 550 xhci->imod_interval = 40000; 551 552 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 553 if (retval) 554 return retval; 555 556 if (!usb_hcd_is_primary_hcd(hcd)) 557 return 0; 558 559 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 560 xhci_pme_acpi_rtd3_enable(pdev); 561 562 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn); 563 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn); 564 565 /* Find any debug ports */ 566 return xhci_pci_reinit(xhci, pdev); 567 } 568 569 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 570 struct usb_tt *tt, gfp_t mem_flags) 571 { 572 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 573 if (!hdev->parent) 574 xhci_find_lpm_incapable_ports(hcd, hdev); 575 576 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 577 } 578 579 /* 580 * We need to register our own PCI probe function (instead of the USB core's 581 * function) in order to create a second roothub under xHCI. 582 */ 583 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) 584 { 585 int retval; 586 struct xhci_hcd *xhci; 587 struct usb_hcd *hcd; 588 struct reset_control *reset; 589 590 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 591 if (IS_ERR(reset)) 592 return PTR_ERR(reset); 593 reset_control_reset(reset); 594 595 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 596 pm_runtime_get_noresume(&dev->dev); 597 598 /* Register the USB 2.0 roothub. 599 * FIXME: USB core must know to register the USB 2.0 roothub first. 600 * This is sort of silly, because we could just set the HCD driver flags 601 * to say USB 2.0, but I'm not sure what the implications would be in 602 * the other parts of the HCD code. 603 */ 604 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 605 606 if (retval) 607 goto put_runtime_pm; 608 609 /* USB 2.0 roothub is stored in the PCI device now. */ 610 hcd = dev_get_drvdata(&dev->dev); 611 xhci = hcd_to_xhci(hcd); 612 xhci->reset = reset; 613 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 614 pci_name(dev), hcd); 615 if (!xhci->shared_hcd) { 616 retval = -ENOMEM; 617 goto dealloc_usb2_hcd; 618 } 619 620 retval = xhci_ext_cap_init(xhci); 621 if (retval) 622 goto put_usb3_hcd; 623 624 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 625 IRQF_SHARED); 626 if (retval) 627 goto put_usb3_hcd; 628 /* Roothub already marked as USB 3.0 speed */ 629 630 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 631 HCC_MAX_PSA(xhci->hcc_params) >= 4) 632 xhci->shared_hcd->can_do_streams = 1; 633 634 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 635 pm_runtime_put_noidle(&dev->dev); 636 637 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 638 pm_runtime_forbid(&dev->dev); 639 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 640 pm_runtime_allow(&dev->dev); 641 642 dma_set_max_seg_size(&dev->dev, UINT_MAX); 643 644 return 0; 645 646 put_usb3_hcd: 647 usb_put_hcd(xhci->shared_hcd); 648 dealloc_usb2_hcd: 649 usb_hcd_pci_remove(dev); 650 put_runtime_pm: 651 pm_runtime_put_noidle(&dev->dev); 652 return retval; 653 } 654 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, xhci); 655 656 static const struct pci_device_id pci_ids_reject[] = { 657 /* handled by xhci-pci-renesas */ 658 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, 659 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, 660 { /* end: all zeroes */ } 661 }; 662 663 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 664 { 665 if (pci_match_id(pci_ids_reject, dev)) 666 return -ENODEV; 667 668 return xhci_pci_common_probe(dev, id); 669 } 670 671 void xhci_pci_remove(struct pci_dev *dev) 672 { 673 struct xhci_hcd *xhci; 674 bool set_power_d3; 675 676 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 677 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 678 679 xhci->xhc_state |= XHCI_STATE_REMOVING; 680 681 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 682 pm_runtime_forbid(&dev->dev); 683 684 if (xhci->shared_hcd) { 685 usb_remove_hcd(xhci->shared_hcd); 686 usb_put_hcd(xhci->shared_hcd); 687 xhci->shared_hcd = NULL; 688 } 689 690 usb_hcd_pci_remove(dev); 691 692 /* Workaround for spurious wakeups at shutdown with HSW */ 693 if (set_power_d3) 694 pci_set_power_state(dev, PCI_D3hot); 695 } 696 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, xhci); 697 698 /* 699 * In some Intel xHCI controllers, in order to get D3 working, 700 * through a vendor specific SSIC CONFIG register at offset 0x883c, 701 * SSIC PORT need to be marked as "unused" before putting xHCI 702 * into D3. After D3 exit, the SSIC port need to be marked as "used". 703 * Without this change, xHCI might not enter D3 state. 704 */ 705 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 706 { 707 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 708 u32 val; 709 void __iomem *reg; 710 int i; 711 712 for (i = 0; i < SSIC_PORT_NUM; i++) { 713 reg = (void __iomem *) xhci->cap_regs + 714 SSIC_PORT_CFG2 + 715 i * SSIC_PORT_CFG2_OFFSET; 716 717 /* Notify SSIC that SSIC profile programming is not done. */ 718 val = readl(reg) & ~PROG_DONE; 719 writel(val, reg); 720 721 /* Mark SSIC port as unused(suspend) or used(resume) */ 722 val = readl(reg); 723 if (suspend) 724 val |= SSIC_PORT_UNUSED; 725 else 726 val &= ~SSIC_PORT_UNUSED; 727 writel(val, reg); 728 729 /* Notify SSIC that SSIC profile programming is done */ 730 val = readl(reg) | PROG_DONE; 731 writel(val, reg); 732 readl(reg); 733 } 734 } 735 736 /* 737 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 738 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 739 */ 740 static void xhci_pme_quirk(struct usb_hcd *hcd) 741 { 742 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 743 void __iomem *reg; 744 u32 val; 745 746 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 747 val = readl(reg); 748 writel(val | BIT(28), reg); 749 readl(reg); 750 } 751 752 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 753 { 754 u32 reg; 755 756 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 757 reg &= ~BIT(SPARSE_DISABLE_BIT); 758 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 759 } 760 761 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 762 { 763 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 764 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 765 int ret; 766 767 /* 768 * Systems with the TI redriver that loses port status change events 769 * need to have the registers polled during D3, so avoid D3cold. 770 */ 771 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 772 pci_d3cold_disable(pdev); 773 774 #ifdef CONFIG_SUSPEND 775 /* d3cold is broken, but only when s2idle is used */ 776 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 777 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 778 pci_d3cold_disable(pdev); 779 #endif 780 781 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 782 xhci_pme_quirk(hcd); 783 784 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 785 xhci_ssic_port_unused_quirk(hcd, true); 786 787 if (xhci->quirks & XHCI_DISABLE_SPARSE) 788 xhci_sparse_control_quirk(hcd); 789 790 ret = xhci_suspend(xhci, do_wakeup); 791 792 /* synchronize irq when using MSI-X */ 793 xhci_msix_sync_irqs(xhci); 794 795 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 796 xhci_ssic_port_unused_quirk(hcd, false); 797 798 return ret; 799 } 800 801 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 802 { 803 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 804 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 805 806 reset_control_reset(xhci->reset); 807 808 /* The BIOS on systems with the Intel Panther Point chipset may or may 809 * not support xHCI natively. That means that during system resume, it 810 * may switch the ports back to EHCI so that users can use their 811 * keyboard to select a kernel from GRUB after resume from hibernate. 812 * 813 * The BIOS is supposed to remember whether the OS had xHCI ports 814 * enabled before resume, and switch the ports back to xHCI when the 815 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 816 * writers. 817 * 818 * Unconditionally switch the ports back to xHCI after a system resume. 819 * It should not matter whether the EHCI or xHCI controller is 820 * resumed first. It's enough to do the switchover in xHCI because 821 * USB core won't notice anything as the hub driver doesn't start 822 * running again until after all the devices (including both EHCI and 823 * xHCI host controllers) have been resumed. 824 */ 825 826 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 827 usb_enable_intel_xhci_ports(pdev); 828 829 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 830 xhci_ssic_port_unused_quirk(hcd, false); 831 832 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 833 xhci_pme_quirk(hcd); 834 835 return xhci_resume(xhci, msg); 836 } 837 838 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 839 { 840 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 841 struct xhci_port *port; 842 struct usb_device *udev; 843 u32 portsc; 844 int i; 845 846 /* 847 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 848 * cause significant boot delay if usb ports are in suspended U3 state 849 * during boot. Some USB devices survive in U3 state over S4 hibernate 850 * 851 * Disable ports that are in U3 if remote wake is not enabled for either 852 * host controller or connected device 853 */ 854 855 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 856 return 0; 857 858 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 859 port = &xhci->hw_ports[i]; 860 portsc = readl(port->addr); 861 862 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 863 continue; 864 865 if (!port->slot_id || !xhci->devs[port->slot_id]) { 866 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 867 port->slot_id, port->rhub->hcd->self.busnum, 868 port->hcd_portnum + 1); 869 continue; 870 } 871 872 udev = xhci->devs[port->slot_id]->udev; 873 874 /* if wakeup is enabled then don't disable the port */ 875 if (udev->do_remote_wakeup && do_wakeup) 876 continue; 877 878 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 879 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 880 portsc = xhci_port_state_to_neutral(portsc); 881 writel(portsc | PORT_PE, port->addr); 882 } 883 884 return 0; 885 } 886 887 static void xhci_pci_shutdown(struct usb_hcd *hcd) 888 { 889 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 890 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 891 892 xhci_shutdown(hcd); 893 xhci_cleanup_msix(xhci); 894 895 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 896 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 897 pci_set_power_state(pdev, PCI_D3hot); 898 } 899 900 /*-------------------------------------------------------------------------*/ 901 902 /* PCI driver selection metadata; PCI hotplugging uses this */ 903 static const struct pci_device_id pci_ids[] = { 904 /* handle any USB 3.0 xHCI controller */ 905 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 906 }, 907 { /* end: all zeroes */ } 908 }; 909 MODULE_DEVICE_TABLE(pci, pci_ids); 910 911 /* pci driver glue; this is a "new style" PCI driver module */ 912 static struct pci_driver xhci_pci_driver = { 913 .name = hcd_name, 914 .id_table = pci_ids, 915 916 .probe = xhci_pci_probe, 917 .remove = xhci_pci_remove, 918 /* suspend and resume implemented later */ 919 920 .shutdown = usb_hcd_pci_shutdown, 921 .driver = { 922 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 923 }, 924 }; 925 926 static int __init xhci_pci_init(void) 927 { 928 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 929 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 930 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 931 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 932 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 933 xhci_pci_hc_driver.stop = xhci_pci_stop; 934 return pci_register_driver(&xhci_pci_driver); 935 } 936 module_init(xhci_pci_init); 937 938 static void __exit xhci_pci_exit(void) 939 { 940 pci_unregister_driver(&xhci_pci_driver); 941 } 942 module_exit(xhci_pci_exit); 943 944 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 945 MODULE_LICENSE("GPL"); 946