1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 42 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 43 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 46 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 47 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 48 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 49 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 50 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 51 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 52 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 53 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 54 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 55 56 /* Thunderbolt */ 57 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 58 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 59 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 60 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 61 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 62 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 63 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 64 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 65 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 66 67 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 72 73 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 74 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 75 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 76 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 77 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 78 79 static const char hcd_name[] = "xhci_hcd"; 80 81 static struct hc_driver __read_mostly xhci_pci_hc_driver; 82 83 static int xhci_pci_setup(struct usb_hcd *hcd); 84 static int xhci_pci_run(struct usb_hcd *hcd); 85 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 86 struct usb_tt *tt, gfp_t mem_flags); 87 88 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 89 .reset = xhci_pci_setup, 90 .start = xhci_pci_run, 91 .update_hub_device = xhci_pci_update_hub_device, 92 }; 93 94 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 95 { 96 struct usb_hcd *hcd = xhci_to_hcd(xhci); 97 98 if (hcd->msix_enabled) { 99 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 100 101 /* for now, the driver only supports one primary interrupter */ 102 synchronize_irq(pci_irq_vector(pdev, 0)); 103 } 104 } 105 106 /* Free any IRQs and disable MSI-X */ 107 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 108 { 109 struct usb_hcd *hcd = xhci_to_hcd(xhci); 110 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 111 112 /* return if using legacy interrupt */ 113 if (hcd->irq > 0) 114 return; 115 116 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 117 pci_free_irq_vectors(pdev); 118 hcd->msix_enabled = 0; 119 } 120 121 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 122 static int xhci_try_enable_msi(struct usb_hcd *hcd) 123 { 124 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 125 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 126 int ret; 127 128 /* 129 * Some Fresco Logic host controllers advertise MSI, but fail to 130 * generate interrupts. Don't even try to enable MSI. 131 */ 132 if (xhci->quirks & XHCI_BROKEN_MSI) 133 goto legacy_irq; 134 135 /* unregister the legacy interrupt */ 136 if (hcd->irq) 137 free_irq(hcd->irq, hcd); 138 hcd->irq = 0; 139 140 /* 141 * calculate number of MSI-X vectors supported. 142 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 143 * with max number of interrupters based on the xhci HCSPARAMS1. 144 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 145 * Add additional 1 vector to ensure always available interrupt. 146 */ 147 xhci->nvecs = min(num_online_cpus() + 1, 148 HCS_MAX_INTRS(xhci->hcs_params1)); 149 150 /* TODO: Check with MSI Soc for sysdev */ 151 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 152 PCI_IRQ_MSIX | PCI_IRQ_MSI); 153 if (xhci->nvecs < 0) { 154 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 155 "failed to allocate IRQ vectors"); 156 goto legacy_irq; 157 } 158 159 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 160 xhci_to_hcd(xhci)); 161 if (ret) 162 goto free_irq_vectors; 163 164 hcd->msi_enabled = 1; 165 hcd->msix_enabled = pdev->msix_enabled; 166 return 0; 167 168 free_irq_vectors: 169 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 170 pdev->msix_enabled ? "MSI-X" : "MSI"); 171 pci_free_irq_vectors(pdev); 172 173 legacy_irq: 174 if (!pdev->irq) { 175 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 176 return -EINVAL; 177 } 178 179 if (!strlen(hcd->irq_descr)) 180 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 181 hcd->driver->description, hcd->self.busnum); 182 183 /* fall back to legacy interrupt */ 184 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 185 if (ret) { 186 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 187 return ret; 188 } 189 hcd->irq = pdev->irq; 190 return 0; 191 } 192 193 static int xhci_pci_run(struct usb_hcd *hcd) 194 { 195 int ret; 196 197 if (usb_hcd_is_primary_hcd(hcd)) { 198 ret = xhci_try_enable_msi(hcd); 199 if (ret) 200 return ret; 201 } 202 203 return xhci_run(hcd); 204 } 205 206 static void xhci_pci_stop(struct usb_hcd *hcd) 207 { 208 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 209 210 xhci_stop(hcd); 211 212 if (usb_hcd_is_primary_hcd(hcd)) 213 xhci_cleanup_msix(xhci); 214 } 215 216 /* called after powerup, by probe or system-pm "wakeup" */ 217 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 218 { 219 /* 220 * TODO: Implement finding debug ports later. 221 * TODO: see if there are any quirks that need to be added to handle 222 * new extended capabilities. 223 */ 224 225 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 226 if (!pci_set_mwi(pdev)) 227 xhci_dbg(xhci, "MWI active\n"); 228 229 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 230 return 0; 231 } 232 233 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 234 { 235 struct pci_dev *pdev = to_pci_dev(dev); 236 struct xhci_driver_data *driver_data; 237 const struct pci_device_id *id; 238 239 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 240 241 if (id && id->driver_data) { 242 driver_data = (struct xhci_driver_data *)id->driver_data; 243 xhci->quirks |= driver_data->quirks; 244 } 245 246 /* Look for vendor-specific quirks */ 247 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 248 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 249 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 250 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 251 pdev->revision == 0x0) { 252 xhci->quirks |= XHCI_RESET_EP_QUIRK; 253 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 254 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 255 } 256 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 257 pdev->revision == 0x4) { 258 xhci->quirks |= XHCI_SLOW_SUSPEND; 259 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 260 "QUIRK: Fresco Logic xHC revision %u" 261 "must be suspended extra slowly", 262 pdev->revision); 263 } 264 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 265 xhci->quirks |= XHCI_BROKEN_STREAMS; 266 /* Fresco Logic confirms: all revisions of this chip do not 267 * support MSI, even though some of them claim to in their PCI 268 * capabilities. 269 */ 270 xhci->quirks |= XHCI_BROKEN_MSI; 271 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 272 "QUIRK: Fresco Logic revision %u " 273 "has broken MSI implementation", 274 pdev->revision); 275 } 276 277 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 278 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 279 xhci->quirks |= XHCI_BROKEN_STREAMS; 280 281 if (pdev->vendor == PCI_VENDOR_ID_NEC) 282 xhci->quirks |= XHCI_NEC_HOST; 283 284 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 285 xhci->quirks |= XHCI_AMD_0x96_HOST; 286 287 /* AMD PLL quirk */ 288 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 289 xhci->quirks |= XHCI_AMD_PLL_FIX; 290 291 if (pdev->vendor == PCI_VENDOR_ID_AMD && 292 (pdev->device == 0x145c || 293 pdev->device == 0x15e0 || 294 pdev->device == 0x15e1 || 295 pdev->device == 0x43bb)) 296 xhci->quirks |= XHCI_SUSPEND_DELAY; 297 298 if (pdev->vendor == PCI_VENDOR_ID_AMD && 299 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 300 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 301 302 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 303 xhci->quirks |= XHCI_DISABLE_SPARSE; 304 xhci->quirks |= XHCI_RESET_ON_RESUME; 305 } 306 307 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 308 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 309 310 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 311 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 312 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 313 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 314 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 315 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 316 317 if (pdev->vendor == PCI_VENDOR_ID_AMD && 318 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 319 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 320 321 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 322 xhci->quirks |= XHCI_LPM_SUPPORT; 323 xhci->quirks |= XHCI_INTEL_HOST; 324 xhci->quirks |= XHCI_AVOID_BEI; 325 } 326 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 327 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 328 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 329 xhci->limit_active_eps = 64; 330 xhci->quirks |= XHCI_SW_BW_CHECKING; 331 /* 332 * PPT desktop boards DH77EB and DH77DF will power back on after 333 * a few seconds of being shutdown. The fix for this is to 334 * switch the ports from xHCI to EHCI on shutdown. We can't use 335 * DMI information to find those particular boards (since each 336 * vendor will change the board name), so we have to key off all 337 * PPT chipsets. 338 */ 339 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 340 } 341 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 342 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 343 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 344 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 345 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 346 } 347 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 348 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 349 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 350 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 351 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 352 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 353 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 354 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 355 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 356 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 357 } 358 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 359 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 360 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 361 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 362 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 363 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 364 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 365 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 366 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 367 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 368 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 369 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 370 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 371 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 372 xhci->quirks |= XHCI_MISSING_CAS; 373 374 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 375 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 376 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 377 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 378 379 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 380 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 381 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 382 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 383 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 384 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 385 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 386 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 389 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 390 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 391 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 392 393 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 394 pdev->device == PCI_DEVICE_ID_EJ168) { 395 xhci->quirks |= XHCI_RESET_ON_RESUME; 396 xhci->quirks |= XHCI_BROKEN_STREAMS; 397 } 398 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 399 pdev->device == 0x0014) { 400 xhci->quirks |= XHCI_ZERO_64B_REGS; 401 } 402 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 403 pdev->device == 0x0015) { 404 xhci->quirks |= XHCI_RESET_ON_RESUME; 405 xhci->quirks |= XHCI_ZERO_64B_REGS; 406 } 407 if (pdev->vendor == PCI_VENDOR_ID_VIA) 408 xhci->quirks |= XHCI_RESET_ON_RESUME; 409 410 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 411 if (pdev->vendor == PCI_VENDOR_ID_VIA && 412 pdev->device == 0x3432) 413 xhci->quirks |= XHCI_BROKEN_STREAMS; 414 415 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 416 xhci->quirks |= XHCI_LPM_SUPPORT; 417 418 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 419 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 420 /* 421 * try to tame the ASMedia 1042 controller which reports 0.96 422 * but appears to behave more like 1.0 423 */ 424 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 425 xhci->quirks |= XHCI_BROKEN_STREAMS; 426 } 427 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 428 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 429 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 430 } 431 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 432 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 433 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 434 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 435 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 436 437 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 438 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 439 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 440 441 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 442 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 443 444 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 445 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 446 pdev->device == 0x9026) 447 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 448 449 if (pdev->vendor == PCI_VENDOR_ID_AMD && 450 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 451 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 452 xhci->quirks |= XHCI_NO_SOFT_RETRY; 453 454 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 455 xhci->quirks |= XHCI_ZHAOXIN_HOST; 456 xhci->quirks |= XHCI_LPM_SUPPORT; 457 458 if (pdev->device == 0x9202) { 459 xhci->quirks |= XHCI_RESET_ON_RESUME; 460 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 461 } 462 463 if (pdev->device == 0x9203) 464 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 465 } 466 467 /* xHC spec requires PCI devices to support D3hot and D3cold */ 468 if (xhci->hci_version >= 0x120) 469 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 470 471 if (xhci->quirks & XHCI_RESET_ON_RESUME) 472 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 473 "QUIRK: Resetting on resume"); 474 } 475 476 #ifdef CONFIG_ACPI 477 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 478 { 479 static const guid_t intel_dsm_guid = 480 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 481 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 482 union acpi_object *obj; 483 484 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 485 NULL); 486 ACPI_FREE(obj); 487 } 488 489 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 490 { 491 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 492 struct xhci_hub *rhub = &xhci->usb3_rhub; 493 int ret; 494 int i; 495 496 /* This is not the usb3 roothub we are looking for */ 497 if (hcd != rhub->hcd) 498 return; 499 500 if (hdev->maxchild > rhub->num_ports) { 501 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 502 return; 503 } 504 505 for (i = 0; i < hdev->maxchild; i++) { 506 ret = usb_acpi_port_lpm_incapable(hdev, i); 507 508 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 509 510 if (ret >= 0) { 511 rhub->ports[i]->lpm_incapable = ret; 512 continue; 513 } 514 } 515 } 516 517 #else 518 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 519 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 520 #endif /* CONFIG_ACPI */ 521 522 /* called during probe() after chip reset completes */ 523 static int xhci_pci_setup(struct usb_hcd *hcd) 524 { 525 struct xhci_hcd *xhci; 526 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 527 int retval; 528 529 xhci = hcd_to_xhci(hcd); 530 if (!xhci->sbrn) 531 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 532 533 /* imod_interval is the interrupt moderation value in nanoseconds. */ 534 xhci->imod_interval = 40000; 535 536 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 537 if (retval) 538 return retval; 539 540 if (!usb_hcd_is_primary_hcd(hcd)) 541 return 0; 542 543 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 544 xhci_pme_acpi_rtd3_enable(pdev); 545 546 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 547 548 /* Find any debug ports */ 549 return xhci_pci_reinit(xhci, pdev); 550 } 551 552 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 553 struct usb_tt *tt, gfp_t mem_flags) 554 { 555 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 556 if (!hdev->parent) 557 xhci_find_lpm_incapable_ports(hcd, hdev); 558 559 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 560 } 561 562 /* 563 * We need to register our own PCI probe function (instead of the USB core's 564 * function) in order to create a second roothub under xHCI. 565 */ 566 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 567 { 568 int retval; 569 struct xhci_hcd *xhci; 570 struct usb_hcd *hcd; 571 struct xhci_driver_data *driver_data; 572 struct reset_control *reset; 573 574 driver_data = (struct xhci_driver_data *)id->driver_data; 575 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 576 retval = renesas_xhci_check_request_fw(dev, id); 577 if (retval) 578 return retval; 579 } 580 581 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 582 if (IS_ERR(reset)) 583 return PTR_ERR(reset); 584 reset_control_reset(reset); 585 586 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 587 pm_runtime_get_noresume(&dev->dev); 588 589 /* Register the USB 2.0 roothub. 590 * FIXME: USB core must know to register the USB 2.0 roothub first. 591 * This is sort of silly, because we could just set the HCD driver flags 592 * to say USB 2.0, but I'm not sure what the implications would be in 593 * the other parts of the HCD code. 594 */ 595 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 596 597 if (retval) 598 goto put_runtime_pm; 599 600 /* USB 2.0 roothub is stored in the PCI device now. */ 601 hcd = dev_get_drvdata(&dev->dev); 602 xhci = hcd_to_xhci(hcd); 603 xhci->reset = reset; 604 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 605 pci_name(dev), hcd); 606 if (!xhci->shared_hcd) { 607 retval = -ENOMEM; 608 goto dealloc_usb2_hcd; 609 } 610 611 retval = xhci_ext_cap_init(xhci); 612 if (retval) 613 goto put_usb3_hcd; 614 615 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 616 IRQF_SHARED); 617 if (retval) 618 goto put_usb3_hcd; 619 /* Roothub already marked as USB 3.0 speed */ 620 621 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 622 HCC_MAX_PSA(xhci->hcc_params) >= 4) 623 xhci->shared_hcd->can_do_streams = 1; 624 625 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 626 pm_runtime_put_noidle(&dev->dev); 627 628 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 629 pm_runtime_forbid(&dev->dev); 630 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 631 pm_runtime_allow(&dev->dev); 632 633 dma_set_max_seg_size(&dev->dev, UINT_MAX); 634 635 return 0; 636 637 put_usb3_hcd: 638 usb_put_hcd(xhci->shared_hcd); 639 dealloc_usb2_hcd: 640 usb_hcd_pci_remove(dev); 641 put_runtime_pm: 642 pm_runtime_put_noidle(&dev->dev); 643 return retval; 644 } 645 646 static void xhci_pci_remove(struct pci_dev *dev) 647 { 648 struct xhci_hcd *xhci; 649 650 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 651 652 xhci->xhc_state |= XHCI_STATE_REMOVING; 653 654 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 655 pm_runtime_forbid(&dev->dev); 656 657 if (xhci->shared_hcd) { 658 usb_remove_hcd(xhci->shared_hcd); 659 usb_put_hcd(xhci->shared_hcd); 660 xhci->shared_hcd = NULL; 661 } 662 663 /* Workaround for spurious wakeups at shutdown with HSW */ 664 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 665 pci_set_power_state(dev, PCI_D3hot); 666 667 usb_hcd_pci_remove(dev); 668 } 669 670 /* 671 * In some Intel xHCI controllers, in order to get D3 working, 672 * through a vendor specific SSIC CONFIG register at offset 0x883c, 673 * SSIC PORT need to be marked as "unused" before putting xHCI 674 * into D3. After D3 exit, the SSIC port need to be marked as "used". 675 * Without this change, xHCI might not enter D3 state. 676 */ 677 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 678 { 679 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 680 u32 val; 681 void __iomem *reg; 682 int i; 683 684 for (i = 0; i < SSIC_PORT_NUM; i++) { 685 reg = (void __iomem *) xhci->cap_regs + 686 SSIC_PORT_CFG2 + 687 i * SSIC_PORT_CFG2_OFFSET; 688 689 /* Notify SSIC that SSIC profile programming is not done. */ 690 val = readl(reg) & ~PROG_DONE; 691 writel(val, reg); 692 693 /* Mark SSIC port as unused(suspend) or used(resume) */ 694 val = readl(reg); 695 if (suspend) 696 val |= SSIC_PORT_UNUSED; 697 else 698 val &= ~SSIC_PORT_UNUSED; 699 writel(val, reg); 700 701 /* Notify SSIC that SSIC profile programming is done */ 702 val = readl(reg) | PROG_DONE; 703 writel(val, reg); 704 readl(reg); 705 } 706 } 707 708 /* 709 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 710 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 711 */ 712 static void xhci_pme_quirk(struct usb_hcd *hcd) 713 { 714 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 715 void __iomem *reg; 716 u32 val; 717 718 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 719 val = readl(reg); 720 writel(val | BIT(28), reg); 721 readl(reg); 722 } 723 724 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 725 { 726 u32 reg; 727 728 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 729 reg &= ~BIT(SPARSE_DISABLE_BIT); 730 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 731 } 732 733 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 734 { 735 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 736 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 737 int ret; 738 739 /* 740 * Systems with the TI redriver that loses port status change events 741 * need to have the registers polled during D3, so avoid D3cold. 742 */ 743 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 744 pci_d3cold_disable(pdev); 745 746 #ifdef CONFIG_SUSPEND 747 /* d3cold is broken, but only when s2idle is used */ 748 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 749 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 750 pci_d3cold_disable(pdev); 751 #endif 752 753 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 754 xhci_pme_quirk(hcd); 755 756 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 757 xhci_ssic_port_unused_quirk(hcd, true); 758 759 if (xhci->quirks & XHCI_DISABLE_SPARSE) 760 xhci_sparse_control_quirk(hcd); 761 762 ret = xhci_suspend(xhci, do_wakeup); 763 764 /* synchronize irq when using MSI-X */ 765 xhci_msix_sync_irqs(xhci); 766 767 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 768 xhci_ssic_port_unused_quirk(hcd, false); 769 770 return ret; 771 } 772 773 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 774 { 775 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 776 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 777 int retval = 0; 778 779 reset_control_reset(xhci->reset); 780 781 /* The BIOS on systems with the Intel Panther Point chipset may or may 782 * not support xHCI natively. That means that during system resume, it 783 * may switch the ports back to EHCI so that users can use their 784 * keyboard to select a kernel from GRUB after resume from hibernate. 785 * 786 * The BIOS is supposed to remember whether the OS had xHCI ports 787 * enabled before resume, and switch the ports back to xHCI when the 788 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 789 * writers. 790 * 791 * Unconditionally switch the ports back to xHCI after a system resume. 792 * It should not matter whether the EHCI or xHCI controller is 793 * resumed first. It's enough to do the switchover in xHCI because 794 * USB core won't notice anything as the hub driver doesn't start 795 * running again until after all the devices (including both EHCI and 796 * xHCI host controllers) have been resumed. 797 */ 798 799 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 800 usb_enable_intel_xhci_ports(pdev); 801 802 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 803 xhci_ssic_port_unused_quirk(hcd, false); 804 805 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 806 xhci_pme_quirk(hcd); 807 808 retval = xhci_resume(xhci, msg); 809 return retval; 810 } 811 812 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 813 { 814 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 815 struct xhci_port *port; 816 struct usb_device *udev; 817 u32 portsc; 818 int i; 819 820 /* 821 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 822 * cause significant boot delay if usb ports are in suspended U3 state 823 * during boot. Some USB devices survive in U3 state over S4 hibernate 824 * 825 * Disable ports that are in U3 if remote wake is not enabled for either 826 * host controller or connected device 827 */ 828 829 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 830 return 0; 831 832 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 833 port = &xhci->hw_ports[i]; 834 portsc = readl(port->addr); 835 836 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 837 continue; 838 839 if (!port->slot_id || !xhci->devs[port->slot_id]) { 840 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 841 port->slot_id, port->rhub->hcd->self.busnum, 842 port->hcd_portnum + 1); 843 continue; 844 } 845 846 udev = xhci->devs[port->slot_id]->udev; 847 848 /* if wakeup is enabled then don't disable the port */ 849 if (udev->do_remote_wakeup && do_wakeup) 850 continue; 851 852 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 853 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 854 portsc = xhci_port_state_to_neutral(portsc); 855 writel(portsc | PORT_PE, port->addr); 856 } 857 858 return 0; 859 } 860 861 static void xhci_pci_shutdown(struct usb_hcd *hcd) 862 { 863 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 864 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 865 866 xhci_shutdown(hcd); 867 xhci_cleanup_msix(xhci); 868 869 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 870 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 871 pci_set_power_state(pdev, PCI_D3hot); 872 } 873 874 /*-------------------------------------------------------------------------*/ 875 876 static const struct xhci_driver_data reneses_data = { 877 .quirks = XHCI_RENESAS_FW_QUIRK, 878 .firmware = "renesas_usb_fw.mem", 879 }; 880 881 /* PCI driver selection metadata; PCI hotplugging uses this */ 882 static const struct pci_device_id pci_ids[] = { 883 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014), 884 .driver_data = (unsigned long)&reneses_data, 885 }, 886 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015), 887 .driver_data = (unsigned long)&reneses_data, 888 }, 889 /* handle any USB 3.0 xHCI controller */ 890 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 891 }, 892 { /* end: all zeroes */ } 893 }; 894 MODULE_DEVICE_TABLE(pci, pci_ids); 895 896 /* 897 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 898 * load firmware, so don't encumber the xhci-pci driver with it. 899 */ 900 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 901 MODULE_FIRMWARE("renesas_usb_fw.mem"); 902 #endif 903 904 /* pci driver glue; this is a "new style" PCI driver module */ 905 static struct pci_driver xhci_pci_driver = { 906 .name = hcd_name, 907 .id_table = pci_ids, 908 909 .probe = xhci_pci_probe, 910 .remove = xhci_pci_remove, 911 /* suspend and resume implemented later */ 912 913 .shutdown = usb_hcd_pci_shutdown, 914 .driver = { 915 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 916 }, 917 }; 918 919 static int __init xhci_pci_init(void) 920 { 921 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 922 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 923 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 924 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 925 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 926 xhci_pci_hc_driver.stop = xhci_pci_stop; 927 return pci_register_driver(&xhci_pci_driver); 928 } 929 module_init(xhci_pci_init); 930 931 static void __exit xhci_pci_exit(void) 932 { 933 pci_unregister_driver(&xhci_pci_driver); 934 } 935 module_exit(xhci_pci_exit); 936 937 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 938 MODULE_LICENSE("GPL"); 939