1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_ETRON_EJ168 0x7023 39 #define PCI_DEVICE_ID_ETRON_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 53 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed 54 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 55 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 56 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 57 58 #define PCI_VENDOR_ID_PHYTIUM 0x1db7 59 #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27 60 61 /* Thunderbolt */ 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 64 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 65 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 66 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 67 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 68 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 69 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 70 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 71 72 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 73 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 74 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 75 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 76 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 77 78 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 79 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 80 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 81 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 82 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 83 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 84 85 static const char hcd_name[] = "xhci_hcd"; 86 87 static struct hc_driver __read_mostly xhci_pci_hc_driver; 88 89 static int xhci_pci_setup(struct usb_hcd *hcd); 90 static int xhci_pci_run(struct usb_hcd *hcd); 91 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 92 struct usb_tt *tt, gfp_t mem_flags); 93 94 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 95 .reset = xhci_pci_setup, 96 .start = xhci_pci_run, 97 .update_hub_device = xhci_pci_update_hub_device, 98 }; 99 100 /* 101 * Primary Legacy and MSI IRQ are synced in suspend_common(). 102 * All MSI-X IRQs and secondary MSI IRQs should be synced here. 103 */ 104 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 105 { 106 struct usb_hcd *hcd = xhci_to_hcd(xhci); 107 108 if (hcd->msix_enabled) { 109 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 110 111 /* for now, the driver only supports one primary interrupter */ 112 synchronize_irq(pci_irq_vector(pdev, 0)); 113 } 114 } 115 116 /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */ 117 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 118 { 119 struct usb_hcd *hcd = xhci_to_hcd(xhci); 120 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 121 122 if (hcd->irq > 0) 123 return; 124 125 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 126 pci_free_irq_vectors(pdev); 127 hcd->msix_enabled = 0; 128 } 129 130 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 131 static int xhci_try_enable_msi(struct usb_hcd *hcd) 132 { 133 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 134 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 135 int ret; 136 137 /* 138 * Some Fresco Logic host controllers advertise MSI, but fail to 139 * generate interrupts. Don't even try to enable MSI. 140 */ 141 if (xhci->quirks & XHCI_BROKEN_MSI) 142 goto legacy_irq; 143 144 /* unregister the legacy interrupt */ 145 if (hcd->irq) 146 free_irq(hcd->irq, hcd); 147 hcd->irq = 0; 148 149 /* 150 * Calculate number of MSI/MSI-X vectors supported. 151 * - max_interrupters: the max number of interrupts requested, capped to xhci HCSPARAMS1. 152 * - num_online_cpus: one vector per CPUs core, with at least one overall. 153 */ 154 xhci->nvecs = min(num_online_cpus() + 1, xhci->max_interrupters); 155 156 /* TODO: Check with MSI Soc for sysdev */ 157 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 158 PCI_IRQ_MSIX | PCI_IRQ_MSI); 159 if (xhci->nvecs < 0) { 160 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 161 "failed to allocate IRQ vectors"); 162 goto legacy_irq; 163 } 164 165 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 166 xhci_to_hcd(xhci)); 167 if (ret) 168 goto free_irq_vectors; 169 170 hcd->msi_enabled = 1; 171 hcd->msix_enabled = pdev->msix_enabled; 172 return 0; 173 174 free_irq_vectors: 175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 176 pdev->msix_enabled ? "MSI-X" : "MSI"); 177 pci_free_irq_vectors(pdev); 178 179 legacy_irq: 180 if (!pdev->irq) { 181 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 182 return -EINVAL; 183 } 184 185 if (!strlen(hcd->irq_descr)) 186 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 187 hcd->driver->description, hcd->self.busnum); 188 189 /* fall back to legacy interrupt */ 190 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 191 if (ret) { 192 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 193 return ret; 194 } 195 hcd->irq = pdev->irq; 196 return 0; 197 } 198 199 static int xhci_pci_run(struct usb_hcd *hcd) 200 { 201 int ret; 202 203 if (usb_hcd_is_primary_hcd(hcd)) { 204 ret = xhci_try_enable_msi(hcd); 205 if (ret) 206 return ret; 207 } 208 209 return xhci_run(hcd); 210 } 211 212 static void xhci_pci_stop(struct usb_hcd *hcd) 213 { 214 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 215 216 xhci_stop(hcd); 217 218 if (usb_hcd_is_primary_hcd(hcd)) 219 xhci_cleanup_msix(xhci); 220 } 221 222 /* called after powerup, by probe or system-pm "wakeup" */ 223 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 224 { 225 /* 226 * TODO: Implement finding debug ports later. 227 * TODO: see if there are any quirks that need to be added to handle 228 * new extended capabilities. 229 */ 230 231 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 232 if (!pci_set_mwi(pdev)) 233 xhci_dbg(xhci, "MWI active\n"); 234 235 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 236 return 0; 237 } 238 239 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 240 { 241 struct pci_dev *pdev = to_pci_dev(dev); 242 243 /* Look for vendor-specific quirks */ 244 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 245 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 246 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 247 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 248 pdev->revision == 0x0) { 249 xhci->quirks |= XHCI_RESET_EP_QUIRK; 250 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 251 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 252 } 253 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 254 pdev->revision == 0x4) { 255 xhci->quirks |= XHCI_SLOW_SUSPEND; 256 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 257 "QUIRK: Fresco Logic xHC revision %u" 258 "must be suspended extra slowly", 259 pdev->revision); 260 } 261 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 262 xhci->quirks |= XHCI_BROKEN_STREAMS; 263 /* Fresco Logic confirms: all revisions of this chip do not 264 * support MSI, even though some of them claim to in their PCI 265 * capabilities. 266 */ 267 xhci->quirks |= XHCI_BROKEN_MSI; 268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 269 "QUIRK: Fresco Logic revision %u " 270 "has broken MSI implementation", 271 pdev->revision); 272 } 273 274 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 275 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 276 xhci->quirks |= XHCI_BROKEN_STREAMS; 277 278 if (pdev->vendor == PCI_VENDOR_ID_NEC) 279 xhci->quirks |= XHCI_NEC_HOST; 280 281 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 282 xhci->quirks |= XHCI_AMD_0x96_HOST; 283 284 /* AMD PLL quirk */ 285 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 286 xhci->quirks |= XHCI_AMD_PLL_FIX; 287 288 if (pdev->vendor == PCI_VENDOR_ID_AMD && 289 (pdev->device == 0x145c || 290 pdev->device == 0x15e0 || 291 pdev->device == 0x15e1 || 292 pdev->device == 0x43bb)) 293 xhci->quirks |= XHCI_SUSPEND_DELAY; 294 295 if (pdev->vendor == PCI_VENDOR_ID_AMD && 296 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 297 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 298 299 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 300 xhci->quirks |= XHCI_DISABLE_SPARSE; 301 xhci->quirks |= XHCI_RESET_ON_RESUME; 302 } 303 304 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 305 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 306 307 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 308 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 309 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 310 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 311 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 312 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 313 314 if (pdev->vendor == PCI_VENDOR_ID_AMD && 315 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 316 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 317 318 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 319 xhci->quirks |= XHCI_LPM_SUPPORT; 320 xhci->quirks |= XHCI_INTEL_HOST; 321 xhci->quirks |= XHCI_AVOID_BEI; 322 } 323 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 324 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 325 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 326 xhci->limit_active_eps = 64; 327 xhci->quirks |= XHCI_SW_BW_CHECKING; 328 /* 329 * PPT desktop boards DH77EB and DH77DF will power back on after 330 * a few seconds of being shutdown. The fix for this is to 331 * switch the ports from xHCI to EHCI on shutdown. We can't use 332 * DMI information to find those particular boards (since each 333 * vendor will change the board name), so we have to key off all 334 * PPT chipsets. 335 */ 336 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 337 } 338 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 339 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 340 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 341 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 342 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 343 } 344 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 345 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 346 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 347 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 348 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 349 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 350 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 351 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 352 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 353 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 354 } 355 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 356 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 357 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 358 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 359 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 360 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 361 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 362 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 363 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 364 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 365 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 366 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 367 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 368 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 369 xhci->quirks |= XHCI_MISSING_CAS; 370 371 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 372 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || 373 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 374 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 375 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 376 377 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 378 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 379 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 380 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 381 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 382 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 383 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 384 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 385 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 386 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 389 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 390 391 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 392 (pdev->device == PCI_DEVICE_ID_ETRON_EJ168 || 393 pdev->device == PCI_DEVICE_ID_ETRON_EJ188)) { 394 xhci->quirks |= XHCI_ETRON_HOST; 395 xhci->quirks |= XHCI_RESET_ON_RESUME; 396 xhci->quirks |= XHCI_BROKEN_STREAMS; 397 xhci->quirks |= XHCI_NO_SOFT_RETRY; 398 } 399 400 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 401 pdev->device == 0x0014) { 402 xhci->quirks |= XHCI_ZERO_64B_REGS; 403 } 404 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 405 pdev->device == 0x0015) { 406 xhci->quirks |= XHCI_RESET_ON_RESUME; 407 xhci->quirks |= XHCI_ZERO_64B_REGS; 408 } 409 if (pdev->vendor == PCI_VENDOR_ID_VIA) 410 xhci->quirks |= XHCI_RESET_ON_RESUME; 411 412 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM && 413 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) 414 xhci->quirks |= XHCI_RESET_ON_RESUME; 415 416 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 417 if (pdev->vendor == PCI_VENDOR_ID_VIA && 418 pdev->device == 0x3432) 419 xhci->quirks |= XHCI_BROKEN_STREAMS; 420 421 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 422 xhci->quirks |= XHCI_LPM_SUPPORT; 423 424 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 425 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 426 /* 427 * try to tame the ASMedia 1042 controller which reports 0.96 428 * but appears to behave more like 1.0 429 */ 430 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 431 xhci->quirks |= XHCI_BROKEN_STREAMS; 432 } 433 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 434 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 435 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 436 } 437 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 438 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 439 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 440 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 441 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 442 443 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 444 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 445 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 446 447 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 448 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) 449 xhci->quirks |= XHCI_RESET_ON_RESUME; 450 451 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 452 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 453 454 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 455 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 456 pdev->device == 0x9026) 457 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 458 459 if (pdev->vendor == PCI_VENDOR_ID_AMD && 460 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 461 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 462 xhci->quirks |= XHCI_NO_SOFT_RETRY; 463 464 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 465 xhci->quirks |= XHCI_ZHAOXIN_HOST; 466 xhci->quirks |= XHCI_LPM_SUPPORT; 467 468 if (pdev->device == 0x9202) { 469 xhci->quirks |= XHCI_RESET_ON_RESUME; 470 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 471 } 472 473 if (pdev->device == 0x9203) 474 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 475 } 476 477 if (pdev->vendor == PCI_VENDOR_ID_CDNS && 478 pdev->device == PCI_DEVICE_ID_CDNS_USBSSP) 479 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 480 481 /* xHC spec requires PCI devices to support D3hot and D3cold */ 482 if (xhci->hci_version >= 0x120) 483 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 484 485 if (xhci->quirks & XHCI_RESET_ON_RESUME) 486 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 487 "QUIRK: Resetting on resume"); 488 } 489 490 #ifdef CONFIG_ACPI 491 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 492 { 493 static const guid_t intel_dsm_guid = 494 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 495 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 496 union acpi_object *obj; 497 498 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 499 NULL); 500 ACPI_FREE(obj); 501 } 502 503 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 504 { 505 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 506 struct xhci_hub *rhub = &xhci->usb3_rhub; 507 int ret; 508 int i; 509 510 /* This is not the usb3 roothub we are looking for */ 511 if (hcd != rhub->hcd) 512 return; 513 514 if (hdev->maxchild > rhub->num_ports) { 515 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 516 return; 517 } 518 519 for (i = 0; i < hdev->maxchild; i++) { 520 ret = usb_acpi_port_lpm_incapable(hdev, i); 521 522 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 523 524 if (ret >= 0) { 525 rhub->ports[i]->lpm_incapable = ret; 526 continue; 527 } 528 } 529 } 530 531 #else 532 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 533 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 534 #endif /* CONFIG_ACPI */ 535 536 /* called during probe() after chip reset completes */ 537 static int xhci_pci_setup(struct usb_hcd *hcd) 538 { 539 struct xhci_hcd *xhci; 540 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 541 int retval; 542 u8 sbrn; 543 544 xhci = hcd_to_xhci(hcd); 545 546 /* imod_interval is the interrupt moderation value in nanoseconds. */ 547 xhci->imod_interval = 40000; 548 549 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 550 if (retval) 551 return retval; 552 553 if (!usb_hcd_is_primary_hcd(hcd)) 554 return 0; 555 556 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 557 xhci_pme_acpi_rtd3_enable(pdev); 558 559 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn); 560 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn); 561 562 /* Find any debug ports */ 563 return xhci_pci_reinit(xhci, pdev); 564 } 565 566 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 567 struct usb_tt *tt, gfp_t mem_flags) 568 { 569 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 570 if (!hdev->parent) 571 xhci_find_lpm_incapable_ports(hcd, hdev); 572 573 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 574 } 575 576 /* 577 * We need to register our own PCI probe function (instead of the USB core's 578 * function) in order to create a second roothub under xHCI. 579 */ 580 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) 581 { 582 int retval; 583 struct xhci_hcd *xhci; 584 struct usb_hcd *hcd; 585 struct reset_control *reset; 586 587 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 588 if (IS_ERR(reset)) 589 return PTR_ERR(reset); 590 reset_control_reset(reset); 591 592 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 593 pm_runtime_get_noresume(&dev->dev); 594 595 /* Register the USB 2.0 roothub. 596 * FIXME: USB core must know to register the USB 2.0 roothub first. 597 * This is sort of silly, because we could just set the HCD driver flags 598 * to say USB 2.0, but I'm not sure what the implications would be in 599 * the other parts of the HCD code. 600 */ 601 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 602 603 if (retval) 604 goto put_runtime_pm; 605 606 /* USB 2.0 roothub is stored in the PCI device now. */ 607 hcd = dev_get_drvdata(&dev->dev); 608 xhci = hcd_to_xhci(hcd); 609 xhci->reset = reset; 610 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 611 pci_name(dev), hcd); 612 if (!xhci->shared_hcd) { 613 retval = -ENOMEM; 614 goto dealloc_usb2_hcd; 615 } 616 617 retval = xhci_ext_cap_init(xhci); 618 if (retval) 619 goto put_usb3_hcd; 620 621 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 622 IRQF_SHARED); 623 if (retval) 624 goto put_usb3_hcd; 625 /* Roothub already marked as USB 3.0 speed */ 626 627 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 628 HCC_MAX_PSA(xhci->hcc_params) >= 4) 629 xhci->shared_hcd->can_do_streams = 1; 630 631 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 632 pm_runtime_put_noidle(&dev->dev); 633 634 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 635 pm_runtime_get(&dev->dev); 636 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 637 pm_runtime_allow(&dev->dev); 638 639 dma_set_max_seg_size(&dev->dev, UINT_MAX); 640 641 if (device_property_read_bool(&dev->dev, "ti,pwron-active-high")) 642 pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22); 643 644 return 0; 645 646 put_usb3_hcd: 647 usb_put_hcd(xhci->shared_hcd); 648 dealloc_usb2_hcd: 649 usb_hcd_pci_remove(dev); 650 put_runtime_pm: 651 pm_runtime_put_noidle(&dev->dev); 652 return retval; 653 } 654 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, xhci); 655 656 static const struct pci_device_id pci_ids_reject[] = { 657 /* handled by xhci-pci-renesas */ 658 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, 659 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, 660 { /* end: all zeroes */ } 661 }; 662 663 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 664 { 665 if (pci_match_id(pci_ids_reject, dev)) 666 return -ENODEV; 667 668 return xhci_pci_common_probe(dev, id); 669 } 670 671 void xhci_pci_remove(struct pci_dev *dev) 672 { 673 struct xhci_hcd *xhci; 674 bool set_power_d3; 675 676 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 677 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 678 679 xhci->xhc_state |= XHCI_STATE_REMOVING; 680 681 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 682 pm_runtime_put(&dev->dev); 683 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 684 pm_runtime_forbid(&dev->dev); 685 686 if (xhci->shared_hcd) { 687 usb_remove_hcd(xhci->shared_hcd); 688 usb_put_hcd(xhci->shared_hcd); 689 xhci->shared_hcd = NULL; 690 } 691 692 usb_hcd_pci_remove(dev); 693 694 /* Workaround for spurious wakeups at shutdown with HSW */ 695 if (set_power_d3) 696 pci_set_power_state(dev, PCI_D3hot); 697 } 698 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, xhci); 699 700 /* 701 * In some Intel xHCI controllers, in order to get D3 working, 702 * through a vendor specific SSIC CONFIG register at offset 0x883c, 703 * SSIC PORT need to be marked as "unused" before putting xHCI 704 * into D3. After D3 exit, the SSIC port need to be marked as "used". 705 * Without this change, xHCI might not enter D3 state. 706 */ 707 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 708 { 709 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 710 u32 val; 711 void __iomem *reg; 712 int i; 713 714 for (i = 0; i < SSIC_PORT_NUM; i++) { 715 reg = (void __iomem *) xhci->cap_regs + 716 SSIC_PORT_CFG2 + 717 i * SSIC_PORT_CFG2_OFFSET; 718 719 /* Notify SSIC that SSIC profile programming is not done. */ 720 val = readl(reg) & ~PROG_DONE; 721 writel(val, reg); 722 723 /* Mark SSIC port as unused(suspend) or used(resume) */ 724 val = readl(reg); 725 if (suspend) 726 val |= SSIC_PORT_UNUSED; 727 else 728 val &= ~SSIC_PORT_UNUSED; 729 writel(val, reg); 730 731 /* Notify SSIC that SSIC profile programming is done */ 732 val = readl(reg) | PROG_DONE; 733 writel(val, reg); 734 readl(reg); 735 } 736 } 737 738 /* 739 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 740 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 741 */ 742 static void xhci_pme_quirk(struct usb_hcd *hcd) 743 { 744 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 745 void __iomem *reg; 746 u32 val; 747 748 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 749 val = readl(reg); 750 writel(val | BIT(28), reg); 751 readl(reg); 752 } 753 754 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 755 { 756 u32 reg; 757 758 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 759 reg &= ~BIT(SPARSE_DISABLE_BIT); 760 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 761 } 762 763 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 764 { 765 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 766 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 767 int ret; 768 769 /* 770 * Systems with the TI redriver that loses port status change events 771 * need to have the registers polled during D3, so avoid D3cold. 772 */ 773 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 774 pci_d3cold_disable(pdev); 775 776 #ifdef CONFIG_SUSPEND 777 /* d3cold is broken, but only when s2idle is used */ 778 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 779 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 780 pci_d3cold_disable(pdev); 781 #endif 782 783 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 784 xhci_pme_quirk(hcd); 785 786 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 787 xhci_ssic_port_unused_quirk(hcd, true); 788 789 if (xhci->quirks & XHCI_DISABLE_SPARSE) 790 xhci_sparse_control_quirk(hcd); 791 792 ret = xhci_suspend(xhci, do_wakeup); 793 794 /* synchronize irq when using MSI-X */ 795 xhci_msix_sync_irqs(xhci); 796 797 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 798 xhci_ssic_port_unused_quirk(hcd, false); 799 800 return ret; 801 } 802 803 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 804 { 805 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 806 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 807 808 reset_control_reset(xhci->reset); 809 810 /* The BIOS on systems with the Intel Panther Point chipset may or may 811 * not support xHCI natively. That means that during system resume, it 812 * may switch the ports back to EHCI so that users can use their 813 * keyboard to select a kernel from GRUB after resume from hibernate. 814 * 815 * The BIOS is supposed to remember whether the OS had xHCI ports 816 * enabled before resume, and switch the ports back to xHCI when the 817 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 818 * writers. 819 * 820 * Unconditionally switch the ports back to xHCI after a system resume. 821 * It should not matter whether the EHCI or xHCI controller is 822 * resumed first. It's enough to do the switchover in xHCI because 823 * USB core won't notice anything as the hub driver doesn't start 824 * running again until after all the devices (including both EHCI and 825 * xHCI host controllers) have been resumed. 826 */ 827 828 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 829 usb_enable_intel_xhci_ports(pdev); 830 831 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 832 xhci_ssic_port_unused_quirk(hcd, false); 833 834 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 835 xhci_pme_quirk(hcd); 836 837 return xhci_resume(xhci, msg); 838 } 839 840 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 841 { 842 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 843 struct xhci_port *port; 844 struct usb_device *udev; 845 u32 portsc; 846 int i; 847 848 /* 849 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 850 * cause significant boot delay if usb ports are in suspended U3 state 851 * during boot. Some USB devices survive in U3 state over S4 hibernate 852 * 853 * Disable ports that are in U3 if remote wake is not enabled for either 854 * host controller or connected device 855 */ 856 857 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 858 return 0; 859 860 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 861 port = &xhci->hw_ports[i]; 862 portsc = readl(port->addr); 863 864 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 865 continue; 866 867 if (!port->slot_id || !xhci->devs[port->slot_id]) { 868 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 869 port->slot_id, port->rhub->hcd->self.busnum, 870 port->hcd_portnum + 1); 871 continue; 872 } 873 874 udev = xhci->devs[port->slot_id]->udev; 875 876 /* if wakeup is enabled then don't disable the port */ 877 if (udev->do_remote_wakeup && do_wakeup) 878 continue; 879 880 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 881 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 882 portsc = xhci_port_state_to_neutral(portsc); 883 writel(portsc | PORT_PE, port->addr); 884 } 885 886 return 0; 887 } 888 889 static void xhci_pci_shutdown(struct usb_hcd *hcd) 890 { 891 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 892 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 893 894 xhci_shutdown(hcd); 895 xhci_cleanup_msix(xhci); 896 897 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 898 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 899 pci_set_power_state(pdev, PCI_D3hot); 900 } 901 902 /*-------------------------------------------------------------------------*/ 903 904 /* PCI driver selection metadata; PCI hotplugging uses this */ 905 static const struct pci_device_id pci_ids[] = { 906 /* handle any USB 3.0 xHCI controller */ 907 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 908 }, 909 { /* end: all zeroes */ } 910 }; 911 MODULE_DEVICE_TABLE(pci, pci_ids); 912 913 /* pci driver glue; this is a "new style" PCI driver module */ 914 static struct pci_driver xhci_pci_driver = { 915 .name = hcd_name, 916 .id_table = pci_ids, 917 918 .probe = xhci_pci_probe, 919 .remove = xhci_pci_remove, 920 /* suspend and resume implemented later */ 921 922 .shutdown = usb_hcd_pci_shutdown, 923 .driver = { 924 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 925 }, 926 }; 927 928 static int __init xhci_pci_init(void) 929 { 930 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 931 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 932 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 933 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 934 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 935 xhci_pci_hc_driver.stop = xhci_pci_stop; 936 return pci_register_driver(&xhci_pci_driver); 937 } 938 module_init(xhci_pci_init); 939 940 static void __exit xhci_pci_exit(void) 941 { 942 pci_unregister_driver(&xhci_pci_driver); 943 } 944 module_exit(xhci_pci_exit); 945 946 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 947 MODULE_LICENSE("GPL"); 948