1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 53 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed 54 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 55 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 56 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 57 58 #define PCI_VENDOR_ID_PHYTIUM 0x1db7 59 #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27 60 61 /* Thunderbolt */ 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 64 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 65 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 66 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 67 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 68 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 69 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 70 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 71 72 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 73 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 74 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 75 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 76 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 77 78 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 79 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 80 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 81 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 82 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 83 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 84 85 #define PCI_DEVICE_ID_CADENCE 0x17CD 86 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200 87 88 static const char hcd_name[] = "xhci_hcd"; 89 90 static struct hc_driver __read_mostly xhci_pci_hc_driver; 91 92 static int xhci_pci_setup(struct usb_hcd *hcd); 93 static int xhci_pci_run(struct usb_hcd *hcd); 94 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 95 struct usb_tt *tt, gfp_t mem_flags); 96 97 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 98 .reset = xhci_pci_setup, 99 .start = xhci_pci_run, 100 .update_hub_device = xhci_pci_update_hub_device, 101 }; 102 103 /* 104 * Primary Legacy and MSI IRQ are synced in suspend_common(). 105 * All MSI-X IRQs and secondary MSI IRQs should be synced here. 106 */ 107 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 108 { 109 struct usb_hcd *hcd = xhci_to_hcd(xhci); 110 111 if (hcd->msix_enabled) { 112 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 113 114 /* for now, the driver only supports one primary interrupter */ 115 synchronize_irq(pci_irq_vector(pdev, 0)); 116 } 117 } 118 119 /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */ 120 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 121 { 122 struct usb_hcd *hcd = xhci_to_hcd(xhci); 123 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 124 125 if (hcd->irq > 0) 126 return; 127 128 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 129 pci_free_irq_vectors(pdev); 130 hcd->msix_enabled = 0; 131 } 132 133 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 134 static int xhci_try_enable_msi(struct usb_hcd *hcd) 135 { 136 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 137 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 138 int ret; 139 140 /* 141 * Some Fresco Logic host controllers advertise MSI, but fail to 142 * generate interrupts. Don't even try to enable MSI. 143 */ 144 if (xhci->quirks & XHCI_BROKEN_MSI) 145 goto legacy_irq; 146 147 /* unregister the legacy interrupt */ 148 if (hcd->irq) 149 free_irq(hcd->irq, hcd); 150 hcd->irq = 0; 151 152 /* 153 * calculate number of MSI-X vectors supported. 154 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 155 * with max number of interrupters based on the xhci HCSPARAMS1. 156 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 157 * Add additional 1 vector to ensure always available interrupt. 158 */ 159 xhci->nvecs = min(num_online_cpus() + 1, 160 HCS_MAX_INTRS(xhci->hcs_params1)); 161 162 /* TODO: Check with MSI Soc for sysdev */ 163 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 164 PCI_IRQ_MSIX | PCI_IRQ_MSI); 165 if (xhci->nvecs < 0) { 166 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 167 "failed to allocate IRQ vectors"); 168 goto legacy_irq; 169 } 170 171 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 172 xhci_to_hcd(xhci)); 173 if (ret) 174 goto free_irq_vectors; 175 176 hcd->msi_enabled = 1; 177 hcd->msix_enabled = pdev->msix_enabled; 178 return 0; 179 180 free_irq_vectors: 181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 182 pdev->msix_enabled ? "MSI-X" : "MSI"); 183 pci_free_irq_vectors(pdev); 184 185 legacy_irq: 186 if (!pdev->irq) { 187 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 188 return -EINVAL; 189 } 190 191 if (!strlen(hcd->irq_descr)) 192 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 193 hcd->driver->description, hcd->self.busnum); 194 195 /* fall back to legacy interrupt */ 196 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 197 if (ret) { 198 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 199 return ret; 200 } 201 hcd->irq = pdev->irq; 202 return 0; 203 } 204 205 static int xhci_pci_run(struct usb_hcd *hcd) 206 { 207 int ret; 208 209 if (usb_hcd_is_primary_hcd(hcd)) { 210 ret = xhci_try_enable_msi(hcd); 211 if (ret) 212 return ret; 213 } 214 215 return xhci_run(hcd); 216 } 217 218 static void xhci_pci_stop(struct usb_hcd *hcd) 219 { 220 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 221 222 xhci_stop(hcd); 223 224 if (usb_hcd_is_primary_hcd(hcd)) 225 xhci_cleanup_msix(xhci); 226 } 227 228 /* called after powerup, by probe or system-pm "wakeup" */ 229 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 230 { 231 /* 232 * TODO: Implement finding debug ports later. 233 * TODO: see if there are any quirks that need to be added to handle 234 * new extended capabilities. 235 */ 236 237 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 238 if (!pci_set_mwi(pdev)) 239 xhci_dbg(xhci, "MWI active\n"); 240 241 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 242 return 0; 243 } 244 245 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 246 { 247 struct pci_dev *pdev = to_pci_dev(dev); 248 249 /* Look for vendor-specific quirks */ 250 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 251 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 252 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 253 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 254 pdev->revision == 0x0) { 255 xhci->quirks |= XHCI_RESET_EP_QUIRK; 256 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 257 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 258 } 259 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 260 pdev->revision == 0x4) { 261 xhci->quirks |= XHCI_SLOW_SUSPEND; 262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 263 "QUIRK: Fresco Logic xHC revision %u" 264 "must be suspended extra slowly", 265 pdev->revision); 266 } 267 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 268 xhci->quirks |= XHCI_BROKEN_STREAMS; 269 /* Fresco Logic confirms: all revisions of this chip do not 270 * support MSI, even though some of them claim to in their PCI 271 * capabilities. 272 */ 273 xhci->quirks |= XHCI_BROKEN_MSI; 274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 275 "QUIRK: Fresco Logic revision %u " 276 "has broken MSI implementation", 277 pdev->revision); 278 } 279 280 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 281 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 282 xhci->quirks |= XHCI_BROKEN_STREAMS; 283 284 if (pdev->vendor == PCI_VENDOR_ID_NEC) 285 xhci->quirks |= XHCI_NEC_HOST; 286 287 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 288 xhci->quirks |= XHCI_AMD_0x96_HOST; 289 290 /* AMD PLL quirk */ 291 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 292 xhci->quirks |= XHCI_AMD_PLL_FIX; 293 294 if (pdev->vendor == PCI_VENDOR_ID_AMD && 295 (pdev->device == 0x145c || 296 pdev->device == 0x15e0 || 297 pdev->device == 0x15e1 || 298 pdev->device == 0x43bb)) 299 xhci->quirks |= XHCI_SUSPEND_DELAY; 300 301 if (pdev->vendor == PCI_VENDOR_ID_AMD && 302 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 303 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 304 305 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 306 xhci->quirks |= XHCI_DISABLE_SPARSE; 307 xhci->quirks |= XHCI_RESET_ON_RESUME; 308 } 309 310 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 311 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 312 313 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 314 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 315 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 316 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 317 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 318 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 319 320 if (pdev->vendor == PCI_VENDOR_ID_AMD && 321 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 322 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 323 324 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 325 xhci->quirks |= XHCI_LPM_SUPPORT; 326 xhci->quirks |= XHCI_INTEL_HOST; 327 xhci->quirks |= XHCI_AVOID_BEI; 328 } 329 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 330 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 331 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 332 xhci->limit_active_eps = 64; 333 xhci->quirks |= XHCI_SW_BW_CHECKING; 334 /* 335 * PPT desktop boards DH77EB and DH77DF will power back on after 336 * a few seconds of being shutdown. The fix for this is to 337 * switch the ports from xHCI to EHCI on shutdown. We can't use 338 * DMI information to find those particular boards (since each 339 * vendor will change the board name), so we have to key off all 340 * PPT chipsets. 341 */ 342 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 343 } 344 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 345 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 346 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 347 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 348 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 349 } 350 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 351 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 352 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 353 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 354 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 355 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 356 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 357 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 358 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 359 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 360 } 361 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 362 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 363 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 364 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 365 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 366 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 367 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 368 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 369 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 370 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 371 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 372 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 373 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 374 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 375 xhci->quirks |= XHCI_MISSING_CAS; 376 377 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 378 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || 379 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 380 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 381 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 382 383 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 384 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 385 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 386 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 389 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 390 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 391 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 392 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 393 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 394 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 395 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 396 397 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 398 pdev->device == PCI_DEVICE_ID_EJ168) { 399 xhci->quirks |= XHCI_RESET_ON_RESUME; 400 xhci->quirks |= XHCI_BROKEN_STREAMS; 401 } 402 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 403 pdev->device == PCI_DEVICE_ID_EJ188) { 404 xhci->quirks |= XHCI_RESET_ON_RESUME; 405 xhci->quirks |= XHCI_BROKEN_STREAMS; 406 } 407 408 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 409 pdev->device == 0x0014) { 410 xhci->quirks |= XHCI_ZERO_64B_REGS; 411 } 412 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 413 pdev->device == 0x0015) { 414 xhci->quirks |= XHCI_RESET_ON_RESUME; 415 xhci->quirks |= XHCI_ZERO_64B_REGS; 416 } 417 if (pdev->vendor == PCI_VENDOR_ID_VIA) 418 xhci->quirks |= XHCI_RESET_ON_RESUME; 419 420 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM && 421 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) 422 xhci->quirks |= XHCI_RESET_ON_RESUME; 423 424 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 425 if (pdev->vendor == PCI_VENDOR_ID_VIA && 426 pdev->device == 0x3432) 427 xhci->quirks |= XHCI_BROKEN_STREAMS; 428 429 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 430 xhci->quirks |= XHCI_LPM_SUPPORT; 431 432 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 433 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 434 /* 435 * try to tame the ASMedia 1042 controller which reports 0.96 436 * but appears to behave more like 1.0 437 */ 438 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 439 xhci->quirks |= XHCI_BROKEN_STREAMS; 440 } 441 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 442 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 443 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 444 } 445 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 446 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 447 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 448 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 449 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 450 451 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 452 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 453 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 454 455 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 456 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) 457 xhci->quirks |= XHCI_RESET_ON_RESUME; 458 459 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 460 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 461 462 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 463 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 464 pdev->device == 0x9026) 465 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 466 467 if (pdev->vendor == PCI_VENDOR_ID_AMD && 468 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 469 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 470 xhci->quirks |= XHCI_NO_SOFT_RETRY; 471 472 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 473 xhci->quirks |= XHCI_ZHAOXIN_HOST; 474 xhci->quirks |= XHCI_LPM_SUPPORT; 475 476 if (pdev->device == 0x9202) { 477 xhci->quirks |= XHCI_RESET_ON_RESUME; 478 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 479 } 480 481 if (pdev->device == 0x9203) 482 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 483 } 484 485 if (pdev->vendor == PCI_DEVICE_ID_CADENCE && 486 pdev->device == PCI_DEVICE_ID_CADENCE_SSP) 487 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 488 489 /* xHC spec requires PCI devices to support D3hot and D3cold */ 490 if (xhci->hci_version >= 0x120) 491 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 492 493 if (xhci->quirks & XHCI_RESET_ON_RESUME) 494 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 495 "QUIRK: Resetting on resume"); 496 } 497 498 #ifdef CONFIG_ACPI 499 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 500 { 501 static const guid_t intel_dsm_guid = 502 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 503 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 504 union acpi_object *obj; 505 506 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 507 NULL); 508 ACPI_FREE(obj); 509 } 510 511 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 512 { 513 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 514 struct xhci_hub *rhub = &xhci->usb3_rhub; 515 int ret; 516 int i; 517 518 /* This is not the usb3 roothub we are looking for */ 519 if (hcd != rhub->hcd) 520 return; 521 522 if (hdev->maxchild > rhub->num_ports) { 523 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 524 return; 525 } 526 527 for (i = 0; i < hdev->maxchild; i++) { 528 ret = usb_acpi_port_lpm_incapable(hdev, i); 529 530 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 531 532 if (ret >= 0) { 533 rhub->ports[i]->lpm_incapable = ret; 534 continue; 535 } 536 } 537 } 538 539 #else 540 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 541 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 542 #endif /* CONFIG_ACPI */ 543 544 /* called during probe() after chip reset completes */ 545 static int xhci_pci_setup(struct usb_hcd *hcd) 546 { 547 struct xhci_hcd *xhci; 548 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 549 int retval; 550 u8 sbrn; 551 552 xhci = hcd_to_xhci(hcd); 553 554 /* imod_interval is the interrupt moderation value in nanoseconds. */ 555 xhci->imod_interval = 40000; 556 557 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 558 if (retval) 559 return retval; 560 561 if (!usb_hcd_is_primary_hcd(hcd)) 562 return 0; 563 564 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 565 xhci_pme_acpi_rtd3_enable(pdev); 566 567 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn); 568 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn); 569 570 /* Find any debug ports */ 571 return xhci_pci_reinit(xhci, pdev); 572 } 573 574 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 575 struct usb_tt *tt, gfp_t mem_flags) 576 { 577 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 578 if (!hdev->parent) 579 xhci_find_lpm_incapable_ports(hcd, hdev); 580 581 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 582 } 583 584 /* 585 * We need to register our own PCI probe function (instead of the USB core's 586 * function) in order to create a second roothub under xHCI. 587 */ 588 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) 589 { 590 int retval; 591 struct xhci_hcd *xhci; 592 struct usb_hcd *hcd; 593 struct reset_control *reset; 594 595 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 596 if (IS_ERR(reset)) 597 return PTR_ERR(reset); 598 reset_control_reset(reset); 599 600 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 601 pm_runtime_get_noresume(&dev->dev); 602 603 /* Register the USB 2.0 roothub. 604 * FIXME: USB core must know to register the USB 2.0 roothub first. 605 * This is sort of silly, because we could just set the HCD driver flags 606 * to say USB 2.0, but I'm not sure what the implications would be in 607 * the other parts of the HCD code. 608 */ 609 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 610 611 if (retval) 612 goto put_runtime_pm; 613 614 /* USB 2.0 roothub is stored in the PCI device now. */ 615 hcd = dev_get_drvdata(&dev->dev); 616 xhci = hcd_to_xhci(hcd); 617 xhci->reset = reset; 618 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 619 pci_name(dev), hcd); 620 if (!xhci->shared_hcd) { 621 retval = -ENOMEM; 622 goto dealloc_usb2_hcd; 623 } 624 625 retval = xhci_ext_cap_init(xhci); 626 if (retval) 627 goto put_usb3_hcd; 628 629 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 630 IRQF_SHARED); 631 if (retval) 632 goto put_usb3_hcd; 633 /* Roothub already marked as USB 3.0 speed */ 634 635 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 636 HCC_MAX_PSA(xhci->hcc_params) >= 4) 637 xhci->shared_hcd->can_do_streams = 1; 638 639 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 640 pm_runtime_put_noidle(&dev->dev); 641 642 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 643 pm_runtime_forbid(&dev->dev); 644 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 645 pm_runtime_allow(&dev->dev); 646 647 dma_set_max_seg_size(&dev->dev, UINT_MAX); 648 649 return 0; 650 651 put_usb3_hcd: 652 usb_put_hcd(xhci->shared_hcd); 653 dealloc_usb2_hcd: 654 usb_hcd_pci_remove(dev); 655 put_runtime_pm: 656 pm_runtime_put_noidle(&dev->dev); 657 return retval; 658 } 659 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, xhci); 660 661 static const struct pci_device_id pci_ids_reject[] = { 662 /* handled by xhci-pci-renesas */ 663 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, 664 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, 665 { /* end: all zeroes */ } 666 }; 667 668 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 669 { 670 if (pci_match_id(pci_ids_reject, dev)) 671 return -ENODEV; 672 673 return xhci_pci_common_probe(dev, id); 674 } 675 676 void xhci_pci_remove(struct pci_dev *dev) 677 { 678 struct xhci_hcd *xhci; 679 bool set_power_d3; 680 681 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 682 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 683 684 xhci->xhc_state |= XHCI_STATE_REMOVING; 685 686 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 687 pm_runtime_forbid(&dev->dev); 688 689 if (xhci->shared_hcd) { 690 usb_remove_hcd(xhci->shared_hcd); 691 usb_put_hcd(xhci->shared_hcd); 692 xhci->shared_hcd = NULL; 693 } 694 695 usb_hcd_pci_remove(dev); 696 697 /* Workaround for spurious wakeups at shutdown with HSW */ 698 if (set_power_d3) 699 pci_set_power_state(dev, PCI_D3hot); 700 } 701 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, xhci); 702 703 /* 704 * In some Intel xHCI controllers, in order to get D3 working, 705 * through a vendor specific SSIC CONFIG register at offset 0x883c, 706 * SSIC PORT need to be marked as "unused" before putting xHCI 707 * into D3. After D3 exit, the SSIC port need to be marked as "used". 708 * Without this change, xHCI might not enter D3 state. 709 */ 710 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 711 { 712 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 713 u32 val; 714 void __iomem *reg; 715 int i; 716 717 for (i = 0; i < SSIC_PORT_NUM; i++) { 718 reg = (void __iomem *) xhci->cap_regs + 719 SSIC_PORT_CFG2 + 720 i * SSIC_PORT_CFG2_OFFSET; 721 722 /* Notify SSIC that SSIC profile programming is not done. */ 723 val = readl(reg) & ~PROG_DONE; 724 writel(val, reg); 725 726 /* Mark SSIC port as unused(suspend) or used(resume) */ 727 val = readl(reg); 728 if (suspend) 729 val |= SSIC_PORT_UNUSED; 730 else 731 val &= ~SSIC_PORT_UNUSED; 732 writel(val, reg); 733 734 /* Notify SSIC that SSIC profile programming is done */ 735 val = readl(reg) | PROG_DONE; 736 writel(val, reg); 737 readl(reg); 738 } 739 } 740 741 /* 742 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 743 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 744 */ 745 static void xhci_pme_quirk(struct usb_hcd *hcd) 746 { 747 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 748 void __iomem *reg; 749 u32 val; 750 751 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 752 val = readl(reg); 753 writel(val | BIT(28), reg); 754 readl(reg); 755 } 756 757 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 758 { 759 u32 reg; 760 761 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 762 reg &= ~BIT(SPARSE_DISABLE_BIT); 763 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 764 } 765 766 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 767 { 768 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 769 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 770 int ret; 771 772 /* 773 * Systems with the TI redriver that loses port status change events 774 * need to have the registers polled during D3, so avoid D3cold. 775 */ 776 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 777 pci_d3cold_disable(pdev); 778 779 #ifdef CONFIG_SUSPEND 780 /* d3cold is broken, but only when s2idle is used */ 781 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 782 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 783 pci_d3cold_disable(pdev); 784 #endif 785 786 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 787 xhci_pme_quirk(hcd); 788 789 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 790 xhci_ssic_port_unused_quirk(hcd, true); 791 792 if (xhci->quirks & XHCI_DISABLE_SPARSE) 793 xhci_sparse_control_quirk(hcd); 794 795 ret = xhci_suspend(xhci, do_wakeup); 796 797 /* synchronize irq when using MSI-X */ 798 xhci_msix_sync_irqs(xhci); 799 800 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 801 xhci_ssic_port_unused_quirk(hcd, false); 802 803 return ret; 804 } 805 806 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 807 { 808 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 809 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 810 811 reset_control_reset(xhci->reset); 812 813 /* The BIOS on systems with the Intel Panther Point chipset may or may 814 * not support xHCI natively. That means that during system resume, it 815 * may switch the ports back to EHCI so that users can use their 816 * keyboard to select a kernel from GRUB after resume from hibernate. 817 * 818 * The BIOS is supposed to remember whether the OS had xHCI ports 819 * enabled before resume, and switch the ports back to xHCI when the 820 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 821 * writers. 822 * 823 * Unconditionally switch the ports back to xHCI after a system resume. 824 * It should not matter whether the EHCI or xHCI controller is 825 * resumed first. It's enough to do the switchover in xHCI because 826 * USB core won't notice anything as the hub driver doesn't start 827 * running again until after all the devices (including both EHCI and 828 * xHCI host controllers) have been resumed. 829 */ 830 831 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 832 usb_enable_intel_xhci_ports(pdev); 833 834 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 835 xhci_ssic_port_unused_quirk(hcd, false); 836 837 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 838 xhci_pme_quirk(hcd); 839 840 return xhci_resume(xhci, msg); 841 } 842 843 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 844 { 845 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 846 struct xhci_port *port; 847 struct usb_device *udev; 848 u32 portsc; 849 int i; 850 851 /* 852 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 853 * cause significant boot delay if usb ports are in suspended U3 state 854 * during boot. Some USB devices survive in U3 state over S4 hibernate 855 * 856 * Disable ports that are in U3 if remote wake is not enabled for either 857 * host controller or connected device 858 */ 859 860 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 861 return 0; 862 863 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 864 port = &xhci->hw_ports[i]; 865 portsc = readl(port->addr); 866 867 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 868 continue; 869 870 if (!port->slot_id || !xhci->devs[port->slot_id]) { 871 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 872 port->slot_id, port->rhub->hcd->self.busnum, 873 port->hcd_portnum + 1); 874 continue; 875 } 876 877 udev = xhci->devs[port->slot_id]->udev; 878 879 /* if wakeup is enabled then don't disable the port */ 880 if (udev->do_remote_wakeup && do_wakeup) 881 continue; 882 883 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 884 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 885 portsc = xhci_port_state_to_neutral(portsc); 886 writel(portsc | PORT_PE, port->addr); 887 } 888 889 return 0; 890 } 891 892 static void xhci_pci_shutdown(struct usb_hcd *hcd) 893 { 894 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 895 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 896 897 xhci_shutdown(hcd); 898 xhci_cleanup_msix(xhci); 899 900 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 901 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 902 pci_set_power_state(pdev, PCI_D3hot); 903 } 904 905 /*-------------------------------------------------------------------------*/ 906 907 /* PCI driver selection metadata; PCI hotplugging uses this */ 908 static const struct pci_device_id pci_ids[] = { 909 /* handle any USB 3.0 xHCI controller */ 910 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 911 }, 912 { /* end: all zeroes */ } 913 }; 914 MODULE_DEVICE_TABLE(pci, pci_ids); 915 916 /* pci driver glue; this is a "new style" PCI driver module */ 917 static struct pci_driver xhci_pci_driver = { 918 .name = hcd_name, 919 .id_table = pci_ids, 920 921 .probe = xhci_pci_probe, 922 .remove = xhci_pci_remove, 923 /* suspend and resume implemented later */ 924 925 .shutdown = usb_hcd_pci_shutdown, 926 .driver = { 927 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 928 }, 929 }; 930 931 static int __init xhci_pci_init(void) 932 { 933 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 934 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 935 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 936 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 937 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 938 xhci_pci_hc_driver.stop = xhci_pci_stop; 939 return pci_register_driver(&xhci_pci_driver); 940 } 941 module_init(xhci_pci_init); 942 943 static void __exit xhci_pci_exit(void) 944 { 945 pci_unregister_driver(&xhci_pci_driver); 946 } 947 module_exit(xhci_pci_exit); 948 949 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 950 MODULE_LICENSE("GPL"); 951