1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 53 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 54 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 55 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 56 57 /* Thunderbolt */ 58 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 59 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 60 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 61 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 62 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 63 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 64 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 65 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 66 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 67 68 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 72 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 73 74 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 75 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 76 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 77 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 78 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 79 80 static const char hcd_name[] = "xhci_hcd"; 81 82 static struct hc_driver __read_mostly xhci_pci_hc_driver; 83 84 static int xhci_pci_setup(struct usb_hcd *hcd); 85 static int xhci_pci_run(struct usb_hcd *hcd); 86 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 87 struct usb_tt *tt, gfp_t mem_flags); 88 89 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 90 .reset = xhci_pci_setup, 91 .start = xhci_pci_run, 92 .update_hub_device = xhci_pci_update_hub_device, 93 }; 94 95 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 96 { 97 struct usb_hcd *hcd = xhci_to_hcd(xhci); 98 99 if (hcd->msix_enabled) { 100 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 101 102 /* for now, the driver only supports one primary interrupter */ 103 synchronize_irq(pci_irq_vector(pdev, 0)); 104 } 105 } 106 107 /* Free any IRQs and disable MSI-X */ 108 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 109 { 110 struct usb_hcd *hcd = xhci_to_hcd(xhci); 111 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 112 113 /* return if using legacy interrupt */ 114 if (hcd->irq > 0) 115 return; 116 117 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 118 pci_free_irq_vectors(pdev); 119 hcd->msix_enabled = 0; 120 } 121 122 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 123 static int xhci_try_enable_msi(struct usb_hcd *hcd) 124 { 125 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 126 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 127 int ret; 128 129 /* 130 * Some Fresco Logic host controllers advertise MSI, but fail to 131 * generate interrupts. Don't even try to enable MSI. 132 */ 133 if (xhci->quirks & XHCI_BROKEN_MSI) 134 goto legacy_irq; 135 136 /* unregister the legacy interrupt */ 137 if (hcd->irq) 138 free_irq(hcd->irq, hcd); 139 hcd->irq = 0; 140 141 /* 142 * calculate number of MSI-X vectors supported. 143 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 144 * with max number of interrupters based on the xhci HCSPARAMS1. 145 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 146 * Add additional 1 vector to ensure always available interrupt. 147 */ 148 xhci->nvecs = min(num_online_cpus() + 1, 149 HCS_MAX_INTRS(xhci->hcs_params1)); 150 151 /* TODO: Check with MSI Soc for sysdev */ 152 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 153 PCI_IRQ_MSIX | PCI_IRQ_MSI); 154 if (xhci->nvecs < 0) { 155 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 156 "failed to allocate IRQ vectors"); 157 goto legacy_irq; 158 } 159 160 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 161 xhci_to_hcd(xhci)); 162 if (ret) 163 goto free_irq_vectors; 164 165 hcd->msi_enabled = 1; 166 hcd->msix_enabled = pdev->msix_enabled; 167 return 0; 168 169 free_irq_vectors: 170 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 171 pdev->msix_enabled ? "MSI-X" : "MSI"); 172 pci_free_irq_vectors(pdev); 173 174 legacy_irq: 175 if (!pdev->irq) { 176 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 177 return -EINVAL; 178 } 179 180 if (!strlen(hcd->irq_descr)) 181 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 182 hcd->driver->description, hcd->self.busnum); 183 184 /* fall back to legacy interrupt */ 185 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 186 if (ret) { 187 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 188 return ret; 189 } 190 hcd->irq = pdev->irq; 191 return 0; 192 } 193 194 static int xhci_pci_run(struct usb_hcd *hcd) 195 { 196 int ret; 197 198 if (usb_hcd_is_primary_hcd(hcd)) { 199 ret = xhci_try_enable_msi(hcd); 200 if (ret) 201 return ret; 202 } 203 204 return xhci_run(hcd); 205 } 206 207 static void xhci_pci_stop(struct usb_hcd *hcd) 208 { 209 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 210 211 xhci_stop(hcd); 212 213 if (usb_hcd_is_primary_hcd(hcd)) 214 xhci_cleanup_msix(xhci); 215 } 216 217 /* called after powerup, by probe or system-pm "wakeup" */ 218 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 219 { 220 /* 221 * TODO: Implement finding debug ports later. 222 * TODO: see if there are any quirks that need to be added to handle 223 * new extended capabilities. 224 */ 225 226 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 227 if (!pci_set_mwi(pdev)) 228 xhci_dbg(xhci, "MWI active\n"); 229 230 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 231 return 0; 232 } 233 234 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 235 { 236 struct pci_dev *pdev = to_pci_dev(dev); 237 struct xhci_driver_data *driver_data; 238 const struct pci_device_id *id; 239 240 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 241 242 if (id && id->driver_data) { 243 driver_data = (struct xhci_driver_data *)id->driver_data; 244 xhci->quirks |= driver_data->quirks; 245 } 246 247 /* Look for vendor-specific quirks */ 248 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 249 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 250 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 251 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 252 pdev->revision == 0x0) { 253 xhci->quirks |= XHCI_RESET_EP_QUIRK; 254 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 255 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 256 } 257 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 258 pdev->revision == 0x4) { 259 xhci->quirks |= XHCI_SLOW_SUSPEND; 260 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 261 "QUIRK: Fresco Logic xHC revision %u" 262 "must be suspended extra slowly", 263 pdev->revision); 264 } 265 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 266 xhci->quirks |= XHCI_BROKEN_STREAMS; 267 /* Fresco Logic confirms: all revisions of this chip do not 268 * support MSI, even though some of them claim to in their PCI 269 * capabilities. 270 */ 271 xhci->quirks |= XHCI_BROKEN_MSI; 272 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 273 "QUIRK: Fresco Logic revision %u " 274 "has broken MSI implementation", 275 pdev->revision); 276 } 277 278 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 279 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 280 xhci->quirks |= XHCI_BROKEN_STREAMS; 281 282 if (pdev->vendor == PCI_VENDOR_ID_NEC) 283 xhci->quirks |= XHCI_NEC_HOST; 284 285 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 286 xhci->quirks |= XHCI_AMD_0x96_HOST; 287 288 /* AMD PLL quirk */ 289 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 290 xhci->quirks |= XHCI_AMD_PLL_FIX; 291 292 if (pdev->vendor == PCI_VENDOR_ID_AMD && 293 (pdev->device == 0x145c || 294 pdev->device == 0x15e0 || 295 pdev->device == 0x15e1 || 296 pdev->device == 0x43bb)) 297 xhci->quirks |= XHCI_SUSPEND_DELAY; 298 299 if (pdev->vendor == PCI_VENDOR_ID_AMD && 300 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 301 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 302 303 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 304 xhci->quirks |= XHCI_DISABLE_SPARSE; 305 xhci->quirks |= XHCI_RESET_ON_RESUME; 306 } 307 308 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 309 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 310 311 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 312 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 313 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 314 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 315 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 316 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 317 318 if (pdev->vendor == PCI_VENDOR_ID_AMD && 319 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 320 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 321 322 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 323 xhci->quirks |= XHCI_LPM_SUPPORT; 324 xhci->quirks |= XHCI_INTEL_HOST; 325 xhci->quirks |= XHCI_AVOID_BEI; 326 } 327 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 328 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 329 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 330 xhci->limit_active_eps = 64; 331 xhci->quirks |= XHCI_SW_BW_CHECKING; 332 /* 333 * PPT desktop boards DH77EB and DH77DF will power back on after 334 * a few seconds of being shutdown. The fix for this is to 335 * switch the ports from xHCI to EHCI on shutdown. We can't use 336 * DMI information to find those particular boards (since each 337 * vendor will change the board name), so we have to key off all 338 * PPT chipsets. 339 */ 340 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 341 } 342 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 343 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 344 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 345 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 346 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 347 } 348 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 349 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 350 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 351 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 352 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 353 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 354 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 355 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 356 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 357 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 358 } 359 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 360 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 361 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 362 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 363 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 364 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 365 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 366 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 367 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 368 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 369 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 370 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 371 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 372 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 373 xhci->quirks |= XHCI_MISSING_CAS; 374 375 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 376 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 377 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 378 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 379 380 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 381 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 382 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 383 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 384 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 385 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 386 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 389 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 390 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 391 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 392 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 393 394 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 395 pdev->device == PCI_DEVICE_ID_EJ168) { 396 xhci->quirks |= XHCI_RESET_ON_RESUME; 397 xhci->quirks |= XHCI_BROKEN_STREAMS; 398 } 399 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 400 pdev->device == PCI_DEVICE_ID_EJ188) { 401 xhci->quirks |= XHCI_RESET_ON_RESUME; 402 xhci->quirks |= XHCI_BROKEN_STREAMS; 403 } 404 405 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 406 pdev->device == 0x0014) { 407 xhci->quirks |= XHCI_ZERO_64B_REGS; 408 } 409 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 410 pdev->device == 0x0015) { 411 xhci->quirks |= XHCI_RESET_ON_RESUME; 412 xhci->quirks |= XHCI_ZERO_64B_REGS; 413 } 414 if (pdev->vendor == PCI_VENDOR_ID_VIA) 415 xhci->quirks |= XHCI_RESET_ON_RESUME; 416 417 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 418 if (pdev->vendor == PCI_VENDOR_ID_VIA && 419 pdev->device == 0x3432) 420 xhci->quirks |= XHCI_BROKEN_STREAMS; 421 422 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 423 xhci->quirks |= XHCI_LPM_SUPPORT; 424 425 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 426 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 427 /* 428 * try to tame the ASMedia 1042 controller which reports 0.96 429 * but appears to behave more like 1.0 430 */ 431 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 432 xhci->quirks |= XHCI_BROKEN_STREAMS; 433 } 434 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 435 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 436 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 437 } 438 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 439 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 440 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 441 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 442 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 443 444 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 445 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 446 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 447 448 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 449 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 450 451 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 452 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 453 pdev->device == 0x9026) 454 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 455 456 if (pdev->vendor == PCI_VENDOR_ID_AMD && 457 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 458 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 459 xhci->quirks |= XHCI_NO_SOFT_RETRY; 460 461 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 462 xhci->quirks |= XHCI_ZHAOXIN_HOST; 463 xhci->quirks |= XHCI_LPM_SUPPORT; 464 465 if (pdev->device == 0x9202) { 466 xhci->quirks |= XHCI_RESET_ON_RESUME; 467 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 468 } 469 470 if (pdev->device == 0x9203) 471 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 472 } 473 474 /* xHC spec requires PCI devices to support D3hot and D3cold */ 475 if (xhci->hci_version >= 0x120) 476 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 477 478 if (xhci->quirks & XHCI_RESET_ON_RESUME) 479 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 480 "QUIRK: Resetting on resume"); 481 } 482 483 #ifdef CONFIG_ACPI 484 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 485 { 486 static const guid_t intel_dsm_guid = 487 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 488 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 489 union acpi_object *obj; 490 491 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 492 NULL); 493 ACPI_FREE(obj); 494 } 495 496 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 497 { 498 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 499 struct xhci_hub *rhub = &xhci->usb3_rhub; 500 int ret; 501 int i; 502 503 /* This is not the usb3 roothub we are looking for */ 504 if (hcd != rhub->hcd) 505 return; 506 507 if (hdev->maxchild > rhub->num_ports) { 508 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 509 return; 510 } 511 512 for (i = 0; i < hdev->maxchild; i++) { 513 ret = usb_acpi_port_lpm_incapable(hdev, i); 514 515 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 516 517 if (ret >= 0) { 518 rhub->ports[i]->lpm_incapable = ret; 519 continue; 520 } 521 } 522 } 523 524 #else 525 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 526 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 527 #endif /* CONFIG_ACPI */ 528 529 /* called during probe() after chip reset completes */ 530 static int xhci_pci_setup(struct usb_hcd *hcd) 531 { 532 struct xhci_hcd *xhci; 533 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 534 int retval; 535 536 xhci = hcd_to_xhci(hcd); 537 if (!xhci->sbrn) 538 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 539 540 /* imod_interval is the interrupt moderation value in nanoseconds. */ 541 xhci->imod_interval = 40000; 542 543 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 544 if (retval) 545 return retval; 546 547 if (!usb_hcd_is_primary_hcd(hcd)) 548 return 0; 549 550 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 551 xhci_pme_acpi_rtd3_enable(pdev); 552 553 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 554 555 /* Find any debug ports */ 556 return xhci_pci_reinit(xhci, pdev); 557 } 558 559 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 560 struct usb_tt *tt, gfp_t mem_flags) 561 { 562 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 563 if (!hdev->parent) 564 xhci_find_lpm_incapable_ports(hcd, hdev); 565 566 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 567 } 568 569 /* 570 * We need to register our own PCI probe function (instead of the USB core's 571 * function) in order to create a second roothub under xHCI. 572 */ 573 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 574 { 575 int retval; 576 struct xhci_hcd *xhci; 577 struct usb_hcd *hcd; 578 struct xhci_driver_data *driver_data; 579 struct reset_control *reset; 580 581 driver_data = (struct xhci_driver_data *)id->driver_data; 582 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 583 retval = renesas_xhci_check_request_fw(dev, id); 584 if (retval) 585 return retval; 586 } 587 588 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 589 if (IS_ERR(reset)) 590 return PTR_ERR(reset); 591 reset_control_reset(reset); 592 593 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 594 pm_runtime_get_noresume(&dev->dev); 595 596 /* Register the USB 2.0 roothub. 597 * FIXME: USB core must know to register the USB 2.0 roothub first. 598 * This is sort of silly, because we could just set the HCD driver flags 599 * to say USB 2.0, but I'm not sure what the implications would be in 600 * the other parts of the HCD code. 601 */ 602 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 603 604 if (retval) 605 goto put_runtime_pm; 606 607 /* USB 2.0 roothub is stored in the PCI device now. */ 608 hcd = dev_get_drvdata(&dev->dev); 609 xhci = hcd_to_xhci(hcd); 610 xhci->reset = reset; 611 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 612 pci_name(dev), hcd); 613 if (!xhci->shared_hcd) { 614 retval = -ENOMEM; 615 goto dealloc_usb2_hcd; 616 } 617 618 retval = xhci_ext_cap_init(xhci); 619 if (retval) 620 goto put_usb3_hcd; 621 622 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 623 IRQF_SHARED); 624 if (retval) 625 goto put_usb3_hcd; 626 /* Roothub already marked as USB 3.0 speed */ 627 628 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 629 HCC_MAX_PSA(xhci->hcc_params) >= 4) 630 xhci->shared_hcd->can_do_streams = 1; 631 632 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 633 pm_runtime_put_noidle(&dev->dev); 634 635 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 636 pm_runtime_forbid(&dev->dev); 637 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 638 pm_runtime_allow(&dev->dev); 639 640 dma_set_max_seg_size(&dev->dev, UINT_MAX); 641 642 return 0; 643 644 put_usb3_hcd: 645 usb_put_hcd(xhci->shared_hcd); 646 dealloc_usb2_hcd: 647 usb_hcd_pci_remove(dev); 648 put_runtime_pm: 649 pm_runtime_put_noidle(&dev->dev); 650 return retval; 651 } 652 653 static void xhci_pci_remove(struct pci_dev *dev) 654 { 655 struct xhci_hcd *xhci; 656 657 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 658 659 xhci->xhc_state |= XHCI_STATE_REMOVING; 660 661 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 662 pm_runtime_forbid(&dev->dev); 663 664 if (xhci->shared_hcd) { 665 usb_remove_hcd(xhci->shared_hcd); 666 usb_put_hcd(xhci->shared_hcd); 667 xhci->shared_hcd = NULL; 668 } 669 670 /* Workaround for spurious wakeups at shutdown with HSW */ 671 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 672 pci_set_power_state(dev, PCI_D3hot); 673 674 usb_hcd_pci_remove(dev); 675 } 676 677 /* 678 * In some Intel xHCI controllers, in order to get D3 working, 679 * through a vendor specific SSIC CONFIG register at offset 0x883c, 680 * SSIC PORT need to be marked as "unused" before putting xHCI 681 * into D3. After D3 exit, the SSIC port need to be marked as "used". 682 * Without this change, xHCI might not enter D3 state. 683 */ 684 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 685 { 686 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 687 u32 val; 688 void __iomem *reg; 689 int i; 690 691 for (i = 0; i < SSIC_PORT_NUM; i++) { 692 reg = (void __iomem *) xhci->cap_regs + 693 SSIC_PORT_CFG2 + 694 i * SSIC_PORT_CFG2_OFFSET; 695 696 /* Notify SSIC that SSIC profile programming is not done. */ 697 val = readl(reg) & ~PROG_DONE; 698 writel(val, reg); 699 700 /* Mark SSIC port as unused(suspend) or used(resume) */ 701 val = readl(reg); 702 if (suspend) 703 val |= SSIC_PORT_UNUSED; 704 else 705 val &= ~SSIC_PORT_UNUSED; 706 writel(val, reg); 707 708 /* Notify SSIC that SSIC profile programming is done */ 709 val = readl(reg) | PROG_DONE; 710 writel(val, reg); 711 readl(reg); 712 } 713 } 714 715 /* 716 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 717 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 718 */ 719 static void xhci_pme_quirk(struct usb_hcd *hcd) 720 { 721 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 722 void __iomem *reg; 723 u32 val; 724 725 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 726 val = readl(reg); 727 writel(val | BIT(28), reg); 728 readl(reg); 729 } 730 731 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 732 { 733 u32 reg; 734 735 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 736 reg &= ~BIT(SPARSE_DISABLE_BIT); 737 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 738 } 739 740 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 741 { 742 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 743 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 744 int ret; 745 746 /* 747 * Systems with the TI redriver that loses port status change events 748 * need to have the registers polled during D3, so avoid D3cold. 749 */ 750 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 751 pci_d3cold_disable(pdev); 752 753 #ifdef CONFIG_SUSPEND 754 /* d3cold is broken, but only when s2idle is used */ 755 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 756 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 757 pci_d3cold_disable(pdev); 758 #endif 759 760 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 761 xhci_pme_quirk(hcd); 762 763 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 764 xhci_ssic_port_unused_quirk(hcd, true); 765 766 if (xhci->quirks & XHCI_DISABLE_SPARSE) 767 xhci_sparse_control_quirk(hcd); 768 769 ret = xhci_suspend(xhci, do_wakeup); 770 771 /* synchronize irq when using MSI-X */ 772 xhci_msix_sync_irqs(xhci); 773 774 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 775 xhci_ssic_port_unused_quirk(hcd, false); 776 777 return ret; 778 } 779 780 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 781 { 782 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 783 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 784 int retval = 0; 785 786 reset_control_reset(xhci->reset); 787 788 /* The BIOS on systems with the Intel Panther Point chipset may or may 789 * not support xHCI natively. That means that during system resume, it 790 * may switch the ports back to EHCI so that users can use their 791 * keyboard to select a kernel from GRUB after resume from hibernate. 792 * 793 * The BIOS is supposed to remember whether the OS had xHCI ports 794 * enabled before resume, and switch the ports back to xHCI when the 795 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 796 * writers. 797 * 798 * Unconditionally switch the ports back to xHCI after a system resume. 799 * It should not matter whether the EHCI or xHCI controller is 800 * resumed first. It's enough to do the switchover in xHCI because 801 * USB core won't notice anything as the hub driver doesn't start 802 * running again until after all the devices (including both EHCI and 803 * xHCI host controllers) have been resumed. 804 */ 805 806 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 807 usb_enable_intel_xhci_ports(pdev); 808 809 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 810 xhci_ssic_port_unused_quirk(hcd, false); 811 812 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 813 xhci_pme_quirk(hcd); 814 815 retval = xhci_resume(xhci, msg); 816 return retval; 817 } 818 819 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 820 { 821 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 822 struct xhci_port *port; 823 struct usb_device *udev; 824 u32 portsc; 825 int i; 826 827 /* 828 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 829 * cause significant boot delay if usb ports are in suspended U3 state 830 * during boot. Some USB devices survive in U3 state over S4 hibernate 831 * 832 * Disable ports that are in U3 if remote wake is not enabled for either 833 * host controller or connected device 834 */ 835 836 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 837 return 0; 838 839 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 840 port = &xhci->hw_ports[i]; 841 portsc = readl(port->addr); 842 843 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 844 continue; 845 846 if (!port->slot_id || !xhci->devs[port->slot_id]) { 847 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 848 port->slot_id, port->rhub->hcd->self.busnum, 849 port->hcd_portnum + 1); 850 continue; 851 } 852 853 udev = xhci->devs[port->slot_id]->udev; 854 855 /* if wakeup is enabled then don't disable the port */ 856 if (udev->do_remote_wakeup && do_wakeup) 857 continue; 858 859 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 860 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 861 portsc = xhci_port_state_to_neutral(portsc); 862 writel(portsc | PORT_PE, port->addr); 863 } 864 865 return 0; 866 } 867 868 static void xhci_pci_shutdown(struct usb_hcd *hcd) 869 { 870 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 871 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 872 873 xhci_shutdown(hcd); 874 xhci_cleanup_msix(xhci); 875 876 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 877 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 878 pci_set_power_state(pdev, PCI_D3hot); 879 } 880 881 /*-------------------------------------------------------------------------*/ 882 883 static const struct xhci_driver_data reneses_data = { 884 .quirks = XHCI_RENESAS_FW_QUIRK, 885 .firmware = "renesas_usb_fw.mem", 886 }; 887 888 /* PCI driver selection metadata; PCI hotplugging uses this */ 889 static const struct pci_device_id pci_ids[] = { 890 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014), 891 .driver_data = (unsigned long)&reneses_data, 892 }, 893 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015), 894 .driver_data = (unsigned long)&reneses_data, 895 }, 896 /* handle any USB 3.0 xHCI controller */ 897 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 898 }, 899 { /* end: all zeroes */ } 900 }; 901 MODULE_DEVICE_TABLE(pci, pci_ids); 902 903 /* 904 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 905 * load firmware, so don't encumber the xhci-pci driver with it. 906 */ 907 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 908 MODULE_FIRMWARE("renesas_usb_fw.mem"); 909 #endif 910 911 /* pci driver glue; this is a "new style" PCI driver module */ 912 static struct pci_driver xhci_pci_driver = { 913 .name = hcd_name, 914 .id_table = pci_ids, 915 916 .probe = xhci_pci_probe, 917 .remove = xhci_pci_remove, 918 /* suspend and resume implemented later */ 919 920 .shutdown = usb_hcd_pci_shutdown, 921 .driver = { 922 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 923 }, 924 }; 925 926 static int __init xhci_pci_init(void) 927 { 928 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 929 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 930 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 931 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 932 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 933 xhci_pci_hc_driver.stop = xhci_pci_stop; 934 return pci_register_driver(&xhci_pci_driver); 935 } 936 module_init(xhci_pci_init); 937 938 static void __exit xhci_pci_exit(void) 939 { 940 pci_unregister_driver(&xhci_pci_driver); 941 } 942 module_exit(xhci_pci_exit); 943 944 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 945 MODULE_LICENSE("GPL"); 946