1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36 #define PCI_VENDOR_ID_ETRON 0x1b6f 37 #define PCI_DEVICE_ID_EJ168 0x7023 38 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 63 64 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 69 70 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 71 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 72 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 73 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 74 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 75 76 static const char hcd_name[] = "xhci_hcd"; 77 78 static struct hc_driver __read_mostly xhci_pci_hc_driver; 79 80 static int xhci_pci_setup(struct usb_hcd *hcd); 81 static int xhci_pci_run(struct usb_hcd *hcd); 82 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 83 struct usb_tt *tt, gfp_t mem_flags); 84 85 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 86 .reset = xhci_pci_setup, 87 .start = xhci_pci_run, 88 .update_hub_device = xhci_pci_update_hub_device, 89 }; 90 91 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 92 { 93 struct usb_hcd *hcd = xhci_to_hcd(xhci); 94 95 if (hcd->msix_enabled) { 96 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 97 int i; 98 99 for (i = 0; i < xhci->msix_count; i++) 100 synchronize_irq(pci_irq_vector(pdev, i)); 101 } 102 } 103 104 /* Free any IRQs and disable MSI-X */ 105 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 106 { 107 struct usb_hcd *hcd = xhci_to_hcd(xhci); 108 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 109 110 if (xhci->quirks & XHCI_PLAT) 111 return; 112 113 /* return if using legacy interrupt */ 114 if (hcd->irq > 0) 115 return; 116 117 if (hcd->msix_enabled) { 118 int i; 119 120 for (i = 0; i < xhci->msix_count; i++) 121 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 122 } else { 123 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 124 } 125 126 pci_free_irq_vectors(pdev); 127 hcd->msix_enabled = 0; 128 } 129 130 /* 131 * Set up MSI 132 */ 133 static int xhci_setup_msi(struct xhci_hcd *xhci) 134 { 135 int ret; 136 /* 137 * TODO:Check with MSI Soc for sysdev 138 */ 139 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 140 141 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 142 if (ret < 0) { 143 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 144 "failed to allocate MSI entry"); 145 return ret; 146 } 147 148 ret = request_irq(pdev->irq, xhci_msi_irq, 149 0, "xhci_hcd", xhci_to_hcd(xhci)); 150 if (ret) { 151 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 152 "disable MSI interrupt"); 153 pci_free_irq_vectors(pdev); 154 } 155 156 return ret; 157 } 158 159 /* 160 * Set up MSI-X 161 */ 162 static int xhci_setup_msix(struct xhci_hcd *xhci) 163 { 164 int i, ret; 165 struct usb_hcd *hcd = xhci_to_hcd(xhci); 166 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 167 168 /* 169 * calculate number of msi-x vectors supported. 170 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 171 * with max number of interrupters based on the xhci HCSPARAMS1. 172 * - num_online_cpus: maximum msi-x vectors per CPUs core. 173 * Add additional 1 vector to ensure always available interrupt. 174 */ 175 xhci->msix_count = min(num_online_cpus() + 1, 176 HCS_MAX_INTRS(xhci->hcs_params1)); 177 178 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 179 PCI_IRQ_MSIX); 180 if (ret < 0) { 181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 182 "Failed to enable MSI-X"); 183 return ret; 184 } 185 186 for (i = 0; i < xhci->msix_count; i++) { 187 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 188 "xhci_hcd", xhci_to_hcd(xhci)); 189 if (ret) 190 goto disable_msix; 191 } 192 193 hcd->msix_enabled = 1; 194 return ret; 195 196 disable_msix: 197 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 198 while (--i >= 0) 199 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 200 pci_free_irq_vectors(pdev); 201 return ret; 202 } 203 204 static int xhci_try_enable_msi(struct usb_hcd *hcd) 205 { 206 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 207 struct pci_dev *pdev; 208 int ret; 209 210 /* The xhci platform device has set up IRQs through usb_add_hcd. */ 211 if (xhci->quirks & XHCI_PLAT) 212 return 0; 213 214 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 215 /* 216 * Some Fresco Logic host controllers advertise MSI, but fail to 217 * generate interrupts. Don't even try to enable MSI. 218 */ 219 if (xhci->quirks & XHCI_BROKEN_MSI) 220 goto legacy_irq; 221 222 /* unregister the legacy interrupt */ 223 if (hcd->irq) 224 free_irq(hcd->irq, hcd); 225 hcd->irq = 0; 226 227 ret = xhci_setup_msix(xhci); 228 if (ret) 229 /* fall back to msi*/ 230 ret = xhci_setup_msi(xhci); 231 232 if (!ret) { 233 hcd->msi_enabled = 1; 234 return 0; 235 } 236 237 if (!pdev->irq) { 238 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 239 return -EINVAL; 240 } 241 242 legacy_irq: 243 if (!strlen(hcd->irq_descr)) 244 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 245 hcd->driver->description, hcd->self.busnum); 246 247 /* fall back to legacy interrupt*/ 248 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 249 hcd->irq_descr, hcd); 250 if (ret) { 251 xhci_err(xhci, "request interrupt %d failed\n", 252 pdev->irq); 253 return ret; 254 } 255 hcd->irq = pdev->irq; 256 return 0; 257 } 258 259 static int xhci_pci_run(struct usb_hcd *hcd) 260 { 261 int ret; 262 263 if (usb_hcd_is_primary_hcd(hcd)) { 264 ret = xhci_try_enable_msi(hcd); 265 if (ret) 266 return ret; 267 } 268 269 return xhci_run(hcd); 270 } 271 272 static void xhci_pci_stop(struct usb_hcd *hcd) 273 { 274 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 275 276 xhci_stop(hcd); 277 278 if (usb_hcd_is_primary_hcd(hcd)) 279 xhci_cleanup_msix(xhci); 280 } 281 282 /* called after powerup, by probe or system-pm "wakeup" */ 283 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 284 { 285 /* 286 * TODO: Implement finding debug ports later. 287 * TODO: see if there are any quirks that need to be added to handle 288 * new extended capabilities. 289 */ 290 291 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 292 if (!pci_set_mwi(pdev)) 293 xhci_dbg(xhci, "MWI active\n"); 294 295 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 296 return 0; 297 } 298 299 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 300 { 301 struct pci_dev *pdev = to_pci_dev(dev); 302 struct xhci_driver_data *driver_data; 303 const struct pci_device_id *id; 304 305 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 306 307 if (id && id->driver_data) { 308 driver_data = (struct xhci_driver_data *)id->driver_data; 309 xhci->quirks |= driver_data->quirks; 310 } 311 312 /* Look for vendor-specific quirks */ 313 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 314 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 315 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 316 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 317 pdev->revision == 0x0) { 318 xhci->quirks |= XHCI_RESET_EP_QUIRK; 319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 320 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 321 } 322 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 323 pdev->revision == 0x4) { 324 xhci->quirks |= XHCI_SLOW_SUSPEND; 325 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 326 "QUIRK: Fresco Logic xHC revision %u" 327 "must be suspended extra slowly", 328 pdev->revision); 329 } 330 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 331 xhci->quirks |= XHCI_BROKEN_STREAMS; 332 /* Fresco Logic confirms: all revisions of this chip do not 333 * support MSI, even though some of them claim to in their PCI 334 * capabilities. 335 */ 336 xhci->quirks |= XHCI_BROKEN_MSI; 337 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 338 "QUIRK: Fresco Logic revision %u " 339 "has broken MSI implementation", 340 pdev->revision); 341 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 342 } 343 344 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 345 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 346 xhci->quirks |= XHCI_BROKEN_STREAMS; 347 348 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 349 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 350 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 351 352 if (pdev->vendor == PCI_VENDOR_ID_NEC) 353 xhci->quirks |= XHCI_NEC_HOST; 354 355 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 356 xhci->quirks |= XHCI_AMD_0x96_HOST; 357 358 /* AMD PLL quirk */ 359 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 360 xhci->quirks |= XHCI_AMD_PLL_FIX; 361 362 if (pdev->vendor == PCI_VENDOR_ID_AMD && 363 (pdev->device == 0x145c || 364 pdev->device == 0x15e0 || 365 pdev->device == 0x15e1 || 366 pdev->device == 0x43bb)) 367 xhci->quirks |= XHCI_SUSPEND_DELAY; 368 369 if (pdev->vendor == PCI_VENDOR_ID_AMD && 370 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 371 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 372 373 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 374 xhci->quirks |= XHCI_DISABLE_SPARSE; 375 xhci->quirks |= XHCI_RESET_ON_RESUME; 376 } 377 378 if (pdev->vendor == PCI_VENDOR_ID_AMD) 379 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 380 381 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 382 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 383 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 384 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 385 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 386 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 387 388 if (pdev->vendor == PCI_VENDOR_ID_AMD && 389 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 390 xhci->quirks |= XHCI_BROKEN_D3COLD; 391 392 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 393 xhci->quirks |= XHCI_LPM_SUPPORT; 394 xhci->quirks |= XHCI_INTEL_HOST; 395 xhci->quirks |= XHCI_AVOID_BEI; 396 } 397 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 398 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 399 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 400 xhci->limit_active_eps = 64; 401 xhci->quirks |= XHCI_SW_BW_CHECKING; 402 /* 403 * PPT desktop boards DH77EB and DH77DF will power back on after 404 * a few seconds of being shutdown. The fix for this is to 405 * switch the ports from xHCI to EHCI on shutdown. We can't use 406 * DMI information to find those particular boards (since each 407 * vendor will change the board name), so we have to key off all 408 * PPT chipsets. 409 */ 410 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 411 } 412 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 413 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 414 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 415 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 416 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 417 } 418 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 419 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 420 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 421 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 422 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 423 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 424 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 425 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 426 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 427 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 428 } 429 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 430 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 431 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 432 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 433 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 434 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 435 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 436 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 437 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 438 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 439 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 440 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 441 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 442 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 443 xhci->quirks |= XHCI_MISSING_CAS; 444 445 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 446 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 447 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 448 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 449 450 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 451 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 452 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 456 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 457 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 458 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 459 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 460 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 461 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 462 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 463 464 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 465 pdev->device == PCI_DEVICE_ID_EJ168) { 466 xhci->quirks |= XHCI_RESET_ON_RESUME; 467 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 468 xhci->quirks |= XHCI_BROKEN_STREAMS; 469 } 470 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 471 pdev->device == 0x0014) { 472 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 473 xhci->quirks |= XHCI_ZERO_64B_REGS; 474 } 475 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 476 pdev->device == 0x0015) { 477 xhci->quirks |= XHCI_RESET_ON_RESUME; 478 xhci->quirks |= XHCI_ZERO_64B_REGS; 479 } 480 if (pdev->vendor == PCI_VENDOR_ID_VIA) 481 xhci->quirks |= XHCI_RESET_ON_RESUME; 482 483 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 484 if (pdev->vendor == PCI_VENDOR_ID_VIA && 485 pdev->device == 0x3432) 486 xhci->quirks |= XHCI_BROKEN_STREAMS; 487 488 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 489 xhci->quirks |= XHCI_LPM_SUPPORT; 490 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 491 } 492 493 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 494 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 495 /* 496 * try to tame the ASMedia 1042 controller which reports 0.96 497 * but appears to behave more like 1.0 498 */ 499 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 500 xhci->quirks |= XHCI_BROKEN_STREAMS; 501 } 502 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 503 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 504 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 505 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 506 } 507 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 508 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 509 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 510 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 511 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 512 513 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 514 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 515 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 516 517 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 518 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 519 520 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 521 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 522 pdev->device == 0x9026) 523 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 524 525 if (pdev->vendor == PCI_VENDOR_ID_AMD && 526 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 527 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 528 xhci->quirks |= XHCI_NO_SOFT_RETRY; 529 530 /* xHC spec requires PCI devices to support D3hot and D3cold */ 531 if (xhci->hci_version >= 0x120) 532 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 533 534 if (xhci->quirks & XHCI_RESET_ON_RESUME) 535 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 536 "QUIRK: Resetting on resume"); 537 } 538 539 #ifdef CONFIG_ACPI 540 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 541 { 542 static const guid_t intel_dsm_guid = 543 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 544 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 545 union acpi_object *obj; 546 547 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 548 NULL); 549 ACPI_FREE(obj); 550 } 551 552 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 553 { 554 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 555 struct xhci_hub *rhub = &xhci->usb3_rhub; 556 int ret; 557 int i; 558 559 /* This is not the usb3 roothub we are looking for */ 560 if (hcd != rhub->hcd) 561 return; 562 563 if (hdev->maxchild > rhub->num_ports) { 564 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 565 return; 566 } 567 568 for (i = 0; i < hdev->maxchild; i++) { 569 ret = usb_acpi_port_lpm_incapable(hdev, i); 570 571 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 572 573 if (ret >= 0) { 574 rhub->ports[i]->lpm_incapable = ret; 575 continue; 576 } 577 } 578 } 579 580 #else 581 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 582 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 583 #endif /* CONFIG_ACPI */ 584 585 /* called during probe() after chip reset completes */ 586 static int xhci_pci_setup(struct usb_hcd *hcd) 587 { 588 struct xhci_hcd *xhci; 589 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 590 int retval; 591 592 xhci = hcd_to_xhci(hcd); 593 if (!xhci->sbrn) 594 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 595 596 /* imod_interval is the interrupt moderation value in nanoseconds. */ 597 xhci->imod_interval = 40000; 598 599 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 600 if (retval) 601 return retval; 602 603 if (!usb_hcd_is_primary_hcd(hcd)) 604 return 0; 605 606 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 607 xhci_pme_acpi_rtd3_enable(pdev); 608 609 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 610 611 /* Find any debug ports */ 612 return xhci_pci_reinit(xhci, pdev); 613 } 614 615 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 616 struct usb_tt *tt, gfp_t mem_flags) 617 { 618 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 619 if (!hdev->parent) 620 xhci_find_lpm_incapable_ports(hcd, hdev); 621 622 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 623 } 624 625 /* 626 * We need to register our own PCI probe function (instead of the USB core's 627 * function) in order to create a second roothub under xHCI. 628 */ 629 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 630 { 631 int retval; 632 struct xhci_hcd *xhci; 633 struct usb_hcd *hcd; 634 struct xhci_driver_data *driver_data; 635 struct reset_control *reset; 636 637 driver_data = (struct xhci_driver_data *)id->driver_data; 638 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 639 retval = renesas_xhci_check_request_fw(dev, id); 640 if (retval) 641 return retval; 642 } 643 644 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 645 if (IS_ERR(reset)) 646 return PTR_ERR(reset); 647 reset_control_reset(reset); 648 649 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 650 pm_runtime_get_noresume(&dev->dev); 651 652 /* Register the USB 2.0 roothub. 653 * FIXME: USB core must know to register the USB 2.0 roothub first. 654 * This is sort of silly, because we could just set the HCD driver flags 655 * to say USB 2.0, but I'm not sure what the implications would be in 656 * the other parts of the HCD code. 657 */ 658 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 659 660 if (retval) 661 goto put_runtime_pm; 662 663 /* USB 2.0 roothub is stored in the PCI device now. */ 664 hcd = dev_get_drvdata(&dev->dev); 665 xhci = hcd_to_xhci(hcd); 666 xhci->reset = reset; 667 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 668 pci_name(dev), hcd); 669 if (!xhci->shared_hcd) { 670 retval = -ENOMEM; 671 goto dealloc_usb2_hcd; 672 } 673 674 retval = xhci_ext_cap_init(xhci); 675 if (retval) 676 goto put_usb3_hcd; 677 678 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 679 IRQF_SHARED); 680 if (retval) 681 goto put_usb3_hcd; 682 /* Roothub already marked as USB 3.0 speed */ 683 684 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 685 HCC_MAX_PSA(xhci->hcc_params) >= 4) 686 xhci->shared_hcd->can_do_streams = 1; 687 688 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 689 pm_runtime_put_noidle(&dev->dev); 690 691 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 692 pm_runtime_allow(&dev->dev); 693 694 dma_set_max_seg_size(&dev->dev, UINT_MAX); 695 696 return 0; 697 698 put_usb3_hcd: 699 usb_put_hcd(xhci->shared_hcd); 700 dealloc_usb2_hcd: 701 usb_hcd_pci_remove(dev); 702 put_runtime_pm: 703 pm_runtime_put_noidle(&dev->dev); 704 return retval; 705 } 706 707 static void xhci_pci_remove(struct pci_dev *dev) 708 { 709 struct xhci_hcd *xhci; 710 711 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 712 713 xhci->xhc_state |= XHCI_STATE_REMOVING; 714 715 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 716 pm_runtime_forbid(&dev->dev); 717 718 if (xhci->shared_hcd) { 719 usb_remove_hcd(xhci->shared_hcd); 720 usb_put_hcd(xhci->shared_hcd); 721 xhci->shared_hcd = NULL; 722 } 723 724 /* Workaround for spurious wakeups at shutdown with HSW */ 725 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 726 pci_set_power_state(dev, PCI_D3hot); 727 728 usb_hcd_pci_remove(dev); 729 } 730 731 /* 732 * In some Intel xHCI controllers, in order to get D3 working, 733 * through a vendor specific SSIC CONFIG register at offset 0x883c, 734 * SSIC PORT need to be marked as "unused" before putting xHCI 735 * into D3. After D3 exit, the SSIC port need to be marked as "used". 736 * Without this change, xHCI might not enter D3 state. 737 */ 738 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 739 { 740 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 741 u32 val; 742 void __iomem *reg; 743 int i; 744 745 for (i = 0; i < SSIC_PORT_NUM; i++) { 746 reg = (void __iomem *) xhci->cap_regs + 747 SSIC_PORT_CFG2 + 748 i * SSIC_PORT_CFG2_OFFSET; 749 750 /* Notify SSIC that SSIC profile programming is not done. */ 751 val = readl(reg) & ~PROG_DONE; 752 writel(val, reg); 753 754 /* Mark SSIC port as unused(suspend) or used(resume) */ 755 val = readl(reg); 756 if (suspend) 757 val |= SSIC_PORT_UNUSED; 758 else 759 val &= ~SSIC_PORT_UNUSED; 760 writel(val, reg); 761 762 /* Notify SSIC that SSIC profile programming is done */ 763 val = readl(reg) | PROG_DONE; 764 writel(val, reg); 765 readl(reg); 766 } 767 } 768 769 /* 770 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 771 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 772 */ 773 static void xhci_pme_quirk(struct usb_hcd *hcd) 774 { 775 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 776 void __iomem *reg; 777 u32 val; 778 779 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 780 val = readl(reg); 781 writel(val | BIT(28), reg); 782 readl(reg); 783 } 784 785 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 786 { 787 u32 reg; 788 789 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 790 reg &= ~BIT(SPARSE_DISABLE_BIT); 791 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 792 } 793 794 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 795 { 796 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 797 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 798 int ret; 799 800 /* 801 * Systems with the TI redriver that loses port status change events 802 * need to have the registers polled during D3, so avoid D3cold. 803 */ 804 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 805 pci_d3cold_disable(pdev); 806 807 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 808 xhci_pme_quirk(hcd); 809 810 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 811 xhci_ssic_port_unused_quirk(hcd, true); 812 813 if (xhci->quirks & XHCI_DISABLE_SPARSE) 814 xhci_sparse_control_quirk(hcd); 815 816 ret = xhci_suspend(xhci, do_wakeup); 817 818 /* synchronize irq when using MSI-X */ 819 xhci_msix_sync_irqs(xhci); 820 821 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 822 xhci_ssic_port_unused_quirk(hcd, false); 823 824 return ret; 825 } 826 827 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 828 { 829 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 830 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 831 int retval = 0; 832 833 reset_control_reset(xhci->reset); 834 835 /* The BIOS on systems with the Intel Panther Point chipset may or may 836 * not support xHCI natively. That means that during system resume, it 837 * may switch the ports back to EHCI so that users can use their 838 * keyboard to select a kernel from GRUB after resume from hibernate. 839 * 840 * The BIOS is supposed to remember whether the OS had xHCI ports 841 * enabled before resume, and switch the ports back to xHCI when the 842 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 843 * writers. 844 * 845 * Unconditionally switch the ports back to xHCI after a system resume. 846 * It should not matter whether the EHCI or xHCI controller is 847 * resumed first. It's enough to do the switchover in xHCI because 848 * USB core won't notice anything as the hub driver doesn't start 849 * running again until after all the devices (including both EHCI and 850 * xHCI host controllers) have been resumed. 851 */ 852 853 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 854 usb_enable_intel_xhci_ports(pdev); 855 856 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 857 xhci_ssic_port_unused_quirk(hcd, false); 858 859 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 860 xhci_pme_quirk(hcd); 861 862 retval = xhci_resume(xhci, hibernated); 863 return retval; 864 } 865 866 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 867 { 868 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 869 struct xhci_port *port; 870 struct usb_device *udev; 871 unsigned int slot_id; 872 u32 portsc; 873 int i; 874 875 /* 876 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 877 * cause significant boot delay if usb ports are in suspended U3 state 878 * during boot. Some USB devices survive in U3 state over S4 hibernate 879 * 880 * Disable ports that are in U3 if remote wake is not enabled for either 881 * host controller or connected device 882 */ 883 884 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 885 return 0; 886 887 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 888 port = &xhci->hw_ports[i]; 889 portsc = readl(port->addr); 890 891 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 892 continue; 893 894 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 895 port->hcd_portnum + 1); 896 if (!slot_id || !xhci->devs[slot_id]) { 897 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 898 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 899 continue; 900 } 901 902 udev = xhci->devs[slot_id]->udev; 903 904 /* if wakeup is enabled then don't disable the port */ 905 if (udev->do_remote_wakeup && do_wakeup) 906 continue; 907 908 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 909 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 910 portsc = xhci_port_state_to_neutral(portsc); 911 writel(portsc | PORT_PE, port->addr); 912 } 913 914 return 0; 915 } 916 917 static void xhci_pci_shutdown(struct usb_hcd *hcd) 918 { 919 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 920 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 921 922 xhci_shutdown(hcd); 923 xhci_cleanup_msix(xhci); 924 925 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 926 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 927 pci_set_power_state(pdev, PCI_D3hot); 928 } 929 930 /*-------------------------------------------------------------------------*/ 931 932 static const struct xhci_driver_data reneses_data = { 933 .quirks = XHCI_RENESAS_FW_QUIRK, 934 .firmware = "renesas_usb_fw.mem", 935 }; 936 937 /* PCI driver selection metadata; PCI hotplugging uses this */ 938 static const struct pci_device_id pci_ids[] = { 939 { PCI_DEVICE(0x1912, 0x0014), 940 .driver_data = (unsigned long)&reneses_data, 941 }, 942 { PCI_DEVICE(0x1912, 0x0015), 943 .driver_data = (unsigned long)&reneses_data, 944 }, 945 /* handle any USB 3.0 xHCI controller */ 946 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 947 }, 948 { /* end: all zeroes */ } 949 }; 950 MODULE_DEVICE_TABLE(pci, pci_ids); 951 952 /* 953 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 954 * load firmware, so don't encumber the xhci-pci driver with it. 955 */ 956 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 957 MODULE_FIRMWARE("renesas_usb_fw.mem"); 958 #endif 959 960 /* pci driver glue; this is a "new style" PCI driver module */ 961 static struct pci_driver xhci_pci_driver = { 962 .name = hcd_name, 963 .id_table = pci_ids, 964 965 .probe = xhci_pci_probe, 966 .remove = xhci_pci_remove, 967 /* suspend and resume implemented later */ 968 969 .shutdown = usb_hcd_pci_shutdown, 970 .driver = { 971 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 972 }, 973 }; 974 975 static int __init xhci_pci_init(void) 976 { 977 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 978 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 979 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 980 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 981 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 982 xhci_pci_hc_driver.stop = xhci_pci_stop; 983 return pci_register_driver(&xhci_pci_driver); 984 } 985 module_init(xhci_pci_init); 986 987 static void __exit xhci_pci_exit(void) 988 { 989 pci_unregister_driver(&xhci_pci_driver); 990 } 991 module_exit(xhci_pci_exit); 992 993 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 994 MODULE_LICENSE("GPL"); 995