1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 33 #define PCI_VENDOR_ID_ETRON 0x1b6f 34 #define PCI_DEVICE_ID_ASROCK_P67 0x7023 35 36 static const char hcd_name[] = "xhci_hcd"; 37 38 /* called after powerup, by probe or system-pm "wakeup" */ 39 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 40 { 41 /* 42 * TODO: Implement finding debug ports later. 43 * TODO: see if there are any quirks that need to be added to handle 44 * new extended capabilities. 45 */ 46 47 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 48 if (!pci_set_mwi(pdev)) 49 xhci_dbg(xhci, "MWI active\n"); 50 51 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 52 return 0; 53 } 54 55 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 56 { 57 struct pci_dev *pdev = to_pci_dev(dev); 58 59 /* Look for vendor-specific quirks */ 60 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 61 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { 62 if (pdev->revision == 0x0) { 63 xhci->quirks |= XHCI_RESET_EP_QUIRK; 64 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" 65 " endpoint cmd after reset endpoint\n"); 66 } 67 /* Fresco Logic confirms: all revisions of this chip do not 68 * support MSI, even though some of them claim to in their PCI 69 * capabilities. 70 */ 71 xhci->quirks |= XHCI_BROKEN_MSI; 72 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " 73 "has broken MSI implementation\n", 74 pdev->revision); 75 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 76 } 77 78 if (pdev->vendor == PCI_VENDOR_ID_NEC) 79 xhci->quirks |= XHCI_NEC_HOST; 80 81 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 82 xhci->quirks |= XHCI_AMD_0x96_HOST; 83 84 /* AMD PLL quirk */ 85 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 86 xhci->quirks |= XHCI_AMD_PLL_FIX; 87 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 88 xhci->quirks |= XHCI_LPM_SUPPORT; 89 xhci->quirks |= XHCI_INTEL_HOST; 90 } 91 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 92 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 93 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 94 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 95 xhci->limit_active_eps = 64; 96 xhci->quirks |= XHCI_SW_BW_CHECKING; 97 /* 98 * PPT desktop boards DH77EB and DH77DF will power back on after 99 * a few seconds of being shutdown. The fix for this is to 100 * switch the ports from xHCI to EHCI on shutdown. We can't use 101 * DMI information to find those particular boards (since each 102 * vendor will change the board name), so we have to key off all 103 * PPT chipsets. 104 */ 105 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 106 xhci->quirks |= XHCI_AVOID_BEI; 107 } 108 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 109 pdev->device == PCI_DEVICE_ID_ASROCK_P67) { 110 xhci->quirks |= XHCI_RESET_ON_RESUME; 111 xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); 112 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 113 } 114 if (pdev->vendor == PCI_VENDOR_ID_VIA) 115 xhci->quirks |= XHCI_RESET_ON_RESUME; 116 } 117 118 /* called during probe() after chip reset completes */ 119 static int xhci_pci_setup(struct usb_hcd *hcd) 120 { 121 struct xhci_hcd *xhci; 122 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 123 int retval; 124 125 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 126 if (retval) 127 return retval; 128 129 xhci = hcd_to_xhci(hcd); 130 if (!usb_hcd_is_primary_hcd(hcd)) 131 return 0; 132 133 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 134 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 135 136 /* Find any debug ports */ 137 retval = xhci_pci_reinit(xhci, pdev); 138 if (!retval) 139 return retval; 140 141 kfree(xhci); 142 return retval; 143 } 144 145 /* 146 * We need to register our own PCI probe function (instead of the USB core's 147 * function) in order to create a second roothub under xHCI. 148 */ 149 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 150 { 151 int retval; 152 struct xhci_hcd *xhci; 153 struct hc_driver *driver; 154 struct usb_hcd *hcd; 155 156 driver = (struct hc_driver *)id->driver_data; 157 /* Register the USB 2.0 roothub. 158 * FIXME: USB core must know to register the USB 2.0 roothub first. 159 * This is sort of silly, because we could just set the HCD driver flags 160 * to say USB 2.0, but I'm not sure what the implications would be in 161 * the other parts of the HCD code. 162 */ 163 retval = usb_hcd_pci_probe(dev, id); 164 165 if (retval) 166 return retval; 167 168 /* USB 2.0 roothub is stored in the PCI device now. */ 169 hcd = dev_get_drvdata(&dev->dev); 170 xhci = hcd_to_xhci(hcd); 171 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 172 pci_name(dev), hcd); 173 if (!xhci->shared_hcd) { 174 retval = -ENOMEM; 175 goto dealloc_usb2_hcd; 176 } 177 178 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 179 * is called by usb_add_hcd(). 180 */ 181 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 182 183 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 184 IRQF_SHARED); 185 if (retval) 186 goto put_usb3_hcd; 187 /* Roothub already marked as USB 3.0 speed */ 188 189 /* We know the LPM timeout algorithms for this host, let the USB core 190 * enable and disable LPM for devices under the USB 3.0 roothub. 191 */ 192 if (xhci->quirks & XHCI_LPM_SUPPORT) 193 hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1; 194 195 return 0; 196 197 put_usb3_hcd: 198 usb_put_hcd(xhci->shared_hcd); 199 dealloc_usb2_hcd: 200 usb_hcd_pci_remove(dev); 201 return retval; 202 } 203 204 static void xhci_pci_remove(struct pci_dev *dev) 205 { 206 struct xhci_hcd *xhci; 207 208 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 209 if (xhci->shared_hcd) { 210 usb_remove_hcd(xhci->shared_hcd); 211 usb_put_hcd(xhci->shared_hcd); 212 } 213 usb_hcd_pci_remove(dev); 214 kfree(xhci); 215 } 216 217 #ifdef CONFIG_PM 218 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 219 { 220 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 221 int retval = 0; 222 223 if (hcd->state != HC_STATE_SUSPENDED || 224 xhci->shared_hcd->state != HC_STATE_SUSPENDED) 225 return -EINVAL; 226 227 retval = xhci_suspend(xhci); 228 229 return retval; 230 } 231 232 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 233 { 234 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 235 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 236 int retval = 0; 237 238 /* The BIOS on systems with the Intel Panther Point chipset may or may 239 * not support xHCI natively. That means that during system resume, it 240 * may switch the ports back to EHCI so that users can use their 241 * keyboard to select a kernel from GRUB after resume from hibernate. 242 * 243 * The BIOS is supposed to remember whether the OS had xHCI ports 244 * enabled before resume, and switch the ports back to xHCI when the 245 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 246 * writers. 247 * 248 * Unconditionally switch the ports back to xHCI after a system resume. 249 * We can't tell whether the EHCI or xHCI controller will be resumed 250 * first, so we have to do the port switchover in both drivers. Writing 251 * a '1' to the port switchover registers should have no effect if the 252 * port was already switched over. 253 */ 254 if (usb_is_intel_switchable_xhci(pdev)) 255 usb_enable_xhci_ports(pdev); 256 257 retval = xhci_resume(xhci, hibernated); 258 return retval; 259 } 260 #endif /* CONFIG_PM */ 261 262 static const struct hc_driver xhci_pci_hc_driver = { 263 .description = hcd_name, 264 .product_desc = "xHCI Host Controller", 265 .hcd_priv_size = sizeof(struct xhci_hcd *), 266 267 /* 268 * generic hardware linkage 269 */ 270 .irq = xhci_irq, 271 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 272 273 /* 274 * basic lifecycle operations 275 */ 276 .reset = xhci_pci_setup, 277 .start = xhci_run, 278 #ifdef CONFIG_PM 279 .pci_suspend = xhci_pci_suspend, 280 .pci_resume = xhci_pci_resume, 281 #endif 282 .stop = xhci_stop, 283 .shutdown = xhci_shutdown, 284 285 /* 286 * managing i/o requests and associated device resources 287 */ 288 .urb_enqueue = xhci_urb_enqueue, 289 .urb_dequeue = xhci_urb_dequeue, 290 .alloc_dev = xhci_alloc_dev, 291 .free_dev = xhci_free_dev, 292 .alloc_streams = xhci_alloc_streams, 293 .free_streams = xhci_free_streams, 294 .add_endpoint = xhci_add_endpoint, 295 .drop_endpoint = xhci_drop_endpoint, 296 .endpoint_reset = xhci_endpoint_reset, 297 .check_bandwidth = xhci_check_bandwidth, 298 .reset_bandwidth = xhci_reset_bandwidth, 299 .address_device = xhci_address_device, 300 .update_hub_device = xhci_update_hub_device, 301 .reset_device = xhci_discover_or_reset_device, 302 303 /* 304 * scheduling support 305 */ 306 .get_frame_number = xhci_get_frame, 307 308 /* Root hub support */ 309 .hub_control = xhci_hub_control, 310 .hub_status_data = xhci_hub_status_data, 311 .bus_suspend = xhci_bus_suspend, 312 .bus_resume = xhci_bus_resume, 313 /* 314 * call back when device connected and addressed 315 */ 316 .update_device = xhci_update_device, 317 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 318 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, 319 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, 320 }; 321 322 /*-------------------------------------------------------------------------*/ 323 324 /* PCI driver selection metadata; PCI hotplugging uses this */ 325 static const struct pci_device_id pci_ids[] = { { 326 /* handle any USB 3.0 xHCI controller */ 327 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 328 .driver_data = (unsigned long) &xhci_pci_hc_driver, 329 }, 330 { /* end: all zeroes */ } 331 }; 332 MODULE_DEVICE_TABLE(pci, pci_ids); 333 334 /* pci driver glue; this is a "new style" PCI driver module */ 335 static struct pci_driver xhci_pci_driver = { 336 .name = (char *) hcd_name, 337 .id_table = pci_ids, 338 339 .probe = xhci_pci_probe, 340 .remove = xhci_pci_remove, 341 /* suspend and resume implemented later */ 342 343 .shutdown = usb_hcd_pci_shutdown, 344 #ifdef CONFIG_PM_SLEEP 345 .driver = { 346 .pm = &usb_hcd_pci_pm_ops 347 }, 348 #endif 349 }; 350 351 int __init xhci_register_pci(void) 352 { 353 return pci_register_driver(&xhci_pci_driver); 354 } 355 356 void xhci_unregister_pci(void) 357 { 358 pci_unregister_driver(&xhci_pci_driver); 359 } 360