1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 22 #include "xhci.h" 23 #include "xhci-mtk.h" 24 25 /* ip_pw_ctrl0 register */ 26 #define CTRL0_IP_SW_RST BIT(0) 27 28 /* ip_pw_ctrl1 register */ 29 #define CTRL1_IP_HOST_PDN BIT(0) 30 31 /* ip_pw_ctrl2 register */ 32 #define CTRL2_IP_DEV_PDN BIT(0) 33 34 /* ip_pw_sts1 register */ 35 #define STS1_IP_SLEEP_STS BIT(30) 36 #define STS1_U3_MAC_RST BIT(16) 37 #define STS1_XHCI_RST BIT(11) 38 #define STS1_SYS125_RST BIT(10) 39 #define STS1_REF_RST BIT(8) 40 #define STS1_SYSPLL_STABLE BIT(0) 41 42 /* ip_xhci_cap register */ 43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46 /* u3_ctrl_p register */ 47 #define CTRL_U3_PORT_HOST_SEL BIT(2) 48 #define CTRL_U3_PORT_PDN BIT(1) 49 #define CTRL_U3_PORT_DIS BIT(0) 50 51 /* u2_ctrl_p register */ 52 #define CTRL_U2_PORT_HOST_SEL BIT(2) 53 #define CTRL_U2_PORT_PDN BIT(1) 54 #define CTRL_U2_PORT_DIS BIT(0) 55 56 /* u2_phy_pll register */ 57 #define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59 /* usb remote wakeup registers in syscon */ 60 61 /* mt8173 etc */ 62 #define PERI_WK_CTRL1 0x4 63 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 64 #define WC1_IS_EN BIT(25) 65 #define WC1_IS_P BIT(6) /* polarity for ip sleep */ 66 67 /* mt8183 */ 68 #define PERI_WK_CTRL0 0x0 69 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */ 70 #define WC0_IS_P BIT(12) /* polarity */ 71 #define WC0_IS_EN BIT(6) 72 73 /* mt8192 */ 74 #define WC0_SSUSB0_CDEN BIT(6) 75 #define WC0_IS_SPM_EN BIT(1) 76 77 /* mt2712 etc */ 78 #define PERI_SSUSB_SPM_CTRL 0x0 79 #define SSC_IP_SLEEP_EN BIT(4) 80 #define SSC_SPM_INT_EN BIT(1) 81 82 enum ssusb_uwk_vers { 83 SSUSB_UWK_V1 = 1, 84 SSUSB_UWK_V2, 85 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ 86 SSUSB_UWK_V1_2, /* specific revision 1.2 */ 87 }; 88 89 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 90 { 91 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 92 u32 value, check_val; 93 int u3_ports_disabled = 0; 94 int ret; 95 int i; 96 97 if (!mtk->has_ippc) 98 return 0; 99 100 /* power on host ip */ 101 value = readl(&ippc->ip_pw_ctr1); 102 value &= ~CTRL1_IP_HOST_PDN; 103 writel(value, &ippc->ip_pw_ctr1); 104 105 /* power on and enable u3 ports except skipped ones */ 106 for (i = 0; i < mtk->num_u3_ports; i++) { 107 if ((0x1 << i) & mtk->u3p_dis_msk) { 108 u3_ports_disabled++; 109 continue; 110 } 111 112 value = readl(&ippc->u3_ctrl_p[i]); 113 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 114 value |= CTRL_U3_PORT_HOST_SEL; 115 writel(value, &ippc->u3_ctrl_p[i]); 116 } 117 118 /* power on and enable all u2 ports */ 119 for (i = 0; i < mtk->num_u2_ports; i++) { 120 value = readl(&ippc->u2_ctrl_p[i]); 121 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 122 value |= CTRL_U2_PORT_HOST_SEL; 123 writel(value, &ippc->u2_ctrl_p[i]); 124 } 125 126 /* 127 * wait for clocks to be stable, and clock domains reset to 128 * be inactive after power on and enable ports 129 */ 130 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 131 STS1_SYS125_RST | STS1_XHCI_RST; 132 133 if (mtk->num_u3_ports > u3_ports_disabled) 134 check_val |= STS1_U3_MAC_RST; 135 136 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 137 (check_val == (value & check_val)), 100, 20000); 138 if (ret) { 139 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 140 return ret; 141 } 142 143 return 0; 144 } 145 146 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 147 { 148 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 149 u32 value; 150 int ret; 151 int i; 152 153 if (!mtk->has_ippc) 154 return 0; 155 156 /* power down u3 ports except skipped ones */ 157 for (i = 0; i < mtk->num_u3_ports; i++) { 158 if ((0x1 << i) & mtk->u3p_dis_msk) 159 continue; 160 161 value = readl(&ippc->u3_ctrl_p[i]); 162 value |= CTRL_U3_PORT_PDN; 163 writel(value, &ippc->u3_ctrl_p[i]); 164 } 165 166 /* power down all u2 ports */ 167 for (i = 0; i < mtk->num_u2_ports; i++) { 168 value = readl(&ippc->u2_ctrl_p[i]); 169 value |= CTRL_U2_PORT_PDN; 170 writel(value, &ippc->u2_ctrl_p[i]); 171 } 172 173 /* power down host ip */ 174 value = readl(&ippc->ip_pw_ctr1); 175 value |= CTRL1_IP_HOST_PDN; 176 writel(value, &ippc->ip_pw_ctr1); 177 178 /* wait for host ip to sleep */ 179 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 180 (value & STS1_IP_SLEEP_STS), 100, 100000); 181 if (ret) { 182 dev_err(mtk->dev, "ip sleep failed!!!\n"); 183 return ret; 184 } 185 return 0; 186 } 187 188 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 189 { 190 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 191 u32 value; 192 193 if (!mtk->has_ippc) 194 return 0; 195 196 /* reset whole ip */ 197 value = readl(&ippc->ip_pw_ctr0); 198 value |= CTRL0_IP_SW_RST; 199 writel(value, &ippc->ip_pw_ctr0); 200 udelay(1); 201 value = readl(&ippc->ip_pw_ctr0); 202 value &= ~CTRL0_IP_SW_RST; 203 writel(value, &ippc->ip_pw_ctr0); 204 205 /* 206 * device ip is default power-on in fact 207 * power down device ip, otherwise ip-sleep will fail 208 */ 209 value = readl(&ippc->ip_pw_ctr2); 210 value |= CTRL2_IP_DEV_PDN; 211 writel(value, &ippc->ip_pw_ctr2); 212 213 value = readl(&ippc->ip_xhci_cap); 214 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 215 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 216 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 217 mtk->num_u2_ports, mtk->num_u3_ports); 218 219 return xhci_mtk_host_enable(mtk); 220 } 221 222 /* only clocks can be turn off for ip-sleep wakeup mode */ 223 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 224 { 225 u32 reg, msk, val; 226 227 switch (mtk->uwk_vers) { 228 case SSUSB_UWK_V1: 229 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 230 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 231 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 232 break; 233 case SSUSB_UWK_V1_1: 234 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 235 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P; 236 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0; 237 break; 238 case SSUSB_UWK_V1_2: 239 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 240 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; 241 val = enable ? msk : 0; 242 break; 243 case SSUSB_UWK_V2: 244 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 245 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 246 val = enable ? msk : 0; 247 break; 248 default: 249 return; 250 } 251 regmap_update_bits(mtk->uwk, reg, msk, val); 252 } 253 254 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 255 struct device_node *dn) 256 { 257 struct of_phandle_args args; 258 int ret; 259 260 /* Wakeup function is optional */ 261 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 262 if (!mtk->uwk_en) 263 return 0; 264 265 ret = of_parse_phandle_with_fixed_args(dn, 266 "mediatek,syscon-wakeup", 2, 0, &args); 267 if (ret) 268 return ret; 269 270 mtk->uwk_reg_base = args.args[0]; 271 mtk->uwk_vers = args.args[1]; 272 mtk->uwk = syscon_node_to_regmap(args.np); 273 of_node_put(args.np); 274 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 275 mtk->uwk_reg_base, mtk->uwk_vers); 276 277 return PTR_ERR_OR_ZERO(mtk->uwk); 278 } 279 280 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 281 { 282 if (mtk->uwk_en) 283 usb_wakeup_ip_sleep_set(mtk, enable); 284 } 285 286 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 287 { 288 struct clk_bulk_data *clks = mtk->clks; 289 290 clks[0].id = "sys_ck"; 291 clks[1].id = "xhci_ck"; 292 clks[2].id = "ref_ck"; 293 clks[3].id = "mcu_ck"; 294 clks[4].id = "dma_ck"; 295 296 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks); 297 } 298 299 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 300 { 301 int ret; 302 303 ret = regulator_enable(mtk->vbus); 304 if (ret) { 305 dev_err(mtk->dev, "failed to enable vbus\n"); 306 return ret; 307 } 308 309 ret = regulator_enable(mtk->vusb33); 310 if (ret) { 311 dev_err(mtk->dev, "failed to enable vusb33\n"); 312 regulator_disable(mtk->vbus); 313 return ret; 314 } 315 return 0; 316 } 317 318 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 319 { 320 regulator_disable(mtk->vbus); 321 regulator_disable(mtk->vusb33); 322 } 323 324 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 325 { 326 struct usb_hcd *hcd = xhci_to_hcd(xhci); 327 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 328 329 /* 330 * As of now platform drivers don't provide MSI support so we ensure 331 * here that the generic code does not try to make a pci_dev from our 332 * dev struct in order to setup MSI 333 */ 334 xhci->quirks |= XHCI_PLAT; 335 xhci->quirks |= XHCI_MTK_HOST; 336 /* 337 * MTK host controller gives a spurious successful event after a 338 * short transfer. Ignore it. 339 */ 340 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 341 if (mtk->lpm_support) 342 xhci->quirks |= XHCI_LPM_SUPPORT; 343 if (mtk->u2_lpm_disable) 344 xhci->quirks |= XHCI_HW_LPM_DISABLE; 345 346 /* 347 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, 348 * and it's 3 when support it. 349 */ 350 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) 351 xhci->quirks |= XHCI_BROKEN_STREAMS; 352 } 353 354 /* called during probe() after chip reset completes */ 355 static int xhci_mtk_setup(struct usb_hcd *hcd) 356 { 357 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 358 int ret; 359 360 if (usb_hcd_is_primary_hcd(hcd)) { 361 ret = xhci_mtk_ssusb_config(mtk); 362 if (ret) 363 return ret; 364 } 365 366 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 367 if (ret) 368 return ret; 369 370 if (usb_hcd_is_primary_hcd(hcd)) { 371 ret = xhci_mtk_sch_init(mtk); 372 if (ret) 373 return ret; 374 } 375 376 return ret; 377 } 378 379 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 380 .reset = xhci_mtk_setup, 381 .add_endpoint = xhci_mtk_add_ep, 382 .drop_endpoint = xhci_mtk_drop_ep, 383 .check_bandwidth = xhci_mtk_check_bandwidth, 384 .reset_bandwidth = xhci_mtk_reset_bandwidth, 385 }; 386 387 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 388 389 static int xhci_mtk_probe(struct platform_device *pdev) 390 { 391 struct device *dev = &pdev->dev; 392 struct device_node *node = dev->of_node; 393 struct xhci_hcd_mtk *mtk; 394 const struct hc_driver *driver; 395 struct xhci_hcd *xhci; 396 struct resource *res; 397 struct usb_hcd *hcd; 398 int ret = -ENODEV; 399 int wakeup_irq; 400 int irq; 401 402 if (usb_disabled()) 403 return -ENODEV; 404 405 driver = &xhci_mtk_hc_driver; 406 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 407 if (!mtk) 408 return -ENOMEM; 409 410 mtk->dev = dev; 411 mtk->vbus = devm_regulator_get(dev, "vbus"); 412 if (IS_ERR(mtk->vbus)) { 413 dev_err(dev, "fail to get vbus\n"); 414 return PTR_ERR(mtk->vbus); 415 } 416 417 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 418 if (IS_ERR(mtk->vusb33)) { 419 dev_err(dev, "fail to get vusb33\n"); 420 return PTR_ERR(mtk->vusb33); 421 } 422 423 ret = xhci_mtk_clks_get(mtk); 424 if (ret) 425 return ret; 426 427 irq = platform_get_irq_byname_optional(pdev, "host"); 428 if (irq < 0) { 429 if (irq == -EPROBE_DEFER) 430 return irq; 431 432 /* for backward compatibility */ 433 irq = platform_get_irq(pdev, 0); 434 if (irq < 0) 435 return irq; 436 } 437 438 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 439 if (wakeup_irq == -EPROBE_DEFER) 440 return wakeup_irq; 441 442 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 443 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); 444 /* optional property, ignore the error if it does not exist */ 445 of_property_read_u32(node, "mediatek,u3p-dis-msk", 446 &mtk->u3p_dis_msk); 447 448 ret = usb_wakeup_of_property_parse(mtk, node); 449 if (ret) { 450 dev_err(dev, "failed to parse uwk property\n"); 451 return ret; 452 } 453 454 pm_runtime_set_active(dev); 455 pm_runtime_use_autosuspend(dev); 456 pm_runtime_set_autosuspend_delay(dev, 4000); 457 pm_runtime_enable(dev); 458 pm_runtime_get_sync(dev); 459 460 ret = xhci_mtk_ldos_enable(mtk); 461 if (ret) 462 goto disable_pm; 463 464 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 465 if (ret) 466 goto disable_ldos; 467 468 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 469 if (!hcd) { 470 ret = -ENOMEM; 471 goto disable_clk; 472 } 473 474 /* 475 * USB 2.0 roothub is stored in the platform_device. 476 * Swap it with mtk HCD. 477 */ 478 mtk->hcd = platform_get_drvdata(pdev); 479 platform_set_drvdata(pdev, mtk); 480 481 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 482 hcd->regs = devm_ioremap_resource(dev, res); 483 if (IS_ERR(hcd->regs)) { 484 ret = PTR_ERR(hcd->regs); 485 goto put_usb2_hcd; 486 } 487 hcd->rsrc_start = res->start; 488 hcd->rsrc_len = resource_size(res); 489 490 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 491 if (res) { /* ippc register is optional */ 492 mtk->ippc_regs = devm_ioremap_resource(dev, res); 493 if (IS_ERR(mtk->ippc_regs)) { 494 ret = PTR_ERR(mtk->ippc_regs); 495 goto put_usb2_hcd; 496 } 497 mtk->has_ippc = true; 498 } 499 500 device_init_wakeup(dev, true); 501 502 xhci = hcd_to_xhci(hcd); 503 xhci->main_hcd = hcd; 504 505 /* 506 * imod_interval is the interrupt moderation value in nanoseconds. 507 * The increment interval is 8 times as much as that defined in 508 * the xHCI spec on MTK's controller. 509 */ 510 xhci->imod_interval = 5000; 511 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 512 513 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 514 dev_name(dev), hcd); 515 if (!xhci->shared_hcd) { 516 ret = -ENOMEM; 517 goto disable_device_wakeup; 518 } 519 520 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 521 if (ret) 522 goto put_usb3_hcd; 523 524 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && 525 !(xhci->quirks & XHCI_BROKEN_STREAMS)) 526 xhci->shared_hcd->can_do_streams = 1; 527 528 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 529 if (ret) 530 goto dealloc_usb2_hcd; 531 532 if (wakeup_irq > 0) { 533 ret = dev_pm_set_dedicated_wake_irq(dev, wakeup_irq); 534 if (ret) { 535 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq); 536 goto dealloc_usb3_hcd; 537 } 538 dev_info(dev, "wakeup irq %d\n", wakeup_irq); 539 } 540 541 device_enable_async_suspend(dev); 542 pm_runtime_mark_last_busy(dev); 543 pm_runtime_put_autosuspend(dev); 544 pm_runtime_forbid(dev); 545 546 return 0; 547 548 dealloc_usb3_hcd: 549 usb_remove_hcd(xhci->shared_hcd); 550 xhci->shared_hcd = NULL; 551 552 dealloc_usb2_hcd: 553 usb_remove_hcd(hcd); 554 555 put_usb3_hcd: 556 xhci_mtk_sch_exit(mtk); 557 usb_put_hcd(xhci->shared_hcd); 558 559 disable_device_wakeup: 560 device_init_wakeup(dev, false); 561 562 put_usb2_hcd: 563 usb_put_hcd(hcd); 564 565 disable_clk: 566 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 567 568 disable_ldos: 569 xhci_mtk_ldos_disable(mtk); 570 571 disable_pm: 572 pm_runtime_put_sync_autosuspend(dev); 573 pm_runtime_disable(dev); 574 return ret; 575 } 576 577 static int xhci_mtk_remove(struct platform_device *pdev) 578 { 579 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev); 580 struct usb_hcd *hcd = mtk->hcd; 581 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 582 struct usb_hcd *shared_hcd = xhci->shared_hcd; 583 struct device *dev = &pdev->dev; 584 585 pm_runtime_get_sync(dev); 586 xhci->xhc_state |= XHCI_STATE_REMOVING; 587 dev_pm_clear_wake_irq(dev); 588 device_init_wakeup(dev, false); 589 590 usb_remove_hcd(shared_hcd); 591 xhci->shared_hcd = NULL; 592 usb_remove_hcd(hcd); 593 usb_put_hcd(shared_hcd); 594 usb_put_hcd(hcd); 595 xhci_mtk_sch_exit(mtk); 596 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 597 xhci_mtk_ldos_disable(mtk); 598 599 pm_runtime_disable(dev); 600 pm_runtime_put_noidle(dev); 601 pm_runtime_set_suspended(dev); 602 603 return 0; 604 } 605 606 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 607 { 608 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 609 struct usb_hcd *hcd = mtk->hcd; 610 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 611 int ret; 612 613 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 614 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 615 del_timer_sync(&hcd->rh_timer); 616 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 617 del_timer_sync(&xhci->shared_hcd->rh_timer); 618 619 ret = xhci_mtk_host_disable(mtk); 620 if (ret) 621 goto restart_poll_rh; 622 623 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 624 usb_wakeup_set(mtk, true); 625 return 0; 626 627 restart_poll_rh: 628 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 629 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 630 usb_hcd_poll_rh_status(xhci->shared_hcd); 631 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 632 usb_hcd_poll_rh_status(hcd); 633 return ret; 634 } 635 636 static int __maybe_unused xhci_mtk_resume(struct device *dev) 637 { 638 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 639 struct usb_hcd *hcd = mtk->hcd; 640 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 641 int ret; 642 643 usb_wakeup_set(mtk, false); 644 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 645 if (ret) 646 goto enable_wakeup; 647 648 ret = xhci_mtk_host_enable(mtk); 649 if (ret) 650 goto disable_clks; 651 652 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 653 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 654 usb_hcd_poll_rh_status(xhci->shared_hcd); 655 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 656 usb_hcd_poll_rh_status(hcd); 657 return 0; 658 659 disable_clks: 660 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 661 enable_wakeup: 662 usb_wakeup_set(mtk, true); 663 return ret; 664 } 665 666 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev) 667 { 668 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 669 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 670 int ret = 0; 671 672 if (xhci->xhc_state) 673 return -ESHUTDOWN; 674 675 if (device_may_wakeup(dev)) 676 ret = xhci_mtk_suspend(dev); 677 678 /* -EBUSY: let PM automatically reschedule another autosuspend */ 679 return ret ? -EBUSY : 0; 680 } 681 682 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev) 683 { 684 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 685 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 686 int ret = 0; 687 688 if (xhci->xhc_state) 689 return -ESHUTDOWN; 690 691 if (device_may_wakeup(dev)) 692 ret = xhci_mtk_resume(dev); 693 694 return ret; 695 } 696 697 static const struct dev_pm_ops xhci_mtk_pm_ops = { 698 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 699 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend, 700 xhci_mtk_runtime_resume, NULL) 701 }; 702 703 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL) 704 705 static const struct of_device_id mtk_xhci_of_match[] = { 706 { .compatible = "mediatek,mt8173-xhci"}, 707 { .compatible = "mediatek,mtk-xhci"}, 708 { }, 709 }; 710 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 711 712 static struct platform_driver mtk_xhci_driver = { 713 .probe = xhci_mtk_probe, 714 .remove = xhci_mtk_remove, 715 .driver = { 716 .name = "xhci-mtk", 717 .pm = DEV_PM_OPS, 718 .of_match_table = mtk_xhci_of_match, 719 }, 720 }; 721 722 static int __init xhci_mtk_init(void) 723 { 724 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 725 return platform_driver_register(&mtk_xhci_driver); 726 } 727 module_init(xhci_mtk_init); 728 729 static void __exit xhci_mtk_exit(void) 730 { 731 platform_driver_unregister(&mtk_xhci_driver); 732 } 733 module_exit(xhci_mtk_exit); 734 735 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 736 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 737 MODULE_LICENSE("GPL v2"); 738